Semiconductor device

Abstract

To provide a semiconductor device in which the avalanche resistance in a termination region can be improved.SOLUTION: A semiconductor device in an embodiment includes a semiconductor part, a first electrode, a second electrode, a control electrode, and a third electrode. The semiconductor part includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The semiconductor part in a first region further includes a third semiconductor layer of the first conductivity type provided between the second semiconductor layer and the second electrode. The semiconductor part further includes a fourth semiconductor layer of the second conductivity type provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode. The distance between the first electrode and the second semiconductor layer in contact with the fourth semiconductor layer in a second region that surrounds the first region is smaller than the distance between the first electrode and the second semiconductor layer in contact with the fourth semiconductor layer in the first region.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] The termination region of a field plate metal-oxide-semiconductor (FPMOS) has low avalanche resistance and can be easily destroyed. The termination region is the region outside the cell region where current flows through the channel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-96841 [Patent Document 2] Patent No. 7171527 [Patent Document 3] Patent No. 7246423 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of improving the avalanche resistance in a termination region is provided. [Means for solving the problem]

[0005] The semiconductor device according to this embodiment includes a semiconductor portion, a first electrode, a second electrode, a control electrode, and a third electrode. The semiconductor portion includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The first electrode is provided on a back surface of the semiconductor portion. The second electrode is provided on a front surface of the semiconductor portion. The first semiconductor layer extends between the first electrode and the second electrode, and the second semiconductor layer is provided between the first semiconductor layer and the second electrode. The control electrode is provided within the semiconductor portion. The third electrode is located between the control electrode and the first electrode in a first direction from the first electrode to the second electrode. The semiconductor portion in the first region further includes a third semiconductor layer of the first conductivity type provided between the second semiconductor layer and the second electrode. The semiconductor portion further includes a fourth semiconductor layer of the second conductivity type provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode. In the second region surrounding the first region, the distance between the second semiconductor layer in contact with the fourth semiconductor layer and the first electrode is smaller than the distance between the second semiconductor layer in contact with the fourth semiconductor layer and the first electrode in the first region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a schematic layout diagram showing a semiconductor device according to a first embodiment. [Figure 3] 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 5] FIG. 10 is a schematic layout diagram showing a semiconductor device according to a third embodiment. [Figure 6] FIG. 10 is a schematic layout diagram showing a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual, and the proportions of the various parts are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0009] (First embodiment) FIG. 1 is a schematic cross-sectional view showing a semiconductor device 1 according to a first embodiment. The semiconductor device 1 is, for example, a MOSFET. The semiconductor device 1 has a trench gate structure. The semiconductor device 1 includes a semiconductor portion 10, a first electrode 20, a second electrode 30, a control electrode 40, and a third electrode 50. The semiconductor portion 10 is, for example, silicon.

[0010] The semiconductor portion 10 has, for example, a back surface on which the first electrode 20 is provided and a front surface opposite thereto. The second electrode 30 is provided on the front surface side of the semiconductor portion 10. The first electrode 20 is a drain electrode. The first electrode 20 is provided on the back surface of the semiconductor portion 10. The second electrode 30 is a source electrode.

[0011] The semiconductor portion 10 includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 13 of a second conductivity type, a third semiconductor layer 15 of the first conductivity type, a fourth semiconductor layer 17 of the second conductivity type, and a fifth semiconductor layer 19 of the first conductivity type. For example, the first conductivity type is n-type, and the second conductivity type is p-type.

[0012] The first semiconductor layer 11 is a so-called drift layer. The first semiconductor layer 11 extends between the first electrode 20 and the second electrode 30.

[0013] The second semiconductor layer 13 is a so-called p-type diffusion layer. The second semiconductor layer 13 is provided between the first semiconductor layer 11 and the second electrode 30.

[0014] The third semiconductor layer 15 is a so-called n-type source layer. The third semiconductor layer 15 is provided between the second semiconductor layer 13 and the second electrode 30. The third semiconductor layer 15 contains a first conductivity type impurity at a concentration higher than the first conductivity type impurity concentration of the first semiconductor layer 11, and is electrically connected to the second electrode 30.

[0015] The fourth semiconductor layer 17 is a so-called p-type contact layer. The fourth semiconductor layer 17 is provided between the second semiconductor layer 13 and the second electrode 30. The fourth semiconductor layer 17 contains a higher concentration of second conductivity type impurities than the second conductivity type impurities of the second semiconductor layer 13, and is electrically connected to the second electrode 30. In this example, the fourth semiconductor layer 17 is provided in the second semiconductor layer 13. The second semiconductor layer 13 is electrically connected to the second electrode 30 via the fourth semiconductor layer 17.

[0016] The fifth semiconductor layer 19 is a so-called n-type drain layer. The fifth semiconductor layer 19 is provided between the first semiconductor layer 11 and the first electrode 20. The fifth semiconductor layer 19 contains a first conductivity type impurity at a concentration higher than the first conductivity type impurity concentration of the first semiconductor layer 11, and is electrically connected to the first electrode 20.

[0017] The control electrode 40 is a gate electrode. The control electrode 40 is located between the first electrode 20 and the second electrode 30, and is provided inside a trench TR provided in the semiconductor portion 10. The third electrode 50 is a so-called field plate. The third electrode 50 is electrically connected to the second electrode 30, and is provided together with the control electrode 40 inside the trench TR.

[0018] 1, the control electrode 40 is provided at the same level as the second semiconductor layer 13 in a direction from the first electrode 20 toward the second electrode 30, for example, in the Z direction. The control electrode 40 includes a first control unit 40A and a second control unit 40B. The first control unit 40A and the second control unit 40B are aligned inside the trench TR in a direction along the boundary between the first semiconductor layer 11 and the second semiconductor layer 13, for example, in the X direction.

[0019] The trench TR extends in a direction from the second electrode 30 toward the first electrode 20, and has a depth that reaches from the surface side of the semiconductor portion 10 into the first semiconductor layer 11. The third electrode 50 is provided, for example, to be located in the first semiconductor layer 11. Within the trench TR, the distance from the third electrode 50 to the first electrode 20 is shorter than the distance from the control electrode 40 to the first electrode 20.

[0020] As shown in FIG. 1, the semiconductor device 1 further includes a first insulating film 41, a second insulating film 43, a third insulating film 45, a fourth insulating film 55, and a fifth insulating film 57.

[0021] The first insulating film 41 is a so-called gate insulating film. The first insulating film 41 is provided between the semiconductor portion 10 and the control electrode 40, and electrically insulates the control electrode 40 from the semiconductor portion 10. The second semiconductor layer 13 is provided to face the control electrode 40 with the first insulating film 41 interposed therebetween. The third semiconductor layer 15 is in contact with the first insulating film 41 between the second semiconductor layer 13 and the second electrode 30.

[0022] A plurality of trenches TR are provided, and are aligned, for example, in the X direction. The second semiconductor layers 13 are provided between the plurality of trenches TR, and face the first control portions 40A and second control portions 40B of the control electrode 40 with the first insulating film 41 interposed therebetween.

[0023] The second insulating film 43 is provided inside the trench TR so as to cover the first control portion 40A and the second control portion 40B of the control electrode 40.

[0024] The third insulating film 45 is provided between the second electrode 30 and the control electrode 40 and electrically insulates the control electrode 40 from the second electrode 30. The second insulating film 43 is located between the control electrode 40 and the third insulating film 45. The third insulating film 45 has a first portion located between the first control unit 40A of the control electrode 40 and the second electrode 30, a second portion located between the second control unit 40B and the second electrode 30, and a third portion extending between the first control unit 40A and the second control unit 40B.

[0025] The second insulating film 43 and the third insulating film 45 serve as an interlayer insulating film that electrically insulates the control electrode 40 from the second electrode 30 .

[0026] The fourth insulating film 55 is provided between the semiconductor portion 10 and the third electrode 50, and electrically insulates the third electrode 50 from the semiconductor portion 10. The third electrode 50 is located, for example, in the first semiconductor layer 11, and the fourth insulating film 55 is located between the first semiconductor layer 11 and the third electrode 50.

[0027] The fourth insulating film 55 is provided, for example, so as to be in contact with the control electrode 40. The width in the X direction of the portion of the fourth insulating film 55 in contact with the control electrode 40 is wider than the width in the X direction of the first control unit 40A and the width in the X direction of the second control unit 40B of the control electrode 40. The third insulating film 45 faces the fourth insulating film 55 with the second insulating film 43 interposed therebetween.

[0028] The fifth insulating film 57 is provided between the third portion of the third insulating film 45 and the third electrode 50. The second insulating film 43 includes a portion located between the third portion of the third insulating film 45 and the fifth insulating film 57. The portion of the second insulating film 43 located between the third portion of the third insulating film 45 and the fifth insulating film 57 is located between the portion of the fourth insulating film 55 that contacts the first control unit 40A and the portion of the fourth insulating film 55 that contacts the second control unit 40B.

[0029] 1, the second electrode 30 includes a first metal layer 31, a second metal layer 33, and a third metal layer 35. The first metal layer 31 is provided on a third insulating film 45. The second metal layer 33 and the third metal layer 35 are stacked in this order on the first metal layer 31.

[0030] The first metal layer 31 acts as a so-called barrier layer that suppresses diffusion of metal atoms into the semiconductor portion 10. The second metal layer 33 is filled inside the contact trench CT that extends from the third insulating film 45 to the semiconductor portion 10. The second metal layer 33 is provided as a so-called buried layer. The third metal layer 35 is provided as a so-called bonding layer, and is connected to a conductor such as a metal wire.

[0031] The second electrode 30 includes a contact portion 30cp extending from the upper surface of the third insulating film 45 into the semiconductor portion 10. The contact portion 30cp contacts and is electrically connected to the third semiconductor layer 15 and the fourth semiconductor layer 17 on the inner surface of the contact trench CT.

[0032] In the first embodiment, the third electrode 50 has a first end on the first electrode 20 side and a second end on the second electrode 30 side. The second end of the third electrode 50 is located, for example, in the Z direction below the level of the boundary between the control electrode 40 and the fourth insulating film 55. The third electrode 50 is provided so as not to overlap with the control electrode 40 when viewed, for example, in the X direction. However, the first embodiment is not limited thereto, and the second end of the third electrode 50 may be located between the first control unit 40A and the second control unit 40B of the control electrode 40.

[0033] 2 is a schematic layout diagram showing the semiconductor device 1 according to the first embodiment. FIG. 1 is a cross-sectional view taken along line AA shown in FIG.

[0034] FIG. 2 shows a partial area of ​​the termination portion of the semiconductor device 1. As shown in FIG.

[0035] As shown in FIG. 2, the trench TR and the contact trench CT extend in the Y direction.

[0036] The source contact portion SC electrically connects the third electrode 50 extended to the termination region to the second electrode 30, which is the source electrode.

[0037] The gate contact portion GC electrically connects the control electrode 40 extended to the termination region to a gate wiring (not shown).

[0038] The first region (cell region or effective cell region) is a region where the third semiconductor layer 15 is provided. The cell region is a region where a current flows through a channel. The line AA shown in Fig. 2 is inside the cell region.

[0039] The second region (termination region) surrounding the cell region is a region where the third semiconductor layer 15 is not provided. The termination region is a region other than the cell region.

[0040] The base region (the region outside the dashed dotted line shown in FIG. 2) is a region for forming a mask in photolithography for forming the second semiconductor layer 13.

[0041] The source poly region (the region outside the two-dot chain line shown in FIG. 2) is a region related to the formation of a mask in photolithography for forming the source contact portion SC by partially shallowly etching the third electrode 50 within the chip of the semiconductor device 1. The source poly region is a region that protects the third electrode 50 when the third electrode 50 is etched.

[0042] The FP region (outside the dashed line shown in FIG. 2) is a region related to the formation of a mask in photolithography to protect the fourth insulating film 55 at the Y-direction end portion of the trench TR without removing it when removing the fourth insulating film 55 in the region where the control electrode 40 is to be formed. The FP region is a region where the control electrode 40 is not to be formed.

[0043] The 2ndFP region (the region outside the thin solid line shown in FIG. 2) is a region related to the formation of a mask in photolithography for forming the seventh insulating film 71. Details of the seventh insulating film 71 will be described later with reference to FIG. 3. The seventh insulating film 71 is provided in the 2ndFP region. The 2ndFP region surrounds the cell region, i.e., the third semiconductor layer 15 and its vicinity.

[0044] The 2ndP+ region (the region sandwiched between the thick solid lines in FIG. 2) is a region into which a high concentration of second conductivity type (p-type) impurities is implanted. Details of the implantation of a high concentration of second conductivity type impurities will be described later with reference to FIG. 3. The 2ndP+ region does not overlap with the cell region, but surrounds the cell region.

[0045] Next, the fourth semiconductor layer 17 will be described in detail.

[0046] The fourth semiconductor layer 17 provided at the bottom of the contact trench CT is provided for, for example, the following two purposes. The first is to fix the base at zero V by an ohmic connection between the second semiconductor layer 13 (base) and the third semiconductor layer 15 (source). The second is to suppress the operation of a parasitic bipolar transistor. During avalanche breakdown, holes are extracted from the bottom of the contact trench CT. At that time, if a voltage drop occurs across the base resistance Rb and the second semiconductor layer 13 rises to a voltage exceeding 0.5 V, a parasitic bipolar transistor with the third semiconductor layer 15 (source), the second semiconductor layer 13 (base), and the first semiconductor layer 11 as the emitter, base, and collector, respectively, will operate, destroying the device. To suppress this, a high concentration of second conductivity type (p-type) impurities is implanted at the bottom of the contact trench CT, and then a p-type diffusion layer is expanded around it by heat treatment to reduce the base resistance Rb.

[0047] Next, the trade-off between avalanche resistance and on-resistance in the cell region will be described.

[0048] When a high concentration of second conductivity type (p-type) impurities is implanted and heat treatment is performed to improve avalanche resistance, the following problems may occur. The fourth semiconductor layer 17 may expand due to heat and reach the channel portion. In this case, the threshold voltage increases and the on-resistance worsens. Furthermore, in the example shown in FIG. 1, the fourth semiconductor layer 17 is formed in the center of the mesa portion between the trenches TR, but in reality, there is a "misalignment." This makes the problem of increased threshold voltage even more serious. It can be said that the trade-off between avalanche resistance and on-resistance (threshold voltage increase) determines the limit of cell pitch shrink.

[0049] Furthermore, if a product cannot be commercialized without avalanche resistance, the following measures may be taken even at the expense of on-resistance.

[0050] The first solution is, for example, to make the second conductivity type impurity at the bottom of the contact trench CT (fourth semiconductor layer 17) more concentrated or to implant it deeper. However, if the second conductivity type impurity is implanted too deeply, the concentration will be high all the way to the bottom end of the second semiconductor layer 13, and when measuring the DS (drain-source) breakdown voltage, the electric field near the bottom end of the second semiconductor layer 13 will be strengthened, lowering the breakdown voltage. Therefore, this method has its limitations.

[0051] The second solution involves injecting a relatively low concentration of second-conductivity-type impurities (lower than the impurity concentration of the fourth semiconductor layer 17 but higher than the impurity concentration of the second semiconductor layer 13) from the bottom of the contact trench CT, and then annealing the resulting structure to achieve an impurity concentration similar to that of the second semiconductor layer 13. As a result, for example, a structure is obtained in which the second semiconductor layer 13 in the cell region extends into the first semiconductor layer 11. This structure further suppresses the operation of the parasitic bipolar transistor. This is thought to be because the path of holes toward the contact trench CT widens, reducing resistance, or because the base thickness of the parasitic bipolar transistor increases. However, the on-resistance worsens for the following reason. The on-resistance worsens because the current path during on-state is narrower than in the structure in which the fourth semiconductor layer 17 is thermally widened as described above. Furthermore, due to "misalignment," the on-resistance of the side where the current path is narrowed due to the misalignment is further reduced.

[0052] Next, the termination region will be described.

[0053] As shown in FIG. 2, there are regions in the +Y direction from the right end of the contact trench CT and in the -Y direction from the left end of the contact trench CT where the contact trench CT is not provided. In these regions, when a surge occurs from the backside, such as at the moment of power-off, a displacement current flows into the second semiconductor layer 13 via the junction capacitance between the second semiconductor layer 13 and the first semiconductor layer 11, making it easy for the potential of the second semiconductor layer 13 to rise. This occurs because the contact trench CT is not located nearby and potential fixing is insufficient. As a result, a parasitic bipolar transistor may operate, potentially destroying the device.

[0054] In order to suppress the operation of the parasitic bipolar transistor in the termination region, it is conceivable to form a p-type heavily doped layer (guard ring diffusion layer) in the region where the contact trench CT is not formed. The p-type heavily doped layer contains a p-type impurity at a higher concentration than the p-type impurity (second conductivity type impurity) of the second semiconductor layer 13. The p-type heavily doped layer reduces resistance and suppresses potential rise, making it less likely that the element will be destroyed at the termination.

[0055] However, even if a p-type high concentration layer is formed over the entire termination area, the area immediately adjacent to the third semiconductor layer 15 is an important area, and it is necessary to more appropriately suppress the potential from rising.

[0056] Therefore, in the first embodiment, a process for improving avalanche resistance (suppressing the operation of the parasitic bipolar transistor) is performed in the termination region, but no process for improving avalanche resistance is performed in the cell region. In the termination region, no current flows through the channel, so the problem of increased on-resistance does not occur. Therefore, it is possible to improve the avalanche resistance in the termination region near the third semiconductor layer 15 while suppressing an increase in on-resistance.

[0057] Fig. 3 is a schematic cross-sectional view showing the semiconductor device 1 according to the first embodiment. Fig. 3 is a cross-sectional view taken along the line BB shown in Fig. 2. The line BB shown in Fig. 2 is located inside the termination region and also inside the 2nd P+ region.

[0058] The semiconductor device 1 further includes a seventh insulating film 71 and an eighth insulating film 73.

[0059] The seventh insulating film 71 functions as a gate insulating film together with the first insulating film 41. By making the gate insulating film thicker in the termination region, the avalanche resistance can be improved and the element can be made less likely to break down even if the potential rises.

[0060] The seventh insulating film 71 has a first portion located between the first control unit 40A and the first insulating film 41, a second portion located between the second control unit 40B and the first insulating film 41, and a third portion located between the second insulating film 43 and the fourth insulating film 55.

[0061] The eighth insulating film 73 is provided between the seventh insulating film 71 and the fifth insulating film 57. The eighth insulating film 73 is, for example, a BPSG (Boron Phosphorus Silicate Glass) film.

[0062] 3, in the termination region, the distance between the second semiconductor layer 13 in contact with the fourth semiconductor layer 17 and the first electrode 20 is smaller than the distance between the second semiconductor layer 13 in contact with the fourth semiconductor layer 17 and the first electrode 20 in the cell region. In addition, the front surface side of the first semiconductor layer 11 facing the fourth semiconductor layer 17 in the Z direction in the termination region is located closer to the back surface side than the front surface side of the first semiconductor layer 11 facing the fourth semiconductor layer 17 in the Z direction in the cell region. This makes it possible to improve the avalanche resistance in the termination region near the third semiconductor layer 15 while suppressing an increase in on-resistance.

[0063] More specifically, the second semiconductor layer 13 located on the back surface side of the fourth semiconductor layer 17 in the termination region extends into the first semiconductor layer 11. The second semiconductor layer 13 located on the back surface side of the fourth semiconductor layer 17 in the termination region extends so as to protrude by, for example, about 1 nm into the first semiconductor layer 11. On the other hand, the second semiconductor layer 13 located on the back surface side of the fourth semiconductor layer 17 in the cell region does not extend into the first semiconductor layer 11 (see FIG. 1).

[0064] As described above, according to the first embodiment, in the termination region, the distance between the second semiconductor layer 13 in contact with the fourth semiconductor layer 17 and the first electrode 20 is smaller than the distance in the cell region between the second semiconductor layer 13 in contact with the fourth semiconductor layer 17 and the first electrode 20. This makes it possible to improve the avalanche resistance in the termination region near the third semiconductor layer 15 while suppressing an increase in on-resistance.

[0065] The impurity concentration of the portion of the second semiconductor layer 13 that protrudes into the first semiconductor layer 11 does not necessarily have to be the same as the impurity concentration of the second semiconductor layer 13. In other words, the protruding portion may be another semiconductor layer of the second conductivity type.

[0066] (Variation) As a modification of the first embodiment, the contact trench CT does not have to be provided. In this case, the fourth semiconductor layer 17 is located at approximately the same level as the third semiconductor layer 15 in the Z direction.

[0067] The contact trench CT may not be provided as in the modification of the first embodiment. The semiconductor device according to the modification of the first embodiment can obtain the same effects as the first embodiment.

[0068] (Second embodiment) 4 is a schematic cross-sectional view showing a semiconductor device 1 according to the second embodiment. In the second embodiment, the concentration of the second conductivity type impurity in the fourth semiconductor layer 17 is different from that in the first embodiment.

[0069] The concentration of the second conductivity type impurity in the fourth semiconductor layer 17 in the termination region is different from the concentration of the second conductivity type impurity in the fourth semiconductor layer 17 in the cell region. More specifically, the concentration of the second conductivity type impurity in the fourth semiconductor layer 17 in the termination region is higher than the concentration of the second conductivity type impurity in the fourth semiconductor layer 17 in the cell region. This makes it possible to improve the avalanche resistance in the termination region near the third semiconductor layer 15 while suppressing an increase in on-resistance. The concentration of the second conductivity type impurity in the fourth semiconductor layer 17 in the termination region is, for example, twice the concentration of the second conductivity type impurity in the fourth semiconductor layer 17 in the cell region. In this case, the concentration of the second conductivity type impurity in the fourth semiconductor layer 17 in the termination region is, for example, 3×10 19 (atoms / cm 3 ), and the concentration of the second conductivity type impurity in the fourth semiconductor layer 17 in the cell region is, for example, 6×10 19 (atoms / cm 3 )

[0070] The size of the fourth semiconductor layer 17 in the termination region may be larger than the size of the fourth semiconductor layer 17 in the cell region.

[0071] As in the modified example of the first embodiment, the concentration of the second conductivity type impurity in the fourth semiconductor layer 17 may be changed. The semiconductor device according to the second embodiment can achieve the same effects as the first embodiment. The semiconductor device according to the second embodiment may also be combined with the first embodiment. In this case, in the termination region, the shapes of the first semiconductor layer 11 and the second semiconductor layer 13 according to the first embodiment and the concentration of the fourth semiconductor layer 17 according to the second embodiment are combined.

[0072] (Third embodiment) 5 is a schematic layout diagram showing a semiconductor device 1 according to the third embodiment. The third embodiment differs from the first embodiment in that the 2nd FP region is not provided.

[0073] In the third embodiment, the seventh insulating film 71 shown in Fig. 3 is not provided. As described in the first embodiment, the seventh insulating film 71 is provided to improve the avalanche resistance. Since the avalanche resistance is improved by the structure shown in Fig. 3, the seventh insulating film 71 can be omitted.

[0074] As in the modified example of the third embodiment, the second FP region does not have to be provided. The semiconductor device according to the third embodiment can achieve the same effects as the first embodiment. Furthermore, the semiconductor device according to the third embodiment may be combined with the second embodiment.

[0075] (Fourth embodiment) 6 is a schematic layout diagram showing a semiconductor device 1 according to the fourth embodiment. The fourth embodiment differs from the first embodiment in that a p-type high concentration layer 80 is provided.

[0076] The p-type heavily doped layer 80 (sixth semiconductor layer) is provided on the surface side of the semiconductor portion 10. As described in the first embodiment, the p-type heavily doped layer 80 is provided to suppress the operation of the parasitic bipolar transistor and improve the avalanche resistance. Therefore, the p-type heavily doped layer 80 (sixth semiconductor layer) can further improve the avalanche resistance in the termination region.

[0077] As in the fourth embodiment, a p-type high concentration layer 80 may be provided. The semiconductor device according to the fourth embodiment can obtain the same effects as those of the first embodiment. Furthermore, the semiconductor device according to the fourth embodiment may be combined with the second and third embodiments.

[0078] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0079] 1...semiconductor device, 10...semiconductor portion, 11...first semiconductor layer, 13...second semiconductor layer, 15...third semiconductor layer, 17...fourth semiconductor layer, 19...fifth semiconductor layer, 20...first electrode, 30...second electrode, 30cp...contact portion, 31...first metal layer, 33...second metal layer, 35...third metal layer, 40...control electrode, 40A...first control portion, 40B...second control portion, 41...first insulating film, 43...second insulating film, 45...third insulating film, 50...third electrode, 55...fourth insulating film, 57...fifth insulating film, CT...contact trench, TR...trench

Claims

1. a semiconductor portion including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion, the first semiconductor layer extending between the first electrode and the second electrode, and the second semiconductor layer being provided between the first semiconductor layer and the second electrode; a control electrode provided in the semiconductor portion; a third electrode located between the control electrode and the first electrode in a first direction from the first electrode toward the second electrode; Equipped with the semiconductor portion in the first region further includes a third semiconductor layer of a first conductivity type provided between the second semiconductor layer and the second electrode; the semiconductor portion further includes a fourth semiconductor layer of a second conductivity type provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode; a distance between the second semiconductor layer in contact with the fourth semiconductor layer and the first electrode in a second region surrounding the first region is smaller than a distance between the second semiconductor layer in contact with the fourth semiconductor layer and the first electrode in the first region.

2. the second semiconductor layer located on the back surface side of the fourth semiconductor layer in the second region extends into the first semiconductor layer, The semiconductor device according to claim 1 , wherein the second semiconductor layer located on the back surface side of the fourth semiconductor layer in the first region does not extend into the first semiconductor layer.

3. 2. The semiconductor device according to claim 1, wherein a concentration of the second conductivity type impurity in said fourth semiconductor layer in said second region is different from a concentration of the second conductivity type impurity in said fourth semiconductor layer in said first region.

4. 4. The semiconductor device according to claim 3, wherein a concentration of the second conductivity type impurity in said fourth semiconductor layer in said second region is higher than a concentration of the second conductivity type impurity in said fourth semiconductor layer in said first region.

5. a semiconductor portion including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion, the first semiconductor layer extending between the first electrode and the second electrode, and the second semiconductor layer being provided between the first semiconductor layer and the second electrode; a control electrode provided in the semiconductor portion; a third electrode located between the control electrode and the first electrode in a first direction from the first electrode toward the second electrode; Equipped with the semiconductor portion in the first region further includes a third semiconductor layer of a first conductivity type provided between the second semiconductor layer and the second electrode; the semiconductor portion further includes a fourth semiconductor layer of a second conductivity type provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode; a second region surrounding the first region and including a second conductivity type impurity concentration of the fourth semiconductor layer different from a second conductivity type impurity concentration of the fourth semiconductor layer in the first region;

6. 6. The semiconductor device according to claim 5, wherein a concentration of the second conductivity type impurity in said fourth semiconductor layer in said second region is higher than a concentration of the second conductivity type impurity in said fourth semiconductor layer in said first region.

7. the second electrode is provided inside a trench having a depth reaching from the surface side of the semiconductor portion into the second semiconductor layer, and includes a contact portion extending from the surface side of the semiconductor portion into the second semiconductor layer; The semiconductor device according to claim 1 , wherein the fourth semiconductor layer is provided between the second semiconductor layer and the contact portion and is electrically connected to the contact portion.

8. The semiconductor device according to claim 1 , wherein the fourth semiconductor layer is positioned at approximately the same level as the third semiconductor layer in the first direction.

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