Display device and method for manufacturing display device

Abstract

To provide a display device in which an aperture ratio can be increased, and a method for manufacturing the display device.SOLUTION: A display device according to one embodiment comprises: a first insulating layer; a first lower electrode positioned on the first insulating layer and having a first peripheral edge; a second insulating layer positioned on the first insulating layer; a second lower electrode positioned on the second insulating layer and having a second peripheral edge; a third insulating layer positioned on the second insulating layer; a third lower electrode positioned on the third insulating layer and having a third peripheral edge; a rib layer formed of an inorganic material and overlapping the first peripheral edge, second peripheral edge, and third peripheral edge; a first organic layer positioned on the first lower electrode; a second organic layer positioned on the second lower electrode; a third organic layer positioned on the third lower electrode; a first upper electrode positioned on the first organic layer; a second upper electrode positioned on the second organic layer; and a third upper electrode positioned on the third organic layer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a display device and a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements comprise a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer emits light in response to the potential difference between the lower and upper electrodes.

[0003] To realize a display device with a high aperture ratio, it is necessary to narrow the gap between the lower electrodes of adjacent display elements. However, due to limitations in processing technology, it is difficult to narrow the gap between the lower electrodes sufficiently. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device that can achieve a high aperture ratio and a method for manufacturing the display device. [Means for solving the problem]

[0006] A display device according to one embodiment comprises a first insulating layer, a first lower electrode located on the first insulating layer and having a first peripheral portion, a second insulating layer located on the first insulating layer, a second lower electrode located on the second insulating layer and having a second peripheral portion, a third insulating layer located on the second insulating layer, a third lower electrode located on the third insulating layer and having a third peripheral portion, a rib layer formed of an inorganic material that overlaps the first peripheral portion, the second peripheral portion, and the third peripheral portion, a first organic layer located on the first lower electrode, a second organic layer located on the second lower electrode, a third organic layer located on the third lower electrode, a first upper electrode located on the first organic layer, a second upper electrode located on the second organic layer, and a third upper electrode located on the third organic layer.

[0007] A manufacturing method of a display device according to one embodiment includes forming a first insulating layer, forming a first lower electrode on the first insulating layer, forming a second insulating layer on the first insulating layer, forming a second lower electrode on the second insulating layer, forming a third insulating layer on the second insulating layer, forming a third lower electrode on the third insulating layer, forming a rib layer overlapping a first peripheral portion of the first lower electrode, a second peripheral portion of the second lower electrode, and a third peripheral portion of the third lower electrode, and forming a first organic layer and a first upper electrode overlapping the first lower electrode, a second organic layer and a second upper electrode overlapping the second lower electrode, and a third organic layer and a third upper electrode overlapping the third lower electrode. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a diagram showing an example of a layer structure that can be applied to a display element. [Figure 5] FIG. 5 is a schematic cross-sectional view of the display device taken along line VV in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view of the display device taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a part of the method for manufacturing the display device according to the first embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 21]FIG. 21 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 23] FIG. 23 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 24] FIG. 24 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 25] FIG. 25 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 26] FIG. 26 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 27] FIG. 27 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 28] FIG. 28 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 30] FIG. 30 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 31] FIG. 31 is a schematic cross-sectional view of a display device according to the second embodiment. [Figure 32] FIG. 32 is a schematic cross-sectional view of a display device according to the third embodiment. [Figure 33] FIG. 33 is a schematic cross-sectional view showing a part of a method for manufacturing a display device according to the third embodiment. [Figure 34] FIG. 34 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 35] FIG. 35 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 36] FIG. 36 is a schematic cross-sectional view of a display device according to the fourth embodiment. [Figure 37] FIG. 37 is a diagram showing an example of a layer structure that can be applied to the display element according to the fourth embodiment. [Figure 38] FIG. 38 is a schematic cross-sectional view of a display device according to the fifth embodiment. [Figure 39] FIG. 39 is a schematic cross-sectional view showing a part of the manufacturing method of the display device according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0010] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. Viewing various elements parallel to the Z direction is referred to as a planar view.

[0011] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0012] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. However, the pixel PX may also include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the drive transistor 3 and the capacitor 4. The source electrode of the drive transistor 3 is connected to the power line PL and the capacitor 4. The drain electrode of the drive transistor 3 is connected to the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example shown in Fig. 2, subpixels SP1 and SP2 are aligned with subpixel SP3 in the X direction. Furthermore, subpixels SP1 and SP2 are aligned with each other in the Y direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP2 are alternately arranged in the Y direction and columns in which multiple subpixels SP3 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel aperture AP3 is larger than the pixel aperture AP2, which is larger than the pixel aperture AP1. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP3 has the largest aperture ratio, and the subpixel SP1 has the smallest aperture ratio. Note that the sizes of the pixel apertures AP1, AP2, and AP3 are not limited to this example. For example, the pixel apertures AP1 and AP2 may have the same size.

[0022] The subpixel SP1 includes a lower electrode LE1 (first lower electrode), an upper electrode UE1 (first upper electrode), and an organic layer OR1 (first organic layer) that overlap with the pixel aperture AP1. The subpixel SP2 includes a lower electrode LE2 (second lower electrode), an upper electrode UE2 (second upper electrode), and an organic layer OR2 (second organic layer) that overlap with the pixel aperture AP2. The subpixel SP3 includes a lower electrode LE3 (third lower electrode), an upper electrode UE3 (third upper electrode), and an organic layer OR3 (third organic layer) that overlap with the pixel aperture AP3.

[0023] The lower electrode LE1, upper electrode UE1, and organic layer OR1 overlapping with the pixel aperture AP1 form the display element DE1 of the subpixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 overlapping with the pixel aperture AP2 form the display element DE2 of the subpixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 overlapping with the pixel aperture AP3 form the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] The pixel circuits 1 of the subpixels SP1, SP2, and SP3 (see FIG. 1) are disposed below the lower electrodes LE1, LE2, and LE3, respectively. The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0025] Partition walls 6 are arranged in the display area DA. The partition walls 6 are located above the rib layer 5 and entirely overlap the rib layer 5. In the example of FIG. 2, the partition walls 6 have the same planar shape as the rib layer 5. That is, the partition walls 6 have openings in the subpixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition walls 6 have a lattice shape in a planar view and surround the display elements DE1, DE2, and DE3, respectively. Specifically, the rib layer 5 and the partition walls 6 surround the lower electrodes LE1, LE2, and LE3, the organic layers OR1, OR2, and OR3, and the upper electrodes UE1, UE2, and UE3, respectively. The partition walls 6 serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0026] Fig. 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in Fig. 2. A circuit layer 11 is disposed on the above-mentioned substrate 10. The circuit layer 11 includes various circuits and wiring such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in Fig. 1.

[0027] The display device DSP includes insulating layers IL1, IL2, and IL3. The circuit layer 11 is covered with the insulating layer IL1 (first insulating layer). The insulating layer IL1 functions as a planarizing film that flattens unevenness caused by the circuit layer 11. The lower electrode LE1 and the insulating layer IL2 (second insulating layer) are located on the insulating layer IL1. In the example shown in FIG. 3, the lower electrode LE1 and the insulating layer IL2 are spaced apart. The lower electrode LE2 and the insulating layer IL3 (third insulating layer) are located on the insulating layer IL2. In the example shown in FIG. 3, the lower electrode LE2 and the insulating layer IL3 are spaced apart. The lower electrode LE3 is located on the insulating layer IL3.

[0028] The lower electrode LE1 has a peripheral edge E1 (first peripheral edge), the lower electrode LE2 has a peripheral edge E2 (second peripheral edge), and the lower electrode LE3 has a peripheral edge E3 (third peripheral edge). The peripheral edge E1 overlaps the insulating layer IL1 in the Z direction. The peripheral edge E2 overlaps the insulating layers IL1 and IL2 in the Z direction. The peripheral edge E3 overlaps the insulating layers IL1, IL2, and IL3 in the Z direction.

[0029] The rib layer 5 overlaps the peripheral edges E1, E2, and E3. In the example shown in Fig. 3, the rib layer 5 directly covers the peripheral edges E1, E2, and E3. The rib layer 5 also covers the ends of the insulating layers IL2 and IL3. Furthermore, the rib layer 5 contacts the insulating layer IL1 between the lower electrodes LE1 and LE2 and between the lower electrodes LE2 and LE3.

[0030] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. This shape of the partition wall 6 is called an overhanging shape. Peripheral portions E1, E2, and E3 are located directly below the partition wall 6.

[0031] In the example of Figure 3, the lower part 61 has a bottom layer 63 and a shaft layer 64. The bottom layer 63 is located on the rib layer 5 and is formed thinner than the shaft layer 64. The shaft layer 64 is located on the bottom layer 63. Also, in the example of Figure 3, both end parts of the bottom layer 63 protrude from the side surfaces of the shaft layer 64. Furthermore, the end parts of the bottom layer 63 are located between the end parts of the upper part 62 and the side surfaces of the shaft layer 64 in a plan view. The upper part 62 is located on the shaft layer 64.

[0032] The organic layer OR1 is located on the lower electrode LE1, and the upper electrode UE1 is located on the organic layer OR1. The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1.

[0033] The organic layer OR2 is located on the lower electrode LE2, and the upper electrode UE2 is located on the organic layer OR2. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2.

[0034] The organic layer OR3 is located on the lower electrode LE3, and the upper electrode UE3 is located on the organic layer OR3. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. In the example shown in FIG. 3, the organic layers OR1, OR2, and OR3 are configured to emit light of different colors. The upper electrodes UE1, UE2, and UE3 are in contact with the side surfaces of the lower portion 61 of the partition wall 6.

[0035] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0036] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0037] A portion of the laminated film FL1 is located on the upper portion 62. This portion is separated from a portion of the laminated film FL1 that is located around the partition wall 6 (a portion that constitutes the display element DE1). Similarly, a portion of the laminated film FL2 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL2 that is located around the partition wall 6 (a portion that constitutes the display element DE2). Furthermore, a portion of the laminated film FL3 is located on the upper portion 62, and this portion is separated from a portion of the laminated film FL3 that is located around the partition wall 6 (a portion that constitutes the display element DE3).

[0038] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively, to cover the stacked films FL1, FL2, and FL3. Specifically, the sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0039] 3, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 are spaced apart from the stacked film FL2 and the sealing layer SE12 on the partition wall 6. In addition, the stacked film FL1 and the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 are spaced apart from the stacked film FL3 and the sealing layer SE13 on the partition wall 6.

[0040] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0041] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0042] The insulating layer IL1 is formed of an organic insulating material such as polyimide. The insulating layers IL2 and IL3, the rib layer 5, and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the insulating layers IL2 and IL3 and the rib layer 5 are formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0043] The lower electrodes LE1, LE2, and LE3 each include a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. The reflective layer can be made of a metal material with excellent light reflectivity, such as silver. Each conductive oxide layer can be made of a transparent conductive oxide, such as ITO (indium tin oxide), IZO (indium zinc oxide), or IGZO (indium gallium zinc oxide).

[0044] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0045] The bottom layer 63 and the shaft layer 64 of the partition wall 6 are formed of, for example, a metal material. Examples of the metal material for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum (Al), an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a laminated structure of multiple layers. The shaft layer 64 may also include a layer formed of an insulating material.

[0046] For example, the upper portion 62 of the partition wall 6 has a laminated structure of a lower layer formed of a metal material and an upper layer formed of a conductive oxide. Examples of the metal material that can be used to form the lower layer include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the upper layer include ITO and IZO. The upper portion 62 may also have a single-layer structure of a metal material. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0047] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the side surfaces of the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0048] 4 is a diagram showing an example of a layer structure that can be applied to display elements DE1, DE2, and DE3. Here, the case where the lower electrodes LE1, LE2, and LE3 correspond to anodes and the upper electrodes UE1, UE2, and UE3 correspond to cathodes will be described as an example.

[0049] The organic layer OR1 includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emitting layer EM1, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. The hole injection layer HIL is located on the lower electrode LE1, the hole transport layer HTL is located on the hole injection layer HIL, the electron blocking layer EBL is located on the hole transport layer HTL, the emitting layer EM1 is located on the electron blocking layer EBL, the hole blocking layer HBL is located on the emitting layer EM1, the electron transport layer ETL is located on the hole blocking layer HBL, the electron injection layer EIL is located on the electron transport layer ETL, and the upper electrode UE1 is located on the electron injection layer EIL. The emitting layer EM1 is formed of a material that emits light in the red wavelength region.

[0050] In addition to the above-mentioned functional layers, the organic layer OR1 may include other functional layers such as a carrier generation layer as needed, or at least one of the above-mentioned functional layers may be omitted.

[0051] Display element DE2 is configured similarly to display element DE1, except that the organic layer OR2 between the lower electrode LE2 and the upper electrode UE includes an emitting layer EM2 instead of the emitting layer EM1. Display element DE3 is configured similarly to display element DE1, except that the organic layer OR3 between the lower electrode LE3 and the upper electrode UE3 includes an emitting layer EM3 instead of the emitting layer EM1. The emitting layer EM2 is formed of a material that emits light in the green wavelength range. The emitting layer EM3 is formed of a material that emits light in the blue wavelength range.

[0052] Fig. 5 is a schematic cross-sectional view of the display device DSP taken along line VV in Fig. 2. The substrate 10, resin layers RS1 and RS2, and sealing layer SE2 shown in Fig. 3 are omitted from Figs.

[0053] The insulating layer IL1 has a contact hole CH1 (first contact hole) that overlaps with the lower electrode LE1 in the Z direction. The contact hole CH1 penetrates the insulating layer IL1. The lower electrode LE1 is in contact with a conductive layer CL included in the circuit layer 11 through the contact hole CH1. The conductive layer CL corresponds to, for example, the source electrode or drain electrode of the driving transistor 3 shown in FIG. 1.

[0054] 6 is a schematic cross-sectional view of the display device DSP taken along line VI-VI in FIG. 2. The insulating layer IL1 has a contact hole CH21 (second contact hole) that overlaps with the lower electrode LE2 in the Z direction. The contact hole CH21 penetrates the insulating layer IL1. The insulating layer IL2 has a contact hole CH22 (fourth contact hole) that overlaps with the contact hole CH11 in the Z direction. The contact hole CH22 penetrates the insulating layer IL2. The contact hole CH2 is composed of the contact holes CH21 and CH22. The lower electrode LE2 is in contact with the conductive layer CL through the contact hole CH2.

[0055] 7 is a schematic cross-sectional view of the display device DSP taken along line VII-VII in FIG. 2. The insulating layer IL1 has a contact hole CH31 (third contact hole) that overlaps with the lower electrode LE3 in the Z direction. The contact hole CH31 penetrates the insulating layer IL1. The insulating layer IL2 has a contact hole CH32 (fifth contact hole) that overlaps with the contact hole CH31 in the Z direction. The contact hole CH32 penetrates the insulating layer IL2. The insulating layer IL3 has a contact hole CH33 (sixth contact hole) that overlaps with the contact holes CH31 and CH32 in the Z direction. The contact hole CH33 penetrates the insulating layer IL3. The contact hole CH3 is composed of contact holes CH31, CH32, and CH33. The lower electrode LE3 is in contact with the conductive layer CL through the contact hole CH3.

[0056] Next, an example of a method for manufacturing the display device DSP will be described.

[0057] 8 to 30 are schematic cross-sectional views showing a part of the method for manufacturing the display device DSP according to the first embodiment. In these figures, the substrate 10 shown in FIG.

[0058] After forming the circuit layer 11 including the conductive layer CL on the substrate 10, an insulating layer IL1 is formed on the circuit layer 11 as shown in FIG. 8. Then, as shown in FIG. 9, a resist R1 is disposed on the insulating layer IL1. The resist R1 covers a portion of the insulating layer IL1. Then, by etching using the resist R1 as a mask, the portion of the insulating layer IL1 exposed by the resist R1 is removed. As a result, contact holes CH1, CH21, and CH31 are formed in the insulating layer IL1 as shown in FIG. 10. Then, as shown in FIG. 11, a lower electrode LE1 is formed so as to overlap the contact hole CH1. The lower electrode LE1 is in contact with the conductive layer CL through the contact hole CH1.

[0059] Next, as shown in FIG. 12, an insulating layer IL2 is formed on the insulating layer IL1 and the lower electrode LE1. Then, as shown in FIG. 13, a resist R2 is disposed on the insulating layer IL2. The resist R2 covers a portion of the insulating layer IL2. Then, by etching using the resist R2 as a mask, the portion of the insulating layer IL2 exposed by the resist R2 is removed. As a result, contact holes CH22 and CH32 are formed in the insulating layer IL2, as shown in FIG. 14. The contact hole CH2 is formed by the contact hole CH21 formed in the insulating layer IL1 and the contact hole CH22 formed in the insulating layer IL2. Furthermore, this etching exposes a portion of the insulating layer IL1 from the insulating layer IL2. Then, as shown in FIG. 15, a lower electrode LE2 overlapping the contact hole CH2 is formed on the insulating layer IL2. The lower electrode LE2 is in contact with the conductive layer CL through the contact hole CH2.

[0060] Next, as shown in FIG. 16, an insulating layer IL3 is formed on the insulating layer IL2 and the lower electrode LE2. Then, as shown in FIG. 17, a resist R3 is disposed on the insulating layer IL3. The resist R3 covers a portion of the insulating layer IL3. Then, by etching using the resist R3 as a mask, the portion of the insulating layer IL3 exposed by the resist R3 is removed. As a result, a contact hole CH33 is formed in the insulating layer IL3, as shown in FIG. 18. The contact hole CH3 is formed by the contact hole CH31 formed in the insulating layer IL1, the contact hole CH32 formed in the insulating layer IL2, and the contact hole CH33 formed in the insulating layer IL3. Furthermore, this etching exposes a portion of the insulating layer IL1 from the insulating layer IL3. Then, as shown in FIG. 19, a lower electrode LE3 overlapping the contact hole CH3 is formed on the insulating layer IL3. The lower electrode LE3 is in contact with the conductive layer CL through the contact hole CH3.

[0061] Next, as shown in Fig. 20, a resist R4 is disposed to cover the lower electrode LE3. After that, the insulating layers IL2 and IL3 located on the lower electrode LE1 and the insulating layer IL3 located on the lower electrode LE2 are removed by etching using the resist R4 as a mask. As a result, the lower electrodes LE1 and LE2 are exposed, as shown in Fig. 21.

[0062] 22, a rib layer 5 is formed to cover the lower electrodes LE1, LE2, and LE3. The rib layer 5 covers the ends of the insulating layers IL2 and IL3. The rib layer 5 is in contact with the insulating layer IL1 between the lower electrodes LE1, LE2, and LE3.

[0063] 23, a resist R5 is disposed on the rib layer 5. The resist R5 covers a portion of the rib layer 5. After that, the portion of the rib layer 5 exposed by the resist R5 is removed by etching using the resist R5 as a mask. As a result, as shown in FIG. 24, a pixel opening AP1 overlapping with the lower electrode LE1, a pixel opening AP2 overlapping with the lower electrode LE2, and a pixel opening AP3 overlapping with the lower electrode LE3 are formed in the rib layer 5.

[0064] Next, as shown in FIG. 25 , partition walls 6 are formed on the rib layer 5. In the process of forming the partition walls 6, conductive lower portions 61 are formed on the rib layer 5. The lower portions 61 include a bottom layer 63 formed on the rib layer 5 and an axis layer 64 formed on the bottom layer 63. Then, upper portions 62 protruding from the side surfaces of the lower portions are formed on the axis layer 64 (lower portions 61). Note that the process of forming the partition walls 6 is not limited to the above process. For example, a layer to be processed into the bottom layer 63, a layer to be processed into the axis layer 64, and a layer to be processed into the upper portions 62 may be stacked in this order on the rib layer 5, and then the upper portions 62, the axis layer 64, and the bottom layer 63 may be formed in this order by etching. In this embodiment, the partition walls 6 are formed after the pixel openings AP1, AP2, and AP3 are formed. However, the partition walls 6 may be formed before the pixel openings AP1, AP2, and AP3 are formed.

[0065] After the rib layer 5 and the partition walls 6 are formed, a process for forming the display elements DE1, DE2, and DE3 is carried out. In this embodiment, it is assumed that the display element DE1 is formed first, the display element DE2 is formed next, and the display element DE3 is formed last. However, the order in which the display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0066] To form the display element DE1, first, as shown in FIG. 26, a laminated film FL1 and a sealing layer SE11 are formed. The laminated film FL1 includes an organic layer OR1, an upper electrode UE1, and a cap layer CP1. The organic layer OR1 is formed on the lower electrode LE1 and covers the lower electrode LE1. The organic layer OR1 is in contact with the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 is formed on the organic layer OR1 and covers the organic layer OR1. The cap layer CP1 is formed on the upper electrode UE1 and covers the upper electrode UE1. The sealing layer SE11 is formed on the cap layer CP1 and covers the cap layer CP1.

[0067] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by vapor deposition. The sealing layer SE11 is formed by CVD (Chemical Vapor Deposition). The stacked film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the stacked film FL1 and the partition walls 6.

[0068] After the stacked film FL1 and the sealing layer SE11 are formed, a resist R6 is disposed on the sealing layer SE11 as shown in FIG. 27. The resist R6 covers the subpixel SP1 and part of the partition wall 6 around it. Then, the stacked film FL1 and the sealing layer SE11 are etched using the resist R2 as a mask to remove the exposed portions of the resist R6. As a result, a display element DE1 is formed in the subpixel SP1 as shown in FIG. 28. For example, the etching may include wet etching and dry etching, which are sequentially performed on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist R6 is removed.

[0069] The display element DE2 is formed by the same procedure as that of the display element DE1. That is, when forming the display element DE2, as shown in FIG. 29, a stacked film FL2 and a sealing layer SE12 are formed. The stacked film FL2 includes an organic layer OR2, an upper electrode UE2, and a cap layer CP2. The organic layer OR2 is formed on the lower electrode LE2 and covers the lower electrode LE2. The organic layer OR2 is in contact with the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 is formed on the organic layer OR2 and covers the organic layer OR2. The cap layer CP2 is formed on the upper electrode UE2 and covers the upper electrode UE2. The sealing layer SE12 is formed on the cap layer CP2 and covers the cap layer CP2.

[0070] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 are formed by vapor deposition. The sealing layer SE12 is formed by CVD. The stacked film FL2 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE12 continuously covers each divided part of the stacked film FL2 and the partition walls 6.

[0071] The display element DE3 is formed in the same manner as the display elements DE1 and DE2. That is, when forming the display element DE3, as shown in FIG. 30, a stacked film FL3 and a sealing layer SE13 are formed. The stacked film FL3 includes an organic layer OR3, an upper electrode UE3, and a cap layer CP3. The organic layer OR3 is formed on the lower electrode LE3 and covers the lower electrode LE3. The organic layer OR3 is in contact with the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 is formed on the organic layer OR3 and covers the organic layer OR3. The cap layer CP3 is formed on the upper electrode UE3 and covers the upper electrode UE3. The sealing layer SE13 is formed on the cap layer CP3 and covers the cap layer CP3.

[0072] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 are formed by vapor deposition. The sealing layer SE13 is formed by CVD. The stacked film FL3 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE13 continuously covers each divided part of the stacked film FL3 and the partition walls 6.

[0073] After the display elements DE1, DE2, and DE3 are formed, a resin layer RS1, a sealing layer SE2, and a resin layer RS2 are formed in this order, as shown in Fig. 5. Through these steps, the display device DSP is completed.

[0074] In the display device DSP according to this embodiment, the lower electrode LE1 is located on the insulating layer IL1, the lower electrode LE2 is located on the insulating layer IL2, and the lower electrode LE3 is located on the insulating layer IL3. With this configuration, even if the distance between the lower electrodes LE1, LE2, and LE3 is narrowed, short-circuiting between the lower electrodes LE1, LE2, and LE3 can be suppressed. As a result, the distance between the lower electrodes LE1, LE2, and LE3 can be narrowed, which enables the display device DSP to have a high aperture ratio.

[0075] [Second embodiment] Next, a second embodiment will be described. Note that configurations not specifically mentioned are the same as those in the first embodiment.

[0076] 31 is a schematic cross-sectional view of a display device DSP according to the second embodiment. In this embodiment, the lower electrodes LE1 and LE2 are located on an insulating layer IL1, and the lower electrode LE3 is located on an insulating layer IL2. Even with this configuration, it is possible to reduce the distance between the lower electrodes LE2 and LE3, and the distance between the lower electrodes LE1 and LE3, thereby achieving the same effects as those described above.

[0077] Alternatively, the lower electrode LE1 may be located on the insulating layer IL1, and the lower electrodes LE2 and LE3 may be located on the insulating layer IL2. That is, it is sufficient that at least one of the lower electrodes LE1, LE2, and LE3 is located on the insulating layer IL1, and at least one of the lower electrodes LE1, LE2, and LE3 is located on the insulating layer IL2. Even with this configuration, the same effects as those described above can be obtained.

[0078] [Third embodiment] Next, a third embodiment will be described. Note that configurations not specifically mentioned are the same as those in the above-described embodiments.

[0079] 32 is a schematic cross-sectional view of a display device DSP according to a third embodiment. In this embodiment, an insulating layer IL2 directly covers a peripheral edge E1 of a lower electrode LE1, and an insulating layer IL3 directly covers a peripheral edge E2 of a lower electrode LE2. A rib layer 5 is located on the insulating layer IL3 and directly covers a peripheral edge E3 of a lower electrode LE3. The peripheral edges E1, E2, and E3 overlap each other in a plan view.

[0080] Next, an example of a method for manufacturing the display device DSP according to the third embodiment will be described. 33 to 35 are schematic cross-sectional views showing a part of the manufacturing method of the display device DSP according to the third embodiment. In these figures, the contact holes CH1, CH2, and CH3 shown in FIG. 2 and the substrate 10 and circuit layer 11 shown in FIG. 32 are omitted.

[0081] The insulating layer IL1 and the lower electrode LE1 are formed by processes equivalent to those described with reference to FIGS. 8 to 11. After the lower electrode LE1 is formed, as shown in FIG. 33, an insulating layer IL2 covering the lower electrode LE1 is formed on the insulating layer IL1 and the lower electrode LE1. Then, the lower electrode LE2 is formed on the insulating layer IL2. The peripheral edge E2 of the lower electrode LE2 overlaps the peripheral edge E1 of the lower electrode LE1 in the Z direction. Then, an insulating layer IL3 covering the lower electrode LE2 is formed on the insulating layer IL2 and the lower electrode LE2. Then, the lower electrode LE3 is formed on the insulating layer IL3. The peripheral edge E3 of the lower electrode LE3 overlaps the peripheral edge E2 of the lower electrode LE2 in the Z direction. Although not shown, the peripheral edge E3 of the lower electrode LE3 overlaps the peripheral edge E1 of the lower electrode LE1 in the Z direction. Then, a rib layer 5 covering the lower electrode LE3 is formed on the insulating layer IL3 and the lower electrode LE3.

[0082] Although not shown, after the step of forming the insulating layer IL2, contact holes CH22 and CH32 are formed in the insulating layer IL2 by a step similar to the step described with reference to Figures 13 and 14. Furthermore, after the step of forming the insulating layer IL3, contact hole CH33 is formed in the insulating layer IL3 by a step similar to the step described with reference to Figures 17 and 18.

[0083] Next, as shown in Fig. 34, a resist R11 is disposed on the rib layer 5. The resist R11 covers a portion of the rib layer 5. After that, the rib layer 5 and the insulating layers IL2 and IL3 that are exposed from the resist R11 are removed by etching using the resist R11 as a mask. This forms pixel openings AP1, AP2, and AP3 as shown in Fig. 35. After that, the display device DSP is completed through steps similar to those described above.

[0084] In this embodiment, the peripheral portions E1, E2, and E3 of the lower electrodes LE1, LE2, and LE3 overlap each other in plan view. In this configuration, the aperture ratio of the pixel apertures AP1, AP2, and AP3 can be made higher than in the display devices DSP according to the first and second embodiments.

[0085] [Fourth embodiment] Next, a fourth embodiment will be described. Note that configurations not specifically mentioned are the same as those in the above-described embodiments.

[0086] 36 is a schematic cross-sectional view of a display device DSP according to a fourth embodiment. In this embodiment, the organic layers OR1, OR2, and OR3 are configured to emit white light. The stacked films FL1, FL2, and FL3 entirely cover the upper surface of the partition wall 6 (the upper surface of the upper portion 62).

[0087] The display device DSP further includes a color filter layer CF. The color filter layer CF is located above the lower electrodes LE1, LE2, and LE3 (display elements DE1, DE2, and DE3). In the example shown in FIG. 36, the color filter layer CF is located on the sealing layer SE2 and covered with a resin layer RS2. Note that the position of the color filter layer CF is not limited to this position.

[0088] The color filter layer CF includes color filters CF1, CF2, and CF3. In one example, color filter CF1 is formed of a resin material colored red, color filter CF2 is formed of a resin material colored green, and color filter CF3 is formed of a resin material colored blue. Color filter CF1 is located directly above the lower electrode LE1 (display element DE1). Color filter CF2 is located directly above the lower electrode LE2 (display element DE2). Color filter CF3 is located directly above the lower electrode LE3 (display element DE3).

[0089] A light-shielding film BM is disposed between the color filter layer CF and the sealing layer SE2. In one example, the light-shielding film BM is formed in a lattice shape and overlaps with the rib layer 5 and the partition walls 6 in plan view.

[0090] Fig. 37 is a diagram showing an example of a layer structure applicable to display elements DE1, DE2, DE3 according to embodiment 4. The display elements DE1, DE2, DE3 shown in Fig. 37 are formed in the same manner as the display elements DE1, DE2, DE3 shown in Fig. 4, except for the layer structure of the emitting layers EM1, EM2, EM3.

[0091] The light-emitting layer EM1 included in the organic layer OR1 includes a light-emitting layer EM11 (first light-emitting layer) that emits red light, a light-emitting layer EM12 (second light-emitting layer) that emits green light, and a light-emitting layer EM13 (third light-emitting layer) that emits blue light. The light-emitting layers EM11, EM12, and EM13 are stacked. Specifically, the light-emitting layer EM11 is located on the electron blocking layer EBL, the light-emitting layer EM12 is located on the light-emitting layer EM11, and the light-emitting layer EM13 is located on the light-emitting layer EM12. The stacking order of the light-emitting layers EM11, EM12, and EM13 is not limited to this example. The organic layer OR1 may also include a light-emitting layer that emits light in a color other than the above colors.

[0092] The light-emitting layer EM2 included in the organic layer OR2 includes a light-emitting layer EM21 (first light-emitting layer) that emits red light, a light-emitting layer EM22 (second light-emitting layer) that emits green light, and a light-emitting layer EM23 (third light-emitting layer) that emits blue light. The light-emitting layers EM21, EM22, and EM23 are stacked. Specifically, the light-emitting layer EM21 is located on the electron blocking layer EBL, the light-emitting layer EM22 is located on the light-emitting layer EM21, and the light-emitting layer EM23 is located on the light-emitting layer EM22. The stacking order of the light-emitting layers EM21, EM22, and EM23 is not limited to this example. The organic layer OR2 may also include a light-emitting layer that emits light in a color other than the above colors.

[0093] The light-emitting layer EM3 included in the organic layer OR3 includes a light-emitting layer EM31 (first light-emitting layer) that emits red light, a light-emitting layer EM32 (second light-emitting layer) that emits green light, and a light-emitting layer EM33 (third light-emitting layer) that emits blue light. The light-emitting layers EM31, EM32, and EM33 are stacked. Specifically, the light-emitting layer EM31 is located on the electron blocking layer EBL, the light-emitting layer EM32 is located on the light-emitting layer EM31, and the light-emitting layer EM33 is located on the light-emitting layer EM32. The stacking order of the light-emitting layers EM31, EM32, and EM33 is not limited to this example. The organic layer OR3 may also include a light-emitting layer that emits light in a color other than the above colors.

[0094] With this configuration, the same effects as those described above can be obtained.

[0095] [Fifth embodiment] Next, a fifth embodiment will be described. Note that configurations not specifically mentioned are the same as those in the above-described embodiments.

[0096] FIG. 38 is a schematic cross-sectional view of a display device DSP according to a fifth embodiment. Unlike the other embodiments, the display device DSP according to the fifth embodiment does not include a partition wall 6. The organic layers OR1, OR2, and OR3 are an integrally formed common layer. Similarly, the upper electrodes UE1, UE2, and UE3 are an integrally formed common electrode, the cap layers CP1, CP2, and CP3 are an integrally formed common layer, and the sealing layers SE11, SE12, and SE13 are an integrally formed common layer. In the example of FIG. 38, the display elements DE1, DE2, and DE3 are composed of layers similar to those of the display elements DE1, DE2, and DE3 shown in FIG. 37. That is, the organic layers OR1, OR2, and OR3 are configured to emit white light.

[0097] Next, an example of a method for manufacturing the display device DSP according to the fifth embodiment will be described. FIG. 39 is a schematic cross-sectional view showing a part of a manufacturing method for the display device DSP according to the fifth embodiment.

[0098] The steps up to the formation of the rib layer 5 are the same as those described with reference to Figures 8 to 24. After the rib layer 5 is formed, organic layers OR1, OR2, and OR3 are integrally formed on the lower electrodes LE1, LE2, and LE3, as shown in Figure 39. The organic layers OR1, OR2, and OR3 cover the lower electrodes LE1, LE2, and LE3 through the pixel openings AP1, AP2, and AP3, respectively.

[0099] Then, upper electrodes UE1, UE2, and UE3 are integrally formed on the organic layers OR1, OR2, and OR3. Then, cap layers CP1, CP2, and CP3 are formed on the upper electrodes UE1, UE2, and UE3. Then, cap layers CP1, CP2, and CP3 are formed on the sealing layers SE11, SE12, and SE13. Then, the display device DSP is completed through processes similar to those described above.

[0100] With this configuration, the same effects as those described above can be obtained.

[0101] All display devices and display device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display devices and display device manufacturing methods described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0102] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0103] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0104] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, 5...rib layer, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axial layer, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, AP1, AP2, AP3...pixel opening, IL1, IL2, IL3...insulating layer.

Claims

1. a first insulating layer; a first lower electrode located on the first insulating layer and having a first periphery; a second insulating layer located on the first insulating layer; a second lower electrode located on the second insulating layer and having a second periphery; a third insulating layer located on the second insulating layer; a third lower electrode located on the third insulating layer and having a third periphery; a rib layer formed of an inorganic material and overlapping the first peripheral edge portion, the second peripheral edge portion, and the third peripheral edge portion; a first organic layer located on the first lower electrode; a second organic layer located on the second lower electrode; a third organic layer located on the third lower electrode; a first upper electrode located on the first organic layer; a second upper electrode located on the second organic layer; a third upper electrode located on the third organic layer; A display device comprising:

2. the rib layer directly covers the first peripheral edge portion, the second peripheral edge portion, and the third peripheral edge portion; The display device according to claim 1 .

3. The rib layer is in contact with the first insulating layer. The display device according to claim 2 .

4. the second insulating layer directly covers the first peripheral edge portion; the third insulating layer directly covers the second peripheral edge portion; the rib layer is located on the third insulating layer and directly covers the third peripheral edge portion. The display device according to claim 1 .

5. At least two of the first peripheral edge portion, the second peripheral edge portion, and the third peripheral edge portion overlap each other in a plan view. The display device according to claim 1 .

6. the first peripheral edge portion, the second peripheral edge portion, and the third peripheral edge portion overlap each other in a plan view; The display device according to claim 1 .

7. a partition wall including a conductive lower portion disposed on the rib layer and an upper portion protruding from a side surface of the lower portion and disposed on the lower portion; the partition wall surrounds the first organic layer, the second organic layer, the third organic layer, the first upper electrode, the second upper electrode, and the third upper electrode, respectively; the first upper electrode, the second upper electrode, and the third upper electrode are in contact with the lower portion; The display device according to claim 1 .

8. the first peripheral portion, the second peripheral portion, and the third peripheral portion are located directly below the partition wall; The display device according to claim 7 .

9. the first organic layer, the second organic layer, and the third organic layer are configured to emit light of different colors. The display device according to claim 7 .

10. the first organic layer, the second organic layer, and the third organic layer are a common layer integrally formed, the first upper electrode, the second upper electrode, and the third upper electrode are a common electrode formed integrally with each other; The display device according to claim 1 .

11. the first organic layer, the second organic layer, and the third organic layer are configured to emit white light; The display device according to claim 7 or 10.

12. Each of the first organic layer, the second organic layer, and the third organic layer comprises: a first light-emitting layer that emits red light; a second light-emitting layer that emits green light; a third light-emitting layer that emits blue light, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer are stacked. The display device according to claim 11.

13. further comprising a color filter layer located above the first lower electrode, the second lower electrode, and the third lower electrode; The display device according to claim 1 .

14. the second insulating layer and the third insulating layer are formed of an inorganic material. The display device according to claim 1 .

15. the first insulating layer has a first contact hole overlapping with the first lower electrode, a second contact hole overlapping with the second lower electrode, and a third contact hole overlapping with the third lower electrode; the second insulating layer has a fourth contact hole overlapping with the second contact hole and a fifth contact hole overlapping with the third contact hole; the third insulating layer has a sixth contact hole overlapping the fifth contact hole; The display device according to claim 1 .

16. forming a first insulating layer; forming a first lower electrode on the first insulating layer; forming a second insulating layer on the first insulating layer; forming a second lower electrode on the second insulating layer; forming a third insulating layer on the second insulating layer; forming a third lower electrode on the third insulating layer; forming a rib layer overlapping a first peripheral edge portion of the first lower electrode, a second peripheral edge portion of the second lower electrode, and a third peripheral edge portion of the third lower electrode; forming a first organic layer and a first upper electrode overlapping the first lower electrode, a second organic layer and a second upper electrode overlapping the second lower electrode, and a third organic layer and a third upper electrode overlapping the third lower electrode; A method for manufacturing a display device.

17. After forming the rib layer, a partition wall is formed on the rib layer; In the step of forming the partition wall, forming a conductive lower portion on the rib layer; forming an upper portion on the lower portion so as to protrude from a side surface of the lower portion; The method for manufacturing a display device according to claim 16.

18. In the step of forming the first organic layer, the first upper electrode, the second organic layer, the second upper electrode, the third organic layer, and the third upper electrode, forming the first organic layer on the first lower electrode; forming the first upper electrode on the first organic layer; forming the second organic layer on the second lower electrode; forming the second upper electrode on the second organic layer; forming the third organic layer on the third lower electrode; forming the third upper electrode on the third organic layer; The method for manufacturing a display device according to claim 17 .

19. After forming the first upper electrode and before forming the second organic layer, forming a cap layer on the first upper electrode; forming an encapsulation layer on the cap layer; The method for manufacturing a display device according to claim 18.

20. In the step of forming the first organic layer, the first upper electrode, the second organic layer, the second upper electrode, the third organic layer, and the third upper electrode, the first organic layer, the second organic layer, and the third organic layer are integrally formed on the first lower electrode, the second lower electrode, and the third lower electrode; forming the first upper electrode, the second upper electrode, and the third upper electrode integrally on the first organic layer, the second organic layer, and the third organic layer; The method for manufacturing a display device according to claim 16.

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