Semiconductor device

Abstract

To provide a semiconductor device with a large storage capacity.SOLUTION: A semiconductor device includes first to fourth insulators, a first conductor, a second conductor, and a first semiconductor. The first semiconductor includes a first surface and a second surface. A first side surface of the first conductor is on the first surface of the first semiconductor, and a first side surface of the first insulator is on a second side surface of the first conductor. The second insulator has a region including a second side surface and an upper surface of the first insulator, an upper surface of the first conductor, and the second surface of the first semiconductor. The third insulator is provided on a formation surface of the second insulator, and the fourth insulator is provided on a formation surface of the third insulator. The second conductor has a region overlapping the second surface of the first semiconductor in a region where the fourth insulator is formed. The third insulator has a function of accumulating charge. By applying a potential to the second conductor, a tunneling current is induced between the second surface of the first semiconductor and the third insulator via the second insulator.SELECTED DRAWING: None

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, a semiconductor wafer, a memory device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. Process, machine, manufacture, or composition of matter Therefore, the technology of one embodiment of the present invention disclosed in this specification more specifically relates to the above. Fields include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, Storage device, processor, electronic device, driving method thereof, manufacturing method thereof, and inspection method thereof One example is a method or a system including at least one of them. [Background technology]

[0003] In recent years, various electronic devices such as personal computers, smartphones, and digital cameras have become The device has a central processing unit (CPU), a graphics processing unit, The electronic components used are microcomputers, such as graphics processing units (GPUs), memory devices, and sensors. Improvements are being made in various aspects, such as miniaturization and low power consumption.

[0004] In particular, the amount of data handled by the electronic devices mentioned above is increasing, and the storage capacity There is a demand for storage devices with large storage capacities. In Reference 1, a three-dimensional NAND memory element using metal oxide as the channel formation region is described. has been disclosed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 9,634,097 Summary of the Invention [Problem to be solved by the invention]

[0006] The semiconductor layer of a transistor that constitutes a memory element or the like is divided into a channel formation region and a low resistance region. In particular, metal oxide is used as the semiconductor layer of a 3D NAND memory element. When using a metal oxide, it is important to know how to form a low resistance region of the metal oxide. In the metal oxide used as the semiconductor layer of the transistor, In this specification, etc., it may be alternatively described as genuine, substantially genuine, etc. The region with high carrier density functions as a channel forming region, and the region with high carrier density functions as a low resistance region. Therefore, in the fabrication of a three-dimensional NAND memory element using metal oxide as the semiconductor layer, Therefore, the challenge is to separately form a channel formation region and a low resistance region.

[0007] An object of one embodiment of the present invention is to provide a novel semiconductor device. An object of one embodiment of the present invention is to provide a memory device including a novel semiconductor device. One embodiment of the present invention provides an electronic device using a memory device having the novel semiconductor device. Another object of the present invention is to provide a storage device with a large data capacity. Another object of one embodiment of the present invention is to provide a highly reliable storage device. This is one of the challenges.

[0008] Note that the problems of one embodiment of the present invention are not limited to the above-listed problems. This does not preclude the existence of other problems. Problems not mentioned in this section are problems that a person skilled in the art would be able to solve by understanding the specification or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the above-listed objects and other objects. One aspect of the present invention is to solve the above-listed problems and other problems. You don't need to solve all of them. [Means for solving the problem]

[0009] (1) One embodiment of the present invention is a semiconductor device including first to fourth insulators, a first conductor, a second conductor, and a first semiconductor. and a first semiconductor having a first surface and a second surface, and a first insulating The first and second side surfaces of the body overlap with the first surface of the first semiconductor via the first conductor. a first side of the first conductor located on a first surface of the first semiconductor; The surface is located on the second side of the first conductor, and the second insulator is located between the second side of the first insulator and the first insulator. a third insulating layer disposed in a region including the upper surface of the insulating layer, the upper surface of the first conductor, and the second surface of the first semiconductor; The insulator is formed in a region where the second insulator is formed and overlaps with the second surface of the first semiconductor. The fourth insulator is located on the surface where the third insulator is formed, and the first insulator of the first semiconductor is located on the surface where the second insulator is formed. and the second conductor is located in a region overlapping with the surface, and the second conductor is located in a region where the fourth insulator is formed. The third insulator is located in a region overlapping the second surface of the first semiconductor, and has a function of storing charges. By applying a potential to the second conductor, a potential is generated between the second surface of the first semiconductor and the third insulator. The semiconductor device is characterized in that a tunnel current is induced through the second insulator.

[0010] (2) Alternatively, one embodiment of the present invention is a semiconductor device including first to fourth insulators, a first conductor, a second conductor, and a first The semiconductor device has a first surface and a second surface. and the first side surface and the second side surface of the first insulator are connected to the first semiconductor via the first conductor. The first conductor is located in a region overlapping with the first surface, and the first side surface of the first conductor is located on the first surface of the first semiconductor. The first side of the first insulator is located on the second side of the first conductor, and the second insulator is located on the first insulator. a second side surface of the first insulator, a top surface of the first conductor, and a second surface of the first semiconductor. The third insulator is located in a region including the first semiconductor in the region where the second insulator is formed. The fourth insulator is located in an area overlapping the second surface, and the fourth insulator is located between the formation surface of the third insulator and the formation surface of the second insulator. and a region overlapping the first surface of the first semiconductor, and the second semiconductor is connected to the fourth insulator via the fourth insulator. The second conductor is located in a region overlapping with the second surface of the first semiconductor, and the second conductor is located in a region overlapping with the formation surface of the second semiconductor. In the region where the fourth insulator is formed, the fourth insulator is located in a region overlapping with the second surface of the first semiconductor. The third insulator has a function of storing electric charges, and by applying a potential to the second conductor, A tunnel current is induced between the second surface of the first semiconductor and the third insulator through the second insulator. The semiconductor device is characterized by:

[0011] (3) Alternatively, in one aspect of the present invention, in the configuration (1) or (2), the third insulator is The second insulator is also located in a region overlapping with the first surface of the first semiconductor, and the semiconductor is located in an area overlapping the second insulator and the fourth insulator. It is a device.

[0012] (4) Alternatively, one embodiment of the present invention is a semiconductor device including a first insulator, a second insulator, a fourth insulator, and first to third insulators. A semiconductor device having a conductor and a first semiconductor, the first semiconductor having a first surface and a second surface. and the first side surface and the second side surface of the first insulator are connected to the first semiconductor via the first conductor. The first conductor is located in a region overlapping with the first surface, and the first side surface of the first conductor is located on the first surface of the first semiconductor. The first side of the first insulator is located on the second side of the first conductor, and the second insulator is located on the first insulator. a second side surface of the first insulator, a top surface of the first conductor, and a second surface of the first semiconductor. the third conductor is located in a region overlapping the second surface of the first semiconductor via the second insulator; The fourth insulator is located between the surface where the third conductor is formed and the area where the second insulator is formed. a region overlapping the second surface of the first semiconductor via the third conductor, and a region in which the second insulator is formed; a region overlapping the first surface of the first semiconductor via a second insulator, The insulator is formed in a region where the fourth insulator is formed and overlaps with the second surface of the first semiconductor. The third conductor has a function of storing electric charges, and is charged by applying an electric potential to the second conductor. Thus, a tunnel current is passed between the second surface of the first semiconductor and the third conductor through the second insulator. The semiconductor device is characterized by inducing

[0013] (5) Alternatively, one embodiment of the present invention is a semiconductor device according to any one of the above structures (1) to (4), wherein the first half The thickness of the first semiconductor on the second surface of the conductor is This semiconductor device is characterized by its thinness rather than its thickness.

[0014] (6) Alternatively, one aspect of the present invention is a fifth insulating film in any one of the above structures (1) to (5). a fourth conductive material, and a fifth insulator opposite the first and second surfaces of the first semiconductor; the fourth conductor is located on the first surface and the second surface of the first semiconductor via the fifth insulator; The semiconductor device is characterized in that it is located in an overlapping region.

[0015] (7) Alternatively, one embodiment of the present invention is a semiconductor device according to any one of the above structures (1) to (6), wherein the first half The conductor includes a metal oxide, and the second surface of the first semiconductor and the vicinity of the second surface include a first semiconductor. The semiconductor device is characterized in that the oxygen concentration is higher on the first surface than on the first surface and in the vicinity of the first surface.

[0016] (8) Alternatively, in the configuration (7), one aspect of the present invention is a semiconductor device comprising: a first surface of the first semiconductor; The vicinity of the surface is composed of elements contained in the first conductor and elements contained in the first semiconductor. The semiconductor device is characterized by having a compound.

[0017] (9) Alternatively, one embodiment of the present invention is a semiconductor device in any one of the above structures (1) to (6). The first semiconductor includes silicon, and the first semiconductor includes a first conductor in the first surface and in the vicinity of the first surface. a low resistance region is formed by an element contained in the first semiconductor and an element contained in the second semiconductor; The semiconductor device is characterized by the above.

[0018] (10) Alternatively, one embodiment of the present invention is a semiconductor device according to any one of the above structures (1) to (9), wherein the first conductive layer is a conductive layer. A sixth insulator is used instead of the insulator, and the sixth insulator comprises silicon nitride. The semiconductor device is characterized by the above.

[0019] (11) Another embodiment of the present invention is a semiconductor device according to any one of (1) to (10). The semiconductor wafer has a plurality of such wafers and has an area for dicing.

[0020] (12) Another embodiment of the present invention is a semiconductor device according to any one of (1) to (10) above. , and peripheral circuits.

[0021] (13) Another aspect of the present invention is an electronic device including the storage device according to (12) above and a housing. It is a vessel. [Effects of the Invention]

[0022] According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment, a memory device including the novel semiconductor device can be provided. According to one aspect of the present invention, an electronic device using a memory device having a novel semiconductor device is provided. Alternatively, one embodiment of the present invention provides a storage device with a large data capacity. According to one embodiment of the present invention, a highly reliable storage device can be provided. can be done.

[0023] The effects of one embodiment of the present invention are not limited to the effects listed above. This does not preclude the existence of other effects. Other effects may be affected by this item, as described below. The effects not mentioned in this section are obvious to a person skilled in the art from the description or can be derived from the descriptions in the drawings, etc., and can be extracted appropriately from these descriptions. One aspect of the present invention is to achieve at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may have the above-listed effects. In some cases, the [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 2] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 3] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 4] 1 is a timing chart showing an example of the operation of a semiconductor device. [Figure 5] 1 is a timing chart showing an example of the operation of a semiconductor device. [Figure 6] 1A to 1C are a perspective view, a top view, and a cross-sectional view illustrating a structural example of a semiconductor device. [Figure 7] 1A to 1C are a perspective view, a top view, and a cross-sectional view illustrating a structural example of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 10] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 11] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 12] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 13] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 14] 1A and 1B are cross-sectional views and a perspective view illustrating a manufacturing example of a semiconductor device. [Figure 15] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 18] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 19] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 20] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 21] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 22] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 23] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 24] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 25] 1A and 1B are a cross-sectional view and a top view illustrating a manufacturing example of a semiconductor device. [Figure 26] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 27] 1A and 1B are a cross-sectional view and a top view illustrating a manufacturing example of a semiconductor device. [Figure 28] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 29] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 30] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 31] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 32] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 33] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 34] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 35] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 36] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 37] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 38] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 39] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 40] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 41] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 42] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 43] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 44] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 45] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 46] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 47] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 48] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 49] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 50] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 51] 1A and 1B are a cross-sectional view and a top view illustrating a manufacturing example of a semiconductor device. [Figure 52] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 53] 1A and 1B are a cross-sectional view and a top view illustrating a manufacturing example of a semiconductor device. [Figure 54] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 55] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 56] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 57] 1A to 1C are top views illustrating a manufacturing example of a semiconductor device. [Figure 58] 1A to 1C are cross-sectional views illustrating an example of manufacturing a semiconductor device. [Figure 59] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 60] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 61] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 62] 1 is a cross-sectional view illustrating a semiconductor device. [Figure 63] FIG. 1 is a block diagram illustrating an example of a storage device. [Figure 64] FIG. 2 is a diagram for explaining the range of atomic ratios of metal oxides. [Figure 65] 1A and 1B are a flowchart illustrating an example of manufacturing an electronic component, a perspective view of the electronic component, and a perspective view of a semiconductor wafer. [Figure 66] Block diagram explaining a CPU. [Figure 67] FIG. 1 is a perspective view showing an example of an electronic device. [Figure 68] FIG. 1 is a perspective view showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0025] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes called oxide semiconductors. In other words, metal oxides have amplifying and rectifying properties. and a channel forming region of a transistor having at least one of a switching function and a gate electrode. When the metal oxide can be formed, the metal oxide is called a metal oxide semiconductor. It can be abbreviated as OS. It is also written as OS FET. In this case, the transistor may be referred to as a transistor having a metal oxide or an oxide semiconductor. can be done.

[0026] In this specification and the like, a transistor having silicon in a channel formation region is referred to as a Si It may also be referred to as a transistor.

[0027] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides (metal ox). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0028] (Embodiment 1) In this embodiment, a circuit configuration, an operation method, and a semiconductor device according to one embodiment of the disclosed invention will be described. In the following description, for example, "[x, y]" is means the element in the xth row and yth column, and "[z]" means the element in the zth row or zth column. When there is no need to specify rows or columns, these notations are omitted.

[0029] <Circuit configuration example> First, the circuit configuration of a NAND memory element, which is an example of a semiconductor device, is shown in FIG. ) will be described. FIG. 1(A) shows a circuit diagram of a NAND memory element on one page. The NAND memory element of one page is made up of memory cells MC[1] to MC [n] memory cells, wiring WL[1] to wiring WL[n] for controlling them, The wiring BL and wiring SL, and the transistors STr and Ts for selecting the page. The wiring SSL for controlling the transistor STr and the transistor BTr The wiring WL is connected to the memory cell MC described later. The control gate of the cell transistor (in this specification, etc., it may be simply referred to as the gate) ) and the wiring SL and the wiring BL function as wirings for applying a potential to the memory cell MC described later. When it functions as wiring that applies a potential to the first terminal and / or second terminal of the cell transistor There is.

[0030] Each memory cell MC has a cell transistor CTr. The transistor is a transistor that operates with normally-on characteristics and has a control gate and a charge The charge storage layer overlaps the channel formation region via a tunnel insulating film. The control gate is provided in a region overlapping the charge storage layer via a blocking film. The cell transistor is provided in a region. A write potential is applied to the control gate. By applying a predetermined potential to either the first or second terminal of the transistor, a tunnel A current is generated, and electrons are injected from the channel formation region of the cell transistor into the charge storage layer. As a result, in the cell transistor in which electrons are injected into the charge storage layer, the threshold voltage The voltage becomes higher. Note that a floating gate may be used instead of the charge storage layer. NAND A memory element is a semiconductor device that utilizes this principle, and the detailed operating principle will be described later. .

[0031] The first terminal of the cell transistor CTr is connected to the cell of the adjacent memory cell MC in terms of circuit configuration. The second terminal of the transistor CTr is electrically connected in series with the second terminal of the transistor CTr. The circuit configuration shown in Figure 1 is a configuration in which n cell transistors CTr are electrically connected in series. In addition, the second terminal of the cell transistor CTr of the memory cell MC[1] is The first terminal of the transistor STr is electrically connected to the cell transistor of the memory cell MC[n]. The first terminal of the transistor CTr is electrically connected to the first terminal of the transistor BTr. The cell transistors C of the memory cells MC[1] to MC[n] The control gate of the transistor is electrically connected to each of the wirings WL[1] to WL[n]. The second terminal of the transistor STr is electrically connected to the line SL. The gate of transistor BTr is electrically connected to the wiring SSL. , and the gate of the transistor BTr is electrically connected to the wiring BSL. is connected.

[0032] The channel forming region of the cell transistor CTr is made of, for example, silicon, germanium, or gallium. Lithium arsenide, silicon carbide (SiC), metal oxides described in the third embodiment, etc. It is preferable to have one or more materials selected from the above. In the channel forming region, indium, element M (element M is, for example, aluminum, It contains one or more metal oxides selected from the group consisting of gallium, yttrium, tin, and zinc. When the metal oxide is a wide-gap semiconductor, the metal oxide may function as a wide-gap semiconductor. The cell transistor, which contains oxide in the channel formation region, has the characteristic of having a very low off-current. That is, the leakage current in the cell transistor CTr in the off state Therefore, the power consumption of the semiconductor device can be reduced in some cases. In addition, the channel forming regions of the transistors STr and BTr are also The metal oxide may include any of the metal oxides described above.

[0033] The channel forming region of the transistor STr and / or the transistor BTr is The channel forming region of the transistor CTr can have a different structure. For example, The material containing the metal oxide described above is applied to the channel formation region of the transistor CTr, The channel forming region of the transistor STr and / or the transistor BTr contains silicon. The materials that can be used can be applied.

[0034] Note that one embodiment of the present invention is not limited to the semiconductor device illustrated in FIG. In some cases, depending on the circumstances, or as needed, the semiconductor device shown in FIG. For example, one embodiment of the present invention is a circuit configuration in which the As shown, the semiconductor device may have a back gate provided in the cell transistor CTr. The semiconductor device shown in FIG. 1B is a semiconductor device shown in FIG. 1A. In addition to the configuration, the cell transistors of the memory cells MC[1] to MC[n] A back gate is provided in the CTr, and the wiring BGL is electrically connected to each of the back gates. In the semiconductor device shown in FIG. 1B, the wiring BGL is connected to the memory cell M. The back gates of the cell transistors CTr of the memory cells MC[1] to MC[n] The back gates are not electrically connected to each other, but are each independently connected to the back gate. Alternatively, they may be electrically connected to each other and supplied with different potentials. An example of the operation of the semiconductor device shown in FIG. 1(B) will be described later.

[0035] Incidentally, if it is desired to further increase the storage capacity of the semiconductor device shown in FIGS. The semiconductor devices shown in 1(A) and 1(B) may be arranged in a matrix. For example, when the semiconductor devices shown in FIG. 1A are arranged in a matrix, The circuit configuration is as shown in Figure 2. In this specification and the like, the multiple A page of NAND memory elements is referred to as one block of NAND memory elements.

[0036] The semiconductor device shown in FIG. 2 is arranged in m rows (m is 1 or more), with the semiconductor device shown in FIG. 1(A) being one row. The wiring WL is shared with the memory cells MC in the same row. In other words, the semiconductor device shown in FIG. The semiconductor device has a matrix of memory cells MC[1,1] to MC[ Therefore, the semiconductor device shown in FIG. n], wirings BL[1] to BL[m], and wirings BSL[1] to BSL[m] wiring SL[1] to wiring SL[m]; wiring SSL[1] to wiring SSL[m]; Specifically, the memory cells MC[j,i] (j is 1 or more) are electrically connected by is an integer between n and m, and i is an integer between 1 and m. The control gate is electrically connected to the wiring WL[j]. The wiring SL[i] is connected to the transistor. The wiring BL[i] is electrically connected to the second terminal of the transistor STr[i]. It is electrically connected to the second terminal.

[0037] 2 shows memory cells MC[1,1], MC[1,i], and M C[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell MC [j,m], memory cell MC[n,1], memory cell MC[n,i], memory cell MC[ n,m], wiring WL[1], wiring WL[j], wiring WL[n], wiring BL[1], wiring B L[i], wiring BL[m], wiring BSL[1], wiring BSL[j], wiring BSL[n], Wiring SL[1], Wiring SL[i], Wiring SL[m], Wiring SSL[1], Wiring SSL[i ], wiring SSL[m], cell transistor CTr, transistor BTr[1], Transistor BTr[i], transistor BTr[m], transistor STr[1], transistor Only the transistor STr[i] and the transistor STr[m] are shown, and other wiring, elements, Symbols and signs are omitted.

[0038] In addition, the semiconductor device shown in FIG. 1(B) is counted as one row, and m rows (m is an integer of 1 or more) are arranged. The arrangement is shown in FIG. 3. In the semiconductor device shown in FIG. 3, all the memory cells Each transistor in the MC has a back gate. Therefore, the semiconductor device shown in FIG. 3 has wiring B for electrically connecting the respective back gates. The semiconductor device shown in FIG. Please refer to the description of the semiconductor device shown in 2.

[0039] The semiconductor devices shown in FIGS. 2 and 3 are formed by arranging the semiconductor devices shown in FIGS. 1(A) and 1(B) in a matrix. However, one embodiment of the present invention is not limited to this. The circuit configuration can be changed depending on the situation or need. For example, FIG. In FIG. 3, a circuit for controlling the transistors BTr[1] to BTr[m] is shown. Although the wirings BSL[1] to BSL[m] are illustrated as lines, The gates of the transistors BTr[1] to BTr[m] are electrically connected to each other. Similarly, the transistors STr[1] to S The wiring for controlling Tr[m] is not wiring SSL[1] to wiring SSL[m], but 1 The gates of the transistors STr[1] to STr[m] are connected as wiring. The power supply may be electrically connected to the power supply port.

[0040] <Example of operation> Next, an example of the operation method of the semiconductor device shown in FIGS. 1A and 1B will be described with reference to FIG. 5B, 5A, and 5B. Note that the semiconductor device of one embodiment of the present invention is In some cases, it is possible to handle not only binary data but also multi-value or analog data. In the description of this operation method, the data handled in writing and reading is not limited to binary. It shall be deemed to be

[0041] In addition, the low level potential and the high level potential used in the following description mean specific potentials. The actual potential may differ depending on the wiring. For example, The low level potential and the high level potential applied to the wiring BL are The potential may be different from the high-level potential.

[0042] Potential V PGM is applied to the control gate of the cell transistor CTr. is the potential at which electrons can be injected into the charge storage layer of the CTr, and the potential V PS is a cell Applying a voltage to the control gate of the transistor CTr turns the cell transistor CTr on. This is the potential at which

[0043] In this example of the operation method, the wiring BGL shown in FIG. A potential within the range in which the cell transistor CTr operates normally is applied in advance. Therefore, the operations of the semiconductor devices shown in FIGS. 1A and 1B are considered to be the same. It is possible.

[0044] <<Write operation>> FIG. 4A is a timing chart showing an example of an operation of writing data to a semiconductor device. The timing chart in FIG. 4(A) shows the timing of the wiring WL[p] (p is an integer between 1 and n). ), wiring WL[j] (where j is an integer between 1 and n, and is not p) ) shows the change in the magnitude of the potential of the wiring BSL, the wiring SSL, and the wiring BL. The timing chart of FIG. 4(A) shows an example of an operation for writing data to a memory cell MC[p]. This shows:

[0045] Before time T10, a low-level potential is supplied to the wiring BL.

[0046] In addition, between time T10 and time T13, the wiring SSL is always supplied with a low level voltage. This causes a low level potential to be applied to the gate of the transistor STr. Therefore, the transistor STr is turned off.

[0047] Between time T10 and time T11, a high-level potential is supplied to the wiring BSL. As a result, a high-level potential is applied to the gate of the transistor BTr. When the transistor BTr is turned on, The voltage supplied from the line BL is applied to the first terminal of the cell transistor CTr of the memory cell MC[n]. A low level potential is applied.

[0048] Between time T11 and time T12, the wiring WL[j] is supplied with a potential V PS is supplied As a result, the control gate of the cell transistor CTr of the memory cell MC[j] potential V PS At this time, in the memory cell MC[n], the cell transistor Since the low-level potential supplied from the wiring BL is applied to the first terminal of the transistor CTr, The cell transistor CTr of the memory cell MC[n] is turned on. The first terminal of the cell transistor CTr of the memory cell MC[n-1] is supplied with a voltage from the wiring BL. That is, the low level potential supplied to the memory cell MC[j] is applied. The cell transistors CTr are sequentially turned on.

[0049] Between time T11 and time T12, the wiring WL[p] is supplied with a potential V PG M As a result, the voltage of the cell transistor CTr of the memory cell MC[p] is A potential V is applied to the control gate. PGM Also, by the above-mentioned operation, the memory cell MC[p A low-level potential is supplied from the wiring BL to the first terminal of the cell transistor CTr of Since the voltage Vcc is applied, the channel of the cell transistor CTr of the memory cell MC[p] Electrons are injected from the formation region into the charge storage layer. The data is written to the cell transistor CT Electrons are injected from the channel formation region of r into the charge storage layer, The threshold voltage of the transistor CTr increases.

[0050] Until time T12, the low-level potential supplied from the wiring BL Between time T12 and time T13, A low-level potential is applied to the wiring WL[j] and the wiring WL[p].

[0051] After time T13, a low-level potential is supplied to the wiring BSL. Since a low-level potential is applied to the gate of the transistor BTr, the transistor BTr is in the off state. Although not shown in the timing chart of FIG. 4(A), at this time, By not supplying a low-level potential to the line BSL and setting the potential of the wiring BL to a high-level potential, , the transistor BTr can be turned off.

[0052] By the above operation, data is written to the semiconductor device shown in FIGS. It can be done.

[0053] <<Read operation>> FIG. 4B is a timing chart showing an example of an operation of reading data from a semiconductor device. The timing chart of FIG. 4(A) shows the wiring WL[p] and wiring WL[q] (q is 1 is an integer between n and p, and is not p.) An integer that is equal to or less than n and is not equal to p or q.), Wiring BSL, Wiring SSL, Wiring S This shows the change in the magnitude of the potential of L, and the current flowing between the wiring SL and the wiring BL is I READ of The timing chart of FIG. 4B shows the change in the magnitude of the memory cell MC 1 shows an example of an operation to read data from memory cell MC[p] and memory cell MC[q]. Electrons are injected into the charge storage layer of the cell transistor CTr of the memory cell MC[p]. Electrons are not injected into the charge storage layer of the cell transistor CTr of the memory cell MC[q]. It shall be deemed to be

[0054] Before time T20, a low-level potential is supplied to the line SL.

[0055] Between time T20 and time T21, the wiring BSL and the wiring SSL are at a high level. As a result, a potential is supplied to the gates of the transistors BTr and STr. Since a high-level potential is applied, the transistors BTr and STr are in the ON state. In addition, when the transistor STr is turned on, the memory cell MC[1 A low-level potential is applied to the second terminal of the cell transistor CTr from the line SL. can be.

[0056] Between time T21 and time T22, the wiring WL[q] and the wiring WL[j] Potential V PS As a result, the memory cells MC[q] and MC[j] The control gate of the cell transistor CTr is supplied with a potential V PS is applied. The second terminal of the cell transistor CTr of the memory cell MC[q] and / or the memory cell MC[j] When a low-level potential is applied to the cell transistor from the wiring SL, The transistor CTr is turned on.

[0057] On the other hand, between time T21 and time T22, a low-level voltage is applied to the wiring WL[p]. As a result, the voltage of the cell transistor CTr of the memory cell MC[p] is A low level potential is applied to the control gate. Since electrons are injected into the charge storage layer of the memory cell CTr, For the above reasons, the threshold voltage of the memory cell MC[p ] cell transistor CTr is turned off, and no current flows between the wiring SL and the wiring BL. At this time, the amount of current flowing through the wiring BL is measured, and it is confirmed that no current flows between the wiring SL and wiring BL. By showing that the charge storage of the cell transistor CTr of the memory cell MC[p] is It can be said that electrons are injected into the layer.

[0058] Between time T22 and time T23, wiring WL[p], wiring WL[q], wiring A low-level potential is supplied to each of the memory cells MC[1] and WL[j]. The control gate of each cell transistor CTr of the memory cell MC[n] is connected to a low A level potential is applied.

[0059] Between time T23 and time T24, the wiring WL[j] is supplied with a potential V PS is supplied As a result, the control gate of the cell transistor CTr of the memory cell MC[j] potential V PS At this time, the cell transistor CTr of the memory cell MC[j] When a low-level potential supplied from the wiring SL is applied to the first terminal of the cell The transistor CTr is turned on.

[0060] Between time T23 and time T24, the wiring WL[p] is supplied with a potential V PS As a result, the control of the cell transistor CTr of the memory cell MC[p] is The gate potential VPS is applied. Meanwhile, the cell transistor of the memory cell MC[p] Since electrons are injected into the charge storage layer of the memory cell CTr, The threshold voltage of the cell transistor CTr is increased, but the control gate has a potential V PS In this example, the cell transistor CTr is substantially The ON state is assumed to be

[0061] Between time T23 and time T24, a low-level voltage is applied to the wiring WL[q]. As a result, the voltage of the cell transistor CTr of the memory cell MC[j] is A low level potential is applied to the control gate of the memory cell MC. r operates with normally-on characteristics, so the cell transistor C Even if a low-level potential supplied from the line SL is applied to the first terminal of the Tr, the cell The transistor CTr is turned on.

[0062] That is, the cell transistors of the memory cells MC[1] to MC[n] Since the transistor CTr is in the on state, current flows between the source and drain of each transistor. In other words, at this time, the amount of current flowing through the wiring BL is measured, and the By indicating that a current is flowing, the cell transistor C of the memory cell MC[q] This means that electrons are not injected into the charge storage layer of the transistor.

[0063] From time T24 to time T25, wiring WL[p], wiring WL[q], wiring WL A low-level potential is supplied to each of the memory cells MC[1] to [j]. A low level is applied to the control gate of each cell transistor CTr of the memory cell MC[n]. A voltage potential is applied.

[0064] After time T25, a low-level potential is supplied to the wirings BSL and SSL. As a result, a low level voltage is applied to the gates of the transistors BTr and STr. Since a potential is applied, the transistors BTr and STr are turned off.

[0065] That is, when data is read from a memory cell MC, the cell transistor of the memory cell MC is A low level potential is applied to the control gate of the transistor CTr, and the cells of the other memory cells MC A high-level potential is applied to the control gate of the transistor CTr, and a current flows between the wiring SL and the wiring BL. By measuring the amount of current flowing through the memory cell MC, the data stored in the memory cell MC can be read. It is possible.

[0066] By the above operation, data is written into the semiconductor device shown in FIGS. and data can be read out.

[0067] <<Erase operation>> FIG. 5A is a timing chart showing an example of an operation for erasing data held in a semiconductor device. The timing chart in FIG. 5(A) shows the timing of the wiring WL[j] (where j is 1 is an integer equal to or larger than n and equal to or smaller than n.), the potentials of the wirings BSL, SSL, BL, and SL The erase operation for a typical NAND memory element is 1 This is done on a page-by-page basis, and this operation example follows this rule. The present invention is not limited to this, and the erase operation may be performed in units of one block, for example.

[0068] Before time T30, a low-level potential is supplied to the wirings BL and SL. .

[0069] In addition, between time T30 and time T33, the wiring WL[j] is always at a low level. A voltage potential is supplied.

[0070] Between time T30 and time T31, the wiring BSL and the wiring SSL are at a high level. As a result, the transistors BTr and STr are Since a high level potential is applied to the gates of the transistors BTr and STr Also, the transistor BTr and the transistor STr are turned on. As a result, the second terminal of the cell transistor CTr of the memory cell MC[1] is connected to A low level potential is applied from the line SL, and the cell transistor of the memory cell MC[n] A low-level potential supplied from the line BL is applied to a first terminal of the transistor CTr.

[0071] Between time T31 and time T32, the wiring BL and the wiring SL are supplied with a potential V ER The potential V ER is higher than the high-level potential flowing through the wiring BL and the wiring SL. As a result, the memory cells MC[1] to MC[n] Since the potential of the channel formation region of all cell transistors CTr increases, Electrons injected into the charge storage layer of the transistor CTr are extracted to the channel formation region. It can be cut.

[0072] Between time T32 and time T33, a low-level voltage is applied to the wiring BL and the wiring SL. Positions are provided.

[0073] After time T33, a low-level potential is supplied to the wirings BSL and SSL. This causes a low level to be applied to the gates of the transistors BTr and STr. Since a potential is applied, the transistors BTr and STr are turned off.

[0074] By the above operation, data can be erased from the semiconductor device shown in FIGS. This can be done.

[0075] In addition, in the semiconductor device shown in FIG. 1B, by using the wiring BGL, An example of this operation is shown in FIG. 5(B). vinegar.

[0076] Before time T40, a low-level potential is supplied to the wirings BL and SL. .

[0077] In addition, between time T40 and time T45, the wiring WL[j] is always at a low level. A voltage potential is applied.

[0078] Between time T40 and time T41, the wiring BSL and the wiring SSL are As a result, the transistors BTr and STr are supplied with a voltage. Since a low level potential is applied to the gates of the transistors BTr and ST r is turned off. Therefore, the second terminal of the transistor STr and the The gap between this terminal and the first terminal is floating.

[0079] Between time T40 and time T41, the wiring BGL is supplied with a potential V BGER is supplied. BGERThe second terminal of the transistor STr is at a very high potential. The line between the first terminal of the transistor BTr and the line BGL is in a floating state. Place is V BGER As a result, the memory cells MC[1] to MC[n] have The potential of the channel formation region of all cell transistors CTr is boosted by capacitive coupling. Therefore, the electrons injected into the charge storage layer of each cell transistor CTr It is pulled out towards the formation area.

[0080] Between time T41 and time T42, the wiring BSL and the wiring SSL have a high level As a result, the transistors BTr and STr are supplied with a voltage. Since a high level potential is applied to the gates of the transistors BTr and ST r is turned on.

[0081] Between time T42 and time T43, a high-level potential is supplied to the wiring BL. As a result, the electrons extracted from the charge storage layer of the cell transistor CTr are transferred to the wiring B It can be passed to L.

[0082] Between time T43 and time T44, a low level potential is supplied to the wiring BL. Subsequently, at time T44, a low level potential is supplied to the wiring BSL and the wiring SSL. As a result, the gates of the transistors BTr and STr are Since a low-level potential is applied, the transistors BTr and STr are in the off state. Finally, after time T45, a low-level potential is supplied to the wiring BGL. .

[0083] As described above, the semiconductor device shown in FIG. 1B can be realized by using the wiring BGL. You can then erase the data.

[0084] <Structure examples and manufacturing methods> In order to facilitate understanding of the structure of the semiconductor device of this embodiment, a manufacturing method thereof will be described below. Reveal.

[0085] 6A, 6B, and 6C are schematic diagrams showing a part of the semiconductor device of FIG. 2 or FIG. 3. FIG. 6A shows a perspective view of a part of the semiconductor device, and FIG. 6B shows a perspective view of the semiconductor device. 6(A). Furthermore, FIG. 6(C) shows the top view of the dashed line A1-A2 in FIG. 1 shows a cross-sectional view corresponding to FIG.

[0086] The semiconductor device includes wiring WL and an insulator (an area not shown in FIG. 6). and have a structure in which they are stacked.

[0087] An opening is formed in the structure so as to penetrate the insulator and the wiring WL at once. In order to provide memory cells MC in the area AR through which the wiring WL penetrates, An insulator, a conductor, and a semiconductor are formed in the opening. It functions as the source electrode or drain electrode of the cell transistor CTr of the memory cell MC, The semiconductor functions as a channel forming region of the cell transistor CTr. A conductor is not formed, and a channel forming region and a low resistance region are formed in the semiconductor. Even if the low resistance region is used as the source electrode or drain electrode of the cell transistor CTr, In Fig. 6(A), (B), and (C), the opening contains an insulator, a conductor, and a semiconductor. The region where the structure is formed is shown as region HL. The region HL inside the body is shown by a broken line. When a back gate is provided in the transistor, the conductor in the region HL is It may also function as wiring BGL for electrically connecting to the clock gate.

[0088] That is, in FIG. 6(C), the semiconductor device shown in either FIG. 1(A) or (B) has a region The semiconductor device shown in FIG. 2 or 3 is formed in the region SD2. This shows that...

[0089] Incidentally, the region TM where the wiring WL is exposed is a connection terminal for applying a potential to the wiring WL. In other words, by electrically connecting wiring to the area TM, A potential can be applied to the gate of the transistor CTr.

[0090] The shape of the region TM is not limited to the example shown in FIG. The structure of the body device is, for example, an insulator formed on a region TM shown in FIG. 6, and an opening formed in the insulator. The opening may be provided with a conductor PG formed to fill the opening (see FIG. 7(A), (B), (C)). In addition, wiring ER is formed on the conductor PG. As a result, the wiring ER and the wiring WL are electrically connected. The conductor PG provided inside the structure is shown by a broken line, and the broken line in the region HL is omitted. is doing.

[0091] In the following manufacturing method example 1 and manufacturing method example 2, in order to form memory cells MC in the region AR, This article explains how to do this.

[0092] <<Production method example 1>> 8 to 19 are cross-sectional views illustrating a manufacturing example of the semiconductor device shown in FIG. The cross-sectional view is a plan view and a perspective view, and in particular, the cross-sectional view is a view of the cell transistor CTr in the channel length direction. In addition, in the cross-sectional views, top views, and perspective views of FIGS. 8 to 19, the For this reason, some elements are omitted in the illustration.

[0093] As shown in FIG. 8A, the semiconductor device of FIG. 1A has a substrate (not shown) above it. an insulator 101A disposed thereon, a sacrificial layer 141A disposed on the insulator 101A, and a sacrificial layer 141A and the insulator 101B disposed on the sacrificial layer 141 B and an insulator 101C disposed on the sacrificial layer 141B. A laminate having a plurality of sacrificial layers and a plurality of insulators (which may also include conductors depending on the subsequent process) The laminate 100 is described as a laminate 100.

[0094] The substrate may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, and stabilized Zirconia substrates (such as yttria-stabilized zirconia substrates) and resin substrates are also available. The semiconductor substrate may be, for example, a semiconductor substrate of silicon, germanium, or silicon carbide. Silicon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates made of silicon. A semiconductor substrate having a region, such as an SOI (Silicon On Insulator) substrate Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, and the like. Furthermore, a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or a semiconductor is provided on a semiconductor substrate, There are substrates with an insulator provided, and substrates with a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate having elements mounted thereon may be used. The elements include a capacitance element, a resistance element, a switch element, a light-emitting element, a memory element, and the like.

[0095] A flexible substrate may also be used as the substrate. As a method of providing a transistor, a transistor is fabricated on a non-flexible substrate, and then the transistor is Another method is to peel off the substrate and transfer it to a flexible substrate. It is preferable to provide a peeling layer between the substrate and the transistor. Alternatively, a sheet, film, foil, or the like may be used. The substrate may also be stretchable. The substrate may also have the property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate may have a property of not returning to its original shape. m or less, preferably 10 μm or more and 500 μm or less, and more preferably 15 μm or more and 300 μm or less The thickness of the substrate is less than 1 μm. In addition, by making the substrate thinner, it is possible to reduce the weight of the device when using glass, etc. Some materials have elasticity and return to their original shape when bending or pulling is stopped. Therefore, it is necessary to reduce the shock that may be applied to the semiconductor device on the board when it is dropped. That is, a robust semiconductor device can be provided.

[0096] The flexible substrate may be, for example, a metal, an alloy, a resin, or a glass, or The substrate, which is a flexible substrate, has a low linear expansion coefficient. The flexible substrate is preferably a wire substrate, for example, since it is less likely to deform due to the environment. Expansion rate is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less The resin may be, for example, polyester, polyolefin, or poly. Amides (nylon, aramid, etc.), polyimides, polycarbonates, acrylics, etc. In particular, aramid has a low linear expansion coefficient and is therefore suitable as a flexible substrate. .

[0097] In the manufacturing example described in this embodiment, a heat treatment is included in the manufacturing process. It is preferable to use a material that has high heat resistance and a low coefficient of thermal expansion.

[0098] Various materials can be used for the sacrificial layers 141A and 141B. For example, silicon nitride, silicon oxide, aluminum oxide, etc. may be used as the insulator. Alternatively, silicon, gallium, germanium, etc. may be used as the semiconductor. Alternatively, aluminum, copper, titanium, tungsten, tantalum, etc. may be used as the conductor. In other words, the sacrificial layers 141A and 141B are made of the same material as that used in other parts. Any material that can provide an etching selectivity may be used.

[0099] The insulators 101A to 101C are made of insulators having reduced impurity concentrations such as water or hydrogen. For example, the hydrogen of the insulators 101A to 101C is preferably a material having a high hydrogen content. The amount of desorption was measured by thermal desorption spectroscopy (TDS). In the hydrogen spectroscopy)) range from 50°C to 500°C, The amount of desorption converted into molecules per area of ​​any one of the insulators 101A to 101C is Converted to 2 x 10 15 molecules / cm 2 Less than 1 × 10 15 m olecules / cm 2 Less than or equal to 5 × 10 14 molecules / cm 2 Furthermore, the insulators 101A to 101C can be formed such that oxygen is released by heating. However, the insulating material may be formed by using the insulating material suitable for the insulators 101A to 101C. The materials that can be used are not limited to those described above.

[0100] The insulators 101A to 101C may include, for example, boron, carbon, nitrogen, oxygen, fluorine, and the like. Fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, gel Magnesium, yttrium, zirconium, lanthanum, neodymium, hafnium, tantalum, etc. Insulators containing one or more materials selected from the above can be used in a single layer or laminated form. In addition, for example, a material containing silicon oxide or silicon oxynitride may be used. However, the materials that can be used for the insulators 101A to 101C are as follows: The present invention is not limited to the above description.

[0101] In this specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen in its composition. Silicon nitride oxide refers to a material that contains more nitrogen than oxygen. In this specification, aluminum oxynitride refers to a material with a high content. Aluminum oxide nitride is a material that has a higher oxygen content than nitrogen. It refers to a material that contains more nitrogen than oxygen as a constituent.

[0102] In the next step, as shown in FIG. 8(B), resist mask formation and etching are performed. Therefore, an opening 191 is formed in the laminate 100 shown in FIG. 8(A).

[0103] The resist mask is formed by, for example, a lithography method, a printing method, an inkjet method, or the like. If the resist mask is formed by the inkjet method, a photomask Since no etching is used, manufacturing costs may be reduced. The etching method may be a dry etching method or a wet etching method, or may be both.

[0104] Then, in the step shown in FIG. 9(A), the side of the opening 191 is removed by etching or the like. Insulators 101A, 101B, and 101C on the surface are each partially removed. As a result, recesses 195A, 195B, and 195C are formed on the side surface. The insulators 101A, 101B, and 101C are the insulators of the laminate 100. The material (sacrificial layer) is formed so that the body 101A, the insulator 101B, and the insulator 101C can be selectively removed. 141A, a material having a higher etching rate than the sacrificial layer 141B) is used. do.

[0105] In the manufacturing process of the semiconductor device shown in FIG. 8B, when the opening 191 is formed, In some cases, the recesses 195A, 195B, and 195C can be automatically formed.

[0106] In the next step, as shown in FIG. 9(B), the side surface of the opening 191 shown in FIG. 9(A) and The conductor 135 is formed in the recesses 195A, 195B, and 195C. A conductor 135 is formed on each side surface of the insulator 101A to the insulator 101C.

[0107] When the semiconductor 151 described later is a material containing silicon, the conductor 135 may be, for example, For example, a material that can be applied to the conductor 134 described later and that can be applied to the conductor 134 It is preferable that the impurity (element or ion) to be diffused into the semiconductor 151 is contained in the As will be described in detail later, in this example of the manufacturing method, the cell transistor CTr is an n-type transistor. When configured as a transistor, n-type impurities (donors) are used as the impurities. As the impurity, for example, phosphorus, arsenic, etc. can be used. In this case, when the cell transistor CTr is a p-type transistor, the impurity is a p-type Impurities (acceptors) are used. Examples of p-type impurities include boron, aluminum, Gallium or the like can be used. Alternatively, a material capable of forming silicide may be used. For example, nickel, cobalt, molybdenum, tungsten, titanium, etc. may be used.

[0108] Alternatively, the conductor 135 may be made of a material with high conductivity, such as aluminum or copper. Alternatively, the conductor 135 may be made of a material with high heat resistance. For example, , titanium, molybdenum, tungsten, tantalum, etc. may also be used.

[0109] In addition, when the semiconductor 151 described later is a material containing a metal oxide, For example, the resistivity of the semiconductor 151 formed on the area on which the conductor 135 is formed is reduced. It is preferable that the material has a function of reducing the resistance of the semiconductor 151. The conductor 135 has a resistance of 2.4×10 3 [Ω / sq] or less, preferably 1. 0×10 3 [Ω / sq] or less, or a nitride containing a metal element, or a compound containing a metal element The conductive material is, for example, aluminum, ruthenium, or titanium. , metal films such as tantalum, tungsten, and chromium, Al-Ti nitride, titanium nitride, etc. Nitride films containing metal elements, or metal oxides such as indium tin oxide and In-Ga-Zn oxide An oxide film containing a metal element can be used.

[0110] In addition, if the material plays a role in reducing the resistance of the semiconductor 151, the conductor 135 can be For example, the conductive material 135 may be replaced with a material such as silicon nitride. An insulator may be used. An alternative to the conductor 135 is silicon nitride. A semiconductor device using this insulator will be described later.

[0111] In the next step, as shown in FIG. 10(A), resist mask formation and etching are performed. As a result, the conductor 135 remains only in the recesses 195A, 195B, and 195C. The conductor 135 included in the opening 191 is removed so that the sacrificial layer 141 A. The conductor 135 is removed to the extent that the sacrificial layer 141B is exposed. , conductor 135a, conductor 135b, and conductor 135c are formed.

[0112] For details on the formation of the resist mask and the etching process, please refer to the explanation of FIG. 8(B). To pour drinks.

[0113] Next, as shown in FIG. 10(B), the conductor 135a and the conductor 135b are attached to the side surface of the opening 191. The semiconductor 1 is formed to cover the conductor 135b, the conductor 135c, the sacrificial layer 141A, and the sacrificial layer 141B. Form 51.

[0114] When a material containing silicon is used as the semiconductor 151, the semiconductor 151 is conductive. By contacting the conductive body 135a (the conductive body 135b and the conductive body 135c), Impurities (elements, ions, etc.) contained in the semiconductor 151 In this case, depending on the situation or in some cases, the laminate 1 It is preferable to perform a heat treatment on the semiconductor 151. Impurity regions are formed on the surfaces in contact with the conductors 135b and 135c and in the vicinity of the interfaces. .

[0115] The impurities contained in the conductor 135a (conductor 135b, conductor 135c) are n-type impurities. In the case of a material (donor), the region 151b of the semiconductor 151 or the conductor 135a of the semiconductor 151 When an n-type impurity region is formed near the interface with (conductor 135b, conductor 135c) On the other hand, impurities contained in the conductor 135a (conductor 135b, conductor 135c) If the substance is a p-type impurity (acceptor), the region 151b of the semiconductor 151 or the region 151 A p-type impurity region is formed in the vicinity of the interface with the conductor 135a (conductor 135b, conductor 135c). In other words, this may result in the formation of a region 151b of the semiconductor 151, or The conductor 151 has a carrier near the interface with the conductor 135a (conductor 135b, conductor 135c). In some cases, holes are formed, causing the region 151b to have a low resistance.

[0116] Furthermore, by performing a heat treatment, the conductor 135a (conductor 135b, conductor 135c) The conductive material and the components contained in the semiconductor 151 cause the conductor 135 of the semiconductor 151 to When metal silicide is formed near the interface with a (conductor 135b, conductor 135c) In this case, as the metal silicide, Compound 161A (Compound 16) shown in FIG. 10(B) is used. 1B, compound 161C). In some cases, an impurity region may be formed near the interface with the compound 161B or 161C.

[0117] When a material containing a metal oxide is used as the semiconductor 151, the semiconductor 151 and the conductive By performing heat treatment while the conductor 135a (the conductor 135b and the conductor 135c) are in contact with each other, The components contained in the conductor 135a (conductor 135b, conductor 135c) and the components contained in the semiconductor 151 Compound 161A (compound 161B, compound 161C) is formed by the components contained in As a result, the resistance of the region 151b of the semiconductor 151 may be reduced. The surface and interface of 151 that contacts the conductor 135a (conductor 135b, conductor 135c) It is sufficient that the resistance of the vicinity is reduced. 5b, conductor 135c) or in the vicinity of the interface, The portion is absorbed by the conductor 135a (conductor 135b, conductor 135c), and the semiconductor 151 is This is thought to be because an elemental defect is formed, causing the region 151b to have a low resistance.

[0118] In addition, the semiconductor 151 and the conductor 135a (conductor 135b, conductor 135c) are connected to each other. In this state, a heat treatment may be performed in an atmosphere containing nitrogen. From the conductor 135a (conductor 135b, conductor 135c), b, the metal element that is a component of the conductor 135c) is converted into the semiconductor 151 or the semiconductor 151 is converted into the The metal element diffuses into the conductor 135a (conductor 135b, conductor 135c), The semiconductor 151 and the conductor 135a (conductor 135b, conductor 135c) form a metal compound. In this case, the metal element of the semiconductor 151 and the conductor 135a The metal elements of the semiconductor 151 (the conductor 135b and the conductor 135c) may be alloyed. The metal element of the conductor 135a (conductor 135b, conductor 135c) is mixed with the metal element of the conductor 135a. By converting the metal elements into a relatively stable state, it is possible to create highly reliable semiconductor devices. can be provided.

[0119] Furthermore, hydrogen in the semiconductor 151 diffuses into the region 151b, and oxygen present in the region 151b When the oxygen vacancy exists in the region 151a, the state becomes relatively stable. The hydrogen in the defects is released from the oxygen vacancies by heat treatment at 250°C or higher and is transferred to the region 151b. The oxygen diffuses and enters the oxygen vacancies present in the region 151b, becoming relatively stable. By the heat treatment, the resistance of the region 151b is lowered and the region 151a is highly purified (water, water The resulting reduction in impurities such as silicon results in a higher resistance.

[0120] That is, by the above-mentioned manufacturing method, the region 151b of the semiconductor 151 is formed as a low resistance region. The region 151a of the semiconductor 151 can be formed as a channel forming region. The region 151b, which is a low resistance region, is the first region of the cell transistor CTr. Since these correspond to the first terminal and / or the second terminal, they can be electrically connected in series by the above-mentioned manufacturing method. The electrical resistance between the connected cell transistors can be reduced.

[0121] As described above, when a material containing a metal oxide is used for the semiconductor 151, The metal oxide will be described in the third embodiment.

[0122] In the next step, as shown in FIG. 11(A), a semiconductor An insulator 102 is formed on the surface on which the body 151 is formed.

[0123] The insulator 102 is, for example, an insulating material having a function of suppressing oxygen permeation. For example, silicon nitride or silicon oxynitride is preferably used as the insulator 102. It is preferable to use silicon oxynitride, aluminum nitride, aluminum nitride oxide, etc. By forming such an insulator 102, the oxide is removed from the region 151a of the semiconductor 151. The oxygen is released, and the oxygen can be prevented from diffusing into the insulator 102. Oxygen is released from the region 151a of the semiconductor 151, and the region 151b of the semiconductor 151 This can prevent the resistance of a from decreasing.

[0124] The insulator 102 may be, for example, an insulating material that allows oxygen to pass through. For example, the insulator 102 is doped with oxygen and the oxygen is diffused. As a result, oxygen can be supplied to the semiconductor 151. This can prevent the resistance of the region 151a from decreasing.

[0125] Alternatively, a plurality of insulators 102 may be stacked. For example, as shown in FIG. The insulator 102A in contact with the semiconductor 151 is made of silicon oxide. The insulating material 102B may be aluminum oxide or hafnium oxide. For example, when aluminum oxide is formed by sputtering, oxygen is supplied to the insulator 102A. The oxygen supplied to the insulator 102A is supplied to the semiconductor 151. As a result, the semiconductor It is possible to prevent the resistance of the region 151a of the conductor 151 from decreasing.

[0126] The insulator 102 may have a function of suppressing the permeation of impurities such as water and hydrogen. For example, aluminum oxide is preferably used as the insulator 102. However, the materials applicable to the insulator 102 are as described above. The insulator 102 is not limited to a specific material, and may be, for example, a material having a reduced concentration of impurities such as water and hydrogen. As the film, a material applicable to the above-mentioned insulators 101A to 101C is used. can be done.

[0127] Incidentally, when a back gate is provided in a cell transistor of a semiconductor device, as shown in FIG. Instead of (A) and (B), the process shown in FIG. 12 is carried out. The insulator 102 is formed on the surface on which the conductor 151 is formed, and the remaining opening 191 is filled. 34 is deposited.

[0128] In this case, the conductor 134 functions as the wiring BGL shown in FIGS.

[0129] The conductor 134 may be, for example, aluminum, chromium, copper, silver, gold, platinum, or tantalum. , nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, Select from calcium, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more of the above metal elements can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, Silicides such as nickel silicide can also be used.

[0130] The conductor 134 may be, for example, a metal oxide that can be used as the semiconductor 151. A conductive material containing a metal element and oxygen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. In addition, indium tin oxide, tungsten oxide, and other conductive materials can be used. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium zinc oxide, silicon Indium tin oxide doped with nitrogen can also be used. By using such a material, the surrounding insulators In some cases, it may be possible to capture hydrogen that enters from sources such as the atmosphere.

[0131] The conductor 134 may have a function of suppressing the permeation of impurities such as water or hydrogen. It is preferable to use a conductive material having the function of tantalum, tantalum nitride, titanium, etc. It is preferable to use titanium nitride, ruthenium, ruthenium oxide, or the like. Alternatively, the layer may be laminated.

[0132] The conductor 134 may also be configured by laminating multiple layers of the above-mentioned materials. a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen; In addition, the material containing the metal element may be combined with a conductive material containing nitrogen. Also, a laminated structure may be formed by combining the material containing the metal element and the conductive material containing oxygen. A laminated structure may be formed by combining a conductive material containing nitrogen with a conductive material containing nitrogen. By applying an insulator having an excess oxygen region as an insulator in contact with the periphery of the conductor, the insulation of the conductor can be improved. Oxygen may diffuse into the area in contact with the substrate. In some cases, a laminated structure can be formed by combining a conductive material containing oxygen with a conductive material containing oxygen. Similarly, an insulator having an excess nitrogen region is used as an insulator in contact with the periphery of a conductor. When applied, nitrogen may diffuse into the area where the conductor contacts the insulator. This allows for the creation of a laminated structure that combines a material containing a metal element and a conductive material containing nitrogen. It may be possible to form.

[0133] The insulator 102 shown in FIG. 12 may have a laminated structure made up of a plurality of insulators. As a laminated structure of a plurality of insulators, for example, the insulator 102 shown in FIG. 11(B) can be used. A and insulator 102B may be laminated (not shown).

[0134] In the next step, as shown in FIG. 13(A), a resist mask pattern is applied to the laminate 100. The slits 192 are formed by performing a deposition process and an etching process. In this step, rather than forming slits, openings may be formed instead.

[0135] For details on the formation of the resist mask and the etching process, please refer to the explanation of FIG. 8(B). To pour drinks.

[0136] Then, in the step shown in FIG. 13(B), slits 192 are formed by etching or the like. The sacrificial layers 141A and 141B are removed from the side surfaces of the laminate 100, and a recess 196A is formed in the laminate 100. , a recess 196B is formed.

[0137] The recesses 196A and 196B are formed in the step of manufacturing the semiconductor device shown in FIG. 13(A). In some cases, the slit 192 can be formed together with the floor.

[0138] By the way, when a material containing silicon is used as the semiconductor 151, the slit 1 92, after the recesses 196A and 196B are formed, the recesses 196A and 196B are exposed to the recesses 196A and 196B. A process of supplying impurities through a slit 192 to a region 151a of the semiconductor 151 that is being In FIG. 14A, the impurity supply process 10 is performed on the region 151a. During the supply process 10, the semiconductor device is not subjected to heat. It is preferable to perform the process. When the cell transistor CTr is an n-type transistor, In order to make the region 151a of the semiconductor 151 a p-type channel forming region, p-type impurities are added. Impurities (acceptors) are used. Examples of p-type impurities include boron, aluminum, Gallium or the like can be used. Also, the cell transistor CTr can be a p-type transistor. In this case, the region 151a of the semiconductor 151 is made into an n-type channel forming region by adding impurities. As the n-type impurity, for example, phosphorus or arsenic is used. It can be used.

[0139] In addition, when a material having a metal oxide is used as the semiconductor 151, the slit 19 2. After the recesses 196A and 196B are formed, the portions exposed in the recesses 196A and 196B are A process of supplying oxygen through a slit 192 to a region 151a of the semiconductor 151 is performed. In this case, the supply process 10 shown in FIG. 14(A) is an oxygen supply process. Examples of the treatment for supplying oxygen include a plasma treatment under reduced pressure and a treatment under an oxygen atmosphere. In particular, plasma treatments containing oxygen include, for example, It is preferable to use an apparatus having a power source that generates high density plasma using microwaves.

[0140] As described above, in the process of supplying impurities, oxygen, etc. to the semiconductor 151, The supply is not made from the outlet 192, but from the terminal outlet as shown in FIG. 14(B). Impurities, oxygen, etc. may be supplied from the structure shown in FIG. 8 is a perspective view showing a manufacturing process of the semiconductor device shown in FIG. 6 or FIG. 7.

[0141] In the next step, as shown in FIG. 15(A), the side surface of the slit 192 shown in FIG. 13(B) is (side surfaces of the insulators 101A to 101C), the recess 196A, and the recess 196B Then, an insulator 103 is deposited.

[0142] The insulator 103 functions as a tunnel insulating film for the cell transistor CTr.

[0143] The insulator 103 may be made of, for example, silicon oxide or silicon oxynitride. The insulator 103 is preferably made of, for example, aluminum oxide, hafnium oxide, Alternatively, an oxide containing aluminum and hafnium may be used. 03 may be an insulator made by laminating these.

[0144] When the semiconductor 151 is a material containing a metal oxide, the insulator 103 may be the above-mentioned The insulator may be formed by laminating a material applicable to the insulator 102 onto the material described above. The insulator 103 is made of a material that has a function of suppressing the permeation of impurities such as oxygen, water, and hydrogen. By using the semiconductor 151, the diffusion of water or hydrogen into the semiconductor 151 and the desorption of oxygen from the semiconductor 151 are prevented. It may be possible to do this.

[0145] In the next step, as shown in FIG. 15(B), the side surface of the slit 192 shown in FIG. 15(A) is , and an insulator 111 is formed in the formed recess. An insulator 111 is formed on the surface.

[0146] In particular, in the region where the insulator 111 is formed, the semiconductor 151 is The region overlapping with the region 151a functions as a charge storage layer for the cell transistor CTr.

[0147] The insulator 111 may be made of, for example, silicon nitride or silicon nitride oxide. However, the materials that can be used for the insulator 111 are not limited to these.

[0148] In the next step, as shown in FIG. 16(A), the side surface of the slit 192 shown in FIG. 15(A) is , and the insulator 104 is formed in the formed recess. An insulator 104 is formed on the surface.

[0149] The insulator 104 functions as a gate insulating film for the cell transistor CTr.

[0150] The insulator 104 is preferably made of, for example, silicon oxide or silicon oxynitride. The insulator 104 is preferably made of, for example, aluminum oxide, hafnium oxide, or Alternatively, oxides containing aluminum and hafnium can be used. The insulating body 104 may be an insulating body formed by laminating these materials. It is preferable that the insulator 104 is thicker than the insulator 103. As a result, charge is transferred from the semiconductor 151 to the insulator 111 via the insulator 103. It is possible.

[0151] In the next step, as shown in FIG. 16(B), the side surface of the slit 192 shown in FIG. 16(A) is The conductor 136 is formed in the recessed portion. A conductor 136 is formed on the surface.

[0152] For the conductor 136, for example, a material that can be applied to the conductor 134 described above can be used. can be done.

[0153] In the next step, as shown in FIG. 17(A), a resist mask is formed and an etching process is performed. Therefore, the conductor 136 included in the slit 192 is removed so that the conductor 136 remains only in the recessed portion. The conductive material 136 is removed. This forms the conductive material 136a and the conductive material 136b. At this time, the insulator 111 may be removed to the extent that it is not exposed to the slit 192. Part of 04 may be removed.

[0154] For details on the formation of the resist mask and the etching process, please refer to the explanation of FIG. 8(B). To pour drinks.

[0155] By the way, the conductor 136a (conductor 136b) is a cell transistor shown in FIGS. It functions as the gate electrode of the transistor CTr and the wiring WL. In the region 181A (region 181B), the cell transistor CTr is formed.

[0156] In the next step, as shown in FIG. 17(B), the insulator 10 is pressed against the insulating film 10 so that the slit 192 is filled. 5 is deposited.

[0157] For the insulator 105, for example, a material that can be used for the insulator 102 described above is used. can be done.

[0158] As described above, by carrying out the steps from FIG. 8(A) to FIG. 17(B), The semiconductor device shown in FIG.

[0159] 18(A) and 18(B) show the semiconductor device shown in FIG. 17(B) with the dashed dotted line B1- 19(A) shows a top view of the semiconductor device 100 shown in FIG. 6. 1 shows a top view of a semiconductor device in which a plurality of openings 191 are provided as in the configuration example shown in FIG. The top view is taken along the dashed line B1-B2 of the semiconductor device shown in FIG. 19(A) is a top view showing the state where a plurality of openings 191 are provided. The semiconductor device shown has a plurality of slits 192, and an opening is formed between adjacent slits 192. As explained in the process shown in FIG. 13, the slit 192 is not provided. 19(B) shows a case where an opening is formed instead of the slit 192. The opening 193 is provided with the insulators 103 to 105 and the insulator 111 formed therein. The position of the opening 193 is the same as that of the slit 192 in FIG. The electrodes may be provided along rows in two or more different directions, rather than along rows in one direction as shown in FIG. Alternatively, the positions of the openings 193 may be formed without relying on the regularity described above.

[0160] One embodiment of the present invention is not limited to the example of the structure of the semiconductor device illustrated in FIG. One embodiment of the present invention is to use the semiconductor device shown in FIG. 17(B) as needed, depending on the situation, or as required. The conductor device may be modified as appropriate.

[0161] For example, one embodiment of the present invention is a cell transistor as shown in FIG. A back gate may be provided in the transistor CTr. When manufacturing a semiconductor device, the process shown in FIG. 1(A) is carried out. 12 can be carried out instead of the step shown in FIG. By carrying out the steps shown in the above, the semiconductor device shown in FIG. 20 can be fabricated.

[0162] 21(A) and 21(B) show the semiconductor device shown in FIG. 20 along the dashed line B1- 20 shows a top view taken along the dashed line B3-B4. Since this is a configuration example in which the conductive material 134 is formed, the top views shown in FIGS. The structure is such that a conductor 134 is formed inside an insulator 102 shown in FIGS. 18(A) and 18(B). do.

[0163] For example, in one embodiment of the present invention, a material containing a metal oxide is used as the semiconductor 151. In this case, the semiconductor 151 can have a three-layer structure as in the semiconductor device shown in FIG. The semiconductor device shown in FIG. 22 has a three-layer structure of semiconductor 151, and In the process of manufacturing the semiconductor 151, the semiconductor 152 is used in the step shown in FIG. A, semiconductor 152B, and semiconductor 152C can be formed in this order. .

[0164] 23(A) and 23(B) show the semiconductor device shown in FIG. 22 along the dashed line B1-B. 2 shows a top view taken along the dashed line B3-B4. The semiconductor layer is a three-layer structure in which semiconductor 152A, semiconductor 152B, and semiconductor 152C are deposited in this order from the outside. Since this is an example of the structure, the top view shown in Figure 23(A)(B) is the same as Figure 18(A)(B). ) has a three-layer structure.

[0165] The semiconductor 152A is made up of an insulator 103, a conductor 135a (conductor 135b, conductor 135c) and a ), and the semiconductor 152C is preferably provided so as to contact the insulator 102. In this case, the semiconductor 152A and the semiconductor 152C are preferably semiconductors. For 152B, it is preferable to use an oxide with a relatively wide energy gap. Here, oxides with a wide energy gap are called wide gap oxides, and oxides with a narrow energy gap are called The oxide is sometimes called a narrow gap.

[0166] The semiconductor 152A and the semiconductor 152C are narrow-gap semiconductors, and the semiconductor 152B is wide-gap semiconductor. In this case, the energy of the bottom of the conduction band of the semiconductor 152A and the semiconductor 152C is It is preferable that the energy is higher than the energy of the bottom of the conduction band of the conductor 152B. The electron affinity of the semiconductor 152A and the semiconductor 152C is greater than the electron affinity of the semiconductor 152B. It is preferable that the difference be smaller than the above.

[0167] The semiconductors 152A to 152C are made up of different combinations of metal atoms with different atomic ratios. Specifically, it is preferable to use a metal for the semiconductor 152A and the semiconductor 152C. In the oxide, the atomic ratio of element M among the constituent elements is the same as that of the metal oxide used in the semiconductor 152B. It is preferable that the atomic ratio of the element M in the constituent elements in the semiconductor 1 is larger than that in the constituent elements in the semiconductor 1. In metal oxides used in 52A and semiconductor 152C, the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used in semiconductor 152B. In addition, in the metal oxide used for the semiconductor 152B, the In the metal oxides used in the semiconductors 152A and 152C, the atomic ratio of In is It is preferable that the atomic ratio of In to the element M is larger than that of In.

[0168] The semiconductor 152A and the semiconductor 152C are made of, for example, In:Ga:Zn=1:3:4, In :Ga:Zn=1:3:2 or In:Ga:Zn=1:1:1 or its vicinity The semiconductor 152B may be made of a metal oxide having the following composition: n:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, or In: Metal oxides having a composition of Ga:Zn=5:1:6 or a composition close to that may be used. These semiconductors 152A to 152C can be formed by satisfying the above atomic ratio relationship. For example, the semiconductor 152A and the semiconductor 152C are preferably made of In:G Metal oxides and semiconductors having a composition of a:Zn=1:3:4 or a composition close to that metals having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition close to that It is preferable that the oxide is used. The above composition is determined by the atomic ratio in the oxide formed on the substrate. , or the atomic ratio in the sputtering target.

[0169] The semiconductor 152A is a CAAC-OS (described later), and the semiconductor 152B is a It is preferable to use CAC-OS as the semiconductor 152A and the semiconductor 152C. When AAC-OS is used, the c-axis is the semiconductor 152A and the semiconductor 152B in FIG. It is preferable that the orientation of C is perpendicular to the formation surface.

[0170] Here, at the junction between the semiconductor 152A (semiconductor 152C) and the semiconductor 152B, In other words, the lower end of the band changes gradually. The conduction band edge at the junction of 152B is said to be continuously variable or continuous junction. To achieve this, the semiconductor 152A (semiconductor 152C) and the semiconductor 152 It is preferable to reduce the defect level density of the mixed layer formed at the interface with B.

[0171] Specifically, the semiconductor 152A (semiconductor 152C) and the semiconductor 152B have common elements other than oxygen. By containing the element (as the main component), it is possible to form a mixed layer with a low defect level density. For example, when the semiconductor 152B is an In-Ga-Zn oxide, the semiconductor 152A (semiconductor Conductors 152C) include In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. This can reduce the defect level at the interface between the semiconductor 152A and the semiconductor 152B. Therefore, the influence of interface scattering on carrier conduction is small. This may result in the cell transistor being able to obtain a high on-state current.

[0172] The semiconductor device shown in FIG. 22 is a semiconductor device in which the semiconductor 151 in FIG. 17(B) has a three-layer structure. However, it may have a two-layer structure or a four-layer or more structure.

[0173] In addition, for example, in the semiconductor device shown in FIG. 17(B), on the surface on which all the insulators 103 are formed, Although the insulator 111 is included in the cell transistor CTr, one embodiment of the present invention is In FIG. 24A, the insulator 111 can be divided into two parts for each charge accumulation layer. After the process shown in FIG. 15(B), a resist mask is formed and an etching process is performed. The insulator 111 remains only on the surface of the recess 196A and the recess 196B where the insulator 103 is formed. 19. In this example, the insulator 111 included in the slit 192 is removed. In some cases or depending on the situation, in the step of removing the insulator 111, As shown in FIG. 24(a), the area of ​​the insulator 103 exposed in the slit 192 may also be removed. In the next step of A), the same steps as those shown in FIG. 16(A) to FIG. 17(B) are carried out. In this way, the semiconductor device shown in FIG. 25(A) can be formed.

[0174] 25(B) shows the semiconductor device shown in FIG. 25(A) along the dashed line B1-B2. The semiconductor device shown in FIG. 25A includes a conductor 135a (conductor 135b). 5b, the conductor 135c) in the region overlapping with the region 151a of the semiconductor 151. 25B. Since the insulator 111 is removed, the top view shown in FIG. In the top view shown in FIG. 18(B), the insulator 111 between the insulator 103 and the insulator 104 is not present. By the way, the top view taken along the dashed line B3-B4 in FIG. may have a configuration similar to that shown in FIG. 18(B).

[0175] Furthermore, for example, one aspect of the present invention is to improve the reliability of the cell transistor CTr. The configuration of the gate electrode of the cell transistor CTr is changed from the configuration shown in FIG. 17(B). 26(A), 26(B), and 27(A) show an example of a method for manufacturing the semiconductor device. In FIG. 26(A), the side surface of the slit 192 and the recessed portion in FIG. The semiconductor 153 is formed on the surface of the insulator 104 formed in the recess 196A and the recess 196B. It has been done.

[0176] The semiconductor 153 may be, for example, a material containing a metal oxide as described in the third embodiment. However, the materials that can be used for the semiconductor 153 are not limited to these. For example, materials other than metal oxides may be used as the semiconductor 153. For example, instead of the semiconductor 153, a conductor, an insulator, or the like may be used.

[0177] In the next step, as shown in FIG. 26(B), a resist mask is formed and an etching process is performed. By this, the recesses 196A and 196B are formed so that the semiconductor 153 remains in a part of the recesses 196A and 196B. The semiconductor 153 in the remaining portion 196A, the recess 196B, and the semiconductor 153 included in the slit 192 The semiconductor 153 is then removed. This results in the formation of the semiconductor 153a and the semiconductor 153b. do.

[0178] For details on the formation of the resist mask and the etching process, please refer to the explanation of FIG. 8(B). To pour drinks.

[0179] After this, the same steps as those shown in FIG. 16(B) to FIG. 17(B) are carried out to form the 7(A) can be constructed.

[0180] 27(B) shows the semiconductor device shown in FIG. 27(A) along the dashed line B3-B4. The semiconductor device shown in FIG. 27A has a region 151a of a semiconductor 151. In this case, a semiconductor 153a (or a semiconductor 153b) is disposed between the conductor 136a (or the conductor 136b) and the insulator 104. Since the semiconductor 153b) is included, the top view shown in FIG. The semiconductor 153b is included between the conductor 136b and the insulator 104. Incidentally, the top view taken along the dashed line B1-B2 in FIG. 27(A) is the same as FIG. 18(A). The configuration may be almost the same.

[0181] The semiconductor 153a (semiconductor 153b) contacts the insulator 104, and the semiconductor 153a (semiconductor 153b) is included in the insulator 104. Impurities such as hydrogen and water contained in the semiconductor 153a may diffuse into the semiconductor 153b. In addition, the semiconductor 153a (semiconductor 153b) is in contact with the conductor 136a (conductor 136b). By this, impurities such as hydrogen and water contained in the conductor 136a (conductor 136b) are converted into semiconductor In other words, the semiconductor 153a (semiconductor 153b) may diffuse into the semiconductor 153a (semiconductor 153b). 53b) may have the role of capturing impurities such as hydrogen and water. The conductor 153a (semiconductor 153b) has a low resistance, and the gate electrode of the cell transistor CTr That is, the semiconductor device shown in FIG. a (semiconductor 153b) to capture impurities such as hydrogen and water in the surrounding area. This can improve the reliability of the transistor CTr.

[0182] In addition, for example, in one embodiment of the present invention, instead of the insulator 111 used as a charge accumulation layer, Alternatively, a floating gate may be used. Figures 28(A) and 28(B) show an example of the manufacturing method. In FIG. 28(A), the recessed portion 196A and the recessed portion 196B in FIG. The conductor 138a and the conductor 138b are formed. As a method for forming the conductive layer 138, the slit 192, the recess 196A, and the recess 196B are formed. A conductive material for the conductor 138a and the conductor 138b is formed, and then a resist mask is formed and etched. By a bonding process or the like, the conductors 138a and 138b are formed in parts of the recesses 196A and 196B, respectively. The conductive material is removed so that the conductive material 138b remains. 17(B) to the deposition process of the insulator 105 shown in FIG. 17(C). By performing the same steps, the semiconductor device shown in FIG. 28(B) can be fabricated.

[0183] 29 shows the top view of the semiconductor device taken along the dashed line B3-B4 in FIG. 28(B). The semiconductor device shown in FIG. 28B is a semiconductor device having a region 151a overlapping with the region 151b of the semiconductor 151. In the region where the insulator 103 and the insulator 104 are connected, a conductor 138a (conductor 138 Since the structure includes the insulator 103 and the insulator b), the top view shown in FIG. The structure includes a conductor 138b between the bodies 104. ) shows a top view taken along the dashed line B1-B2 in FIG. 25(B). There is a match.

[0184] The conductor 138a and / or the conductor 138b may be, for example, the conductor 136 described above. However, the conductor 138a and / or the conductor 13 The materials applicable to the conductor 138a and / or the conductor 138b are not limited to these. As an alternative to 8b, an insulator, a semiconductor, etc. may be applicable.

[0185] Furthermore, for example, one aspect of the present invention is to provide a film thickness of the channel formation region of the cell transistor CTr. The semiconductor device can be fabricated in a reduced size. In FIG. 30(A), the sacrificial layer 141A and the sacrificial layer 141B in FIG. 13(B) are shown. After removing the layer 141B, the surface of the semiconductor 151 is further removed by etching or the like. As a result, the thickness of the semiconductor 151 included in the region 151a is equal to the thickness of the semiconductor 151 included in the region 151b. This step is performed to form an impurity region on the surface of the semiconductor 151. This is effective when an impurity region is formed, and by carrying out this step, the impurity region is removed. As a result, the region 151a of the semiconductor 151 can be made to have a high resistance.

[0186] The thickness of the semiconductor 151 to be removed in the region 151a is, for example, The thickness of the deposited semiconductor 151 is 30 nm or more and 60 nm or less, or the thickness of the deposited semiconductor 151 is or 1 / 5 or more and 1 / 2 or less of the thickness of the insulator 103 to be formed thereafter. or less than 1 / 2, or 1 / 5 or less of the film thickness of the conductor 135a (conductor 135b, conductor 135c). The thickness of the deposited semiconductor 151 is at least 1 / 2 of the thickness of the upper portion. The thickness of the semiconductor 151 to be removed at 51a is set to be larger than the thickness of the semiconductor 151 to be removed at 51a. By carrying out the same steps as those in (A) to (B) of FIG. 17, the semiconductor shown in (B) of FIG. A body device can be configured.

[0187] 31(A) and 31(B) show the semiconductor device shown in FIG. 30(B) along the dashed line B 30(B) shows a top view taken along the dashed line B3-B4. The device is configured such that the thickness of the semiconductor 151 in the region 151a is greater than the thickness of the semiconductor 151 in the region 151b. Since the film thickness of the semiconductor 15 shown in the top view of FIG. 1 is thinner than the semiconductor 151 in the top view shown in FIG. 31(A).

[0188] Furthermore, for example, in the semiconductor device of one embodiment of the present invention, as described above, the conductor 135 may be replaced with a As the insulating layer, a structure using an insulator such as silicon nitride can be used. The insulators 101A to 101C shown in FIG. 8A are replaced with the insulators 107A to 107C. 7C. As described above, silicon nitride or the like can be used for the insulators 107A to 107C. The material that can be applied to the insulator 107C is not limited to this. The component contained in the insulating layer 107C reacts with the component contained in the semiconductor 151, and the semiconductor 151 If a low resistance region is formed in the region 151b, the insulators 107A to The material applicable to 107C may be other than silicon nitride.

[0189] An opening 191 is formed in the laminate 100A in the same manner as in the step shown in FIG. 8(B). (See FIG. 32(B)). Next, similar to the steps shown in FIG. 10(B) and FIG. 11(A), 2(B), a semiconductor 151 is formed on the side surface of the opening 191, and the shape of the semiconductor 151 is An insulator 102 is formed on the surface to fill the opening 191 (see FIG. 33(A)). When the semiconductor 151 is a metal oxide, in the cross-sectional view shown in FIG. The body 151 is formed at the interface with the insulator 107A (insulator 107B, insulator 107C) and near the interface. Nitrogen diffused from the insulator 107A (insulator 107B, insulator 107C) nearby, Compound 161A (Compound 161B, Compound 161C) ) is formed. This reduces the resistance of the region 151b of the semiconductor 151. When the resistance can be reduced in the electrical connection between adjacent cell transistors CTr There is.

[0190] Thereafter, the same steps as those shown in FIGS. 13(A) and 13(B) and 14 to 17(B) are carried out. Therefore, the semiconductor device shown in FIG. 33(B) can be constructed. 10A to 10C can be omitted. The manufacturing process of the semiconductor device can be shortened.

[0191] 34(A) and 34(B) show the semiconductor device shown in FIG. 33(B) along the dashed line B 33(B) shows a top view taken along the dashed line B3-B4. Since the device is a configuration example in which the formation of the conductors 135a to 135c is omitted, The top view shown in FIG. 34(A)(B) is obtained by changing the conductor 135c (conductor 135c) from FIG. 18(A)(B). 35a and conductor 135b) are omitted.

[0192] <<Production method example 2>> Here, as a semiconductor device of this embodiment, an example of a structure different from that of Manufacturing Method Example 1 will be described. This will be explained with reference to FIGS. 35 to 45.

[0193] 35 to 45 are, similarly to FIGS. 8 to 19, examples of manufacturing the semiconductor device shown in FIG. 1A. 1A and 1B are a cross-sectional view, a top view, and a perspective view for explaining the cell transistor C. 35 to 45 are similar to FIGS. 8 to 19. In the drawings, some elements are omitted for clarity.

[0194] The first step is the same as that described in Example 1 of Fabrication Method from FIG. 8(A) to FIG. 8(B). Please refer to the description below.

[0195] The process shown in Figure 35(A) is a continuation of the process shown in Figure 8(B). In (A), the side surface of the opening 191 (insulators 101A to 101B) shown in FIG. C, the side surfaces of the sacrificial layer 141A and the sacrificial layer 141B) are provided with a conductor 137. can be.

[0196] For the conductor 137, the description of the conductor 135 in Manufacturing Method Example 1 can be referred to.

[0197] In FIG. 35(B), the side surface of the opening 191 shown in FIG. 35(A) and the recess formed therein are shown. In other words, the semiconductor 151 is formed on the surface on which the conductor 137 is formed. will be done.

[0198] For the semiconductor 151, the description of the semiconductor 151 in Manufacturing Method Example 1 can be referred to.

[0199] At this time, the semiconductor 151 is in contact with the conductor 137, so that the semiconductor 151 In some cases, a low resistance region may be formed near the interface with the The region 151d is shown as a low resistance region, and the region 151e is shown as a region having a relatively higher resistance than the low resistance region. The region 151e is shown in the figure. Note that there are cases where the low resistance region is not formed.

[0200] However, if heat treatment is applied at this time, the semiconductor 151 and the conductor 137 may be heated. As a result, a compound is formed between the component contained in the semiconductor 151 and the component contained in the conductor 137. Therefore, no heat treatment is performed after this step unless otherwise specified. Specifically, the heat treatment is not performed until the predetermined process is completed, and the heat treatment is performed after the predetermined process. The theory may also be carried out.

[0201] In the next step, as shown in FIG. 36(A), a semiconductor An insulator 102 is formed on the surface on which the body 151 is formed.

[0202] As an example of the insulator 102, an insulating material having a function of allowing oxygen to pass therethrough is used. For example, it is preferable to dope the insulator 102 with oxygen and diffuse the oxygen. As a result, oxygen can be supplied to the semiconductor 151. This can prevent the resistance of 51a from decreasing.

[0203] Alternatively, a plurality of insulators 102 may be stacked. For example, as shown in FIG. Silicon oxide is used for the insulator 102A in contact with the body 151, and silicon dioxide is used for the insulator 102A in contact with the body 151. The insulator 102B may be made of aluminum oxide, hafnium oxide, or the like. When aluminum oxide is formed by sputtering, oxygen is supplied to the insulator 102A. The oxygen supplied to the insulator 102A is supplied to the semiconductor 151. As a result, the semiconductor 1 In the region 151a formed after 51, the resistance can be prevented from decreasing.

[0204] Other materials that can be used for the insulator 102 include the insulator 10 described in the manufacturing method example 1. Please refer to the description in 2.

[0205] Incidentally, when a back gate is provided in a cell transistor of a semiconductor device, as shown in FIG. Instead of (A) and (B), the process shown in FIG. 37 is carried out. The insulating material 102 is formed on the surface of the opening 191, and the conductor 13 is formed on the opening 191 so as to fill the remaining opening 191. 4 is deposited.

[0206] The insulator 102 shown in FIG. 37 may have a laminated structure made up of multiple insulators ( (Not shown in the figure.) As a structure of a laminate made of a plurality of insulators, for example, the structure shown in FIG. 36(B) can be used. A laminated structure of solid insulator 102A and insulator 102B may also be used.

[0207] In this case, the conductor 134 functions as the wiring BGL shown in FIGS.

[0208] The materials applicable to the conductor 134 include the materials described in the Example of Manufacturing Method 1 for the conductor 134. Please take into consideration the following.

[0209] In the next step, as shown in FIG. 38(A), a resist mask pattern is applied to the laminate 100. The slits 192 are formed by a process such as forming and etching. Instead of a lit, an opening may be formed.

[0210] For details on the formation of the resist mask and the etching process, please refer to the explanation of FIG. 8(B). To pour drinks.

[0211] Then, as shown in FIG. 38(B), the slits 192 are formed by etching or the like. The sacrificial layers 141A and 141B are removed from the side surfaces, and the laminate 100 is provided with the recesses 197A and 197B. A recess 197B is formed.

[0212] The recesses 197A and 197B are formed by slipping the recesses 197A and 197B at the stage of the manufacturing process shown in FIG. 38(A). It may be possible to form it together with To 192.

[0213] Furthermore, as shown in FIG. 39(A), a recess 197A, a recess The conductor 137 in 197B is removed. This exposes the semiconductor 151, and the conductive A conductive body 137a, a conductive body 137b, and a conductive body 137c are formed.

[0214] In the manufacturing process shown in FIG. 39(A), a slip is formed at the stage of the manufacturing process shown in FIG. It may be possible to form it together with To 192.

[0215] In the next step, as shown in FIG. 39(B), the step of FIG. 14(A) described in the Example of Fabrication Method 1 is repeated. In the same manner as the above process, impurities and oxygen are supplied to the semiconductor 151 through the slit 192. In FIG. 39(B), the impurity supply process 10 is performed on the region 151a of the semiconductor 151. This process is performed on the region 151a of the semiconductor 151. This will function as the channel formation region of the cell transistor CTr. As a result, the low resistance region 151d that was present in the region 151a disappears.

[0216] It is also preferable to carry out a heat treatment during or after the treatment of FIG. 39(B). By this heat treatment, the semiconductor 151 is heated near the interface with the conductor 137. The components contained in the conductive material 137 are compound 161A, compound 161B, and compound 161C. That is, in the region 151b of the semiconductor 151, a low resistance region 161C is formed. Compounds 161A, 161B, and 161C are formed. Please refer to the description of Compound 161A, Compound 161B, and Compound 161C explained in Preparation Example 1. do.

[0217] In the next step, as shown in FIG. 40, the side surface (insulating The insulating body 101A to the insulating body 101C are provided with insulating bodies 101B, 101C ... 103 is deposited.

[0218] The materials applicable to the insulator 103 are the same as those described in the manufacturing method example 1. Please take into consideration the following.

[0219] In the next step, as shown in FIG. 41(A), the side surface of the slit 192 shown in FIG. In other words, the insulating material 111 is formed on the surface on which the insulating material 103 is formed. An edge 111 is formed.

[0220] The materials applicable to the insulator 111 are the same as those described in the manufacturing method example 1. Please take into consideration the following.

[0221] In the next step, as shown in FIG. 41(B), the side surface of the slit 192 shown in FIG. 41(A) is , and the insulator 104 is formed in the formed recess. An insulator 104 is formed on the surface.

[0222] The materials applicable to the insulator 104 include the materials described in the manufacturing method example 1. Please take into consideration the following.

[0223] In the next step, as shown in FIG. 42(A), the side surface of the slit 192 shown in FIG. 41(B) is The conductor 136 is formed in the recessed portion. A conductor 136 is formed on the surface.

[0224] The materials applicable to the conductor 136 include the materials described in the Example of Manufacturing Method 1. Please take into consideration the following.

[0225] In the next step, as shown in FIG. 42(B), a resist mask is formed and an etching process is performed. Therefore, the conductor 136 included in the slit 192 is removed so that the conductor 136 remains only in the recessed portion. The conductive material 136 is removed. This forms the conductive material 136a and the conductive material 136b. At this time, the insulator 111 may be removed to the extent that it is not exposed to the slit 192. Part of 04 may be removed.

[0226] For details on the formation of the resist mask and the etching process, please refer to the explanation of FIG. 8(B). To pour drinks.

[0227] The conductor 136a (conductor 136b) is a cell transistor shown in FIGS. It functions as the gate electrode of the transistor CTr and the wiring WL. In the region 181A (region 181B), the cell transistor CTr is formed.

[0228] In the next step, as shown in FIG. 43, the insulator 105 is formed so as to fill the slit 192. It is filmed.

[0229] The insulator 105 may be made of any of the materials applicable to the insulator 102 described above. .

[0230] As described above, by carrying out the steps shown in FIGS. 8(A) and 8(B) and FIGS. 35(A) to 43, In this way, the semiconductor device shown in FIG. 1A can be manufactured.

[0231] 44(A) and 44(B) show the semiconductor device shown in FIG. 43 along the dashed line C1-C2 and the dashed line C3-C4, respectively. 45(A) shows a top view taken along the dashed line C3-C4. 1 shows a top view of a semiconductor device in which a plurality of openings 191 are provided as an example. The top view is a top view of the semiconductor device taken along the dashed line C1-C2 in FIG. This is an exploded view of the semiconductor device shown in FIG. has a plurality of slits 192, and an opening 191 is provided between adjacent slits 192. As explained in FIG. 38, instead of the slit 192, an opening is formed. In FIG. 45(B), an opening 193 is provided instead of the slit 192. The insulators 103 to 105 and the insulator 111 are formed on the insulating film 193. The positions of the openings 193 are arranged along a line in one direction like the slits 192 in FIG. 45(A). Alternatively, the openings 193 may be arranged along rows in two or more different directions. The positions may be formed without following the above-mentioned regularity.

[0232] One embodiment of the present invention is not limited to the structural example of the semiconductor device illustrated in FIG. In some cases, depending on the situation, or as required, the semiconductor device shown in FIG. The configuration can be modified as needed.

[0233] For example, one embodiment of the present invention is a cell transistor as shown in FIG. A back gate may be provided in the transistor CTr. When manufacturing a semiconductor device, the step shown in FIG. 36(A) is carried out in the process of manufacturing FIG. 37 can be carried out instead of the step shown in FIG. By carrying out the steps shown in the above, the semiconductor device shown in FIG. 46 can be fabricated.

[0234] 47(A) and 47(B) show the semiconductor device shown in FIG. 46 along the dashed line C1-C. 2 shows a top view taken along the dashed line C3-C4. 47(A)(B) is a top view of the example shown in FIG. 4(A) and 4(B), a conductor 134 is formed inside an insulator 102.

[0235] Furthermore, for example, when a material having a metal oxide is used as the semiconductor 151, the following is obtained as shown in FIG. The semiconductor 151 can have a three-layer structure like the semiconductor device shown in FIG. The device has a three-layer structure of semiconductor 151, and in the process of manufacturing FIG. 35(B), the semiconductor 151 is made of semiconductor 152A, semiconductor 152B, The semiconductor 152C can be formed in sequence.

[0236] 49(A) and 49(B) show the semiconductor device shown in FIG. 48 along the dashed line C1-C. 2, a top view taken along the dashed line C3-C4. The semiconductor layer has a three-layer structure in which semiconductor 152A, semiconductor 152B, and semiconductor 152C are deposited in this order. Since this is an example, the top view shown in Figures 49(A) and 49(B) is the same as the top view shown in Figures 44(A) and 44(B). The semiconductor 151 has a three-layer structure.

[0237] The semiconductors 152A, 152B, and 152C are the same as those in Example 1 of Fabrication Method. Please refer to the description of the semiconductor 152A, the semiconductor 152B, and the semiconductor 152C. The effect of constructing the semiconductor device shown in 48 is also the same as that explained in Example 1 of Fabrication Method. Please refer to the description of Figure 22.

[0238] In addition, for example, in the semiconductor device shown in FIG. 43, the insulator 103 is formed on the surface on which the insulator 103 is formed. However, in one embodiment of the present invention, the charge The insulator 111 can be divided for each accumulation layer. After the process shown in (A), resist mask formation and etching are performed, and the above-mentioned The insulator 111 is formed only on the surface of the insulator 103 in the recess 196A and the recess 196B. 19 shows a process of removing the insulator 111 contained in the slit 192. Alternatively, depending on the situation, in the step of removing the insulator 111, as shown in FIG. 50(B), The area of ​​the insulator 103 exposed in the slit 192 may then be removed. By carrying out the same steps as those shown in FIG. 1(B) to FIG. 43, the semiconductor device shown in FIG. 51(A) can be obtained. The device can be configured.

[0239] 51(B) shows the semiconductor device shown in FIG. 51(A) along the dashed line C1-C2. The semiconductor device shown in FIG. 51(A) has a conductor 137a (conductor 137b). 7b, conductor 137c) in a region overlapping with region 151a of semiconductor 151. 51(B) shows a top view of the structure in which the insulator 111 is removed. The insulator 111 between the insulator 103 and the insulator 104 is not present. The top view of the dashed line B3-B4 shown in 51(A) is almost the same as that of FIG. 44(B). This may be the case.

[0240] Furthermore, for example, one aspect of the present invention is to improve the reliability of the cell transistor CTr. Even if the configuration of the gate electrode of the cell transistor CTr is changed from that shown in FIG. 52(A), (B) and 53(A) show an example of a method for manufacturing the semiconductor device. In FIG. 52(A), the side surface of the slit 192 and the recess 196 in FIG. A, a semiconductor 153 is formed on the surface of the insulator 104 formed in the recess 196B. There are.

[0241] The semiconductor 153 may be, for example, a material containing a metal oxide as described in the third embodiment. However, the materials that can be used for the semiconductor 153 are not limited to these. For example, materials other than metal oxides may be used as the semiconductor 153. For example, a conductor, an insulator, or the like may be used instead of the semiconductor 153.

[0242] In the next step, as shown in FIG. 52(B), a resist mask is formed and an etching process is performed. By this, the recesses 196A and 196B are formed so that the semiconductor 153 remains in a part of the recesses 196A and 196B. The semiconductor 153 in the remaining portion 196A, the recess 196B, and the semiconductor 153 included in the slit 192 The semiconductor 153 is then removed. This results in the formation of the semiconductor 153a and the semiconductor 153b. do.

[0243] After this, the same steps as those in FIG. 42(A) to FIG. 43 are carried out to obtain the result in FIG. 53(A) ) can be configured.

[0244] 53(B) shows the semiconductor device shown in FIG. 53(A) along the dashed line C3-C4. The semiconductor device shown in FIG. 53A has a region 151a of a semiconductor 151. In this case, a semiconductor 153a (or a semiconductor 153b) is disposed between the conductor 136a (or the conductor 136b) and the insulator 104. Since the semiconductor 153b) is included, the top view shown in FIG. The semiconductor 153b is included between the conductor 136b and the insulator 104. Incidentally, the top view taken along the dashed line C1-C2 in FIG. 53(A) is the same as FIG. 44(A). The configuration may be almost the same.

[0245] The effect of constructing the structure shown in FIG. 53(A) is the same as that of the structure shown in FIG. 26(A) described in the first example of the manufacturing method. ) (B), please refer to the description of Figure 27.

[0246] In addition, for example, in one embodiment of the present invention, instead of the insulator 111 used as a charge accumulation layer, Alternatively, a floating gate may be used. Figures 54(A) and 54(B) show an example of the manufacturing method. In FIG. 54(A), the recessed portion 197A and the recessed portion 197B in FIG. The conductor 138a and the conductor 138b are formed. As a method for forming b, the conductor 138a is formed in the slit 192, the recess 197A, and the recess 197B. A conductive material that will become the conductor 138b is formed, and then a resist mask is formed and etched. By a bonding process or the like, the conductor 138a and the conductor 138b are formed in a part of the recess 197A and the recess 197B, respectively. The conductive material is then removed so that the conductive material 138b remains. 43 to form the semiconductor device shown in FIG. 54(B). can be done.

[0247] 55 shows the top view of the semiconductor device taken along the dashed line C3-C4 in FIG. 54(B). The semiconductor device shown in FIG. 54B is a semiconductor device having a region 151a overlapping with the region 151b of the semiconductor 151. In the region where the insulator 103 and the insulator 104 are connected, a conductor 138a (conductor 138 Since the structure includes the insulator 103 and the insulator b), the top view shown in FIG. The structure includes a conductor 138b between the bodies 104. The top view taken along the dashed line C1-C2 shown in FIG. 51(B) is similar to the configuration shown in FIG. There is a match.

[0248] The conductor 138a and / or the conductor 138b may be, for example, the conductor 136 described above. However, the conductor 138a and / or the conductor 13 The materials applicable to the conductor 138a and / or the conductor 138b are not limited to these. As an alternative to 8b, an insulator, a semiconductor, etc. may be applicable.

[0249] Furthermore, for example, one aspect of the present invention is to provide a film thickness of the channel formation region of the cell transistor CTr. The structure can be made smaller. Figures 56(A) and 56(B) show a method for manufacturing the semiconductor device. In FIG. 56(A), the sacrificial layer 141A and the sacrificial layer 141B are shown. After removing the layer 141B, the surface of the semiconductor 151 is further removed by etching or the like. As a result, the thickness of the semiconductor 151 included in the region 151a is equal to the thickness of the semiconductor 151 included in the region 151b. This step is performed to form an impurity region on the surface of the semiconductor 151. This is effective when an impurity region is formed, and by carrying out this step, the impurity region is removed. As a result, the region 151a of the semiconductor 151 can be made to have a high resistance.

[0250] The thickness of the semiconductor 151 to be removed in the region 151a is, for example, The thickness of the deposited semiconductor 151 is 30 nm or more and 60 nm or less, or the thickness of the deposited semiconductor 151 is or 1 / 5 or more and 1 / 2 or less of the thickness of the insulator 103 to be formed thereafter. or less than 1 / 2, or 1 / 5 or less of the film thickness of the conductor 137a (conductor 137b, conductor 137c). The thickness of the deposited semiconductor 151 is at least 1 / 2 of the thickness of the upper portion. The thickness of the semiconductor 151 to be removed at 51a is set to be larger than the thickness of the semiconductor 151 to be removed at 51a. By carrying out the same steps as those from FIG. 43(B) to FIG. 43(B), the semiconductor device shown in FIG. 56(B) is obtained. can be configured.

[0251] 57(A) and 57(B) show the semiconductor device shown in FIG. 56(B) along the dashed line C 56(B) shows a top view of the semiconductor device shown in FIG. 56(B) along the dashed line C3-C4. The device is configured such that the thickness of the semiconductor 151 in the region 151a is greater than the thickness of the semiconductor 151 in the region 151b. Since the film thickness of the semiconductor 15 shown in the top view of FIG. 57(A) is thinner than the semiconductor 151 in the top view shown in FIG.

[0252] For example, the manufacturing order of the semiconductor device of one embodiment of the present invention may be the same as that shown in FIGS. Limited to the process order shown in Figures 35(A) to 36(A) and Figures 38(A) to 43 The steps shown in FIG. 58(A) may be interchanged to manufacture a semiconductor device. In FIG. 36(A), the step of forming the insulator 102 is not performed, and the sacrificial layer 141A is formed first. This shows the process of removing the sacrificial layer 141B. In this case, the size of the opening 191 is determined based on the size of the opening 191 formed in another manufacturing process. It is preferable to make it smaller than

[0253] In the next step, as shown in FIG. 58(A), the opening is formed in the same manner as in the step shown in FIG. 39(B). A process of supplying impurities and oxygen through the slit 191 and the slit 192 is performed (not shown). This forms a high resistance region on the surface of the exposed semiconductor 151 or in the vicinity of the surface. The side surface of the slit 192, the recessed portion formed, and the opening 191 can be insulated. By forming the insulating film 103, the structure shown in FIG. 58(B) is obtained. 43 to 44, the semiconductor device of FIG. 1A is constructed. It is possible.

[0254] A semiconductor capable of storing a large amount of data by the above-described Manufacturing Method Example 1 or Manufacturing Method Example 2 A device can be fabricated.

[0255] Here, a cross-sectional view of the semiconductor device shown in FIG. 17(B) (the circuit configuration of FIG. 1(A)) is shown in FIG. An example of the configuration of the cell array structure is shown in FIG. 59. Similarly, the semiconductor shown in FIG. The cross-sectional view of the semiconductor device (circuit configuration of FIG. 1(A)) is shown as a configuration example in which the semiconductor device has a cell array structure. 60. The area SD1 corresponds to the area SD1 shown in FIG. 59, as shown in FIG. 60, for a structure in which a conductor, which is a wiring WL, and an insulator are stacked, Then, openings are formed in the same manner as in the above-described Example 1 or Example 2 of Manufacturing Method. By carrying out this manufacturing process, the circuit configuration of FIG. 1(A) can be realized.

[0256] <Example of connection to peripheral circuits> The semiconductor device shown in Manufacturing Method Example 1 or Manufacturing Method Example 2 has a readout circuit and a processor in a lower layer. A peripheral circuit of the memory cell array, such as a recharge circuit, may be formed. The peripheral circuit is formed by forming a Si transistor on a silicon substrate or the like, and then In Example 1 or Manufacturing Method Example 2, a semiconductor device according to one embodiment of the present invention is formed on the peripheral circuit. In Figure 61(A), the peripheral circuit is made up of planar type Si transistors, and the upper layer 62A is a cross-sectional view of a semiconductor device according to one embodiment of the present invention formed in a peripheral circuit. The circuit is configured with a FIN type Si transistor, and the semiconductor device according to one embodiment of the present invention is mounted on the upper layer. It should be noted that the semiconductor device shown in FIG. 61(A) and FIG. 62(A) is an example. Therefore, the configuration of FIG. 17(B) is applied.

[0257] In FIG. 61(A) and FIG. 62(A), the Si transistors constituting the peripheral circuits are The element isolation layer 1701 is formed between a plurality of Si transistors. Conductors 1712 are formed as the source and drain of the Si transistor. The conductor 1730 is formed to extend in the channel width direction, and is connected to other Si transistors or It is connected to a conductor 1712 (not shown).

[0258] The substrate 1700 may be a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor Conductor substrates, compound semiconductor substrates made of silicon germanium, SOI substrates, etc. are used. It is possible.

[0259] The substrate 1700 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, or the like. Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base films, etc. Alternatively, a semiconductor element may be formed on a certain substrate, and then the semiconductor element may be transferred to another substrate. The conductive elements may be transposed. In FIG. 61(A) and FIG. 62(A), as an example, Figure 0 shows an example using a single crystal silicon wafer.

[0260] Here, the details of the Si transistor will be explained. The Si transistor is a planar type shown in FIG. 61(B) which is a cross section in the channel length direction. The Si transistor is shown in a cross section in the channel width direction. A channel forming region 1793, a low concentration impurity region 1794, and High concentration impurity region 1795 (collectively referred to as impurity region) and the impurity region A conductive region 1796 is provided in contact with the channel forming region 1793. a gate insulating film 1797, a gate electrode 1790 provided on the gate insulating film 1797, The gate electrode 1790 has a sidewall insulating layer 1798 and a sidewall insulating layer 1799 formed on its side. The conductive region 1796 may be made of metal silicide or the like.

[0261] The FIN type Si transistor shown in FIG. 62(A) has a cross section in the channel length direction. The FIN type Si transistor shown in FIG. 62(B) is a cross-sectional view in the channel width direction. In the Si transistor shown in FIGS. 62(A) and 62(B), the channel forming region 1793 is It has a convex shape, and the gate insulating film 1797 and the gate electrode 1790 are formed along the side and top surfaces of the convex shape. In this embodiment, when a part of a semiconductor substrate is processed to form a convex portion, However, a semiconductor layer having a convex shape may be formed by processing an SOI substrate.

[0262] A substrate 1700 is formed by a Si transistor, a conductor 1712, a conductor 1730, etc. An insulator 201 is formed on the upper layer of the formed circuit. A conductor 211 for electrical connection to the circuit is formed so as to be embedded. However, if the channel formation region of the cell transistor CTr contains a metal oxide, The insulating material 201 and the conductor 211 are made of an insulating material having barrier properties against hydrogen and the like. This is preferably achieved by connecting the Si transistor via the insulator 201 and / or the conductor 211. This is to suppress the diffusion of hydrogen from the cell transistor CTr to the cell transistor CTr.

[0263] The insulator 201 is made of a material that can be used for the insulators 101A to 101C described above. can be used.

[0264] The conductor 211 is made of, for example, tantalum nitride, which has a barrier property against hydrogen. In addition, by laminating tantalum nitride and highly conductive tungsten, This can suppress hydrogen diffusion from Si transistors while maintaining the overall conductivity. .

[0265] The reference numerals shown in Figures 62(A) and 62(B) are the same as those shown in Figures 61(A) and 61(B). .

[0266] It should be noted that the insulators, conductors, semiconductors, etc. disclosed in this specification and the like may be deposited by PVD (Physical Vapor Deposition). cal vapor deposition) method, CVD (Chemical Vapor Deposition) method, CVD (Chemical Vapor Deposition) method, The PVD method can be, for example, , sputtering method, resistance heating evaporation method, electron beam evaporation method, PLD (Pulsed Laser Deposition) In addition, the CVD method is a plasma In particular, the thermal CVD method can be used to form the film. For example, MOCVD (Metal Organic Chemical Vapor Dep. osition method and ALD (Atomic Layer Deposition) method. Examples include:

[0267] The thermal CVD method is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no further processing is required.

[0268] In the thermal CVD method, the source gas and oxidant are simultaneously fed into a chamber, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the material near or on the substrate under reduced pressure and depositing the material on the substrate. You may go.

[0269] In addition, in the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating this gas introduction sequence. For example, by switching each switching valve (also called high-speed valve), two or more types of The above source gases are supplied to the chamber in order, and the first An inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the raw material gas. The second source gas is introduced. When an inert gas is introduced at the same time, the inert gas is It acts as a carrier gas, and even if an inert gas is introduced at the same time as the second source gas is introduced, Alternatively, instead of introducing an inert gas, the first source gas may be discharged by vacuum evacuation. After that, a second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate to form a first thin film. The first thin layer is formed, and then reacts with the second source gas introduced later, and the second thin layer is formed on the first thin layer. The order of gas introduction is controlled until the desired thickness is reached. By repeating the above steps several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas introduction sequence is repeated. This is possible and is suitable for fabricating miniaturized FETs.

[0270] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It is possible to form various films such as metal films, semiconductor films, and inorganic insulating films. When forming a-Zn-O film, trimethylindium (In(CH3)3), trimethylindium (Tm(CH3)3) Using methylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) Furthermore, the present invention is not limited to these combinations, and trimethylgallium may be replaced with triethylgallium. Zinc (Ga(C2H5)3) can also be used, and diethylzinc ( Zn(C2H5)2) can also be used.

[0271] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl Hafnium amides (hafnium amides such as TDMAH and Hf[N(CH3)2]4) Two types of gases are used: the vaporized source gas and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamido)hafnium.

[0272] For example, when forming an aluminum oxide film using an ALD film forming device, A liquid containing a catalyst and an aluminum precursor compound (trimethylaluminum (TMA), Al(C) Two types of gases are used: vaporized H3)3) and H2O as an oxidizing agent. Other materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanediol), Onato), etc.

[0273] For example, when forming a silicon oxide film using a film forming device that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are removed. The adsorbate is reacted with the adsorbate.

[0274] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by sequentially introducing BH gas and BH gas. The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. SiH4 gas may be used instead of gas.

[0275] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced repeatedly to form a Ga After that, Zn(CH3)2 gas and O3 gas were introduced repeatedly to form an O layer. The order of these layers is not limited to this example. Mixed oxide layers such as In-Ga-O, In-Zn-O, and Ga-Zn-O are formed using It is also possible to use the HClO3 gas. Although H2O gas may be used, it is preferable to use O3 gas that does not contain H. Instead of (CH3)3 gas, In(C2H5)3 gas may be used. 3) Ga(C2H5)3 gas may be used instead of Zn(CH3)2 Gas may also be used.

[0276] Note that the respective configuration examples of the semiconductor device described in this embodiment mode may be combined with each other as appropriate. It can be done.

[0277] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0278] (Embodiment 2) In this embodiment mode, a memory device including the semiconductor device described in the above embodiment mode will be described. Reveal.

[0279] An example of the configuration of a memory device is shown in FIG. 63. The memory device 2600 includes a peripheral circuit 2601 and It has a memory cell array 2610. 2601 is a row decoder 2621 (row decoder), a word line driver circuit 2622 (Word Line Driver Cir.), bit line driver circuit 26 30 (Bit Line Driver Cir.), output circuit 2640 (Output Cir.), Control Logic Circuit 2660(Control Logic Ci r.).

[0280] The semiconductor device illustrated in FIGS. 1A and 1B described in the first embodiment includes a memory cell array 2610 can be applied.

[0281] The bit line driver circuit 2630 includes a column decoder 2631. der), precharge circuit 2632 (Precharge Cir.), sense amplifier 2633 (Sense Amp.), and a write circuit 2634 (Write Cir. The precharge circuit 2632 includes the wiring SL or the wiring SL described in Embodiment 1. BL (not shown in FIG. 63) to a predetermined potential. The amplifier 2633 converts the potential (or current) read from the memory cell MC into a data signal. The amplified data signal is then output to the output circuit. external to storage device 2600 as a digital data signal RDATA via path 2640. is output.

[0282] The storage device 2600 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and A high power supply voltage (VDD) for the circuit 2601, a high power supply voltage (VI L) is supplied.

[0283] The memory device 2600 also receives control signals (CE, WE, RE) and an address signal ADDR. The data signal WDATA is input from the outside. The address signal ADDR is input from the row decoder. 2621 and the column decoder 2631, and the data signal WDATA is input to the write circuit It is entered into 2634.

[0284] The control logic circuit 2660 processes external input signals (CE, WE, RE). It processes the signals to generate control signals for the row decoder 2621 and the column decoder 2631. , is the chip enable signal, WE is the write enable signal, and RE is the read enable signal. The control logic circuit 2660 processes this signal. The present invention is not limited to this, and other control signals may be input as required.

[0285] It should be noted that the above-mentioned circuits and signals can be appropriately selected or omitted as required.

[0286] In addition, a p-channel Si transistor and an oxide semiconductor (preferably A transistor containing an oxide containing In, Ga, and Zn in the channel formation region is used. By applying this to the storage device 2600, a small-sized storage device 2600 can be provided. It is possible to provide a storage device 2600 that can reduce power consumption. In particular, the Si transistor is a p-channel type By doing so, the manufacturing cost can be kept low.

[0287] The configuration example of this embodiment is not limited to the configuration of FIG. 63. For example, the peripheral circuit 26 01, for example, the precharge circuit 2632 or / and the sense amplifier 2633. The configuration may be changed as appropriate, for example, by providing it below the cell array 2610.

[0288] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0289] (Embodiment 3) In this embodiment, the channel formation region of the OS transistor used in the above embodiment is This section explains the metal oxides contained in these materials.

[0290] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, magnesium, etc. One or more of these may be included.

[0291] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, silicon, and titanium. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, Odium, hafnium, tantalum, tungsten, magnesium, etc. However, elements In some cases, M may be a combination of two or more of the above elements.

[0292] Next, using Figures 64(A), (B) and (C), the indium contained in the metal oxide according to the present invention will be described. The preferred range of the atomic ratio of element M to zinc will be explained. In (B) and (C), the atomic ratio of oxygen is not described. The atomic ratio terms of indium, element M, and zinc are [In], [M], and [ Zn].

[0293] In Figure 64(A)(B)(C), the dashed lines indicate [In]:[M]:[Zn]=(1+α ):(1-α):1 atomic ratio (-1≦α≦1), [In]:[M]:[Z n] = (1 + α):(1 - α):2, the atomic ratio of [In]:[M]:[Zn ]=(1+α):(1-α):3 atomic ratio, [In]:[M]:[Zn] = (1 + α): (1 - α): 4 atomic ratio, and [In]: [M]: [Z n] = (1 + α):(1 - α):5.

[0294] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=2:1:β is ]:[M]:[Zn]=1:1:β, the atomic ratio line, [In]:[M]:[Zn ]=1:2:β, and the atomic ratio of [In]:[M]:[Zn]=1:3:β. The atomic ratio of [In]:[M]:[Zn]=1:4:β Represents a line.

[0295] In addition, as shown in Figure 64(A)(B)(C), Metal oxides with an atomic ratio or a value close to this ratio tend to have a spinel-type crystal structure.

[0296] In addition, multiple phases may coexist in metal oxides (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is close to [In]:[M]:[Zn]=0:2:1, the spinel The two phases of the hexagonal crystal structure and the layered crystal structure tend to coexist. When [M]:[Zn] is close to 1:0:0, the bixbyite-type crystal structure and the layered structure When multiple phases coexist in a metal oxide, different crystal structures are formed. Grain boundaries may be formed between the crystal structures.

[0297] The region A shown in FIG. 64(A) is a region containing indium, element M, and zinc in the metal oxide. 1 shows an example of a preferable range of the atomic ratio.

[0298] By increasing the indium content of metal oxides, the carrier mobility of the metal oxides ( Therefore, metal oxides with a high indium content The carrier mobility is higher compared to metal oxides with a lower indium content.

[0299] On the other hand, when the content of indium and zinc in the metal oxide is low, the carrier mobility Therefore, the atomic ratio [In]:[M]:[Zn]=0:1:0 and its vicinity In the case of a near value (for example, region C shown in FIG. 64(C)), the insulating property is high.

[0300] Therefore, the metal oxide of one embodiment of the present invention has high carrier mobility and few crystal grain boundaries. It is preferable that the atomic ratio be that shown in region A in FIG. 64(A), which tends to form a layered structure that is not easily formed. I wish.

[0301] In particular, in the area B shown in FIG. 64(B), the CAAC (c-axis a It is easy to become an optically active (ligned crystalline)-OS, and has excellent carrier mobility. The resulting metal oxide is

[0302] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted and has a distortion. In this case, the direction of the lattice arrangement is changed between an area with a uniform lattice arrangement and another area with a uniform lattice arrangement. indicates the point where a change occurs.

[0303] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is not possible to confirm the presence of grain boundaries (also called grain boundaries). This is because the CAAC-OS has a crystalline structure in the ab-plane direction. The oxygen atoms are not densely packed, and the bond distance between atoms is shortened by the substitution of metal elements. This is thought to be because distortion can be tolerated by changing the thickness of the film.

[0304] CAAC-OS is a highly crystalline metal oxide. Since it is not possible to confirm the grain boundaries, the decrease in electron mobility due to the grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides is reduced by the incorporation of impurities and the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of metal oxides having CAAC-OS are stable. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0305] Region B is [In]:[M]:[Zn]=4:2:3 to 4.1 and its vicinity. Near values ​​include, for example, [In]:[M]:[Zn]=5:3:4 In addition, region B is [In]:[M]:[Zn]=5:1:6 and its neighboring values, and and [In]:[M]:[Zn]=5:1:7, and their neighboring values.

[0306] The properties of metal oxides are not uniquely determined by the atomic ratio. Even if the ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. When depositing a film of an oxide using a sputtering device, the atomic ratio may be different from the atomic ratio of the target. Also, depending on the substrate temperature during film formation, the film may be formed with [Zn] rather than the target [Zn]. The [Zn] of the film may be small. Therefore, the region shown is a region where the metal oxide has a specific characteristic. The boundary between region A and region C is not strict. stomach.

[0307] Next, we will discuss the configuration of CAC (Cloud-Aligned Composite)-OS. and explain.

[0308] In this specification, CAC represents an example of a function or material configuration, and CAAC (c-axis aligned crystal) is an example of a crystal structure. There are.

[0309] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconductor properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making the functions of the two complementary to each other, the switching function (On / Off) is realized. CAC-OS or CAC-metal oxide is given the function of In CAC-OS or CAC-metal oxide, By separating the functions, the functionality of both can be maximized.

[0310] In addition, CAC-OS or CAC-metal oxide is a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive region and the insulating region in the material are formed by nanoparticle layers. The conductive and insulating regions may be separated by a bell. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0311] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0312] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used for the channel region of a transistor. When the transistor is turned on, the current driving force is high, that is, the on-state current is large, and Therefore, a high field effect mobility can be obtained.

[0313] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0314] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0315] (Fourth embodiment) In this embodiment, the semiconductor device described in the above embodiment is used as a memory device. An example of applying this to the above will be explained with reference to FIG.

[0316] In FIG. 65(A), the semiconductor device explained in the above embodiment is applied to an electronic component as a memory device. The electronic component is a semiconductor package or an IC package. This electronic component is available in multiple standards and names depending on the terminal direction and terminal shape. Therefore, in this embodiment, an example of such a case will be described.

[0317] The semiconductor device including the transistors as described in the first embodiment is fabricated in the following steps: After going through the post-processing, multiple detachable parts are attached to the printed circuit board to complete the product.

[0318] The post-processing can be completed by going through the steps shown in Figure 65(A). Specifically, after the element substrate obtained in the previous process is completed (step STP1), (Step STP2) By thinning the substrate at this stage, the thickness of the substrate in the previous process can be reduced. This is to reduce warping and to make the parts smaller.

[0319] The back surface of the substrate is ground and a dicing process is carried out to separate the substrate into multiple chips (step Then, the separated chips are individually picked up and mounted on a lead frame. The die bonding process is carried out (step STP4). In the packaging process, the chip and lead frame are bonded using resin or tape. The appropriate method is selected depending on the product, such as die bonding. It may also be mounted on a poser and bonded.

[0320] In this embodiment, when an element is formed on one surface of the substrate, The surface of the substrate is referred to as the front surface, and the other surface of the substrate (the surface on which no elements are formed) is referred to as the back surface. Let's say.

[0321] Next, the leads of the lead frame and the electrodes on the chip are electrically connected with thin metal wires. Wire bonding is performed to connect the components effectively (step STP5). Wire bonding can be performed using wire or gold wire. Wire bonding can also be performed using ball bonding or , wedge bonding can be used.

[0322] The wire-bonded chip is then molded using epoxy resin or other materials. (Step STP6). The molding process fills the inside of the electronic components with resin. This reduces damage to the built-in circuitry and wires caused by external mechanical forces. This also reduces the deterioration of characteristics due to moisture and dust.

[0323] Next, the leads of the lead frame are plated, and then the leads are cut and shaped. (Step STP7). This plating process prevents the leads from rusting and will later be used on the printed circuit board. This allows for more reliable soldering when mounting the device on a circuit board.

[0324] Next, a printing process (marking) is performed on the surface of the package (step STP8). The electronic components are then completed (step STP1) through a final inspection process (step STP9). 0).

[0325] The electronic component described above may include the semiconductor device described in the above embodiment. Therefore, it is possible to realize an electronic component with excellent reliability.

[0326] A perspective view of the completed electronic component is shown in Figure 65(B). As an example of a component, a perspective schematic diagram of a QFP (Quad Flat Package) is shown below. The electronic component 4700 shown in FIG. 65(B) has leads 4701 and a circuit section 4703. The electronic component 4700 shown in FIG. 65(B) is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components 4700 are combined together, and each is mounted on a printed circuit board. By electrically connecting it to the 4702, it can be installed inside an electronic device. The circuit board 4704 is provided inside an electronic device or the like.

[0327] Note that one embodiment of the present invention is not limited to the shape of the electronic component 4700 described above. The element substrate according to one aspect of the present invention is also included in the present invention. This also includes the element substrate in which the back surface of the substrate in step STP2 has been ground. The element substrate in one embodiment also includes an element substrate that has been subjected to the dicing process in step STP3. For example, a semiconductor wafer 4800 shown in Fig. 65(C) corresponds to the element substrate. A semiconductor wafer 4800 has a plurality of circuit portions 4802 formed on the upper surface of the wafer 4801. On the upper surface of the wafer 4801, the area where the circuit section 4802 is not present is a space. A part of the spacing 4803 is used as a dicing area.

[0328] Dicing is performed along the scribe lines SCL1 and SC indicated by the dashed lines. This is done along L2 (sometimes called the dicing line or cutting line). Spacing 4803 has multiple scribe lines to facilitate the dicing process. SCL1 is set to be parallel, and multiple scribe lines SCL2 are set to be parallel. The scribe line SCL1 and the scribe line SCL2 are set perpendicular to each other. It is preferable that:

[0329] By carrying out the dicing process, a chip 4800a as shown in FIG. 65(D) is obtained. Chip 4800a can be cut from wafer 4801a. , a circuit portion 4802, and spacing 4803a. In this case, it is preferable to make the adjacent circuit portion 4802 as small as possible. The width of the spacing 4803 between may be approximately equal to the scribe margin of the scribe line SCL1 or the scribe margin of the scribe line SCL2. It suffices that the length is approximately equal.

[0330] Note that the shape of the element substrate in one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 65(C). For example, a rectangular semiconductor wafer 4810 shown in FIG. 65(E) may be used. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element. Note that the shape of the element substrate in one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 65(C). For example, a rectangular semiconductor wafer 4810 shown in FIG. 65(E) may be used. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element. Note that the shape of the element substrate in one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 65(C). For example, a rectangular semiconductor wafer 4810 shown in FIG. 65(E) may be used. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element. Note that the shape of the element substrate in one aspect of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in FIG. 65(C). For example, a rectangular semiconductor wafer 4810 shown in FIG. 65(E) may be used. The shape of the element substrate can be appropriately changed according to the element manufacturing process and the apparatus for manufacturing the element.

[0331] Note that the present embodiment can be appropriately combined with other embodiments described in this specification. Note that the present embodiment can be appropriately combined with other embodiments described in this specification.

[0332] (Embodiment 5) In this embodiment, a CPU including the semiconductor device of the above embodiment will be described. In this embodiment, a CPU including the semiconductor device of the above embodiment will be described.

[0333] FIG. 66 is a block diagram showing an example of the configuration of a CPU using a part of the semiconductor device described in Embodiment 1. FIG. 66 is a block diagram showing an example of the configuration of a CPU using a part of the semiconductor device described in Embodiment 1.

[0334] The CPU shown in FIG. 66 includes an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F) on a substrate 1190. The substrate 1190 is a semiconductor substrate, an SOI substrate, FIG. 66 is a block diagram showing an example of the configuration of a CPU using a part of the semiconductor device described in Embodiment 1. FIG. 66 is a block diagram showing an example of the configuration of a CPU using a part of the semiconductor device described in Embodiment 1. FIG. 66 is a block diagram showing an example of the configuration of a CPU using a part of the semiconductor device described in Embodiment 1. FIG. 66 is a block diagram showing an example of the configuration of a CPU using a part of the semiconductor device described in Embodiment 1. FIG. 66 is a block diagram showing an example of the configuration of a CPU using a part of the semiconductor device described in Embodiment 1. The ROM 1199 and the ROM interface 1189 are It may be provided on a separate chip. Of course, the CPU shown in FIG. 66 is a simplified version of the configuration. This is just one example, and actual CPUs have a wide variety of configurations depending on their uses. For example, , the configuration including the CPU or arithmetic circuit shown in FIG. 66 is considered as one core, and , each core can be configured to operate in parallel, i.e., like a GPU. In addition, the number of bits that a CPU can handle in its internal arithmetic circuit and data bus is, for example, 8 bits, 16 bits, It can be 32-bit, 64-bit, etc.

[0335] The instructions input to the CPU via the bus interface 1198 are The signal is input to the decoder 1193, decoded, and then passed to the ALU controller 1192, Interrupt controller 1194, register controller 1197, timing controller It is entered into La1195.

[0336] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal to trigger the program of the CPU. During program execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and master. The register controller 1197 determines the address of the register 1196 and processes it accordingly. Generates an address and reads or writes register 1196 depending on the CPU state. .

[0337] The timing controller 1195 also includes the ALU 1191 and the ALU controller 11 92, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0338] In the CPU shown in FIG. 66, a memory cell is provided in the register 1196. The transistor described in the above embodiment can be used as the memory cell of the memory cell 1196. Cut.

[0339] In the CPU shown in FIG. 66, the register controller 1197 In accordance with the instruction of the register 1196, the holding operation is selected. In the memory cell of 196, data is held by a flip-flop or Select whether to hold data using a flip-flop. When this is selected, the power supply voltage is supplied to the memory cell in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor The supply of the power supply voltage to the memory cells in the register 1196 can be stopped. do.

[0340] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0341] (Embodiment 6) A memory card (e.g., an SD card) that can be equipped with the storage device of the above embodiment , USB (Universal Serial Bus) memory, SSD (Solid This can be applied to various removable storage devices such as a removable storage device (e.g., a removable storage device for a hard disk drive ... In the embodiment, some configuration examples of removable storage devices will be explained with reference to FIG. Reveal.

[0342] 67(A) is a schematic diagram of a USB memory. The USB memory 5100 is , a cap 5102, a USB connector 5103, and a substrate 5104. are housed in a housing 5101. A substrate 5104 includes a memory device and a drive circuit for the memory device. For example, the substrate 5104 is provided with a memory chip 5105, a controller The memory chip 5105 is the same as that in the second embodiment. The memory cell array 2610, the word line driver circuit 2622, and the row decoder 26 21, sense amplifier 2633, precharge circuit 2632, column decoder 2631, etc. The controller chip 5106 specifically includes a processor, a work memory, and The memory chip 5105 and the controller chip are The circuit configuration of each of the chips 5106 is not limited to the above description, but may be changed depending on the situation or occasion. For example, the word line driver circuit 2622, Row decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder The memory chip 5105 is not equipped with the controller 2631, but with the controller chip 5106. The USB connector 5103 may be an interface for connecting to an external device. It functions as a

[0343] Figure 67(B) is a schematic diagram of the external appearance of an SD card, and Figure 67(C) is a schematic diagram of the internal structure of an SD card. The SD card 5110 is a schematic diagram of the structure. The SD card 5110 includes a housing 5111, a connector 5112, and a board. A connector 5112 serves as an interface for connecting to an external device. The board 5113 is housed in a housing 5111. The board 5113 has a memory device. For example, the substrate 5113 is provided with a memory chip. The chip 5114 and controller chip 5115 are installed. 4 includes the memory cell array 2610 and the word line driver circuit 26 described in the second embodiment. 22, row decoder 2621, sense amplifier 2633, precharge circuit 2632, color The controller chip 5115 includes a processor It incorporates a processor, work memory, ECC circuit, etc. The circuit configuration of the controller chip 5115 is not limited to the above description, and may vary depending on the situation. The circuit configuration may be changed accordingly or in some cases. For example, the word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 263 2. The column decoder 2631 is not located on the memory chip 5114 but on the controller chip 511. 5 may be incorporated.

[0344] By providing a memory chip 5114 on the back side of the substrate 5113, the SD card 5110 In addition, a wireless chip having a wireless communication function can be mounted on the substrate 5113. This allows wireless communication between an external device and the SD card 5110. This allows data to be read from and written to the memory chip 5114.

[0345] Figure 67(D) is a schematic diagram of the external appearance of the SSD, and Figure 67(E) is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a board 5153. A connector 5152 functions as an interface for connecting to an external device. The board 5153 is housed in the housing 5151. The board 5153 includes a memory device and a For example, the substrate 5153 includes a memory chip 5154. , memory chip 5155, and controller chip 5156 are installed. The chip 5154 includes the memory cell array 2610 and the word line driver 2610 described in the second embodiment. a buffer circuit 2622, a row decoder 2621, a sense amplifier 2633, a precharge circuit 26 32, column decoder 2631, etc. are built in. There is also a memory card on the back side of the board 5153. By adding a chip 5154, the capacity of the SSD 5150 can be increased. The chip 5155 has a built-in working memory. For example, the memory chip 5155 has The controller chip 5156 includes a processor, an E CC circuits and other circuits are built in. The circuit configurations of the controller chip 5115 and the controller chip 5116 are not limited to those described above. Depending on the situation or circumstances, the circuit configuration may be changed as appropriate. The controller chip 5156 may also be provided with a memory that functions as a work memory.

[0346] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0347] (Embodiment 7) In this embodiment mode, the semiconductor device or memory device described in the above embodiment mode can be applied. An example of such an electronic device will be described below.

[0348] <Notebook personal computer> The semiconductor device or memory device according to one embodiment of the present invention is provided in a notebook personal computer. FIG. 68(A) shows a notebook personal computer, which has a housing 540 1, a display unit 5402, a keyboard 5403, a pointing device 5404, etc. .

[0349] <Smartwatch> The semiconductor device or memory device according to one embodiment of the present invention can be included in a wearable device. FIG. 68(B) shows a smart watch, which is a type of wearable terminal, and the housing 590 1, a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, etc. In addition, a display device having a function as a position input device is used for the display unit 5902. The function as a position input device may be realized by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by using a photo sensor. It can also be added by providing a photoelectric conversion element, also called In addition, the operation button 5903 is a power switch to start the smartwatch, Buttons for operating the touch screen application, volume adjustment button, or display 5902 It can be equipped with either a light or a switch to turn it off. ) shows two operation buttons 5903, The number of operation buttons that the watch has is not limited to this. It also functions as a crown for setting the time on the smartwatch. In addition to setting the time, it is also an input interface for operating smartwatch applications. It may be used as a base for the smart watch shown in Figure 68(B). However, the present invention is not limited to this and may be applied to any device having an operator 5904. It may be configured not to do so.

[0350] <Video camera> The semiconductor device or memory device according to one embodiment of the present invention can be provided in a video camera. FIG. 68(C) shows a video camera, which includes a first housing 5801, a second housing 5802, and a display unit 58 03, operation keys 5804, a lens 5805, a connection part 5806, etc. The lens 5805 is provided in the first housing 5801, and the display unit 5803 is provided in the second housing. The first housing 5801 and the second housing 5802 are connected by a connection part. The first housing 5801 and the second housing 5802 are connected by a The image on the display unit 5803 can be changed by the connection unit 5806. The switch is configured to switch according to the angle between the first housing 5801 and the second housing 5802. That's fine.

[0351] <Mobile phone> The semiconductor device or memory device according to one embodiment of the present invention can be included in a mobile phone. 8(D) is a mobile phone having an information terminal function, and includes a housing 5501, a display unit 5502, The display unit 550 includes a microphone 5503, a speaker 5504, and an operation button 5505. 2, a display device with a function as a position input device may be used. The function as a position input device can be added by providing a touch panel to the display device. Alternatively, the function as a position input device can be realized by using a photoelectric conversion element also known as a photosensor. It can also be added by providing a control button 55 in the pixel section of the display device. 05. Power switch to start the mobile phone, buttons to operate the mobile phone's applications , a volume control button, or a switch for turning on or off the display portion 5502. It can be equipped with either

[0352] In addition, the mobile phone shown in FIG. 68(D) has two operation buttons 5505. However, the number of operation buttons on a mobile phone is not limited to this. The mobile phone shown in Figure 68(D) is equipped with a light-emitting device for use as a flashlight or illumination. The configuration may include a device.

[0353] <Television equipment> The semiconductor device or memory device of one embodiment of the present invention can be applied to a television set. FIG. 68(E) is a perspective view showing a television device. The television device is A body 9000, a display unit 9001, a speaker 9003, operation keys 9005 (power switch, or operation switch), connection terminal 9006, sensor 9007 (force, displacement, position, speed , acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, Measure electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared The storage device according to one embodiment of the present invention includes a television device. The television device may be, for example, 50 inches or more, or 100 inches. It is possible to incorporate more than one display unit 9001.

[0354] <Mobile> The semiconductor device or memory device according to one embodiment of the present invention is suitable for use in the vicinity of a driver's seat of a vehicle, which is a moving object. It can also be used.

[0355] For example, FIG. 68(F) is a diagram showing the area around the windshield inside the interior of a car. In FIG. 68(F), a display panel 5701 and a display panel 5702 are attached to the dashboard. 702, a display panel 5703, and a display panel 5704 attached to the pillar are also shown. are.

[0356] The display panels 5701 to 5703 display navigation information, a speedometer, and tachometer, mileage, fuel level, gear status, air conditioning settings, and various other information. In addition, the display items and layout displayed on the display panel can be It can be changed as needed to suit the user's preferences, improving the design. The display panels 5701 to 5703 can also be used as lighting devices. be.

[0357] The display panel 5704 displays an image captured by an imaging means provided on the vehicle body. This allows the driver to compensate for the blind spot (blind spot) that is blocked by the pillar. By displaying images from the provided imaging means, blind spots can be compensated for and safety can be improved. In addition, by projecting images that complement the invisible parts, it is possible to make the sense of incongruity appear more natural. The display panel 5704 can also be used as a lighting device. can.

[0358] The semiconductor device or memory device of one embodiment of the present invention can be used for, for example, the display panels 5701 to 5703. A frame that temporarily stores image data used when displaying an image on the panel 5704. It is used for system memory and storage devices that store programs that operate systems in mobile devices. You can be there.

[0359] Although not shown, the electronic devices shown in Figures 68(A)(B)(E)(F) are The configuration may include a microphone and a speaker. The device can be equipped with a voice input function.

[0360] Although not shown, the electronic devices shown in Figures 68(A), (B), (D) to (F) , and may have a camera.

[0361] Although not shown, the electronic devices shown in Figures 68(A) to 68(F) have a built-in Sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetic, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration The sensor may have a function to measure movement, smell, infrared rays, etc. In addition, the mobile phone shown in FIG. 68(D) is equipped with a sensor that detects tilt, such as a gyro or an acceleration sensor. By providing a detection device having a sensor, the orientation of the mobile phone (the mobile phone in the vertical direction) can be detected. The screen display of the display unit 5502 is adjusted to match the orientation of the mobile phone. It is possible to automatically switch depending on the

[0362] Although not shown, the electronic devices shown in Figures 68(A) to 68(F) can be used to identify fingerprints, veins, The configuration may include a device for acquiring biometric information such as an iris or a voiceprint. By using this, an electronic device with a biometric authentication function can be realized.

[0363] In addition, flexible substrates are used as the display units of the electronic devices shown in FIGS. Specifically, the display unit may be formed by mounting transistors, capacitors, etc., on a flexible substrate. By applying this configuration, Not only flat-surfaced housings like those shown in Figures 68(A) to 68(F), but also curved housings are available. It is possible to realize an electronic device having a housing with a surface.

[0364] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0365] (Notes regarding the present specification) The following additional notes will be given regarding the description of each component in the above embodiment.

[0366] <Additional Notes Regarding One Aspect of the Present Invention Described in the Embodiments> The configurations shown in each embodiment may be appropriately combined with the configurations shown in other embodiments to realize the present invention. In addition, in one embodiment, multiple configuration examples may be shown. In this case, the configuration examples can be appropriately combined with each other.

[0367] It should be noted that the contents (or even a part of the contents) described in one embodiment may be used in the implementation of the embodiment. Another content (or part of the content) described in the embodiment and one or more other embodiments The content described (or a part of the content) is applied to, combined with, or at least one of the contents. or replacement, etc.

[0368] The contents described in the embodiments are explained using various drawings in each embodiment. This refers to the content stated in the specification or the content stated using the text in the specification.

[0369] In addition, a drawing (or a part thereof) described in one embodiment may be replaced with another part of the drawing. In the embodiment, another figure (or a part thereof) and one or more other embodiments may be used. At least one of the drawings (or a part thereof) described in the embodiment is combined with By adding more, more figures can be constructed.

[0370] <Note on ordinal numbers> In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, the number of components is not limited. The order of the components is not limited to the above. A component referred to as "first" in the specification may be used in other embodiments or in the claims. In addition, for example, in the implementation of this specification, etc. A component referred to as "first" in one embodiment may be used in other embodiments or in a patent. It may be omitted in the claims.

[0371] <Notes regarding the description of the drawings> The embodiments are described with reference to the drawings. However, the embodiments may be implemented in many different ways. It is possible to carry out the invention in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the embodiments. In the configuration, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. It will be used throughout and repeated explanations will be omitted.

[0372] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship is used for convenience in explaining the relationship with reference to the drawings. , and change appropriately depending on the direction in which each configuration is depicted. The above description is not limited to the above, and can be rephrased appropriately depending on the situation. For example, The representation of "insulator on top of conductor" requires rotating the orientation of the drawing by 180 degrees. This can be rephrased as "an insulator on the underside of a conductor."

[0373] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below and directly connected to each other. For example, if the expression is "electrode B on insulating layer A," The electrode B does not need to be formed directly on the insulating layer A, and the insulating layer A and the electrode B This does not exclude the inclusion of other components in between.

[0374] In addition, in the drawings, the size, layer thickness, and area are shown at arbitrary scales for the convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the purpose of clarity, and are not limited to the shapes or values ​​shown in the drawings. fluctuations in signal, voltage, or current due to noise, or signal due to timing deviations These may include variations in signal, voltage, or current.

[0375] In addition, in the drawings, some components are shown in perspective views and the like in order to clarify the drawings. The description of the element may be omitted.

[0376] In addition, in the drawings, the same elements or elements having similar functions, elements made of the same material, or In some cases, the same reference numerals may be used to designate elements that are formed at the same time, and repeated explanations thereof will be omitted. It may be omitted.

[0377] <Notes regarding possible paraphrases> In this specification and the like, when describing the connection relationship of a transistor, The first electrode or the first terminal is referred to as the "source or drain" (or the first electrode or the first terminal). The other of the source and drain is referred to as the "other of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because the names of the source and drain of a transistor change depending on the operating conditions. In this case, the term source (drain) terminal, source (drain) electrode, etc. may be used appropriately depending on the situation. In this specification, the two terminals other than the gate are referred to as the first terminal and the second terminal. In this specification, etc., The channel formation region is the region where the channel is formed, and this region is formed by applying a potential to the gate. A region is formed to allow current to flow between the source and drain.

[0378] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0379] Furthermore, when the transistor described in this specification has two or more gates (this configuration These gates are called the first gate and the second gate. It is sometimes called a front gate or a back gate. " can be simply interchanged with the word "gate." The phrase "backgate" is interchangeable with the phrase "gate." The bottom gate is a gate electrode formed on a lower side than the channel formation region during the manufacture of a transistor. The term "top gate" refers to a terminal that is formed first during the manufacturing of a transistor. The terminal is formed after the channel forming region.

[0380] In addition, the terms "electrode" and "wiring" used in this specification and the like refer to these components functionally. This is not a limitation. For example, an "electrode" may be used as part of a "wiring." , and vice versa. Furthermore, the terms "electrode" and "wiring" may be used interchangeably with "electrodes" and "wiring." This also includes cases where the wiring is formed integrally.

[0381] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. It is the potential difference from the reference potential. For example, the reference potential is the ground potential (earth potential). If we use the term "potential"), we can translate voltage into potential. Ground potential is not necessarily 0V. It does not necessarily mean that the potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0382] In this specification, the terms "film" and "layer" may be used in some cases or depending on the situation. For example, the term "conductive layer" can be used interchangeably with "conductive layer" It may be possible to change the term to "insulating film" or, for example, The term may be changed to "insulating layer" in some cases. Alternatively, depending on the situation, words such as "film" and "layer" may be replaced with other terms. For example, the term "conductive layer" or "conductive film" can be changed to "conductor." In some cases, it may be possible to change the term to, for example, "insulating layer" or "insulating film." It may be possible to change the term to "insulator."

[0383] In this specification, terms such as "wiring," "signal line," and "power line" may be used in some cases. For example, "wiring" and "wiring" can be interchangeable. In some cases, it may be possible to change the term "signal line" to "signal line." It may be possible to change the term "wiring" to a term such as "power line." , and vice versa, terms such as "signal line" and "power line" will be changed to the term "wiring." It may be possible to change terms such as "power line" to terms such as "signal line". The reverse is also true, and terms such as "signal line" may be used interchangeably with "power line" In some cases, it may be possible to change the term to "potential" applied to the wiring. Changing the term to "signal" or similar, as the case may be, or depending on the situation. And vice versa, terms such as "signal" may be used in conjunction with "potential." It may be possible to change it to a different word.

[0384] <Notes on definitions of terms> The following provides definitions of terms used in the above embodiments.

[0385] <<About impurities in semiconductors>> The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor layer. Elements with less than 0.1 atomic % are impurities. The formation of DOS (Density of States) and the carrier mobility The semiconductor may become an oxide semiconductor, and the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1 and Group 2. There are elements, group 13 elements, group 14 elements, group 15 elements, and transition metals other than the main component. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, for example, impurities such as hydrogen can be mixed in. In addition, if the semiconductor is a silicon layer, the characteristics of the semiconductor may be affected. The impurities that change the value of the valence band include, for example, oxygen, group 1 elements excluding hydrogen, group 2 elements, and group 1 elements. These include Group 3 elements and Group 15 elements.

[0386] <<About the switch>> In this specification, a switch is a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It is a device that has the function of controlling whether or not current flows by entering a state where it is in a switched state. A switch is a device that has the function of selecting and switching the path through which current flows.

[0387] For example, an electrical switch or a mechanical switch can be used. The switch is not limited to a specific one as long as it can control the current.

[0388] An example of an electrical switch is a transistor (e.g., a bipolar transistor, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die MIS (Metal Insulator Semiconductor) die diode-connected transistors, etc.), or logic circuits that combine these There is.

[0389] When a transistor is used as a switch, the "conduction state" of the transistor is The state in which the source and drain electrodes of a transistor can be considered to be electrically shorted is called Also, the "non-conducting state" of a transistor means that the source electrode and drain electrode of the transistor are This refers to a state in which the electrodes can be considered to be electrically disconnected. When the transistor is operated as a transistor having a polarity (conductivity type), there is no particular limitation.

[0390] An example of a mechanical switch is a digital micromirror device (DMD). In 2013, a switch using MEMS (microelectromechanical systems) technology was developed. The switch has a mechanically movable electrode, and when the electrode moves, Therefore, the device operates by controlling conduction and non-conduction.

[0391] <<About connection>> In this specification, when it is stated that X and Y are connected, it means that X and Y are electrically connected. There are cases where X and Y are electrically connected, where X and Y are functionally connected, and where X and Y are directly connected. Therefore, a predetermined connection relationship, for example, a diagram or It is not limited to the connection relationships shown in the text, but also includes connection relationships other than those shown in the drawings or text. It shall be.

[0392] X, Y, etc. used here refer to objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, etc.). , conductive film, layer, etc.).

[0393] An example of the case where X and Y are electrically connected is The elements that function as One or more diodes, display elements, light-emitting elements, loads, etc.) are connected between X and Y. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. It has a function to control whether or not water is flushed.

[0394] An example of a case where X and Y are functionally connected is when the functional connection between X and Y is possible. Circuits that perform functions (e.g., logic circuits (inverters, NAND circuits, NOR circuits, etc.)), signal Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, step-down circuits, etc.), level shifter circuits that change the signal potential level, etc. ), voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X X and Y are said to be functionally connected if X is transmitted to Y.

[0395] When it is explicitly stated that X and Y are electrically connected, it means that X and Y are electrically connected. When X and Y are electrically connected (i.e., when another element or circuit is inserted between X and Y) X and Y are functionally connected (i.e., there is no connection between X and Y) When X and Y are connected directly, the two are functionally connected via another circuit. (That is, when X and Y are connected without any other element or circuit between them) In other words, when it is explicitly stated that something is electrically connected, it is not simply is the same as if it were expressly stated only that it is connected to

[0396] For example, if the source (or first terminal, etc.) of the transistor is connected to the The drain (or second terminal, etc.) of the transistor is electrically connected to X. It may be electrically connected to Y through Z2 (or not), or the source of the transistor may be The first terminal (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When a part of Z2 is directly connected to Y, and another part of Z2 is directly connected to Y, it can be expressed as follows: It can be manifested.

[0397] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" 2 terminals) are electrically connected to each other, and X, the source (or The first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and the Y are electrically connected in this order. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Or, "X is the source (or first terminal, etc.) of the transistor. ) and the drain (or second terminal, etc.) of the transistor Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor , Y are provided in this connection order." By using this expression, the order of connections in the circuit configuration can be specified. A distinction is made between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above expressions. Here, X, Y, Z1, and Z2 are the coordinates of the object (for example, the device, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0398] Note that the circuit diagram shows independent components as if they are electrically connected to each other. Even if one component has the functions of multiple components, For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the present invention has the functions of both the electrode and the electrode. Electrical connection means that one conductive film has the functions of multiple components. This case will also be included in that category.

[0399] <<About parallel and perpendicular>> In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Explanation of symbols]

[0400] MC[1]: memory cell, MC[2]: memory cell, MC[n]: memory cell, MC[1 ,1]: memory cell, MC[j,1]: memory cell, MC[n,1]: memory cell, MC [1,i]: memory cell, MC[j,i]: memory cell, MC[n,i]: memory cell, MC[1,m]: memory cell, MC[j,m]: memory cell, MC[n,m]: memory cell WL: wiring, WL[1]: wiring, WL[i]: wiring, WL[n]: wiring, BL: wiring , SL:Wiring, BSL:Wiring, BSL[1]:Wiring, BSL[i]:Wiring, BSL[m] : wiring, SSL: wiring, SSL[1]: wiring, SSL[i]: wiring, SSL[m]: wiring , BGL: Wiring, BGL[1]: Wiring, BGL[i]: Wiring, BGL[m]: Wiring, CT r: cell transistor, BTr: transistor, STr: transistor, PG: conductor, ER: wiring, HL: area, AR: area, TM: area, SCL1: scribe line, SC L2: scribe line, SD1: area, SD2: area, T10: time, T11: time, T12: Time, T13: Time, T20: Time, T21: Time, T22: Time, T23: Time Time, T24: Time, T25: Time, T30: Time, T31: Time, T32: Time, T33 :Time, T40:Time, T41:Time, T42:Time, T43:Time, T44:Time, T 45: time, 10: supply process, 100: stack, 100A: stack, 101A: insulator, 101B: insulator, 101C: insulator, 102: insulator, 102A: insulator, 102B: Insulator, 103: Insulator, 104: Insulator, 105: Insulator, 107A: Insulator, 107 B: insulator, 107C: insulator, 111: insulator, 134: conductor, 135: conductor, 1 35a: conductor, 135b: conductor, 135c: conductor, 136: conductor, 136a: conductor Conductor, 136b: Conductor, 137: Conductor, 137a: Conductor, 137b: Conductor, 13 7c: conductor, 138a: conductor, 138b: conductor, 141A: sacrificial layer, 141B: sacrificial layer sacrificial layer, 151: semiconductor, 151a: region, 151b: region, 151e: region, 151d: Area, 152A: semiconductor, 152B: semiconductor, 152C: semiconductor, 153: semiconductor, 15 3a: Semiconductor, 153b: Semiconductor, 161A: Compound, 161B: Compound, 161C: Chemical compound, 181A: area, 181B: area, 191: opening, 192: slit, 193: Opening, 195A: recess, 195B: recess, 195C: recess, 196A: recess, 196B : recess, 197A: recess, 197B: recess, 201: insulator, 211: conductor, 1189 :ROM interface, 1190:board, 1191:ALU, 1192:ALU controller controller, 1193: instruction decoder, 1194: interrupt controller 1195: timing controller, 1196: register, 1197: register controller Controller, 1198: Bus interface, 1199: ROM, 1700: Board, 17 01: element isolation layer, 1712: conductor, 1730: conductor, 1790: gate electrode, 17 92: well, 1793: channel formation region, 1794: low concentration impurity region, 1795: Highly doped impurity region, 1796: conductive region, 1797: gate insulating film, 1798: sidewall insulating film Edge layer, 1799: Sidewall insulating layer, 2600: Memory device, 2601: Peripheral circuit, 2610: Memory memory cell array, 2621: row decoder, 2622: word line driver circuit, 2630 : bit line driver circuit, 2631: column decoder, 2632: precharge circuit, 2 633: Sense amplifier, 2634: Write circuit, 2640: Output circuit, 2660: Con Control logic circuit, 4700: Electronic components, 4701: Leads, 4702: Printed circuit board board, 4703: circuit portion, 4704: circuit board, 4800: semiconductor wafer, 4800a: 4801: wafer, 4801a: wafer, 4802: circuit part, 4803: space ing, 4803a: spacing, 4810: semiconductor wafer, 5100: USB memory, 5101: Housing, 5102: Cap, 5103: USB connector, 5104: Board, 5 105: Memory chip, 5106: Controller chip, 5110: SD card, 511 1: Housing, 5112: Connector, 5113: Board, 5114: Memory chip, 5115: Controller chip, 5150: SSD, 5151: Housing, 5152: Connector, 515 3: Board, 5154: Memory chip, 5155: Memory chip, 5156: Controller Chip, 5401: Housing, 5402: Display, 5403: Keyboard, 5404: Point device, 5501: housing, 5502: display unit, 5503: microphone, 5504: Speaker, 5505: Operation buttons, 5701: Display panel, 5702: Display panel, 57 03: Display panel, 5704: Display panel, 5801: First housing, 5802: Second housing, 5803: Display unit, 5804: Operation keys, 5805: Lens, 5806: Connection unit, 590 1: Housing, 5902: Display, 5903: Operation buttons, 5904: Operator, 5905: 9000: Housing, 9001: Display, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor

Claims

1. Having a first circuit and a second circuit, Each of the first circuit and the second circuit includes at least a first memory cell and a second memory cell connected in series with the first memory cell. The first memory cell of the first circuit and the first memory cell of the second circuit are each electrically connected to the first wiring. The second memory cell of the first circuit and the second memory cell of the second circuit are each semiconductor devices electrically connected to the second wiring, The first insulating layer, A first conductive layer having a region located above the first insulating layer and functioning as the first wiring, A second insulating layer having a region located above the first conductive layer, A second conductive layer having a region located above the second insulating layer and functioning as the second wiring, A third insulating layer having a region located above the second conductive layer, In a plan view, a first opening is disposed through at least the second conductive layer, the second insulating layer, and the first conductive layer, In a plan view, it has at least the second conductive layer, the second insulating layer, and the first conductive layer, and a second opening that penetrates them. The first memory cell of the first circuit is located inside the first opening. The second memory cell of the first circuit is located inside the first opening and has a region that overlaps with the first memory cell of the first circuit. The first memory cell of the second circuit is located inside the second opening. The second memory cell of the second circuit is located inside the second opening and has a region that overlaps with the first memory cell of the second circuit. In a cross-sectional view, the end of the second conductive layer has a region that protrudes more than the end of the third insulating layer. A semiconductor device wherein, in a cross-sectional view, the edge of the first conductive layer has a region that protrudes more than the edge of the second insulating layer, and this region protrudes more than the edge of the second conductive layer.

2. In Claim 1, In a cross-sectional view, the end of the second insulating layer has a region that protrudes more than the end of the second conductive layer. A semiconductor device wherein, in a cross-sectional view, the edge of the first insulating layer has a region that protrudes more than the edge of the first conductive layer.

3. In Claim 1 or Claim 2, A fourth insulating layer having a region located above the first conductive layer and a region located above the second conductive layer, A first wiring having a region located above the fourth insulating layer, The second wiring comprises a region located above the fourth insulating layer, The first wiring is electrically connected to the first conductive layer through the first opening in the fourth insulating layer. A semiconductor device wherein the second wiring is electrically connected to the second conductive layer through a second opening in the fourth insulating layer.

4. In claim 3, The first opening is multiple, A semiconductor device having multiple second apertures.

5. In claim 3 or claim 4, The semiconductor device has a fourth insulating layer having a region in contact with a portion of the upper surface of the first insulating layer, a region in contact with a portion of the upper surface of the first conductive layer, a region in contact with a portion of the upper surface of the second insulating layer, and a region in contact with a portion of the upper surface of the second conductive layer.

6. In any one of claims 3 to 5, A semiconductor device wherein the fourth insulating layer does not have a region in contact with the upper surface of the third insulating layer.

7. In any one of claims 3 to 6, In a plan view, the end of the second conductive layer has a portion between the first wiring and the second wiring. In a plan view, the first wiring has a portion between the end of the second conductive layer and the end of the first conductive layer, wherein the semiconductor device.

8. In Claims 1 to 7, The first memory cell has a first transistor having an oxide semiconductor in the channel formation region, The second memory cell is a semiconductor device having a second transistor having an oxide semiconductor in the channel formation region.

Images