Semiconductor device

Abstract

To provide a semiconductor device allowing microfabrication or high integration.SOLUTION: A semiconductor device includes a layer 10_1-a layer 10_n. Each layer includes a transistor 20 including: an oxide 22a; conductors 28a and 28b on the oxide 22a; an insulator 34 arranged to cover the conductors 28a and 28b and the oxide 22a; an insulator 36 on the insulator 34; an oxide 22b arranged between the conductors 28a and 28b on the oxide 22a; an insulator 24 on the oxide 22b; a conductor 26 on the insulator 24; and an insulator 38 contacting an upper surface of the insulator 36, an upper surface of the oxide 22b, an upper surface of the insulator 24 and an upper surface 26 of the conductor. The insulators 34 and 38 is less likely to cause oxygen to penetrate than the insulator 36.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. One aspect of the invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device, and The sub-devices and the like may be said to have semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. This concerns the [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are attracting attention as other materials. For example, not only oxides of single metals such as indium oxide and zinc oxide, but also oxides of multi-component metals Among the oxides of multi-component metals, In-Ga-Zn oxide (hereinafter referred to as In-Ga-Zn oxide) is particularly There is a lot of research going on regarding IGZO.

[0005] Research on IGZO has revealed that, among oxide semiconductors, it is neither single crystal nor amorphous. AAC (c-axis aligned crystalline) structure and nc(n A crystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, oxide semiconductors having a CAAC structure are used. The technology for fabricating a transistor is also disclosed. Even oxide semiconductors with lower crystallinity than those containing SiO2 have minute crystals, as reported in Non-Patent Document 4 and and Non-Patent Document 5.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non- Patent Document 6), and LSIs and displays that utilize these properties have been reported (non- See Patent Document 7 and Non-Patent Document 8). [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-patent document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-patent document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-patent document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-patent document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-patent document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of the present invention is to provide a semiconductor device having high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device having an off-state current Another object of one embodiment of the present invention is to provide a semiconductor device with a low power consumption. It is an object of the present invention to provide a semiconductor device with reduced power consumption. An object of one embodiment is to provide a semiconductor device with high productivity.

[0009] One embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time. One object of one embodiment of the present invention is to provide a semiconductor device with a high data writing speed. One object of one embodiment of the present invention is to provide a semiconductor device with high design freedom. One object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device. This is one of the challenges.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a method for manufacturing a semiconductor device having a first layer and a second layer on the first layer, the first layer, and The second layer has a transistor, and the transistors of the first layer and the second layer are a first oxide, a first conductor and a second conductor on the first oxide, and the first conductor; a first insulator disposed over the second conductor and the first oxide; a second insulator and a second oxide disposed between the first conductor and the second conductor on the first oxide; a second oxide, a third insulator on the second oxide, a third conductor on the third insulator, and a the top surface of the second insulator, the top surface of the second oxide, the top surface of the third insulator, and the top surface of the third conductor; and a fourth insulator in contact with the surface, and the first insulator and the fourth insulator are connected to the second insulator. It is a semiconductor device that is less permeable to oxygen than the body.

[0012] In the above, it is preferable that the second oxide has crystallinity. The second oxide is in contact with the side surface of the second insulator and is arranged approximately perpendicular to the side surface. It is preferable that the second oxide has a region in which the c-axis is oriented. Preferably, a third oxide is disposed adjacent to it.

[0013] In the above, a fifth insulator is disposed below the first oxide and the first insulator. A sixth insulator is disposed below the fifth insulator, and the sixth insulator is more oxygen-concentrating than the fifth insulator. In the above, it is preferable that the first insulating layer is disposed under the sixth insulating layer. A fourth conductor is preferably disposed overlying the oxide.

[0014] In the above, the first insulator and the fourth insulator are made of aluminum and hafnium. Preferably, the oxide contains one or both of ammonium and ammonium.

[0015] In the above, the first oxide and the second oxide are composed of In and an element M (M is A It is preferable that the material has a metal oxide (e.g., Zn, Y, or Sn) and Zn.

[0016] In the above, a third layer is disposed under the first layer, and the third layer is a silicon substrate. It is preferable that the fifth conductor has a seventh insulator on the seventh insulator and a fifth conductor on the seventh insulator. [Effects of the Invention]

[0017] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. It is possible.

[0018] Alternatively, a semiconductor device capable of retaining data for a long period of time can be provided. Alternatively, a semiconductor device with a high data writing speed can be provided. It is possible to provide a semiconductor device with high flexibility. A semiconductor device can be provided. Alternatively, a novel semiconductor device can be provided. .

[0019] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above will be self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A to 1D are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A and 1B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 5] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1D are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. [Figure 15]1A and 1B are cross-sectional views illustrating a structure of a memory device according to one embodiment of the present invention. [Figure 16] FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 17] 1A to 1H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 18] 1A and 1B are a schematic view and a perspective view of a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A to 1E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 20] 1A to 1E are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 21] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 22] 1A to 1C are diagrams showing configuration examples of a parallel computer, a computer, and a PC card according to one embodiment of the present invention. [Figure 23] 1 is a cross-sectional TEM image of a transistor according to an embodiment of the present invention. [Figure 24] (A)(B) Cross-sectional TEM images of a transistor according to an embodiment of the present invention. [Figure 25] 1A and 1B are diagrams showing electrical characteristics of a transistor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be practiced in various different ways without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various changes in form and details may be made. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0022] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The examples are shown in the drawings as a schematic illustration, and are not limited to the shapes or values ​​shown in the drawings. For example, In the actual manufacturing process, layers and resist masks are damaged by etching and other processes. However, in order to make it easier to understand, this may not be reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals between different drawings. In addition, when referring to similar functions, In such cases, the hatch pattern may be the same and no particular reference numeral may be assigned.

[0023] In addition, in particular, top views (also called "plan views") and perspective views are used to make the invention easier to understand. In order to avoid this, some components may be omitted. may be omitted.

[0024] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second" The term "the" or "third" can be used interchangeably in the description. The ordinal numbers listed may not match the ordinal numbers used to identify an aspect of the present invention. There may be cases where this is the case.

[0025] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship is used for convenience in describing the same with reference to the drawings. The relationship changes depending on the direction in which each component is depicted. The terms are not limited to those described above, and can be rephrased appropriately depending on the situation.

[0026] For example, in this specification, it is explicitly stated that X and Y are connected. In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification. Therefore, it is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also disclosed in the drawings or text. It shall be.

[0027] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, layer, etc.).

[0028] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0029] In this specification and the like, depending on the structure of the transistor, the channel may not actually be formed. The channel width in the region where the transistor is The channel width shown in the top view of the capacitor (hereinafter also referred to as the "apparent channel width") For example, if the gate electrode covers the side of the semiconductor, the effective channel The width of the channel may become larger than the apparent channel width, and the effect may become unnegligible. For example, in a fine transistor in which the gate electrode covers the side of the semiconductor, In this case, the ratio of the channel formation region formed in the The effective channel width is larger than the channel width.

[0030] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, the effective Channel width is difficult to measure accurately.

[0031] In this specification, when simply referring to the channel width, it refers to the apparent channel width. In this specification, when simply referred to as a channel width, it means an effective channel The channel length, channel width, effective channel width, apparent channel width, The channel width and other parameters can be determined by analyzing cross-sectional TEM images. can.

[0032] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. The DOS (Density of States) of the semiconductor increases and the crystallinity decreases. When the semiconductor is an oxide semiconductor, the semiconductor properties may be The impurities to be changed include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 14 elements. These include elements, Group 15 elements, and transition metals other than the main components of oxide semiconductors, such as: Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of semiconductors, water may also function as an impurity. In some cases, oxygen vacancies may be formed due to the inclusion of impurities. In this case, impurities that change the properties of semiconductors include, for example, oxygen and Group 1 elements excluding hydrogen. , Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0033] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. Silicon nitride oxide is a material that contains a large amount of silicon dioxide rather than oxygen. It has a high nitrogen content.

[0034] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can also be replaced with "semiconductor film" or "semiconductor layer." can.

[0035] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10 degrees or more and 10 degrees or less. Therefore, it includes cases where the angle is between -5 degrees and 5 degrees. In addition, "approximately parallel" means that two straight lines are arranged at an angle of between -30 degrees and 30 degrees. Also, "perpendicular" means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it includes the case where the angle is between 85 degrees and 95 degrees. "Perpendicular" refers to two straight lines that form an angle between 60 degrees and 120 degrees.

[0036] In this specification, the term "barrier film" refers to a film that prevents impurities such as water and hydrogen from permeating, and oxygen. If the barrier film has conductivity, it is called a conductive barrier. It is sometimes called the membrane.

[0037] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal Metal oxides are sometimes called oxide semiconductors. When a transistor is described as a transistor having an oxide or an oxide semiconductor, In other words:

[0038] In this specification, normally off means that no potential is applied to the gate, or The current per 1 μm of channel width that flows through a transistor when a ground potential is applied to the gate is 1×10 at room temperature -20 A or less, 1 x 10 at 85°C -18 A or below, or 1 x 10 at 125°C -16 This means that it is A or below.

[0039] (Embodiment 1) The configuration and characteristics of a semiconductor device according to one embodiment of the present invention will be described below.

[0040] FIG. 1 shows layers 10_1 to 10_n (n is a natural number of 2 or more) from the bottom. 1 is a cross-sectional view of a semiconductor device in which layers 10_1 to 10_2 are stacked in this order. Any layer from 0 to n may be referred to as layer 10 without an ordinal number.

[0041] Each of the layers 10_1 to 10_n has at least one transistor 20. In FIG. 1, each of the layers 10_1 to 10_n includes one transistor 20. However, the number of transistors is not limited to this, and may be any number of transistors. The layer 10 may have different thicknesses depending on the desired function of the semiconductor device. Circuits such as switches, transistors, capacitors, inductors, resistors, and diodes It is sufficient to provide a path element, wiring, electrodes, terminals, etc. as appropriate.

[0042] As shown in FIG. 1, the transistor 20 includes an insulator 30 and an insulator 32 on the insulator 30. , oxide 22a on insulator 32, conductor 28a and conductor 28b on oxide 22a, an insulator 34 disposed over the conductor 28a, the conductor 28b, and the oxide 22a; An insulator 36 on the insulator 34 and an oxide 22a on the oxide 22b are disposed between the conductors 28a and 28b. An oxide 22b is placed on the insulating layer 22b, an insulator 24 is placed on the oxide 22b, and a conductor 26 is placed on the insulator 24. , the top surface of the insulator 36, the top surface of the oxide 22b, the top surface of the insulator 24, and the top surface of the conductor 26. In the following description, the oxide 22a and the oxide 2 2b are sometimes collectively referred to as oxide 22.

[0043] Here, the conductor 28a and the conductor 28b are the source electrodes of the transistor 20, respectively. The conductor 26 also functions as the gate electrode of the transistor 20. and insulator 24 serves as the gate insulator for transistor 20. The conductor 26, the insulator 24, and the oxide 22b are insulated by the insulator 36 and the insulator 34. , conductor 28a, and conductor 28b. As a result, the conductor 26 is positioned in the region between the conductors 28a and 28b. It can be positioned reliably without alignment.

[0044] Here, the insulators 38, 34 and 30 are oxygen (e.g., oxygen atoms, oxygen It is preferable that the material has a function of suppressing the diffusion of oxygen molecules (such as oxygen molecules) (the material is less likely to permeate the oxygen molecules). For example, insulators 38 and 34 are preferably less permeable to oxygen than insulator 30. For example, it is preferable that the insulator 30 is less permeable to oxygen than the insulator 32. An example of an insulator having such a barrier property against oxygen is aluminum. and hafnium, or an oxide containing both of these may be used.

[0045] In addition, the insulator 36 preferably contains oxygen that is desorbed by heating. 6 is preferably an oxide, and contains more oxygen than the stoichiometric composition. In the following, the oxygen released by heating will be referred to as excess oxygen. There is.

[0046] Here, the height of the upper surface of the insulator 36 is the height of the upper surface of the conductor 26, the upper surface of the insulator 24, and the upper surface of the acid It is preferable that the height of the upper surface of the insulator 36 and the conductor 26 is approximately the same as that of the upper surface of the conductor 22b. The insulator 24 and the oxide 22b are preferably covered with an insulator 38. It is preferable that the side surface of the insulator 36 contacts the side surface of the oxide 22b. By this, the insulator 36 is separated from the conductor 26 by the insulator 38 and the oxide 22b. This allows the oxygen contained in the insulator 36 to directly diffuse into the conductor 26. This can prevent this.

[0047] It is also preferable that the lower surface of the insulator 36 contacts the insulator 34. The side of the oxide 22b, the top and side of the conductor 28a, the top and side of the conductor 28b, It is preferable that the insulating layer 22a contacts the side surface of the insulating layer 22a and the top surface of the insulating layer 32. By this, the insulator 36 is formed by the oxide 22b and the insulator 34, and the conductor 28a and the conductor This allows oxygen contained in the insulator 36 to be separated from the conductor 28b. This can prevent the metal from diffusing directly into the conductive material 28a and the conductive material 28b.

[0048] In addition, an insulator 40 may be provided on the insulator 38. In FIG. The insulator 30 of the upper layer 10 is provided in contact with the upper surface of the insulator 40 of the upper layer 10. The layer 10 of the lower layer and the layer 10 of the upper layer are not connected to each other. Circuit elements such as capacitance elements, inductors, resistance elements, and diodes, wiring, electrodes, and In addition, the insulator 40 may be omitted and the insulator 3 of the lower layer 10 may be used. The insulating layer 8 may also serve as the insulating layer 30 of the upper layer 10 .

[0049] The oxide 22a has a channel forming region between the conductor 28a and the conductor 28b, In the vicinity of the region overlapping with the conductor 28a (conductor 28b), a channel forming region is sandwiched between the conductors. It has a source region and a drain region. Note that the source region and / or the drain region In some cases, the conductive body 28a (conductive body 28b) may have a shape that protrudes inward. The channel forming region of the transistor 20 is not only the oxide 22a but also the oxide 22a and the oxide 22b. 2b and / or may be formed in the oxide 22b.

[0050] Here, in the transistor 20, the oxide 22a and the oxide 22b are oxide semiconductors. It is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor. For example, the metal oxides that become the oxide 22a and the oxide 22b include: It is preferable to use a material with a peak voltage of 2 eV or more, preferably 2.5 eV or more. In transistors using wide energy gap metal oxides, the off-current (leakage current) By using such a transistor, a semiconductor device with low power consumption can be provided. Cut.

[0051] For example, the oxide 22a and the oxide 22b may be an In-M-Zn oxide (wherein the element M is Aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium Tungsten, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, Selected from neodymium, hafnium, tantalum, tungsten, or magnesium In particular, the element M may be aluminum, Gallium, yttrium, or tin may be used. As 2b, In-Ga oxide or In-Zn oxide may be used.

[0052] Here, in the metal oxide used for the oxide 22a, the atomic ratio of In to the element M is , which is greater than the atomic ratio of In to element M in the metal oxide used for the oxide 22b. In this way, by disposing the oxide 22b on the oxide 22a, the oxide The diffusion of impurities from the structure formed above the oxide 22b to the oxide 22a is suppressed. In addition, the oxide 22a and the oxide 22b have a common element other than oxygen. By using the oxide 22a as the main component, the defect level density at the interface between the oxide 22a and the oxide 22b is The defect level density at the interface between the oxide 22a and the oxide 22b can be reduced. Therefore, the influence of interface scattering on carrier conduction is small, and a high on-state current is achieved. flow is obtained.

[0053] It is preferable that the oxide 22a and the oxide 22b each have crystallinity. Oxide 22a and oxide 22b are CAAC-OS (c-axis aligned) d crystalline oxide semiconductor) is preferred.

[0054] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0055] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is difficult to confirm the crystal structure (also called "undary") due to the distortion of the lattice arrangement. This is because the CAAC-OS is aligned in the ab-plane direction. In this case, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated by changing the

[0056] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). It is noted that indium and element M tend to have a structure (also called a layered structure). When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) ) layer. Also, when indium in the In layer is replaced with element M, it can be expressed as (In, It can also be expressed as the M layer.

[0057] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS should be free from impurities and defects (oxygen vacancies (V O :oxygen v Therefore, CAAC- Metal oxides with OS have stable physical properties. Metal oxides are heat resistant and highly reliable.

[0058] Here, the analysis was carried out by X-ray diffraction (XRD). An example of CAAC-OS will be described. For example, a CAAC having InGaZnO4 crystals When structural analysis is performed on C-OS using the out-of-plane method, the diffraction angle (2θ) A peak may appear around 31°. This peak is due to the 009) plane, the CAAC-OS crystal has a c-axis orientation, and the c-axis is It can be said that the direction is approximately perpendicular to the formation surface or upper surface.

[0059] We will also explain examples of CAAC-OS analyzed by electron diffraction. For CAAC-OS with GaZnO4 crystals, a probe diameter of 300 mm was used parallel to the sample surface. When an electron beam of 1000 nm is incident, a diffraction pattern (also called a selected area transmission electron diffraction pattern) is generated. This diffraction pattern may appear on the (009) plane of the InGaZnO4 crystal. Therefore, the electron diffraction also revealed spots in the CAAC-OS. The crystals formed have a c-axis orientation, and the c-axis is oriented in a direction approximately perpendicular to the surface on which the crystal is formed or the upper surface. On the other hand, for the same sample, an electron beam with a probe diameter of 300 nm was applied perpendicular to the sample surface. When electrons are incident on the object, a ring-shaped diffraction pattern is observed. However, the a-axis and b-axis of the crystals contained in CAAC-OS do not have any orientation. Cut.

[0060] In a transistor using an oxide semiconductor, a region where a channel is formed in the oxide semiconductor The presence of impurities and oxygen vacancies can cause fluctuations in electrical characteristics and reduce reliability. In addition, oxygen vacancies may be present in a region in an oxide semiconductor where a channel is formed. If impurities (typically hydrogen) are introduced into the oxygen vacancies, the transistor will When oxide semiconductors are heat-treated in a state where oxygen is not supplied, For example, during the transistor manufacturing process, oxygen may be released and oxygen vacancies may be formed. By the heat treatment in step 1, oxygen is absorbed from the oxide semiconductor into the source electrode and the drain electrode, Oxygen vacancies may be formed in the oxide semiconductor.

[0061] In contrast, when an insulator containing excess oxygen is provided near an oxide semiconductor and heat treatment is performed, In addition, the insulator may have a structure in which oxygen can be supplied to the oxide semiconductor. A conductor that functions as a gate, source, or drain is placed in contact with an insulator containing silicon. When the insulator is connected to the conductor, oxygen contained in the insulator is absorbed by the conductor, forming an oxide semiconductor. There is a risk that it will become difficult to supply the necessary resources.

[0062] When a plurality of transistors are stacked as in this embodiment, the transistor in the lower layer The capacitor is exposed to heat treatment during the manufacturing process every time a transistor is manufactured on the upper layer. In other words, the lower the transistor is located, the greater the thermal budget. Therefore, during the manufacturing process of the upper layer transistor, the lower layer transistor contains excess oxygen. There is a risk that oxygen from the insulator will be absorbed by the conductor, making it impossible to supply oxygen to the oxide semiconductor. At this time, the amount of oxygen supplied to the oxide semiconductor is equal to the amount of oxygen absorbed by the oxide semiconductor. Therefore, when the lower layer transistor is completed, the amount of oxygen in the oxide semiconductor Even if the defects are sufficiently reduced, the oxide semiconductor may be damaged during the manufacturing process of the upper layer transistor. Oxygen vacancies are formed.

[0063] Here, when the transistor 20 according to the present embodiment is subjected to a heat treatment, the insulator 36 The behavior of the contained oxygen 50 will be explained with reference to FIG. 2. As described above, in the semiconductor device described in this embodiment, the insulating film containing excess oxygen The conductor 36 is surrounded by an insulator 38, an oxide 22b, and an insulator 34, and the conductor 26 , conductor 28a, and conductor 28b are spaced apart. Even after the treatment, the oxygen 50 in the insulator 36 is transferred to the insulator 38, the oxide 22b, and the insulator 3. 4 and does not diffuse directly into conductor 26, conductor 28a, and conductor 28b.

[0064] Furthermore, when oxygen is released from the oxide 22a by the heat treatment and oxygen vacancies are formed, the oxide In the vicinity of the interface between the oxide 22a and the oxide 22b, oxygen diffuses from the oxide 22b to the oxide 22a. The oxygen supplied to the oxide 22a is dispersed in the oxide 22a to compensate for the oxygen deficiency. The defects are repeatedly filled and diffused into the oxide 22a.

[0065] In addition, by supplying oxygen to the oxide 22a, oxygen vacancies are also formed in the oxide 22b. At this time, the oxide 22b is transferred from the insulator 36 to the oxide 22b in the vicinity of the interface between the insulator 36 and the oxide 22b. Oxygen 50 diffuses into oxide 22b and compensates for the oxygen vacancies. The oxygen atoms diffuse through the oxide 22b, repeatedly filling up oxygen vacancies in the oxide 22b.

[0066] Here, the oxide 22b is preferably CAAC-OS. As shown in Fig. 2, the layer 22bP of the crystal is elongated in the ab-plane direction and the layer c is perpendicular to the ab-plane direction. In the oxide 22b, the c-axis 22bX is It is preferable that the oxide 22b is oriented in a direction substantially perpendicular to the surface on which the oxide 22b is to be formed. The oxide 22b has a c-axis 22bX oriented substantially perpendicular to the upper surface of the oxide 22a. The area is approximately perpendicular to the side surfaces of the conductor 28a, the insulator 34, and the insulator 36. The region in which the c-axis 22bX is oriented and the region in which the conductor 28b, the insulator 34, and the insulator 36 are oriented are also oriented. and a region in which the c-axis 22bX is oriented substantially perpendicular to the side surface.

[0067] CAAC-OS has the property that oxygen diffuses more easily in the ab plane direction than in the c axis direction. Therefore, the oxygen 50 supplied from the insulator 36 to the oxide 22b is preferentially supplied as shown in FIG. First, the oxide 22b is diffused to the vicinity of the interface between the oxide 22a and the oxide 22b, and oxygen vacancies in the oxide 22b are eliminated. It can be compensated.

[0068] As described above, the transistor 20 described in this embodiment can be manufactured without undergoing heat treatment after completion. The insulator 36 supplies oxygen to the oxide 22, and prevents the increase of oxygen vacancies in the oxide 22. Therefore, the fluctuation of the electrical characteristics of the transistor 20 can be prevented even in the lower layer 10. This suppresses the generation of the ions, thereby providing stable electrical characteristics and improving the reliability of the transistor 20. It is possible.

[0069] By stacking layers 10_1 to 10_n including such transistors 20, The area occupied by the semiconductor device described in this embodiment mode in a top view is reduced, and the fine Thinner and more highly integrated circuits can be achieved.

[0070] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. It is possible.

[0071] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0072] (Embodiment 2) Specific examples of the structure of the semiconductor device described in the above embodiment will be described below with reference to FIGS. This will be explained using FIG.

[0073] <Configuration example of semiconductor device> 3(A), 3(B), 3(C), and 3(D) show a transmission line according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view of a transistor 200 and the periphery of the transistor 200. The transistor 200 corresponds to the transistor 20 shown in the previous embodiment. As shown in the embodiment, the transistor 200 can be stacked.

[0074] FIG. 3A is a top view of a semiconductor device including a transistor 200. FIG. 3(B) and FIG. 3(C) are cross-sectional views of the semiconductor device. 3(A) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. FIG. 3(C) is also a cross-sectional view in the longitudinal direction of the panel. 1 is a cross-sectional view of the portion indicated by the arrow A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Also, Fig. 3(D) is a cross-sectional view of the portion indicated by the dashed line A5-A6 in Fig. 3(A). In the top view of FIG. 3(A), some elements are omitted for clarity.

[0075] The semiconductor device of one embodiment of the present invention includes a transistor 200 and an insulator serving as an interlayer film. 214, insulator 274, insulator 280, and insulator 281. The conductor 240 (conductor 240a, and conductor 240b). An insulator 241 (insulator 241a and insulator 241b) is provided therebetween.

[0076] In addition, the insulators 254, 274, and 281 are in contact with the inner walls of the openings. 241 is provided, and the first conductor of the conductor 240 is provided in contact with the side surface of the conductor 241. The second conductor of the conductor 240 is provided on the side. In the transistor 200, the height of the upper surface of the insulator 281 can be made approximately the same. 2 shows a configuration in which a first conductor of the conductor 240 and a second conductor of the conductor 240 are stacked. However, the present invention is not limited to this. For example, the conductor 240 may be a single layer or It may be configured as a laminated structure of three or more layers. Ordinal numbers may be assigned to indicate the order of appearance to distinguish them.

[0077] [Transistor 200] As shown in FIG. 1, transistor 200 comprises an insulator disposed on a substrate (not shown). 214 and an insulator 216, and a conductor 20 disposed so as to be embedded in the insulator 216. 5, an insulator 222 disposed on the insulator 216 and on the conductor 205, and an insulator 223 disposed on the insulator 216. 22 and an oxide 230 (oxide) disposed on the insulator 224. oxide 230a, oxide 230b, oxide 230c1, and oxide 230c2) and oxide An insulator 250 disposed on the object 230 and a conductor 260 ( Conductor 260a and conductor 260b, and a conductive layer in contact with a portion of the top surface of oxide 230b. The body 242a and the conductor 242b, a part of the top surface of the insulator 224, and the side surface of the oxide 230a , the side surface of the oxide 230b, the side surface of the conductor 242a, the top surface of the conductor 242a, the conductor 242 an insulator 254 disposed in contact with the side surface of the conductor 242b and the top surface of the conductor 242b; 4, and an insulator 274 disposed on the insulator 280. The conductor 260 includes a conductor 260a and a conductor 260b. The conductor 260a is disposed so as to surround the bottom and side surfaces of the Thus, the top surface of the conductor 260 is connected to the top surface of the insulator 250, the top surface of the oxide 230c1, and the top surface of the oxide 230c2. The upper surface of the insulating member 280 is disposed so as to be substantially aligned with the upper surface of the insulating member 230c2. 274 contacts the upper surfaces of the conductor 260, the oxide 230c, and the insulator 250. In the following, the oxide 230c1 and the oxide 230c2 are collectively referred to as the oxide 230 Sometimes it is called c.

[0078] Here, the insulator 214 corresponds to the insulator 30 of the transistor 20 of the previous embodiment. Also, the insulator 224 corresponds to the insulator 32 of the transistor 20 of the previous embodiment. Also, the oxide 230b corresponds to the oxide 22a of the transistor 20 of the previous embodiment. The conductor 242a and the conductor 242b are the same as those of the transistor 20 of the previous embodiment. The insulator 254 corresponds to the conductor 28a and the conductor 28b. The insulator 280 corresponds to the insulator 34 of the transistor 20. The oxide 230c corresponds to the insulator 36 of the transistor 20. The insulator 250 corresponds to the oxide 22b of the transistor 20. The conductor 260 corresponds to the insulator 24 of the transistor 20. The insulator 274 corresponds to the conductor 26 of the transistor 20. The insulator 281 corresponds to the insulator 38 of the transistor 20. It should be noted that the insulator 222 corresponds to the insulator 40 of the transistor 20 in the previous embodiment. The insulator 32 may correspond to the insulator 32 of the rotor 20.

[0079] Additionally, the insulator 280 preferably has a region containing oxygen that is desorbed by heating. By providing an insulator 280 that releases oxygen when heated in contact with the oxide 230c1, Oxygen in the insulator 280 is efficiently supplied to the oxide 230b through the oxide 230c1. It is possible.

[0080] The insulators 222, 254, and 274 are made of oxygen (e.g., oxygen atoms, oxygen It is preferable that the insulating material has a function of suppressing the diffusion of at least one of molecules. 222, insulator 254, and insulator 274 are hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). ) is preferably capable of suppressing the diffusion of at least one of the following. , insulator 254, and insulator 274 have higher oxygen and hydrogen content than insulator 224, respectively. Preferably, one or both of the insulators have low permeability. The insulator 274 is more permeable to oxygen and / or hydrogen than the insulator 250, respectively. The insulators 222, 254, and 274 are each an insulator It is preferable that the permeability to one or both of oxygen and hydrogen is lower than that of the insulator 280 .

[0081] As shown in FIGS. 3(B) and 3(C), the insulator 254 is formed on the upper and side surfaces of the conductor 242a. , the top and side surfaces of the conductor 242b, the side surfaces of the oxide 230a and the oxide 230b, and It is preferable that the insulating material 224 contacts the upper surface thereof.

[0082] By using the above-mentioned configuration, the insulator 280 is formed by the insulator 274 and the oxide 230c. This allows the conductor 260 to be separated from the insulator 280. It is possible to prevent the insulator 280 from directly diffusing into the conductor 260. The conductor 242a and the conductor 242b are separated by the oxide 230c and the insulator 254. As a result, oxygen contained in the insulator 280 can be absorbed into the conductor 242a and the conductor This can prevent direct diffusion into the body 242b.

[0083] The oxide 230 is made up of an oxide 230a disposed on the insulator 224 and an oxide 230b. an oxide 230b disposed on the oxide 230a; and at least one It is preferable that the oxide 230c is in contact with the upper surface of the oxide 230b. The oxide 230c is formed by the oxide 230c1 and the oxide 230c1 in contact with the upper surface of the oxide 230c. It may also be a laminated structure with c2.

[0084] In the transistor 200, a region where a channel is formed (hereinafter, referred to as a channel forming region) Also referred to as oxide 230a, oxide 230b, oxide 230c, and oxide 230c are formed in the vicinity of the oxide 230a. Although the present invention is not limited to this, the present invention is not limited to this. For example, a single layer of oxide 230b, a layer of oxide 230b and a layer of oxide 230a a two-layer structure of oxide 230b and oxide 230c2; a two-layer structure of oxide 230a and oxide 2 30b, and oxide 230c1, or a laminated structure of five or more layers. In addition, in the transistor 200, the conductor 260 is shown as having a two-layer stacked structure. However, the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure. Alternatively, it may have a laminated structure of three or more layers.

[0085] Here, the conductor 260 functions as the gate electrode of the transistor, and the conductors 242a and and conductor 242b function as a source electrode and a drain electrode, respectively. The transistor 200 has a conductor 260 that functions as a gate electrode and is surrounded by an insulator 280 or the like. The conductor 260 is formed in a self-aligned manner so as to fill the opening. By doing so, the conductor 260 is positioned in the region between the conductor 242a and the conductor 242b. As shown in FIG. 1, the conductor 260 The conductive member 260 has a conductive member 260a and a conductive member 260b disposed on the conductive member 260a. It is preferable that:

[0086] The transistor 200 also includes an insulator 214 disposed on a substrate (not shown); The insulator 216 is disposed on the insulator 214, and the insulator 214 and the insulator 216 are disposed on the insulator 216. The conductor 205 is disposed so as to be embedded in the insulator 216, and the insulator 216 is disposed on the conductor 205. It is preferable to have an insulator 222 on the insulating layer 224. is preferably arranged.

[0087] The transistor 200 also includes an oxide 230 (oxide 230a) including a channel formation region. , oxide 230b, oxide 230c1 and oxide 230c2) as oxide semiconductors It is preferable to use a functional metal oxide (hereinafter also referred to as an oxide semiconductor).

[0088] The transistor 200 having an oxide semiconductor in a channel formation region has a Since the leakage current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. In addition, oxide semiconductors can be deposited using a sputtering method or the like, making them suitable for highly integrated semiconductors. It can be used for the transistor 200 that constitutes the device.

[0089] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium One or more selected from aluminum, tantalum, tungsten, magnesium, etc. In particular, the element M may be an oxide of a metal such as aluminum, gallium, or yttrium. The oxide 230 may be an In-Ga oxide, an In- Zn oxide may also be used.

[0090] In addition, in a transistor using an oxide semiconductor, a channel is formed in the oxide semiconductor. If impurities and oxygen vacancies exist in the region, the electrical characteristics are likely to fluctuate, resulting in poor reliability. In addition, there are cases where oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor. Therefore, the transistor tends to have normally-on characteristics. It is preferable that oxygen vacancies in the region to be covered are reduced as much as possible. Oxygen can be supplied to the oxide 230b via 0c or the like to compensate for the oxygen deficiency. This suppresses fluctuations in electrical characteristics, providing stable electrical characteristics and improving reliability. A transistor can be provided.

[0091] Also, the oxide 230 is provided on the substrate 230 so as to be in contact with the oxide 230, and functions as a source electrode and a drain electrode. The elements (e.g., When the second element has a function of absorbing oxygen from the oxide 230, the oxide 230 and the conductive When a low resistance region is formed between the bodies 242 or near the surface of the oxide 230 In this case, impurities (hydrogen, nitrogen, or In some cases, the following elements (such as metal elements) function as donors, increasing the carrier density. Below, the hydrogen that has entered the oxygen vacancy is called V O It may be called H.

[0092] 4A is an enlarged view of a portion of the transistor 200 shown in FIG. 3B. As shown in FIG. 4A, a conductor 242 is provided on the oxide 230 so as to be in contact with the oxide. The interface between the conductor 242 and the oxide 230 and the vicinity thereof are provided with a region 243 ( The oxide 230 may be formed in regions 243a and 243b. The region 234 functions as a channel forming region of the transistor 200, and includes a part of the region 243. , the region 231 (region 231a, and region 231b) functioning as a source region or a drain region. 231b). In the following drawings, the area 243 is not shown in an enlarged view. Even if no such region exists, a similar region 243 may be formed.

[0093] The region 243a and the region 243b are formed in the vicinity of the conductor 242 of the oxide 230b. In this example, the electrons are diffused in the depth direction, but the present invention is not limited to this. The regions 243a and 243b are appropriately selected according to the desired electrical characteristics of the transistor. Furthermore, in the oxide 230, the boundaries of the respective regions can be clearly detected. The concentrations of elements detected within each region are not limited to gradual changes from region to region. The value may be varied continuously within each region.

[0094] The transistor 200 of one embodiment of the present invention includes an insulator 274 The lower surface of the conductor 260 is in contact with the upper surface of the oxide 230c, and the conductor 260 is separated from the insulator 280. This prevents oxygen contained in the insulator 280 from being absorbed into the conductor 260. Furthermore, the transistor 200 of one embodiment of the present invention can be formed as shown in FIG. The side of the oxide 230c and the side of the insulator 254 are in contact with each other, and the conductor 242a and The conductor 242b is separated from the insulator 280. This can prevent oxygen from being absorbed into the conductors 242a and 242b.

[0095] Here, an enlarged view of a part of the transistor 200 shown in FIG. 3C is shown in FIG. 4B. FIG. 4B is an enlarged view of the channel formation region in the W width direction of the transistor 200. do.

[0096] As shown in FIG. 4B, the oxide 230a and the oxide 230b are formed on the bottom surface of the insulator 224. The height of the bottom surface of the conductor 260 in the region where the conductor 260 does not overlap with the oxide 230b. is preferably located at a position lower than the height of the bottom surface of the oxide 230b. The height of the bottom surface of the conductor 260 in the region where the oxide 230b and the conductor 260 do not overlap is When the difference between the height of the bottom surface of the oxide 230b and the height of the bottom surface of the oxide 230b is T2, T2 is 0 nm or more and 100 nm or less. nm or less, preferably 3 nm to 50 nm, more preferably 5 nm to 20 nm The following applies.

[0097] In this way, the conductor 260 functioning as the gate electrode is formed on the oxide 2 of the channel forming region. The side and top surfaces of the insulating layer 30b are covered with the oxide 230c and the insulator 250. This makes it easier for the electric field of the conductor 260 to act on the entire oxide 230b in the channel formation region. Therefore, the on-state current of the transistor 200 can be increased, and the frequency characteristics can be improved. can.

[0098] As described above, a semiconductor device including a transistor with large on-state current can be provided. Alternatively, a semiconductor device including a transistor with high frequency characteristics can be provided. Alternatively, the fluctuation of electrical characteristics can be suppressed, and the electrical characteristics can be stabilized while increasing reliability. Alternatively, a semiconductor device having a low off-state current can be provided. It is possible to provide a semiconductor device having the above structure.

[0099] The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0100] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulators 214 and 216. Here, it is preferable to improve the flatness of the upper surface of the conductor 205. For example, The average surface roughness (Ra) of the upper surface of 205 is 1 nm or less, preferably 0.5 nm or less, more preferably This allows the insulating layer formed on the conductor 205 to be The planarity of the oxide 224 is improved, and the crystallinity of the oxide 230b and the oxide 230c is improved. It is possible.

[0101] Here, the conductor 260 functions as a first gate (also called a top gate) electrode. The conductor 205 may also be used as a second gate (also called a bottom gate) electrode. In this case, the potential applied to the conductor 205 may be changed to the potential applied to the conductor 260. The Vth of the transistor 200 is controlled by changing it independently of the potential of the transistor 200. In particular, applying a negative potential to the conductor 205 can turn on the transistor By increasing the Vth of 200 to be greater than 0 V, it becomes possible to reduce the off-current. When a negative potential is applied to the conductor 205, the amount of charge applied to the conductor 260 is larger than when no negative potential is applied. The drain current can be reduced when the applied potential is 0V.

[0102] As shown in FIG. 3(A), the conductor 205 is formed in a region 234 of the oxide 230. In particular, as shown in FIG. 3(C), the conductor 205 is made of oxide 2 The region 234 of the channel 30 extends beyond the end portion thereof intersecting with the channel width direction. That is, it is preferable that the oxide 230 is formed on the outer side of the side surface in the channel width direction. Therefore, it is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator.

[0103] With the above configuration, the electric field of the conductor 260 that functions as the first gate electrode The electric field of the conductor 205, which functions as the second gate electrode, The channel forming region can be electrically surrounded.

[0104] As shown in FIG. 3C, the conductor 205 is extended to function as a wiring. However, the present invention is not limited to this, and a conductive material that functions as a wiring may be provided under the conductive material 205. In addition, the conductor 205 does not necessarily have to be provided for each transistor. For example, the conductor 205 may be shared by multiple transistors. Good too.

[0105] In addition, the conductor 205 has a first conductor formed in contact with the inner wall of the opening of the insulator 216, Further inside, a second conductor is formed. The height of the second conductor and the height of the upper surface of the insulator 216 can be made to be approximately the same. In the example 200, a first conductor and a second conductor of the conductor 205 are stacked. However, the present invention is not limited to this. For example, the conductor 205 may be a single layer or Alternatively, the structure may have a laminated structure of three or more layers. In some cases, ordinal numbers are assigned to indicate the order of their formation to distinguish them.

[0106] The first conductor of the conductor 205 may be a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, Suppresses the diffusion of impurities such as nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. A conductor having a function of blocking the impurities (which makes it difficult for the impurities to permeate) may be used. (e.g., at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material that is difficult for oxygen to permeate. The function of suppressing the diffusion of impurities or oxygen is to suppress the diffusion of either the above impurities or the above oxygen. or the function of suppressing all diffusion.

[0107] The first conductor of the conductor 205 is a conductor having a function of suppressing the diffusion of oxygen. This can prevent the conductor 205 from being oxidized and the conductivity from decreasing. Examples of conductors that have the function of suppressing oxygen diffusion include tantalum, tantalum nitride, It is preferable to use ruthenium or ruthenium oxide. The first conductor 5 may be a single layer or a multilayer of the above conductive material.

[0108] The second conductor of the conductor 205 may be tungsten, copper, or aluminum. It is preferable to use a conductive material as the main component.

[0109] The insulator 214 has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use an insulating material that is permeable to oxygen (the above-mentioned oxygen is hardly permeable). 4 prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Therefore, the insulator 214 preferably functions as a barrier insulating film that prevents hydrogen atoms from molecules, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.) ), and has the function of suppressing the diffusion of impurities such as copper atoms (the impurities mentioned above are difficult to penetrate) Preferably, a soluble material is used.

[0110] For example, it is preferable to use silicon nitride or the like as the insulator 214. Impurities such as water or hydrogen diffuse from the substrate side to the transistor 200 side through the insulator 214 Alternatively, oxygen contained in the insulator 224 can be prevented from being absorbed by the insulator 225. 14 to the substrate side. , an insulating material containing oxides of one or both of aluminum and hafnium; You can also use your body.

[0111] In addition, the insulators 216, 280, and 281 have a higher dielectric strength than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic For example, the capacitance can be reduced by removing the insulators 216, 280, and 28 1. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen Silicon or silicon oxide having vacancies may be used as appropriate.

[0112] The insulator 222 and the insulator 224 function as gate insulators.

[0113] Here, it is preferable that the insulator 224 in contact with the oxide 230 releases oxygen by heating. In this specification, the oxygen released by heating may be referred to as excess oxygen. The insulator 224 may be made of silicon oxide or silicon oxynitride as appropriate. By providing an insulator containing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. This can improve the reliability of the transistor 200.

[0114] Specifically, the insulator 224 is made of an oxide material from which part of the oxygen is released by heating. The oxides that release oxygen by heating are called TDS (Thermal Dissociation Oxygen converted to oxygen atoms in the ion absorption spectroscopy analysis The amount of desorption is 1.0×10 18 atoms / cm 3 or more, preferably 1.0 × 10 19 at oms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 That's all, is 3.0 x 10 20 atoms / cm 3 The oxide film is the above-mentioned TDS content. The surface temperature of the film during deposition is 100°C or higher and 700°C or lower, or 100°C or higher and 40°C or lower. A range of 0°C or less is preferred.

[0115] As shown in FIG. 3C, the insulator 224 does not overlap with the insulator 254 and is oxidized. The film thickness in the region not overlapping with the object 230b may be thinner than the film thickness in the other region. In the insulator 224, a region that does not overlap with the insulator 254 and does not overlap with the oxide 230b The thickness of the film is preferably a thickness that allows sufficient diffusion of the oxygen.

[0116] The insulator 222 inhibits the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the insulator 222 has a function of preventing the oxygen from permeating (i.e., the oxygen is not easily transmitted). It is preferable that the insulator 222 has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of oxygen to the insulator 220 side. In addition, the conductor 205 is preferably made of an insulator 224 or an acid. This can prevent the compound 230 from reacting with oxygen.

[0117] Furthermore, the insulator 222 prevents impurities such as water or hydrogen from penetrating the transistor 20 from the substrate side. It is preferable that the insulating film functions as a barrier insulating film that prevents the inclusion of the insulating film in the 0. 222 preferably has a lower hydrogen permeability than insulator 224. The insulator 224 and the oxide 230 are surrounded by the edge 254, so that the insulating material 224 and the oxide 230 are Impurities such as water or hydrogen can be prevented from entering the transistor 200. .

[0118] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Oxide-containing insulators include aluminum oxide, hafnium oxide, aluminum and hafnium oxide. It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The release of impurities and the introduction of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200 are prevented. It acts as a suppressing layer.

[0119] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, or the like may be added to these insulators. um, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0120] The insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT These include so-called high-k materials such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST). As miniaturization and high integration of transistors progress, If the gate insulator is made thinner, problems such as leakage current may occur. By using a high-k material as an insulator, the physical thickness can be maintained. This makes it possible to reduce the gate potential during transistor operation.

[0121] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. good.

[0122] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b. The oxide 230c is located on the surface of the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from structures formed above oxide 230c into oxide 230b can be suppressed.

[0123] As shown in FIG. 3, the oxide 230c is composed of an oxide 230c1 and an oxide 230 and an oxide 230c2 disposed on the oxide 230c1. contains at least one of the metal elements constituting the metal oxide used in the oxide 230b It is preferable that the oxide 23 contains all of the metal elements. This can reduce the defect state density at the interface between 0b and oxide 230c1.

[0124] The oxide 230 has a layered structure made of oxides with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the constituent elements are preferably The atomic ratio of element M in the oxide 230b is It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In. Oxide 230c is a metal oxide that can be used for oxide 230a or oxide 230b. In addition, a laminated structure of oxide 230c1 and oxide 230c2 can be used. In this case, in the metal oxide used for the oxide 230c2, the atomic ratio of In among the constituent elements is , the atomic ratio of In in the constituent elements in the metal oxide used for the oxide 230c1 is smaller than that By reducing the thickness, it is possible to suppress the diffusion of In to the insulator 250 side.

[0125] In addition, the oxide 230b preferably has crystallinity. It is preferable to use a crystalline oxide such as CAAC-OS. It has a dense structure with little oxygen deficiency and high crystallinity. Alternatively, the extraction of oxygen from the oxide 230b by the drain electrode can be reduced. This reduces the extraction of oxygen from the oxide 230b even when heat treatment is performed. Therefore, the transistor 200 can withstand high temperatures during manufacturing or thermal It is stable against nitrite.

[0126] Moreover, the oxide 230c1 and the oxide 230c2 preferably have crystallinity. For example, it is preferable to use CAAC-OS.

[0127] In addition, the energy of the conduction band minimum of the oxide 230a and the oxide 230c2 is It is preferable that the energy of the oxide is higher than the minimum energy of the conduction band of 30b. The electron affinity of the oxide 230a and the oxide 230c2 is greater than that of the oxide 230b. Small is preferable.

[0128] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, The energy level of the conduction band minimum changes gradually. The energy level of the conduction band minimum at the junction of the oxide 230c and the oxide 230b is It can also be said that the oxide layer is continuously changed or continuously bonded. At the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c In this case, the defect level density of the mixed layer formed in the step (b) is preferably reduced.

[0129] Specifically, the oxide 230a is composed of In:Ga:Zn=1:3:4 [atomic ratio], Alternatively, a metal oxide having an atomic ratio of 1:1:0.5 may be used. In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] The oxide 230c may be a metal oxide of In:Ga:Zn=1:3:4. [Atomic ratio], In:Ga:Zn=4:2:3 [Atomic ratio], Ga:Zn=2:1 [Atomic ratio] The metal oxide having a Ga:Zn=2:5 atomic ratio or a Ga:Zn=2:5 atomic ratio may be used. A specific example of the combination of the compound 230c1 and the oxide 230c2 is In:Ga:Zn = 4:2:3 [atomic ratio] and In:Ga:Zn = 1:3:4 [atomic ratio] stacked structure , In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio] Layer structure, In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio] In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide Layer structure, etc.

[0130] At this time, the main path of the carriers is the oxide 230b. By configuring 30c as described above, the interface between oxide 230a and oxide 230b and the oxide This can reduce the defect state density at the interface between the oxide 230b and the nitride 230c. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 has high A low on-state current and high frequency characteristics can be obtained.

[0131] The oxide 230 is preferably a metal oxide that functions as an oxide semiconductor. For example, the metal oxide that becomes the region 234 has a band gap of 2 eV or more, preferably It is preferable to use a material with a band gap of 2.5 eV or more. By using a metal oxide, the off-state current of a transistor can be reduced. By using a transistor, a semiconductor device with low power consumption can be provided.

[0132] Here, when the transistor 200 according to this embodiment is subjected to a heat treatment, the insulator 28 The behavior of oxygen 290 contained in 0 will be explained using Figures 5 and 6. 6 is an enlarged cross-sectional view of the transistor 200 in the channel length direction. As described above, in the semiconductor device shown in this embodiment, The insulator 280 containing excess oxygen is formed by the insulator 274, the oxide 230c1, the oxide 230c2, and the and insulator 254, and conductor 260, conductor 242a, and conductor 242 Therefore, as shown in Figures 5 and 6, even if heat treatment is performed, the insulating The oxygen 290 of 280 is insulator 274, oxide 230c1, oxide 230c2, and insulator The electric current is blocked by the edge 254 and does not directly reach the conductor 260, the conductor 242a, and the conductor 242b. does not spread.

[0133] Furthermore, when oxygen is released from the oxide 230b by the heat treatment and oxygen vacancies are formed, the oxide In the vicinity of the interface between the oxide 230b and the oxide 230c1, the oxide 230c1 is Oxygen diffuses into oxide 230b to compensate for the oxygen vacancies. The oxygen vacancies in the oxide 230b are repeatedly filled and diffused through the oxide 230b.

[0134] In addition, by supplying oxygen to the oxide 230b, oxygen vacancies are also formed in the oxide 230c1. At this time, the insulator 280 is formed near the interface between the insulator 280 and the oxide 230c1. Oxygen 290 diffuses from the oxide 230c1 to fill the oxygen vacancies. The oxygen 290 supplied to the oxide 230c is repeatedly compensated for oxygen vacancies in the oxide 230c. 5 and 6, the oxide 230c1 is diffused. The oxygen 290 diffuses into the oxide 230c2 and passes through the oxide 230c2 to the oxide 230. It may also be supplied to b.

[0135] Here, the oxide 230c1 is preferably CAAC-OS. 1, as shown in FIGS. 5 and 6, includes a layer 230c1P of crystals elongated in the ab-plane direction, The crystal region has a c-axis 230c1X perpendicular to the ab-plane direction. In the oxide 230c1, the c-axis 230c1X is approximately perpendicular to the surface on which the oxide 230c1 is formed. It is preferable that the oxide 230c1 is oriented in the direction of the oxide 230b. A region in which the c-axis 230c1X is oriented substantially perpendicular to the upper surface, and a conductor 242a , the c-axis 230c is approximately perpendicular to the side surfaces of the insulator 254 and the insulator 280. The region where 1X is oriented and the side surfaces of the conductor 242b, the insulator 254, and the insulator 280 and a region in which the c-axis 230c1X is oriented approximately perpendicular to the oxide. Similar to 230c1, oxide 230c2 is also a CAAC-OS, as shown in FIGS. As shown in the figure, the crystal layer 230c2P is elongated in the ab-plane direction, and the c-axis is perpendicular to the ab-plane direction. 230c2X.

[0136] CAAC-OS has the property that oxygen diffuses more easily in the ab plane direction than in the c axis direction. Therefore, the oxygen supplied from the insulator 280 to the oxide 230c1 and the oxide 230c2 As shown in FIG. 5, 290 preferentially extends to the vicinity of the interface between oxide 230c1 and oxide 230b. The oxygen vacancies in the oxide 230c can be compensated for by the diffusion of the oxygen atoms.

[0137] As described above, the transistor 200 described in this embodiment can be manufactured without undergoing heat treatment after completion. 2, oxygen is supplied from the insulator 280 to the oxide 230, and oxygen vacancies in the oxide 230 increase. Therefore, the current of the transistor 200 can be suppressed even in the lower layer of the stacked structure. The transistor 200 has stable electrical characteristics and is highly reliable. It can improve the performance.

[0138] 5 and 6, the oxygen 290 is present in the oxide 230c1 and the oxide 230c2. However, the present embodiment is not limited to this. The oxygen 290 diffuses only through the oxide 230c1, and the oxide 230c2 prevents the diffusion of the oxygen 290. By adopting such a structure, oxygen 290 is absorbed by the conductor 260. This can further reduce the risk of contamination.

[0139] On the oxide 230b, a conductor 242 is formed, which functions as a source electrode and a drain electrode. The thickness of the conductor 242 is, for example, For example, it may be 1 nm or more and 50 nm or less, and preferably 2 nm or more and 25 nm or less.

[0140] The conductor 242 may be aluminum, chromium, copper, silver, gold, platinum, tantalum, or nickel. Titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, Magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metal element selected from rontium and lanthanum, or an alloy containing the above metal elements Alternatively, it is preferable to use an alloy of the above-mentioned metal elements. tantalum, titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum, an oxide containing lanthanum and nickel, or the like. Tantalum oxide, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Nitrides containing strontium, ruthenium oxide, ruthenium nitride, and oxides containing strontium and ruthenium The oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. This is preferable because it is a material that maintains its conductivity even when absorbed.

[0141] The insulator 254, like the insulator 222, is made of oxygen (for example, oxygen atoms, oxygen molecules, etc.). ) (i.e., the oxygen is less likely to permeate). For example, The insulator 254 preferably has a lower oxygen permeability than the insulator 224. Furthermore, as shown in FIG. As shown in (C), the insulator 254 is disposed on the top and side surfaces of the conductor 242a and on the conductor 242b. the top and side surfaces of the oxide 230a and oxide 230b, and the top surface of the insulator 224. By adopting such a configuration, the oxygen contained in the insulator 280 However, it is possible to prevent the absorption of the conductor 242a and the conductor 242b.

[0142] As shown in FIG. 3D, the oxide 230a and the oxide 230b are formed on the conductor 24. The insulator 254 is formed up to the side surface in the channel width direction of the region overlapping with 2b (conductor 242a). With this configuration, the oxygen contained in the insulator 280 is absorbed by the conductor 2. This can further suppress absorption by the conductor 42a and the conductor 242b.

[0143] Furthermore, impurities such as water or hydrogen may enter the transistor 200 from the insulator 280 side. For example, the insulator 254 is , preferably has lower hydrogen permeability than the insulator 224 .

[0144] The insulator 254 is preferably formed by sputtering. The insulating film of the insulator 224 is formed by sputtering in an atmosphere containing oxygen. Oxygen can be added to the area adjacent to the body 254. This allows oxygen to be released from the area. Oxygen can be supplied to the oxide 230 through the insulator 224. 54 has the function of suppressing the upward diffusion of oxygen, and oxygen is isolated from the oxide 230. The insulator 222 can prevent oxygen from diffusing downward. By having the function of suppressing diffusion, oxygen is prevented from diffusing from the oxide 230 into the insulator 216. In this way, the oxide 230 serving as a channel forming region can be prevented from being broken down. Oxygen is supplied to the region 234 where the oxide 230 is present. This reduces the oxygen vacancies in the oxide 230 and This can prevent the transistor from becoming normally on.

[0145] The insulator 254 may have a multi-layer structure of two or more layers. 4, the first layer is formed using the sputtering method in an oxygen-containing atmosphere, and then the second layer is formed using the ALD method. The ALD method is a film formation method with good coating properties. Therefore, the unevenness of the first layer can prevent the formation of discontinuities and the like.

[0146] The insulator 254 may be, for example, an oxide of one or both of aluminum and hafnium. It is preferable to form an insulator containing an oxide of aluminum or hafnium. Insulators containing both oxides include aluminum oxide, hafnium oxide, and aluminum and It is preferable to use oxides containing hafnium (hafnium aluminate) and the like. Alternatively, the insulator 254 may be made of a nitride having high barrier properties, such as silicon nitride.

[0147] The insulator 250 functions as a gate insulator. The insulator 250 is preferably made of silicon oxide or silicon oxynitride. , silicon oxynitride, silicon nitride, silicon oxide with fluorine addition, carbon-added oxide silicon dioxide, silicon dioxide doped with carbon and nitrogen, and silicon dioxide with vacancies. In particular, silicon oxide and silicon oxynitride are stable against heat, This is preferable.

[0148] Like the insulator 224, the insulator 250 is made of an insulator that releases oxygen when heated. It is preferable to form the insulating material 250 as an insulating material from which oxygen is released by heating. By providing the oxide 230c in contact with the upper surface thereof, the region 234 of the oxide 230b is effectively In addition, like the insulator 224, the water or It is preferable that the concentration of impurities such as hydrogen is reduced. It is preferable that the thickness is m or more and 20 nm or less.

[0149] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen from the insulator 250 to the conductor 260, In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Moreover, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0150] The metal oxide may also function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, the metal oxide It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant. By making the insulating layer 250 and the metal oxide into a laminated structure, the insulating layer 250 is stable against heat. Therefore, the physical properties of the gate insulator can be improved. It is possible to reduce the gate potential applied during transistor operation while maintaining the film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. do.

[0151] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, tantalum, tungsten, titanium, tantalum, nickel, germanium, or magnesium Metal oxides containing one or more selected from the above can be used. Aluminum oxide, an insulator containing oxides of either or both aluminum and hafnium Aluminum, hafnium oxide, oxides containing aluminum and hafnium (hafnium oxide) It is preferable to use a laminate.

[0152] Although the conductor 260 is shown as having a two-layer structure in FIG. 1, it may have a single layer structure or a structure having three or more layers. The above laminated structure may also be used.

[0153] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing a small amount of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of at least (i).

[0154] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can prevent the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and nitride. It is preferable to use tantalum chloride, ruthenium, or ruthenium oxide.

[0155] The conductor 260b is made of a conductive material mainly composed of tungsten, copper, or aluminum. In addition, since the conductor 260 also functions as wiring, It is preferable to use a highly conductive material, such as tungsten, copper, or aluminum. The conductive material 260b may be a laminated structure. For example, a laminated structure of titanium, titanium nitride and the above conductive material may be used. .

[0156] The insulator 280 is connected to the insulator 224, the oxide 230, and the conductor via the insulator 254. The insulator 280 is preferably provided on the insulating layer 242. The insulator 280 preferably contains oxygen that is desorbed by heating. For example, the insulator 280 may be silicon oxide, silicon oxynitride, silicon nitride oxide, Fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide It is preferable that the silicon oxide has a porous structure or a porous silicon oxide. Silicon oxide and silicon oxynitride are preferred because they are thermally stable. Materials such as silicon, silicon oxynitride, and silicon oxide with vacancies are desorbed by heating. This is preferable because it allows for easy formation of a region containing oxygen.

[0157] It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. In addition, the top surface of the insulator 280 may be flattened.

[0158] The insulator 274, like the insulator 210, is configured to prevent impurities such as water or hydrogen from entering from above. It is preferable that the insulating layer functions as a barrier insulating film that prevents the insulator 280 from being mixed with the insulating layer. The insulator 274 may be, for example, an insulator that can be used for the insulator 210, the insulator 254, etc. Just use

[0159] The insulator 274, like the insulator 222, is made of oxygen (e.g., oxygen atoms, oxygen molecules, etc.). ) (i.e., the oxygen is less likely to permeate). For example, The insulator 274 preferably has a lower oxygen permeability than the insulator 280. As shown in (C), the insulator 274 is disposed on the upper surface of the conductor 260, the upper surface of the insulator 250, and the oxide. It is preferable that the upper surface of the insulating layer 230c contacts the upper surface of the insulating layer 230c and the upper surface of the insulating layer 280. By using this composition, it is possible to suppress the oxygen contained in the insulator 280 from being absorbed by the conductor 260. It is possible.

[0160] Furthermore, the insulator 274 prevents impurities such as water or hydrogen from entering the transistor from the insulator 281 side. It is preferable that the insulating film functions as a barrier insulating film that prevents the metal from being mixed into the sintered body 200. For example, Preferably, insulator 274 has a lower hydrogen permeability than insulator 280 .

[0161] The insulator 274 is preferably formed by sputtering. It is more preferable that the insulating film is formed by sputtering in an atmosphere containing oxygen. The insulator 274 is formed by sputtering, so that the insulator 274 of the insulator 280 Excess oxygen can be added to the area adjacent to the contact area. Oxygen can be supplied to the oxide 230b through the insulator 230c. 74 has a function of suppressing the upward diffusion of oxygen, so that oxygen does not diffuse upward from the insulator 280. In addition, the insulator 254 prevents oxygen from diffusing downward. By having the function of preventing oxygen from diffusing downward from the insulator 280, In this way, the oxide 230b is formed in a region 234 that serves as a channel forming region. This reduces the oxygen vacancies in the oxide 230b, and It is possible to suppress marionation.

[0162] In addition, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 274. The insulator 281, like the insulator 224, has a low impurity concentration such as water or hydrogen in the film. is preferably reduced.

[0163] Also, the insulating material 281, the insulating material 274, the insulating material 280, and the insulating material 254 are formed. The conductor 240a and the conductor 240b are placed in the opening. 240b are provided facing each other with the conductor 260 in between. The height of the upper surface of 240b may be flush with the upper surface of the insulator 281.

[0164] The inner walls of the openings of the insulators 281, 274, 280, and 254 The insulator 241a is provided in contact with the first conductor of the conductor 240a. A conductor 242a is located at least partially on the bottom of the opening. , the conductor 240a contacts the conductor 242a. Similarly, the insulator 281, the insulator 274, the insulator An insulator 241b is provided in contact with the inner wall of the opening of the edge 280 and the insulator 254, The first conductor of the conductor 240b is formed in contact with the side surface of the opening. The conductor 242b is located at least in a part of the area where the conductor 240b is in contact with the conductor 242b. do.

[0165] The conductors 240a and 240b are mainly made of tungsten, copper, or aluminum. It is preferable to use a conductive material containing the conductive material 240a and the conductive material 240b. 0b may have a laminated structure.

[0166] In addition, when the conductor 240 has a laminated structure, the oxide 230a, the oxide 230b, the conductor 242, insulator 254, insulator 280, insulator 274, and conductive material in contact with insulator 281. The body is made of a conductive material that has the function of suppressing the permeation of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or It is preferable to use ruthenium oxide or ruthenium oxide. The conductive material having the function of suppressing overflow may be used in a single layer or a multilayer structure. By using the material, the oxygen added to the insulator 280 is transferred to the conductor 240a and the conductor 240b. In addition, it is possible to prevent water or hydrogen from being absorbed into the insulator 281. Which impurities are mixed into the oxide 230 through the conductors 240a and 240b? can be suppressed.

[0167] The insulator 241a and the insulator 241b can be used as the insulator 254, etc. An insulator (for example, aluminum oxide or silicon nitride) may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 254, the insulator 280 Impurities such as water or hydrogen from the above-mentioned electrodes pass through the conductors 240a and 240b and are transferred to the oxygen In addition, the oxygen contained in the insulator 280 can be prevented from being mixed into the oxide 230. This can prevent the electric current from being absorbed by the conductor 240a and the conductor 240b.

[0168] Although not shown, the conductive material 240a and the conductive material 240b are arranged in contact with each other on their upper surfaces. A conductor functioning as a wire may be disposed. The conductor functioning as a wiring may be made of tungsten. It is preferable to use a conductive material containing copper or aluminum as a main component. The conductor may have a laminated structure, for example, a layer of titanium, titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator. You may do so.

[0169] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0170] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or A conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, and silicon substrates. Fire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), resin substrate Semiconductor substrates include those made of silicon or germanium. semiconductor substrates, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide Compound semiconductor substrates made of gallium oxide, zinc oxide, and gallium oxide are also available. A semiconductor substrate having an insulating region inside the semiconductor substrate, for example, SOI (Silicon on Insulator) Conductive substrates include graphite substrates and metal substrates. , alloy substrates, conductive resin substrates, etc. Or, substrates having metal nitrides, metal oxides, etc. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulating substrate. Substrate, substrate with conductor or insulator provided on semiconductor substrate, substrate with semiconductor or insulator provided on conductive substrate There are also substrates with elements mounted on them. The elements provided on the substrate may include a capacitance element, a resistance element, a switch element, a light-emitting element, and the like. There are various types of memory elements.

[0171] <<Insulators>> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0172] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. Therefore, materials should be selected accordingly.

[0173] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides with aluminum, aluminum and hafnium, oxides with silicon and hafnium, oxides with silicon and hafnium, Examples include oxynitrides with hafnium, or nitrides with silicon and hafnium.

[0174] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, Silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies, or resin be.

[0175] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. Insulators having a function of controlling the temperature (insulator 214, insulator 222, insulator 254, and insulator By surrounding the transistor with a metal layer (such as 274), the electrical characteristics of the transistor can be stabilized. Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include porosity. Uron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators including titanium, hafnium, or tantalum may be used in single or multilayer configurations. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttria oxide ammonium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or thiamin oxide Metal oxides such as tantalum, aluminum nitride, titanium aluminum nitride, titanium nitride, and nitride Metal nitrides such as silicon oxide or silicon nitride can be used.

[0176] In addition, the insulator that functions as the gate insulator has a region containing oxygen that is desorbed by heating. For example, it is preferable that the insulating material has a region containing oxygen that is desorbed by heating. By forming a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, the oxide The oxygen deficiency of 230 can be compensated for.

[0177] <<Conductors>> Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sium, Zirconium, Beryllium, Indium, Ruthenium, Iridium, Strontium Metal elements selected from ammonium, lanthanum, etc., or alloys containing the above-mentioned metal elements It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel, or an oxide containing lanthanum and nickel. Tantalum, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitride, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. It is a material that maintains conductivity even after oxidation, and is therefore preferred. Highly conductive semiconductors, such as polycrystalline silicon, nickel silicide, Silicide may also be used.

[0178] Alternatively, a plurality of conductive layers made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining a conductive material containing a silicon dioxide.

[0179] When an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminated structure in which a conductive material containing oxygen is used. It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0180] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate electrode. It is preferable to use a conductive material containing a metal element and oxygen. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. Alternatively, a conductive material containing nitrogen, such as indium tin oxide or tungsten oxide, may be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may also be used. By using such a material, the channel is formed. In some cases, hydrogen contained in the metal oxides surrounding the outer insulating layer can be captured. It may be possible to capture hydrogen that is mixed in from the surroundings.

[0181] <<Metal oxides>> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0182] The metal oxide preferably contains at least indium or zinc. It is preferable that the alloy contains aluminum and zinc. It is preferable that the alloy contains boron, titanium, iron, or the like. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or Or, multiple types may be included.

[0183] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M can be aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, a combination of the aforementioned elements may be used.

[0184] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0185] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor), and Examples include amorphous oxide semiconductors.

[0186] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0187] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor that uses a metal oxide containing metals in the channel formation region is normally on. Therefore, the concentration of alkali metals or alkaline earth metals in metal oxides It is preferable to reduce the degree of Al in the metal oxide obtained by SIMS. Potassium metal or alkaline earth metal concentration (Secondary Ion Mass Spectroscopy (SIMS) The concentration obtained by Daily Ion Mass Spectrometry (DPI) was calculated as x10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Below do.

[0188] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with the oxygen atoms that bond with the metal atoms, forming chiral ions. Therefore, metal oxides containing hydrogen can be used. Such a transistor is likely to have normally-on characteristics.

[0189] For this reason, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. is the hydrogen concentration obtained by SIMS in metal oxides, expressed as 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than 5x1 0 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. By doing so, stable electrical properties can be imparted.

[0190] It is preferable to use a thin film with high crystallinity as the metal oxide used as the semiconductor of a transistor. Use of the thin film can improve the stability or reliability of the transistor. The thin film may be, for example, a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide. However, thin films of single crystal metal oxides or thin films of polycrystalline metal oxides are Formation on a substrate requires high temperature or laser heating processes. This increases the cost of the process and also reduces throughput.

[0191] In 2009, we developed an In-Ga-Zn oxide (CAAC-IGZO) with a CAAC structure. The discovery of a new compound called 'anti-cancer drug' has been reported in Non-Patent Documents 1 and 2. CAAC-IGZO has a c-axis orientation, the grain boundaries are not clearly visible, and it can be grown at low temperatures. It has been reported that it is possible to form a thin film on a substrate using CAAC-IGZO. The resulting transistors have been reported to have excellent electrical properties and reliability.

[0192] In 2013, we also developed an In-Ga-Zn oxide (nc-IGZO) with an nc structure. Here, nc-IGZO is a material that can be grown in minute regions ( For example, the atomic arrangement has periodicity in the region of 1 nm or more and 3 nm or less, and It has been reported that no regularity is observed in the crystal orientation between the two.

[0193] In Non-Patent Documents 4 and 5, the above-mentioned CAAC-IGZO, nc-IGZO, The average crystal size of IGZO thin films and low-crystalline IGZO thin films was measured by electron beam irradiation. The change in the thickness is shown in Fig. 1. In a thin film of IGZO with low crystallinity, before the electron beam irradiation, Even in thin films, crystalline IGZO of about 1 nm has been observed. In this case, completely amorphous structure Furthermore, it has been reported that the presence of IGZO with low crystallinity could not be confirmed. Compared with the thin films of CAAC-IGZO and nc-IGZO, the thin films of CAAC-IGZO and nc-IGZO are more resistant to electron beam irradiation. Therefore, CAA is a promising semiconductor for transistors. It is preferable to use a thin film of C-IGZO or a thin film of nc-IGZO.

[0194] Transistors using metal oxides have extremely low leakage current when they are off. Specifically, the off-state current per 1 μm of the transistor channel width is yA / μm (10 -2 4 A / μm) order is shown in Non-Patent Document 6. For example, Low-power CPUs that utilize the low leakage current characteristics of the transistors used It has been disclosed (see Non-Patent Document 7).

[0195] In addition, the leakage current of a transistor using a metal oxide is low. The application of transistors to display devices has been reported (see Non-Patent Document 8). The displayed image changes several dozen times per second. The refresh rate is also called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, is the cause of eye fatigue. Therefore, the refresh rate of the display device is reduced to improve image clarity. It has been proposed to reduce the number of times the display is rewritten. This driving method can reduce the power consumption of the display device. This is called idling stop (IDS) drive.

[0196] The discovery of the CAAC and nc structures was based on the discovery of metal oxides with the CAAC or nc structures. The electrical characteristics and reliability of the transistor using the material are improved, and the manufacturing process cost is reduced. This contributes to improving throughput and reducing power consumption. Taking advantage of this property, research into the application of this transistor to display devices and LSIs is underway. are.

[0197] <Method for manufacturing semiconductor device> Next, a semiconductor device having a transistor 200 according to the present invention shown in FIG. 1 will be fabricated. The manufacturing method will be described with reference to Figs. 5 to 12. In Figs. 5 to 12, (A ) shows a top view. Also, (B) of each figure shows the part indicated by the dashed line A1-A2 in (A). 1. This is a cross-sectional view corresponding to the position of the transistor 200, and is also a cross-sectional view taken along the channel length direction of the transistor 200. In addition, (C) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A). , (D) in each figure is a cross-sectional view of the transistor 200 in the channel width direction. ) is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in each figure. In the plan view, some elements are omitted for clarity of illustration.

[0198] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The film formation of 14 was carried out by sputtering, chemical vapor deposition (CVD), r Deposition), molecular beam epitaxy (MBE) beam epitaxy, pulsed laser deposition (PLD) Deposition) method or ALD (Atomic Layer Deposit) This can be done using the ion method or the like.

[0199] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0200] The plasma CVD method can produce high-quality films at relatively low temperatures. This film formation method does not use a plasma, so it is possible to reduce plasma damage to the object being treated. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc. included in a semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. In addition, the thermal CVD method can increase the yield of semiconductor devices. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0201] In addition, the ALD method utilizes the self-regulating properties of atoms to deposit atoms one layer at a time. This allows for ultra-thin film deposition, film deposition on structures with high aspect ratios, and pinholes. It is possible to form films with few defects such as holes, and to form films with excellent coverage, and to form films at low temperatures. In addition, the ALD method includes a plasma-based film formation method called PEALD ( This includes the Plasma Enhanced ALD method. This may be preferable as it allows film formation at a lower temperature. Some of the films contain impurities such as carbon. In comparison with the film formed by the film forming method of the first embodiment, the film may contain a large amount of impurities such as carbon. The quantitative determination of impurities was carried out by X-ray photoelectron spectroscopy (XPS). This can be done using spectroscopy.

[0202] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0203] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transport or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0204] In this embodiment, the insulator 214 is formed by depositing silicon nitride by the CVD method. In this way, an insulator that is difficult for copper to penetrate, such as silicon nitride, is used as the insulator 214. Therefore, a metal that easily diffuses, such as copper, is used for the conductor layer (not shown) below the insulator 214. Even if the metal is present, the metal can be prevented from diffusing into layers above the insulator 214.

[0205] Next, an insulator 216 is formed on the insulator 214. The insulator 216 is formed by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 216 is formed by depositing silicon oxide by the CVD method.

[0206] Next, an opening is formed in the insulator 216 by lithography, reaching the insulator 214. The openings include, for example, grooves and slits. The area where the openings are formed is called a "region." The opening may be formed by wet etching. In addition, the insulator 214 is preferably an insulating material. An insulating layer that acts as an etching stopper when etching the edge 216 to form the opening. For example, silicon oxide is used for the insulator 216 that forms the opening. In this case, the insulator 214 is silicon nitride as an insulator that functions as an etching stopper. Silicon, aluminum oxide, and hafnium oxide are preferably used.

[0207] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the resist patterned area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. For example, KrF excimer laser light, ArF excimer laser light, Laser light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. An immersion technique may be used in which the substrate is filled with a liquid (for example, water) and exposed to light. Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not required. Which dry etching process should be performed, which wet etching process should be performed, and which dry etching process should be performed? wet etching after treatment, or wet etching after dry etching A processing can be performed.

[0208] In addition, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film that will become the insulator 216 is formed on the insulating film that will become the hard mask material. An insulating film or a conductive film is formed, a resist mask is formed on it, and a hard mask material is etched. By this etching, a hard mask of a desired shape can be formed. The etching of the insulating film may be performed after removing the resist mask, or after removing the resist mask. In the latter case, the resist mask may be removed during etching. After etching the insulating film that will become the insulator 216, the hard mask is removed by etching. On the other hand, if the hard mask material does not affect the subsequent process or can be used in the subsequent process, If the hard mask can be removed, it is not necessary to remove the hard mask.

[0209] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate type electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching device or the like can be used.

[0210] After the opening is formed, a conductive film that will become the first conductor of the conductor 205 is formed. It is preferable to use a conductive barrier film that has the function of suppressing the permeation of impurities and oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. are tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum tungsten The conductive film that becomes the first conductor of the conductor 205 can be a laminated film with a stainless alloy. The film is formed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. This can be done.

[0211] In this embodiment, the conductive film that becomes the first conductor of the conductor 205 is made of tantalum nitride, Alternatively, a film in which titanium nitride is laminated on tantalum nitride is formed. By using such a metal nitride as a conductor, the second conductor of the conductor 205 Even if a metal that easily diffuses, such as copper, is used, the metal does not diffuse outward from the first conductor of the conductor 205. It is possible to suppress dispersion.

[0212] Next, a second conductor of the conductor 205 is formed on the conductive film that will become the first conductor of the conductor 205. The conductive film is formed by a sputtering method, a CVD method, an MBE method, This can be done by using a PLD method, an ALD method, or the like. The second conductive film in 05 is made of low-resistance materials such as tungsten, copper, and aluminum. A conductive material is deposited.

[0213] Next, CMP (Chemical Mechanical Polishing) processing By performing the above, a conductive film that becomes the first conductor of the conductor 205 and a second conductor of the conductor 205 are formed. A portion of the conductive film that will become the conductor is removed by polishing to expose the insulator 216. Only at the opening, a conductive film that becomes the first conductive material of the conductor 205 and a second conductive material of the conductor 205 are formed. As a result, the conductive film that becomes the conductor remains. , and a second conductor of the conductor 205 can be formed (FIG. 5 (See FIG. 10.) Note that the CMP process may remove a portion of the insulator 216.

[0214] The method for manufacturing the insulator 216 and the conductor 205 is not limited to the above. For example, a conductive film that will become the conductor 205 is formed on the insulator 214, and then the conductive film is formed by lithography. The conductive film is processed to form the conductor 205. An insulating film that will become the insulator 216 is provided, and a part of the insulating film is removed by CMP processing to form the conductor 205 The conductor 205 and the insulator 216 may be formed by removing the insulating film 216 until a portion of the insulating film 216 is exposed. stomach.

[0215] As described above, the conductor 205 and the insulator 216 are formed by using the CMP process. This can improve the flatness of the upper surfaces of the conductor 205 and the insulator 216, and can be oxidized in a later process. The crystallinity of the CAAC-OS constituting the oxide 230a, the oxide 230b, and the oxide 230c is It can be improved.

[0216] Next, the insulator 222 is formed on the insulator 216 and the conductor 205. As the insulating layer, an insulating film containing oxides of one or both of aluminum and hafnium is formed. It is recommended to use an insulator containing oxides of either or both of aluminum and hafnium. Examples include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium. It is preferable to use aluminum and hafnium. Insulators containing oxides of one or both of these metals have barrier properties against oxygen, hydrogen, and water. The insulator 222 has a barrier property against hydrogen and water, and thus the transistor The hydrogen and water contained in the structure provided around the rotor 200 pass through the insulator 222. Diffusion into the inside of the transistor 200 is suppressed, and oxygen vacancies are generated in the oxide 230. can be suppressed.

[0217] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an A method. This can be done using the LD method or the like.

[0218] Next, an insulating film that will become the insulator 224 is formed on the insulator 222. The insulating film is formed by the sputtering method, CVD method, MBE method, PLD method, or ALD method. This can be done using

[0219] Subsequently, it is preferable to carry out a heat treatment. The heat treatment is preferably carried out at a temperature of 250°C or higher and 650°C or lower. Preferably, the temperature is 300°C or higher and 500°C or lower, more preferably 320°C or higher and 450°C or lower. Heat treatment should be carried out in a nitrogen or inert gas atmosphere, or in an atmosphere containing oxidizing gases at a concentration of 10 ppm or less. The heat treatment is carried out in an atmosphere containing 1% or more, or 10% or more. Alternatively, the heat treatment may be performed in a nitrogen or inert gas atmosphere, followed by desorption. To compensate for the lost oxygen, an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas is used. The heat treatment may be carried out in an atmosphere.

[0220] In this embodiment, after performing the treatment at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, Then, the insulating film is heated in an oxygen atmosphere at 400°C for 1 hour. Impurities such as water and hydrogen contained in the body 224 can be removed.

[0221] The heat treatment may be performed after the formation of the insulator 222. Heat treatment conditions can be used.

[0222] Here, in order to form an excess oxygen region in the insulator 224, a plasma containing oxygen is used under reduced pressure. The oxygen-containing plasma treatment may be, for example, a high-density plasma treatment using microwaves. It is preferable to use a device having a power source that generates plasma. Alternatively, RF ( The plasma may have a power source that applies high-density plasma. By doing so, high density oxygen radicals can be generated, and by applying RF to the substrate side, As a result, oxygen radicals generated by the high-density plasma are efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, In order to compensate for the desorbed oxygen, a plasma treatment containing oxygen may be performed. By appropriately selecting the processing conditions, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, the heat treatment is not necessary.

[0223] Here, aluminum oxide is formed on the insulator 224 by, for example, a sputtering method. The aluminum oxide may be deposited and then CMPed until it reaches the insulator 224. By performing CMP, the surface of the insulator 224 is flattened and smoothed. By placing the aluminum oxide on the insulator 224 and performing CMP, C In addition, a part of the insulator 224 is polished by CMP, which makes it easy to detect the end point of the CMP. However, the thickness of the insulator 224 may be reduced by adjusting the thickness during the deposition of the insulator 224. By planarizing and smoothing the surface of the insulator 224, the surface is protected from the oxide film that will be formed later. This may prevent the deterioration of the coverage rate and the decrease in the yield of the semiconductor device. On the insulator 224, an aluminum oxide film is formed by sputtering. Preferably, oxygen can be added to the insulator 224 .

[0224] Next, an oxide film that will become oxide 230a and an oxide film that will become oxide 230b are formed on the insulator 224. It is preferable to form the oxide films in succession without exposing them to the air environment. By forming the film without exposing it to the atmosphere, the oxide film that becomes the oxide 230a and the oxide 2 This prevents impurities or moisture from the atmospheric environment from adhering to the oxide film that will become 30b. The vicinity of the interface between the oxide film that will become oxide 230a and the oxide film that will become oxide 230b is kept clean. It is possible to do this.

[0225] The oxide film that becomes the oxide 230a and the oxide film that becomes the oxide 230b are formed by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. .

[0226] For example, an oxide film that will become oxide 230a and an oxide film that will become oxide 230b are formed by sputtering. When forming a film by the sputtering method, oxygen or a mixture of oxygen and rare gas is used as the sputtering gas. By increasing the oxygen content of the sputtering gas, film formation is The excess oxygen in the oxide film can be increased. When forming a film by this method, the above-mentioned In-M-Zn oxide target can be used. do.

[0227] In particular, when forming the oxide film that becomes the oxide 230a, the amount of oxygen contained in the sputtering gas is A part of the oxide may be supplied to the insulator 224. Therefore, the oxide film that becomes the oxide 230a The proportion of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, Preferably, it should be set to 100%.

[0228] In addition, when the oxide film that becomes the oxide 230b is formed by a sputtering method, the sputtering The percentage of oxygen contained in the gas is 1% or more and 30% or less, preferably 5% or more and 20% or less. When the film is formed using this method, an oxygen-deficient oxide semiconductor is formed. The transistor used in the channel forming region has a relatively high field effect mobility. By forming the film while heating the substrate, the crystallinity of the oxide film can be improved. However, one embodiment of the present invention is not limited to this. When forming by sputtering, the ratio of oxygen contained in the sputtering gas is set to 30%. When the film is formed at a concentration of more than 100%, preferably 70% to 100%, an oxygen-excess type The oxide semiconductor having an oxygen-excess type is formed in the channel formation region. Transistors have relatively high reliability.

[0229] In this embodiment, the oxide film that becomes the oxide 230a is formed by sputtering. In:Ga:Zn=1:1:0.5 (2:2:1), or The film is formed using a target with an atomic ratio of 1:3:4. The oxide film was prepared by sputtering with a composition of In:Ga:Zn=4:2:4.1 [atomic ratio]. The film is formed using a target of the following formula: By selecting the material, it is possible to form the oxide 230 in accordance with the desired properties.

[0230] Here, the insulator 222, the insulator 224, the oxide film that becomes the oxide 230a, and the oxide 2 It is preferable to form the oxide film 30b without exposing it to the atmosphere. A chamber-type film forming device may be used.

[0231] Next, a heat treatment may be carried out. The heat treatment may be carried out under the heat treatment conditions described above. The heat treatment can form an oxide film that becomes the oxide 230a and an oxide film that becomes the oxide 230b. In this embodiment, the nitrogen atmosphere is used. After the treatment at 400°C in an oxygen atmosphere for 1 hour, The treatment is carried out at a temperature of 100°C for 1 hour.

[0232] Next, a conductive film that will become the conductive layer 242A is formed on the oxide film 232B. The film is formed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. It is possible to do so.

[0233] Next, the oxide film that will become the oxide 230a, the oxide film that will become the oxide 230b, and the conductive layer 24 The conductive film to be formed into 2A is processed into an island shape, and oxide 230a, oxide 230b and conductive layer 2 In this step, the oxide 230a of the insulator 224 is not overlapped. The thickness of the film in the hot area may be thin (see Figure 7).

[0234] Here, the oxide 230a, the oxide 230b, and the conductive layer 242A are at least partially The oxide 230a, the oxide 230b, and the conductor 205 are formed so as to overlap each other. The side surface of the conductive layer 242A is preferably approximately perpendicular to the upper surface of the insulator 222. The oxide 230a, the oxide 230b, and the side of the conductive layer 242A are on the insulator 222. By being approximately perpendicular to the surface, when providing a plurality of transistors 200, the area can be reduced, Alternatively, the oxide 230a, the oxide 230b, and the conductive layer 242 may be formed by the same method. The angle between A and the top surface of the insulator 222 may be small. The angle between the side surface of the oxide 230a and the top surface of the insulator 222 is 60° or more and 70° or less. By forming the insulating film 27 in such a shape, it is possible to prevent the insulating film 27 from being damaged in the subsequent process. 3) and other coating properties are improved, and defects such as voids can be reduced.

[0235] In addition, a curved surface is provided between the side surface of the conductive layer 242A and the upper surface of the conductive layer 242A. In other words, it is preferable that the edges of the side surfaces and the top surface are curved (hereinafter referred to as rounded). The curved surface has a radius of curvature of, for example, 3 nm at the end of the conductive layer 242A. The thickness is from 10 nm to 100 nm, preferably from 5 nm to 6 nm. This improves the film coverage in the subsequent film formation process.

[0236] The oxide film and the conductive film may be processed by lithography. This processing can be performed using a dry etching method or a wet etching method. The etching method is suitable for microfabrication.

[0237] Next, on the insulator 224, the oxide 230a, the oxide 230b and the conductive layer 242A, An insulating film 254A is formed (see FIG. 8).

[0238] The insulating film 254A is preferably an insulating film having a function of suppressing oxygen permeation. For example, it is preferable to form an aluminum oxide film by sputtering. Depositing an aluminum oxide film by sputtering using a gas containing oxygen This allows oxygen to be implanted into the insulator 224. That is, the insulator 224 is made of excess It can have oxygen.

[0239] Next, an insulating film that will become the insulator 280 is formed on the insulating film 254A. The insulating film is formed by a method such as sputtering, CVD, MBE, PLD, or ALD. For example, the insulating film that becomes the insulator 280 can be formed by PECVD. In addition, for example, the insulating film that becomes the insulator 280 may be formed using The film may be a silicon oxide film formed by sputtering.

[0240] Next, the insulating film that will become the insulator 280 is subjected to CMP processing to form an insulator 280A with a flat upper surface. (See Figure 8).

[0241] Next, a part of the insulator 280A, a part of the insulating film 254A, and a part of the conductive layer 242A are The opening is processed to reach the oxide 230b. The opening overlaps the conductor 205. The opening allows the conductor 242a, the conductor 242b, and the insulating material to pass through. The edge 254 and the insulator 280 are formed (see FIG. 9).

[0242] In addition, part of the insulator 280, part of the insulating film 254A, and part of the conductor are processed as follows. For example, a part of the insulator 280A may be dry-etched. The insulating film 254A is processed by a wet etching method, and a part of the insulating film 254A is processed by a wet etching method. A part of the insulating film may be processed by dry etching.

[0243] By using conventional dry etching and other processes, the etching gas The resulting impurities adhere to or are present on the surface or inside of the oxide 230a and the oxide 230b. Impurities can be, for example, fluorine or chlorine.

[0244] In order to remove the above impurities, cleaning is performed. These include wet cleaning, plasma treatment using plasma, and cleaning by heat treatment. The above cleaning methods may be combined as appropriate.

[0245] Wet cleaning involves the use of oxalic, phosphoric, or hydrofluoric acids in carbonated or pure water. The cleaning process may be carried out using an aqueous solution diluted with water. Alternatively, pure water or carbonated water may be used. Ultrasonic cleaning may also be performed.

[0246] Next, a heat treatment may be carried out. The heat treatment is carried out under reduced pressure without exposure to the atmosphere. The oxide film 230C1 may be formed continuously. The moisture and hydrogen adsorbed on the surface of the oxide 230b are removed. The moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be reduced. The treatment temperature is preferably 100° C. or more and 400° C. or less. The temperature is set to 200°C (see Figure 10).

[0247] The oxide film 230C1 is formed by sputtering, CVD, MBE, PLD, or This can be done using the ALD method or the like. The oxide film that becomes the oxide 230a or the oxide film that becomes the oxide 230b is formed by the same film forming method. In this embodiment, the oxide film 230C1 is formed by using a spatula. By using the quartz crystal deposition method, a target with an atomic ratio of In:Ga:Zn=4:2:4.1 was prepared. A film is formed using this.

[0248] In particular, when the oxide film 230C1 is formed, a part of the oxygen contained in the sputtering gas is oxidized. The oxide film 230C may be provided with a layer 230a and an oxide film 230b. The proportion of oxygen contained in the sputtering gas in step 1 is 70% or more, preferably 80% or more, and more preferably 100% or more. More preferably, it is set to 100%.

[0249] Furthermore, the oxide film 230C2 is continuously formed by the sputtering method, the CVD method, the MBE method, etc. The oxide film 230C2 can be formed by a PLD method, an ALD method, or the like. Depending on the characteristics, the oxide film that becomes oxide 230a or the oxide film that becomes oxide 230b may be selected. In this embodiment, the oxide film 230C2 is formed by using the same film forming method. 230C2 was deposited by sputtering with a ratio of In:Ga:Zn=1:3:4 [atomic ratio] The film is formed using a target of

[0250] Next, a heat treatment may be carried out. The heat treatment is carried out under reduced pressure without exposure to the atmosphere. The insulating film 250A may be formed continuously. The moisture and hydrogen adsorbed on the surface of 230C2 are removed, and the oxide 23 The moisture concentrations in the oxide 230a, oxide 230b, oxide film 230C1, and oxide film 230C2 are The hydrogen concentration can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. I wish.

[0251] The insulating film 250A is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating film 250A can be formed by a CVD method using a nitriding agent. It is preferable to form a film of silicon dioxide. The film forming temperature when forming the insulating film 250A is The temperature is preferably 350°C or higher and lower than 450°C, and particularly preferably around 400°C. By depositing this at 400°C, an insulator with few impurities can be formed.

[0252] Next, the conductive film 260Aa and the conductive film 260Ab are formed. The conductive film 260Ab can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an A method. This can be done using the LD method or the like. For example, it is preferable to use the CVD method. In this embodiment, the conductive film 260Aa is formed by the ALD method, and the conductive film 260B is formed by the CVD method. 260Ab is deposited (see Figure 11).

[0253] Next, by CMP processing, the oxide film 230C1, the oxide film 230C2, the insulating film 250A, The conductive film 260Aa and the conductive film 260Ab are polished until the insulator 280 is exposed. Therefore, the oxide 230c1, the oxide 230c2, the insulator 250, and the conductor 260 (conductive 12, a conductive body 260a and a conductive body 260b are formed.

[0254] Next, heat treatment may be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. The heat treatment is carried out for 1 hour. The moisture concentration in the insulators 250 and 280 is reduced by the heat treatment. The degree and hydrogen concentration can be reduced.

[0255] Next, an insulating film that will become the insulator 274 is formed on the insulator 280. The insulating film is formed by the sputtering method, CVD method, MBE method, PLD method, or ALD method. The insulating film that becomes the insulator 274 can be formed by, for example, sputtering. It is preferable to form the aluminum oxide film by sputtering. Therefore, by forming an aluminum oxide film, the insulator 280 is desorbed by heat treatment. A substance can be added (see FIG. 12).

[0256] Next, heat treatment may be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. The heat treatment is carried out for 1 hour. By this heat treatment, the insulator 274 is formed into the insulator 280. The added oxygen can be supplied to oxide 230b via oxide 230c.

[0257] Next, an insulator that will become the insulator 281 may be formed on the insulator 274. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using a method such as the above (see FIG. 12).

[0258] Next, the conductor 24 is applied to the insulator 254, the insulator 280, the insulator 274, and the insulator 281. An opening is formed that reaches the conductive material 242a and the conductive material 242b. The opening is formed by lithography. This can be done using the method.

[0259] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator The conductive film 241 is formed by sputtering, CVD, MBE, PL The insulating film to be the insulator 241 can be formed by the ALD method or the ALD method. In the case of ALD, it is preferable to use an insulating film that has a function of suppressing oxygen permeation. It is preferable to form an aluminum oxide film by anisotropic etching. For example, dry etching may be performed. This prevents oxygen from permeating from the outside, and the conductors 240a and 240b to be formed next are In addition, the oxidation of the conductive material 240a and the conductive material 240b can be prevented. This can prevent impurities such as hydrogen from diffusing to the outside.

[0260] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240b has a function of suppressing the permeation of impurities such as water and hydrogen. It is desirable to use a laminated structure containing a conductive material such as tantalum nitride or titanium nitride. The conductor 240 may be a laminate of tungsten, molybdenum, copper, or the like. The conductive film is formed by sputtering, CVD, MBE, PLD or ALD. This can be done using methods such as the

[0261] Next, a CMP process is performed to remove the conductive film that will become the conductors 240a and 240b. A portion of the insulating film is removed to expose the insulator 281. As a result, the conductive film remains only in the opening. By doing so, it is possible to form the conductors 240a and 240b with flat upper surfaces ( (See FIG. 1.) Note that the CMP process may remove a portion of the insulator 281.

[0262] Through the above steps, a semiconductor device including the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIGS. 5 to 12, the semiconductor device can be manufactured by using the manufacturing method of the semiconductor device described in this embodiment mode. In this way, the transistor 200 can be manufactured.

[0263] In order to manufacture a semiconductor device in which transistors are stacked as shown in the above embodiment, The process is repeated to stack the transistors 200. Although an extra heat treatment is required after the formation, as described above, the insulating layer 280 is removed from the oxide layer 230. By supplying oxygen to the oxide 230, it is possible to prevent oxygen vacancies from increasing in the oxide 230. , and the fluctuation of the electrical characteristics of the lower layer transistor 200 is suppressed, and stable electrical characteristics are obtained. Furthermore, it is possible to provide the semiconductor device with good reliability.

[0264] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. It is possible.

[0265] <Modification of Semiconductor Device> Hereinafter, with reference to FIG. 13, the present invention will be described, which is different from the example of the configuration of the semiconductor device shown above. An example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described.

[0266] 13(A) shows a top view, and FIG. 13(B) shows A1 shown in FIG. 1A is a cross-sectional view corresponding to the portion indicated by the dashed line in FIG. 1A, and shows the channel length of the transistor 200. Also, Fig. 13(C) is a cross-sectional view of the A3-A4 dashed line in Fig. 13(A). 1 is a cross-sectional view corresponding to the portion shown in FIG. 1, and is also a cross-sectional view in the channel width direction of the transistor 200. Also, FIG. 13(D) corresponds to the area indicated by the dashed line A3-A4 in FIG. 13(A). In the top view of FIG. 13(A), some elements are omitted for clarity. The diagram is as follows:

[0267] In the semiconductor device shown in FIG. 13, the semiconductor device shown in <Configuration example of semiconductor device> The same reference numerals are used to designate structures that have the same functions as those of the structures constituting the casing (see Figure 1). Regarding the constituent materials of the transistor 200, please refer to the <Configuration Example of Semiconductor Device> in detail. The materials described can be used.

[0268] The transistor 200 shown in FIG. 13 differs from the transistor 200 shown in FIG. 13 in that the conductor 242 is not provided. 13. In the transistor 200 shown in FIG. For example, the oxide 230 may be doped with an element that can increase the carrier density and reduce the resistance. By adding it as a punt, the region 243 may be formed.

[0269] The dopant may be an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. Representative examples of such elements include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gases, etc. may also be used. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. Also, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, etc. Niobium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sodium, zirconium, beryllium, indium, ruthenium, iridium, strontium Add one or more metal elements selected from the group consisting of ruthenium, lanthanum, etc. Among the above, boron and phosphorus are preferred as dopants. , when phosphorus is used as a dopant, amorphous silicon, or low-temperature polysilicon This allows the use of equipment from the same production line, thereby reducing capital investment. The concentration of the above elements may be measured using SIMS or the like.

[0270] In particular, it is preferable to use an element that easily forms an oxide as the element to be added to the region 243. Representative examples of such elements include boron, phosphorus, aluminum, magnesium, and the like. The element added to the region 243 takes oxygen from the oxide 230 and forms the oxide. As a result, many oxygen vacancies occur in the region 243. When the hydrogen in the oxide 230 is bonded to the silicon dioxide, carriers are generated, resulting in an extremely low resistance region. Furthermore, since the element added to the region 243 exists in the region 243 in the form of a stable oxide, Even if a subsequent process requiring high temperatures is performed, the compound is unlikely to be desorbed from the region 243. That is, an element that easily forms an oxide is used as the element to be added to the region 243. This allows the formation of a region in the oxide 230 that is resistant to high resistance even after undergoing a high-temperature process.

[0271] Forming regions 243 in oxide 230 to function as source or drain regions. Thus, the region 243 can be formed without providing a source electrode and a drain electrode made of metal. A conductor 240 can be connected which acts as a plug.

[0272] When region 243 is formed by adding a dopant, for example, A mask such as a resist mask or a hard mask is provided in a position where a channel formation region will be formed. In this case, the mask is thickened in the oxide 230. In the unfolded region, a region 243 containing the above elements can be formed.

[0273] As a method for adding dopants, ionization is performed by mass separating ionized source gases and adding them. ion injection method, ion doping method in which ionized source gas is added without mass separation, Mass separation can be performed by using methods such as ion implantation. When this is done, the ion species to be added and their concentrations can be strictly controlled. If separation is not performed, high concentration ions can be added in a short time. Alternatively, an ion doping method may be used, in which molecular clusters are generated and ionized. A dopant may also be referred to as an ion, a donor, an acceptor, an impurity, or an element. stomach.

[0274] In addition, an element that forms oxygen vacancies in the region 243 is added and heat treatment is performed, thereby forming a channel. The hydrogen contained in the region 234, which functions as a hole formation region, is transferred to the oxygen vacancy contained in the region 243. This gives the transistor 200 stable electrical characteristics and This can improve reliability.

[0275] The configurations and methods shown in the present embodiment may be the same as those shown in other embodiments and examples. It can be used in combination with other methods as appropriate.

[0276] (Embodiment 3) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0277] [Storage device 1] FIG. 14 shows an example of a semiconductor device (memory device) using a capacitor according to one embodiment of the present invention. The semiconductor device of one embodiment of the present invention includes a layer 291 including a transistor 300 and a layer 291 The layer 290_1 has a top layer 290_1 and a layer 290_2 on the layer 290_1. 1 denotes a transistor 200_1, a capacitor 100_1, and wirings 1001_1 to 1001_1. 006_1. The layer 291_2 includes the transistor 200_2 and the capacitor element 100_2 and wirings 1001_2 to 1006_2. Since the layers 291_1 and 291_2 have substantially the same structure, they have similar conductors, insulators, and oxides. The transistors 200_1 and 200_2 are denoted by the same reference numerals. The capacitors 100_1 and 100_2 may be collectively referred to as transistors 200. 00_2 may be collectively referred to as the capacitance element 100. The transistor 200 described in the above embodiment can be used.

[0278] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This allows the memory contents to be retained for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0279] In the semiconductor device shown in FIG. 14, the wiring 1001_1 and the wiring 1001_2 are The wiring 1002_1 and the wiring 1002_2 are electrically connected to the source of the transistor 300. It is electrically connected to the drain of the transistor 300 .

[0280] The wiring 1003_1 is electrically connected to one of the source and drain of the transistor 200_1. The wiring 1004_1 is electrically connected to the first gate of the transistor 200_1. The wiring 1006_1 is electrically connected to the second gate of the transistor 200_1. The other of the source and the drain of the transistor 200_1 is connected to the capacitor 100_ The wiring 1005_1 is electrically connected to one of the electrodes of the capacitor 100_1. The wiring 1001_1 is electrically connected to the wiring 1003_1 and the wiring 1004_2. 1004_1, the wiring 1005_1, or the wiring 1006_1. In addition, the wiring 1002_1 is connected to the wiring 1003_1, the wiring 1004_1, the wiring 1005_1, and the wiring 1006_2. Alternatively, it may be electrically connected to the wiring 1006_1.

[0281] The wiring 1003_2 is electrically connected to one of the source and drain of the transistor 200_2. The wiring 1004_2 is electrically connected to the first gate of the transistor 200_2. The wiring 1006_2 is electrically connected to the second gate of the transistor 200_2. The other of the source and the drain of the transistor 200_2 is connected to the capacitor element 1. The wiring 1005_2 is electrically connected to one electrode of the capacitor 100_2. The wiring 1001_2 is electrically connected to the other of the electrodes. It may be electrically connected to the wire 1004_2, the wire 1005_2, or the wire 1006_2. In addition, the wiring 1002_2 is connected to the wiring 1003_2, the wiring 1004_2, the wiring 1005_ 2, or may be electrically connected to the wiring 1006_2.

[0282] The memory device shown in FIG. 14 uses a capacitor 10 The potential of one of the electrodes can be maintained at 0, making it possible to write, store, and read information. It is possible to extract

[0283] In addition, the memory device shown in FIG. 14 has a memory cell array arranged in a matrix. It can be configured.

[0284] Next, a transistor 300 including layer 291 will be described.

[0285] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 312 serving as a gate electrode. 16, an insulator 315 serving as a gate insulator, and a semiconductor region consisting of a portion of the substrate 311 313, and a low resistance region 314a that functions as a source region or a drain region, and and low resistance region 314b.

[0286] Here, an insulator 315 is disposed on the semiconductor region 313, and a conductor is disposed on the insulator 315. The transistor 300 formed in the same layer is provided with an element isolation insulating layer 316. The insulator 312 serves as a barrier between the semiconductor substrate 10 and the semiconductor substrate 10. ... The transistor 300 can be made of an insulator similar to the insulator 326. The transistor may be either a channel type or an n-channel type.

[0287] The substrate 311 includes a region where the channel of the semiconductor region 313 is formed, a region in the vicinity of the region, a source region, and a semiconductor layer. low resistance region 314a and low resistance region 314b which will be the source region or drain region; In the above, it is preferable that the semiconductor includes a silicon-based semiconductor, and the semiconductor includes single crystal silicon. Alternatively, Ge (germanium), SiGe (silicon germanium), Materials containing GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. The effective mass can be controlled by applying stress to the crystal lattice and changing the lattice spacing. Alternatively, GaAs and GaAlAs may be used. The transistor 300 is a HEMT (High Electron Mobility Transistor). Transistor) may also be used.

[0288] The low resistance region 314a and the low resistance region 314b are formed by the semiconductor layer applied to the semiconductor region 313. In addition to the conductive material, elements that impart n-type conductivity, such as arsenic and phosphorus, or p-type conductivity, such as boron, are added. It contains elements that impart electrical conductivity to the material.

[0289] The conductor 316, which functions as a gate electrode, is made of arsenic, phosphorus, or the like, which provides n-type conductivity. Semiconductor materials such as silicon that contain elements or elements that give them p-type conductivity, such as boron Conductive materials such as aluminum, metal, alloy, or metal oxide materials can be used. .

[0290] In addition, since the work function is determined by the material of the conductor, by changing the material of the conductor, The threshold voltage can be adjusted by using titanium nitride or tantalum nitride as the conductor. It is preferable to use a material such as the following. It is preferable to use a metal material such as tungsten or aluminum as a laminate. Tungsten is preferred in terms of heat resistance.

[0291] Here, the transistor 300 shown in FIG. 14 has a semiconductor region 313 ( The side and top surfaces of the semiconductor region 313 are insulated. A conductor 316 is provided to cover the transistor via an insulating material 315. The transistor 300 is also called a FIN type transistor because it utilizes the protruding portion of the semiconductor substrate. In addition, an insulator is provided in contact with the top of the protrusions and functions as a mask for forming the protrusions. In addition, the case where a part of a semiconductor substrate is processed to form a convex portion is shown here. However, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0292] The transistor 300 is provided with an insulator 320, an insulator 322, an insulator 323, and an insulator 324 as interlayer films. 4, and an insulator 326 are laminated in this order. 22, insulator 324, and insulator 326 are connected to the capacitor element 100 or the transistor 20. 0, and a conductor 330, etc. are embedded. The conductors 328 and 330 function as plugs or wiring.

[0293] In addition, the insulator that functions as an interlayer film acts as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be subjected to chemical mechanical polishing (CMP) to improve flatness. The surface may be planarized by a planarization process using a CMP method or the like.

[0294] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In this case, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0295] The transistor 300 shown in FIG. 14 is an example, and the structure is not limited to this. Appropriate transistors may be used depending on the structure and driving method.

[0296] Next, the capacitance elements 100 and wiring layers of the layers 290_1 and 290_2 will be described. The following description is common to both the layer 290_1 and the layer 290_2. The detailed description of the transistor 200 is omitted since it can be referred to the previous embodiment. do.

[0297] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. a conductor 110 serving as the first electrode and a conductor 120 serving as the second electrode; and an insulator 130 that functions as a dielectric.

[0298] Also, for example, the conductor 112 provided on the conductor 246 and the conductor 110 are formed at the same time. Note that the conductor 112 can be used in the capacitor 100, the transistor 200, and has a function as a plug or wiring electrically connected to the transistor 300.

[0299] In FIG. 14, the conductor 112 and the conductor 110 are shown as having a single-layer structure. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties between weak conductors and highly conductive conductors with good adhesion may form a highly conductive material.

[0300] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, zirconium oxide, aluminum oxide, aluminum oxide nitride, nitridic acid Aluminum nitride, aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium oxynitride Hafnium, hafnium nitride, or the like may be used, and the layer may be formed as a laminate or a single layer. For example, the insulator 130 may be zirconium oxide, aluminum oxide, or zirconium oxide. The insulating films stacked in this order can be used.

[0301] For example, the insulator 130 may be made of a material with high dielectric strength such as silicon oxynitride and a material with high dielectric strength such as silicon oxynitride. It is preferable to use a laminated structure with a high-k material. The element 100 has a high dielectric constant (high-k) insulator, which ensures sufficient capacitance. By using an insulator with a high dielectric strength, the dielectric strength is improved, and the electrostatic breakdown of the capacitance element 100 is prevented. This can suppress the destruction.

[0302] In addition, oxide is used as an insulator for high dielectric constant (high-k) materials (materials with high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium oxides having silicon and hafnium, oxide nitrides having silicon and hafnium, or oxide nitrides having silicon and hafnium Nitrides containing fluorine are also included.

[0303] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. silicon dioxide, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, carbon Doped silicon oxide, carbon and nitrogen doped silicon oxide, silicon oxide with vacancies Examples include concrete or resin.

[0304] <Wiring layer> Between each layer, there may be provided a wiring layer with an interlayer film, wiring, plugs, etc. In addition, multiple wiring layers can be provided depending on the design. Conductors that function as wiring may have multiple structures that are collectively assigned the same symbol. In addition, in this specification and the like, the wiring and the plug electrically connected to the wiring are integrated. That is, when a part of the conductor functions as a wiring, or when a part of the conductor may also function as a plug.

[0305] The insulators 210, 212, 214, and the insulators 216, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262 The body 216 includes a conductor 218 and the conductors that make up the transistor 200 (the conductors 205 ) and the like are embedded. The conductor 218 is a capacitor element 100 or a transistor. 300. 20 and an insulator 150 is provided on the insulator 130 .

[0306] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides that have insulating properties. Examples of such materials include metal nitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0307] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, depending on the function of the insulator, the material It is recommended to select:

[0308] For example, the insulators 150, 212, 352, and 354 have relatively It is preferable to have an insulator with a low dielectric constant. For example, the insulator may be silicon oxide, oxide, or the like. Silicon nitride, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, carbon silicon oxide doped with oxygen, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies Preferably, the insulator comprises silicon or resin. Alternatively, the insulator may comprise silicon oxide. , silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide , carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or vacancy-containing silicon oxide. It is preferable that the insulating layer has a laminated structure of silicon oxide and resin. Silicon oxynitride is thermally stable, so by combining it with resin, The resin may be, for example, polyester, Polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate Examples include acrylic or polyethylene.

[0309] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the Therefore, the insulator 210, the insulator 350, etc. contain impurities such as hydrogen and An insulator having a function of suppressing the permeation of oxygen may be used.

[0310] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttria oxide ammonium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tungsten oxide Metal oxides such as talc, silicon nitride oxide, silicon nitride, etc. can be used. .

[0311] Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium Sodium, niobium, manganese, magnesium, zirconium, beryllium, indium, Materials containing one or more metal elements selected from the group consisting of ruthenium and lithium can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as silicon, Silicides such as nickel silicide may also be used.

[0312] For example, conductor 328, conductor 330, conductor 356, conductor 218, and conductor 1 12, etc., include metal materials, alloy materials, metal nitride materials, or Conductive materials such as metal oxide materials can be used in a single layer or in a laminated form. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which is also electrically conductive. It is preferable to use tungsten. Alternatively, low-resistance conductive materials such as aluminum and copper may be used. It is preferable to form the wiring from a low-resistance conductive material. can be done.

[0313] <<Wiring or plug in a layer provided with an oxide semiconductor>> When an oxide semiconductor is used for the transistor 200, excess An insulator having an oxygen region may be provided. In this case, the insulator having the excess oxygen region An insulating material having a barrier property is provided between the insulating material and the conductor provided on the insulator having the excess oxygen region. It is preferable to provide a body.

[0314] For example, in FIG. 14, an insulating layer is formed between the insulator 224 having excess oxygen and the conductor 246. The insulator 276 is preferably provided in contact with the insulator 222 and the insulator 274. By providing the insulator 224, the transistor 200 has an insulating property having a barrier property. Furthermore, the insulator 276 can be formed into a sealing structure by the insulator 280. It is preferable that the insulator 276 also contacts a part of the insulator 280. This makes it possible to further suppress the diffusion of oxygen and impurities.

[0315] In other words, by providing the insulator 276, the excess oxygen contained in the insulator 224 is absorbed by the conductor 24 Furthermore, the presence of the insulator 276 can prevent impurities from being absorbed by the insulator 276. The diffusion of hydrogen, which is a substance, into the transistor 200 via the conductor 246 is suppressed. It is possible.

[0316] The insulator 276 is made of a material that suppresses the diffusion of impurities such as water or hydrogen, and oxygen. It is advisable to use an insulating material that has the function of insulating the insulating material. For example, aluminum oxide or hafnium oxide It is preferable to use magnesium oxide, gallium oxide, etc. ammonium, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, nickel oxide Metal oxides such as oxydimium or tantalum oxide, silicon oxide nitride or silicon nitride, etc. can be used.

[0317] Although FIG. 14 shows a two-layer laminate structure of the layer 290_1 and the layer 290_2, However, the present invention is not limited to this, and may be configured such that three or more layers including the transistor 200 are stacked. That's fine.

[0318] The above is a description of the configuration example. By using this configuration, Since it is possible to stack layers containing the same, the area occupied by the semiconductor device when viewed from above can be reduced, and the semiconductor device can be made finer. By using this structure, it is possible to thin the semiconductor device having an oxide semiconductor. In a semiconductor device using a transistor, fluctuations in electrical characteristics are suppressed and reliability is improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be improved. Alternatively, a transistor including an oxide semiconductor and having a low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. .

[0319] In the above, the capacitor element 100 is a planar type, but the shape of the capacitor element is As shown in FIG. 15(A), the capacitor element 100 may be formed in a cylindrical shape. The capacitor 100 illustrated in FIG. 15A may include an insulator 281 and an insulator 282. conductor 110 disposed in an opening formed in 83, and a gap between conductor 110 and insulator 28. 3, and the conductor 120 on the insulator 130. The configuration is similar to that of the transistor 200 and the capacitor 100 shown in FIG.

[0320] In FIG. 15A, the capacitor 100 is provided above the transistor 200. However, the present embodiment is not limited to this. In this way, the transistor 200 and the capacitor element 100 may be provided below each other. By arranging them so that they overlap, the area occupied by the transistor and the capacitor in top view is Since the number of wirings can be reduced, the semiconductor device can be further highly integrated.

[0321] As shown in FIG. 15B, the transistor 200a and the transistor 200b In the figure, the conductor 205, the oxide 230a, the oxide 230b, the conductor 242, the conductor 24 6, the insulator 241, and the conductor 112 may be shared. The transistor 200a and the capacitor 100a, and the transistor 200b and the capacitor 10 0b has a structure similar to that of the transistor 200 and the capacitor 100 shown in FIG. Therefore, please refer to the above for details.

[0322] As shown in FIG. 15B, the transistor 200a and the transistor 200b are By sharing the 246, the area occupied by each transistor element when viewed from above is reduced. Since the area required can be reduced, the semiconductor device can be further highly integrated.

[0323] This embodiment mode may be appropriately combined with the configurations described in other embodiment modes and examples. It is possible to implement.

[0324] (Fourth embodiment) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. 16 and 17. Transistors used as conductors (hereinafter sometimes referred to as OS transistors) and capacitors This section explains the storage device to which the OS is applied (hereinafter, sometimes referred to as the OS memory device). The OS memory device includes at least a capacitance element and an OS transistor that controls the charging and discharging of the capacitance element. The off-state current of the OS transistor is extremely small. The memory device has excellent retention characteristics and can function as a non-volatile memory.

[0325] <Storage device configuration example> 16 shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 , a memory cell array 1470_1, and a memory cell array 1470_2. The circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, a control circuit 1440, and a In the following description, the memory cell array 1470_1 and The memory cell array 1470_1 and the memory cell array 1470_2 may be collectively referred to as the memory cell array 1470. do.

[0326] The memory device 1400 corresponds to the memory device shown in Figure 14. The circuit 1430 is in layer 291, the memory cell array 1470_1 is in layer 290_1, and the memory cell The channel array 1470_2 corresponds to the layer 290_2.

[0327] The column circuits 1430 include, for example, column decoders, precharge circuits, sense amplifiers, and write The precharge circuit has the function of precharging the wiring. The sense amplifier has the function of amplifying the data signal read from the memory cell. The above wiring is a wiring connected to a memory cell included in the memory cell array 1470. The amplified data signal is output via an output circuit 1440 as a data signal. RDATA to the outside of the storage device 1400. For example, it has a row decoder, a word line driver circuit, etc., and can select a row to access. do.

[0328] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 14 The high power supply voltage (VDD) for the 11 and the high power supply voltage (VIL) for the memory cell array 1470 are The storage device 1400 also receives control signals (CE, WE, RE), address signals, and The address signal ADDR and the data signal WDATA are input from the outside. The data is input to the decoder and column decoder, and WDATA is input to the write circuit.

[0329] The control logic circuit 1460 processes external input signals (CE, WE, RE). It processes the signal to generate control signals for the row decoder and column decoder. CE is the chip enable signal. where WE is the write enable signal and RE is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these. Instead, other control signals may be input as required.

[0330] The memory cell array 1470_1 is formed on a part of the peripheral circuit 1411. The memory cell array 1470_2 is formed on the memory cell array 1470_1. The array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is The number of memory cells MC in a row is determined by the configuration of the memory cell MC. The number of wires connecting the cell array 1470 and the column circuit 1430 depends on the configuration of the memory cells MC. It is determined by the configuration, the number of memory cells MC in one row, etc.

[0331] In FIG. 16, a two-layer memory cell array 1470 is stacked on the peripheral circuit 1411. Although an example in which layers are formed has been shown, the present embodiment is not limited to this. A configuration in which three or more memory cell arrays are stacked on the side circuit 1411 may be used.

[0332] FIG. 17 illustrates an example of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0333] [DOSRAM] 17A to 17C show examples of circuit configurations of memory cells in a DRAM. In this case, a DRAM using a memory cell of one OS transistor and one capacitor element type is called DOSRA. M(Dynamic Oxide Semiconductor Random Acc The memory cell 1471 shown in FIG. The transistor M1 has a gate (sometimes called a front gate) and a back gate.

[0334] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CAL.

[0335] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, a low level potential is applied to the wiring CAL. The wiring BGL is preferably used to apply a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, The threshold voltage of M1 can be increased or decreased.

[0336] Here, the memory cell 1471 shown in FIG. 17A is the same as the layer 291 of the memory device shown in FIG. _1 or layer 291_2. That is, in layer 291_1, the transistor M1 is connected to the transistor 200_1, the capacitor CA is connected to the capacitor 100_1, and the wiring BIL is connected to Wiring 1003_1, wiring WOL to wiring 1004_1, wiring BGL to wiring 1006_1 In addition, the wiring CAL corresponds to the wiring 1005_1. The transistor M1 is connected to the transistor 200_2, the capacitance element CA is connected to the capacitance element 100_2, and the wiring BIL is connected to wiring 1003_2, wiring WOL is connected to wiring 1004_2, and wiring BGL is connected to wiring 10 The wiring CAL corresponds to the wiring 1005_2. The transistor 300 is connected to the row circuit 1420 and the column circuit 143 of the memory device 1400 shown in FIG. 0.

[0337] Furthermore, the memory cells MC are not limited to the memory cells 1471, and the circuit configuration may be changed. For example, the memory cell MC can be configured as a memory cell 1472 shown in FIG. In addition, the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be configured as the memory cell 14 shown in FIG. As shown in 73, a transistor with a single gate structure, i.e., a transistor without a back gate, The memory cell may be configured with a resistor M1.

[0338] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, The transistor 200 is used as M1, and the capacitance element 100 is used as the capacitance element CA. By using an OS transistor as the transistor M1, This means that the leakage current of the transistor M1 can be made very low. The frequency of memory cell refresh can be reduced by using register M1 for long-term retention. In addition, the refresh operation of the memory cells can be eliminated. In addition, since the leakage current is very low, the memory cells 1471, 1472, The memory cell 1473 can store multi-level data or analog data.

[0339] In addition, in the DOSRAM, as described above, the memory cell array 1470 is overlapped with the By providing a sense amplifier as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0340] [NOSRAM] 17(D) to 17(H) show the configuration of a gain cell type memory cell with two transistors and one capacitor. A circuit configuration example is shown in FIG. 17D. A memory cell 1474 shown in FIG. 17D includes a transistor M2 and The transistor M2 is a front-end transistor. The gate (sometimes simply referred to as a gate) and the back gate are included. The memory cell has a gain cell type memory cell using an OS transistor as the transistor M2. The memory device is NOSRAM (Nonvolatile Oxide Semiconductor It is sometimes called tor RAM.

[0341] The first terminal of the transistor M2 is connected to the first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of transistor B is connected to the line CAL. The first terminal of transistor M3 is connected to the line R BL, the second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M The gate of 3 is connected to the first terminal of the capacitance element CB.

[0342] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL functions as the second wiring of the capacitance element CB. It functions as a wiring for applying a predetermined potential to the terminal. During the data read operation, a low level potential is applied to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the The threshold voltage can be increased or decreased.

[0343] Furthermore, the memory cells MC are not limited to the memory cells 1474, and the circuit configuration may be changed as appropriate. For example, the memory cell MC can be the memory cell 1475 shown in FIG. In this way, the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be the memory cell shown in FIG. Like the 1476, it is a single-gate transistor, i.e., it does not have a back gate. The memory cell may be configured with a transistor M2. As shown in FIG. 17(G), the wiring WBL and the wiring RBL are connected in a single line. The wiring BIL may be integrated.

[0344] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, The transistor 200 is used as the transistor M2 and the transistor M3, and the capacitance element CB is a capacitance element. The element 100 can be used. By using an OS transistor as the transistor M2, This allows the leakage current of the transistor M2 to be very low. The written data can be retained for a long time by the transistor M2, This reduces the frequency of refreshing the memory cells. Furthermore, since the leakage current is very low, the memory cell 14 Multi-value data or analog data can be stored in the memory cell 1475. The same is true for 1477.

[0345] By using OS transistors for the transistors M2 and M3, the memory cell array 147 0 can be constructed using only n-type transistors.

[0346] The transistor M3 is a transistor having silicon in the channel forming region (hereinafter referred to as The conductivity type of the Si transistor may be The Si transistor may be an n-channel type or a p-channel type. The field effect mobility may be higher than that of a read transistor. A Si transistor may be used as the transistor M3 that functions as a By using a Si transistor for transistor M3, a transistor can be stacked on top of transistor M3. Since the memory cell can be provided with the transistor M2, the area occupied by the memory cell can be reduced, and the memory device can be made more efficient. Integration can be achieved.

[0347] FIG. 17(H) shows an example of a gain cell type memory cell with three transistors and one capacitor. The memory cell 1478 shown in FIG. 17(H) includes transistors M4 to M6 and a capacitor The memory cell 1478 has a capacitor CC. The capacitor CC is provided as appropriate. Electrically connected to L, RWL, WWL, BGL, and GNDL. Wire GNDL is a wiring for applying a low level potential. , may be electrically connected to the wirings RBL and WBL.

[0348] The transistor M4 is an OS transistor having a back gate. The back gate and gate of the transistor M4 are electrically connected to the wiring BGL. Alternatively, the transistor M4 may have a back gate. It's not necessary.

[0349] The transistors M5 and M6 are n-channel Si transistors or p-channel Si transistors. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 is circuited using only n-type transistors. A path can be constructed.

[0350] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor M The transistor 200 is used as the transistor M4, and the transistors M5 and M6 are the transistors 300. The capacitor element CC can be a capacitor 100. By using an OS transistor as the gate driver, the leakage current of transistor M4 is very low. It can be made easier.

[0351] Note that the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment The configuration is not limited to the above. The arrangement or function of lines, circuit elements, etc. may be changed, deleted, or added as needed. stomach.

[0352] The structure shown in this embodiment mode may be appropriately combined with structures shown in other embodiment modes and examples. It can be used in combination.

[0353] (Embodiment 5) In this embodiment, a chip 1200 on which the semiconductor device of the present invention is mounted is shown in FIG. A chip 1200 is implemented with multiple circuits (systems). The technology of integrating multiple circuits (systems) on a single chip is called system-on-chip ( It is sometimes called System on Chip (SoC).

[0354] As shown in FIG. 18A, the chip 1200 includes a CPU (Central Processor). ssing Unit) 1211, GPU (Graphics Processing a memory controller 1212, one or more analog calculation units 1213, and one or more memory controllers 1214. controller 1214, one or more interfaces 1215, one or more networks It has a work circuit 1216 and the like.

[0355] The chip 1200 is provided with bumps (not shown), and as shown in FIG. 18(B), Printed Circuit Board (PCB) 1201 No.1 The first surface of the PCB 1201 is connected to the second surface. It is provided and connected to the motherboard 1203.

[0356] The motherboard 1203 is equipped with memory devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with a DOSR as shown in the previous embodiment. For example, the flash memory 1222 may be configured as The NOSRAM shown in FIG.

[0357] The CPU 1211 preferably has multiple CPU cores. It is preferable that the CPU 1211 and the GPU 1 have multiple GPU cores. Each of the CPs 212 may have a memory for temporarily storing data. The memory common to U1211 and GPU1212 is provided on chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. The GPU1212 is also suitable for parallel calculation of large amounts of data, and is ideal for image processing and multiply-and-accumulate operations. The GPU 1212 can be used as an image processing circuit or By providing a multiply-and-accumulate circuit, image processing and multiply-and-accumulate operations can be performed with low power consumption. This becomes possible.

[0358] In addition, the CPU 1211 and GPU 1212 are mounted on the same chip, The wiring between the CPU1211 and GPU1212 can be shortened, and Data transfer from CPU 1211 to GPU 1212, memory After the data transfer between the GPUs and the calculations in GPU1212, the GPU1212 transfers the data to CPU12. The calculation results can be transferred to 11 at high speed.

[0359] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit. The product-sum calculation circuit may be provided in the

[0360] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. , and a circuit that functions as an interface to the flash memory 1222.

[0361] The interface 1215 includes a display device, a speaker, a microphone, a camera, a computer, and the like. The controller has an interface circuit with external devices such as a This includes devices such as mice, keyboards, and game controllers. USB (Universal Serial Bus), HDMI (registered trademark) High-Definition Multimedia Interface) You can be there.

[0362] The network circuit 1216 is a LAN (Local Area Network) or the like. It may also have a circuit for network security. stomach.

[0363] The above circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a soldering iron, and the chip 1200 can be produced at low cost.

[0364] A PCB 1201 on which a chip 1200 having a GPU 1212 is mounted, a DRAM 122 1 and a motherboard 1203 provided with a flash memory 1222. It can be called module 1204.

[0365] The GPU module 1204 includes a chip 1200 using SoC technology. Its size can be reduced. Also, it has excellent image processing capabilities, making it suitable for smart devices. Phones, tablets, laptops, portable (portable) game consoles, etc. It is suitable for use in portable electronic devices. Deep neural networks (DNNs), convolutional neural networks (CNN), recurrent neural network (RNN), autoencoder, deep Boltzmann It can perform operations such as deep belief networks (DBMs) and deep belief networks (DBNs). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a module.

[0366] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0367] (Sixth embodiment) This embodiment mode will describe an application example of a memory device using the semiconductor device described in the above embodiment. The semiconductor device described in the above embodiment can be used in various electronic devices (for example, Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video playback devices, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (for example, D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 19 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a flash memory and used in various storage devices and removable memory.

[0368] 19A is a schematic diagram of a USB memory. The USB memory 1100 is a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, controller chip 1106 is attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 105 or the like.

[0369] Figure 19(B) is a schematic diagram of the external appearance of an SD card, and Figure 19(C) is a schematic diagram of the internal structure of an SD card. The SD card 1110 is a schematic diagram of the structure. The SD card 1110 comprises a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, the SD card 1110 The capacity can be increased. In addition, a wireless chip having a wireless communication function can be installed on the substrate 1113. This allows the host device and the SD card 1110 to communicate wirelessly. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0370] FIG. 19(D) is a schematic diagram of the external appearance of the SSD, and FIG. 19(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a memory The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip may be used. By providing 54, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0371] This embodiment mode may be appropriately combined with the configurations described in other embodiment modes and examples. It is possible to implement.

[0372] (Embodiment 7) A semiconductor device according to one aspect of the present invention is a processor such as a CPU or a GPU, or a chip. 20 to 22 show CPUs, GPUs, and the like according to one embodiment of the present invention. Specific examples of electronic devices equipped with the processor or chip are given below.

[0373] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of electronic devices include television sets, desktop or notebook computers, Personal computers, computer monitors, digital signage Signage: Digital signage), pachinko machines and other large game machines. In addition to electronic devices with large screens, digital cameras, digital video cameras, digital photos Examples include frames, mobile phones, portable game consoles, personal digital assistants, and sound reproduction devices. Furthermore, by providing an integrated circuit or a chip according to one embodiment of the present invention in an electronic device, Artificial intelligence can be installed in the sub-devices.

[0374] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images, information, etc. on the display unit. If the device has a secondary battery, the antenna may be used for contactless power transmission.

[0375] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Number, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared) It may have.

[0376] The electronic device of one embodiment of the present invention can have various functions. (still images, videos, text images, etc.) on the display, touch panel function, calendar Functions such as displaying date and time, running various software (programs) functions, wireless communication functions, and functions to read programs or data recorded on recording media. It can have functions, etc. Figure 20 shows an example of an electronic device.

[0377] [mobile phone] FIG. 20(A) illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 551. It is provided for 0.

[0378] The information terminal 5500 uses a chip according to one embodiment of the present invention to perform a function using artificial intelligence. It is possible to run applications that utilize artificial intelligence. For example, the application recognizes conversations and displays the conversation contents on the display unit 5511. The display unit 5511 recognizes characters, figures, etc. input by the user on the touch panel. and applications to be displayed on the display unit 5511, applications that perform biometric authentication such as fingerprints and voiceprints, etc. Applications, etc.

[0379] [Information terminal 1] 20(B) shows a desktop information terminal 5300. The information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard. It has a code 5303.

[0380] The desktop information terminal 5300 is one of the features of the present invention, similar to the information terminal 5500 described above. By applying the chip of the present invention, it is possible to execute applications using artificial intelligence. Examples of applications that use artificial intelligence include design support software. , writing correction software, automatic menu generation software, etc. By using the laptop information terminal 5300, new artificial intelligence can be developed.

[0381] In the above, a smartphone and a desktop information terminal are used as examples of electronic devices. As shown in Figure 20(A) and (B), the smartphone and desktop It is possible to apply information terminals other than personal information terminals, such as smartphones and desktops. Examples of information terminals other than personal information terminals include PDAs (Personal Digital Assistants). Assistant), notebook information terminals, and workstations.

[0382] [Information terminal 2] FIG. 21(A) shows a tablet information terminal 5000. The information terminal 5000 has a housing 5002 and a display unit 5001, and an input interface. As a face, a touch panel is provided on a display unit 5001, and buttons are provided on a housing 5002. It is assumed.

[0383] By applying the GPU or chip of one aspect of the present invention to the tablet information terminal 5000, Therefore, it is possible to realize a tablet information terminal 5000 with low power consumption. Power consumption can reduce heat generated by the circuit, so the circuit itself is not affected by heat generated. , the influence on the peripheral circuits and the module can be reduced.

[0384] The tablet information terminal 5000 can be held in the center of the controller 5010. By using the controller 5010, the tablet information terminal 5000 can This allows for more precise and faster operation than a panel. The information terminal 5000 can be used as a portable game machine.

[0385] The controller 5010 may also include one or more of the sensors described above. The controller 5010 can be used even when the tablet information terminal 5000 is not being held. , can be connected wired or wirelessly.

[0386] The tablet information terminal 5000 can be held in a cradle 5020. The cradle 5020 is a device for charging the tablet information terminal 5000 and its accessories. The function, the output data of the tablet type information terminal 5000 (for example, video data, audio data, or text data), input devices (e.g., mouse, keyboard, Connect the input data to a recording media drive or controller (such as the 5010) and or a function of transmitting the information to the tablet-type information terminal 5000 via a wired or has at least one function of electrically connecting to a communication line wirelessly.

[0387] By using such a cradle 5020, the tablet information terminal 5000 Use as a personal computer, workstation, or gaming console It is possible.

[0388] The Cradle 5020 also supports GPU chips, main memory, or storage. By having these, for example, it is possible to The output video data can be up-converted.

[0389] [Home video game console] FIG. 20(D) shows a stationary game machine 5100, which is an example of a game machine. The stationary game machine 5100 can be connected to a game machine main body 5101 wirelessly or by wire. The controller 5102 is capable of controlling the

[0390] By applying a GPU or chip according to one embodiment of the present invention to a stationary game console 5100, This makes it possible to realize a low-power-consumption stationary game machine 5100. By using electric power, heat generation from the circuit can be reduced, so the circuit itself and the surroundings The influence on the edge circuits and modules can be reduced.

[0391] [Handheld game console] FIG. 20(E) shows a portable game machine 5200, which is an example of a game machine. The game machine includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0392] By applying the GPU or chip of one embodiment of the present invention to the portable game console 5200, This makes it possible to realize a portable game machine 5200 with low power consumption. This reduces heat generated by the circuit, preventing damage to the circuit itself, peripheral circuits, and And the impact on the module can be reduced.

[0393] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game machine 5200, Therefore, it is possible to realize a portable game machine 5200 having artificial intelligence.

[0394] Originally, the progress of the game, the behavior of the creatures that appear in the game, the phenomena that occur in the game, etc. The expression is determined by the program that the game has, but the portable game machine 52 By applying artificial intelligence to 00, it is possible to create expressions that are not limited to game programs. For example, the questions asked by the player, the game progress, and events during the game The timing of occurrence, the words and actions of the characters appearing in the game, etc. are limited to the game program. It is possible to change and express the image without being affected by the image.

[0395] In addition, when playing games that require multiple players on the portable game console 5200, Noh allows you to create anthropomorphic game players, so your opponents can be artificially By using the game player, you can play the game alone.

[0396] In the above, a stationary game machine and a portable game machine are illustrated as examples of game machines. However, the game machine to which the GPU or chip according to one aspect of the present invention is applied is not limited to this. Examples of game machines that can use the GPU or chip of one aspect of the present invention include those used in amusement facilities (gaming facilities). Arcade game machines installed in sports facilities (music centers, amusement parks, etc.) Examples include a pitching machine for batting practice.

[0397] [electric appliances] FIG. 21(A) shows an electric refrigerator-freezer 5800, which is an example of an electric appliance. The refrigerator 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. do.

[0398] By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, artificial intelligence By utilizing artificial intelligence, an electric refrigerator-freezer 5800 can be realized. The Electric Refrigerator-Freezer 5800 is a refrigerator-freezer that can be used to store food and drink. It has a function to automatically generate menus based on the expiration date of ingredients, and a function to automatically generate menus based on the expiration date of ingredients stored in the electric refrigerator-freezer 5800. It can have a function to automatically adjust the temperature to suit the ingredients being cooked.

[0399] In this example, an electric refrigerator-freezer was described as an electrical appliance, but other electrical appliances may also be used. Examples include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, and induction cookers. , water dispenser, heating and cooling appliances including air conditioners, washing machines, dryers, Examples include audiovisual equipment.

[0400] [Moving object] The GPU or chip of one embodiment of the present invention is used in automobiles, which are moving objects, and in the vicinity of the driver's seat of the automobile. can be applied to.

[0401] FIG. 21(B1) shows an automobile 5700 as an example of a moving object, and FIG. 21(B2) shows an automobile FIG. 21(B2) is a diagram showing the area around the windshield in the interior of a vehicle. Display panels 5701, 5702, and 5703 attached to the board Also shown is a display panel 5704 mounted on the pillar.

[0402] The display panels 5701 to 5703 display a speedometer, a tachometer, It provides various information by displaying the driving distance, fuel gauge, gear status, air conditioning settings, etc. In addition, the display items and layout displayed on the display panel can be adjusted by the user. It can be changed as needed to suit your taste, enhancing the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0403] The display panel 5704 displays images from an imaging device (not shown) installed in the automobile 5700. By projecting images, it is possible to compensate for the blind spots obstructed by the pillars. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, This can compensate for blind spots and increase safety. By doing so, the driver can check for safety more naturally and without any discomfort. 4 can also be used as a lighting device.

[0404] The GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence, e.g. For example, the chip can be used in the autonomous driving system of the automobile 5700. The chip can be used in systems that provide road guidance, risk prediction, etc. Display panel 57 The display panels 5701 to 5704 are configured to display information such as road guidance and risk prediction. Good too.

[0405] In the above description, an automobile is used as an example of a moving body. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, These include vehicles such as drones, airplanes, and rockets. Applying the chip of one aspect of the present invention to a moving object and providing it with a system that utilizes artificial intelligence can be done.

[0406] [Broadcasting System] The GPU or chip according to one aspect of the present invention can be applied to a broadcasting system.

[0407] FIG. 21(C) shows a schematic diagram of data transmission in a broadcasting system. 21(C) shows how radio waves (broadcast signals) transmitted from a broadcasting station 5680 are transmitted to televisions in each home. The diagram shows the path the signal takes to reach the TV receiver (TV) 5600. The broadcast signal received by the antenna 5650 is transmitted to the receiving device (not shown). The data is then sent to the TV5600 via the

[0408] In FIG. 21(C), the antenna 5650 is a UHF (Ultra High Frequency) The antenna shown is a BS 110°CS antenna. Antennas, CS antennas, etc. can also be applied.

[0409] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 The received radio wave 5675A is amplified and radio wave 5675B is transmitted. By receiving radio waves 5675B with Na 5650, you can watch terrestrial TV broadcasts on TV 5600. The broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 21(C), but may be any other type of broadcasting system. It may also be satellite broadcasting using an industrial satellite, data broadcasting via optical fiber lines, or the like.

[0410] The above-described broadcasting system applies the chip according to one aspect of the present invention to broadcast using artificial intelligence. The broadcasting station 5680 transmits broadcast data to the TV 5600 in each home. When the encoder is activated, the broadcast data is compressed and the antenna 5650 receives the broadcast data. When the data is received, the decoder of the receiving device included in the TV 5600 converts the broadcast data into By using artificial intelligence, for example, the compression method of the encoder can be Recognizing display patterns contained in displayed images in motion compensation prediction, which is one of the methods It is also possible to perform intra-frame prediction using artificial intelligence. For example, low-resolution broadcast data is received and then displayed on the TV5600 with high resolution. When displaying the broadcast data, the decoder may perform up-conversion or other operations to restore the broadcast data. Image interpolation can be performed.

[0411] The AI-based broadcasting system described above is expected to be a key component of the ultra-high definition television broadcasting system, which will see an increase in the amount of broadcast data. It is suitable for revision (UHDTV: 4K, 8K) broadcasting.

[0412] In addition, as an application of artificial intelligence on the TV5600 side, for example, By using such a configuration, the recording device By having AI learn user preferences, it can automatically record programs that match the user's preferences. It can be depicted.

[0413] Electronic devices described in the present embodiment, functions of the electronic devices, application examples of artificial intelligence, and their effects etc. can be appropriately combined with descriptions of other electronic devices.

[0414] <Parallel computer> A parallel computer can be constructed by forming a cluster using a plurality of computers according to one embodiment of the present invention. It can be achieved.

[0415] FIG. 22(A) illustrates a large-scale parallel computer 5400. In the example, a rack 5410 stores a plurality of rack-mounted computers 5420 .

[0416] The computer 5420 can have the configuration shown in the perspective view of FIG. In 22(B), a computer 5420 has a motherboard 5430, which is , a plurality of slots 5431, a plurality of connection terminals 5432, and a plurality of connection terminals 5433. A PC card 5421 is inserted into the slot 5431. 21 has a connection terminal 5423, a connection terminal 5424, and a connection terminal 5425, The power supply 5420 is connected to the power supply 5430.

[0417] The PC card 5421 includes a CPU, a GPU, a storage device, and the like according to one embodiment of the present invention. For example, in FIG. 22(C), a PC card 5421 is connected to a board 542 2, and the board 5422 has connection terminals 5423, 5424, and 5425. 5426, a chip 5427, and a connection terminal 5428. Note that FIG. 22(C) shows chips other than the chip 5426 and the chip 5427. 5426 and chip 5427 described below. Please refer to the explanation in 5427.

[0418] The connection terminal 5428 is shaped so that it can be inserted into a slot 5431 on a motherboard 5430. The connection terminal 5428 connects the PC card 5421 and the motherboard 5430. It functions as an interface for connecting. The specifications of the connection terminal 5428 are as follows: For example, PCIe is one example.

[0419] The connection terminals 5423, 5424, and 5425 are, for example, the PC card 54 21 can be used as an interface for supplying power, inputting signals, etc. In addition, for example, an interface for outputting signals calculated by the PC card 5421 is provided. The connection terminal 5423, the connection terminal 5424, the connection terminal 5 425, for example, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Comput er System Interface) and other. When outputting a video signal from the connection terminal 5424 or the connection terminal 5425, An example is HDMI (registered trademark).

[0420] The chip 5426 has a terminal (not shown) for inputting and outputting signals. By inserting the PC card 5421 into a socket (not shown), the chip 5 426 and the PC card 5421 can be electrically connected. can be, for example, a GPU according to one aspect of the present invention.

[0421] The chip 5427 has a plurality of terminals, and the terminals are the same as those of the PC card 5421. For example, by reflow soldering the wiring, the chip 5427 and the PC It can be electrically connected to the card 5421. The chip 5427 can be, for example, Memory device, FPGA (Field Programmable Gate Array) , CPU, etc.

[0422] The computer of one embodiment of the present invention is a computer 5400 of a parallel computer 5400 shown in FIG. 420, it can be used to perform large-scale calculations required for AI learning and inference. It is possible to do so.

[0423] This embodiment mode may be appropriately combined with the configurations described in other embodiment modes and examples. It is possible to implement. [Example]

[0424] In this example, a semiconductor device in which the transistors described in the above embodiment are stacked is manufactured. Scanning Transmission Electron Microscope (STEM) Observation was performed using a tron ​​microscope to measure the electrical characteristics of the transistor. did.

[0425] In this embodiment, a transistor having a similar structure to the transistor 200 described in the previous embodiment is used. A semiconductor device (hereinafter referred to as Sample 1) was fabricated by stacking two layers of transistors. The lower layer transistor is called transistor 200_1, and the upper layer transistor is called transistor In sample 1, the transistors 200_1 and 200_2 are referred to as transistors 200_1 and 200_3. 2, 0.05 particles / μm in each layer 2 were arranged at a density of

[0426] First, the structures of the transistors 200_1 and 200_2 will be described. As shown in FIG. 3, the transistor 200_1 and the transistor 200_2 are insulators. 214, an insulator 216 disposed on the insulator 214, and an insulator 216 embedded therein. The conductor 205 is arranged as shown in FIG. 1, and the insulator 216 and the insulator 216 are arranged on the conductor 205. An edge 222, an insulator 224 disposed on the insulator 222, and a The oxide 230a is formed by depositing the oxide 230a on the surface of the substrate, and the oxide 230b is formed on the surface of the oxide 230a. conductors 242a and 242b spaced apart from each other on conductor 30b; and conductor 242 a, the conductor 242b, and the insulator 254 disposed on the insulator 224, and the insulator 25 4, and an oxide 230c1 disposed on the oxide 230b. and an oxide 230c2 disposed on the oxide 230c1, and an oxide 230c3 disposed on the oxide 230c2. The insulator 250 is placed on the conductor 260a and the conductor 260b are placed on the insulator 250. 60b, an insulator 280, an oxide 230c1, an oxide 230c2, an insulator 250, and and an insulator 274 disposed on the conductor 260.

[0427] The insulator 214 was made of aluminum oxide with a film thickness of 40 nm. Silicon oxynitride was used as the conductor 205. Tantalum nitride, titanium nitride, A conductive film in which tungsten and ZnO were laminated in this order was used.

[0428] The insulator 222 is made of aluminum oxide with a thickness of 5 nm, which is formed by the ALD method. The insulator 224 was made of silicon oxynitride with a film thickness of 35 nm. After film formation, 24 was heat-treated in a nitrogen atmosphere at 400°C for 1 hour, and then in an oxygen atmosphere. Heat treatment was performed at 400°C for 1 hour. Furthermore, the surface of the insulator 224 was subjected to CMP treatment. .

[0429] The oxide 230a is an In film having a thickness of 5 nm, which is formed by DC sputtering. The oxide 230a was formed using In:Ga:Zn=1 A target with an atomic ratio of 3:4 was used, and 45 sccm of oxygen gas was used as the deposition gas. The deposition pressure was 0.7 Pa, the deposition power was 500 W, the substrate temperature was 200° C., and the temperature was 100° C. The distance between the get and the substrate was set to 60 mm.

[0430] The oxide 230b is a 20 nm thick I film formed by DC sputtering. The oxide 230b was formed using an n-Ga-Zn oxide. A target with an atomic ratio of 4:2:4.1 was used, and argon gas was used as the deposition gas at 30 sc. The film deposition pressure was 0.7 Pa and the film deposition power was 500 W. The substrate temperature was set to 200°C, and the distance between the target and the substrate was set to 60 mm. After the film formation of the object 230b, the film was heat-treated at 400°C for 1 hour in a nitrogen atmosphere, and then heat-treated in an oxygen atmosphere. The sample was then heat treated in an air atmosphere at 400°C for 1 hour.

[0431] The conductors 242a and 242b were made of tantalum nitride with a film thickness of 25 nm. The insulator 254 is an aluminum oxide film having a thickness of 5 nm formed by sputtering. A 3 nm thick aluminum oxide layer was formed on top of the silicon dioxide layer using the ALD method.

[0432] The insulator 280 is made of silicon oxynitride formed by PECVD.

[0433] The oxide 230c1 is a 5 nm thick I film formed by DC sputtering. The oxide 230c1 was formed using n-Ga-Zn oxide. A target with an atomic ratio of 4:2:4.1 was used, and the deposition gas was oxygen gas 45 sc. cm, the deposition pressure was 0.7 Pa, the deposition power was 500 W, and the substrate temperature was 200°C. The distance between the target and the substrate was set to 60 mm.

[0434] The oxide 230c2 was formed by DC sputtering. The oxide 230c2 was formed using n-Ga-Zn oxide. A target with an atomic ratio of 1:3:4 was used, and 45 sccm of oxygen gas was used as the deposition gas. The deposition pressure was 0.7 Pa, the deposition power was 500 W, and the substrate temperature was 200°C. The distance between the target and the substrate was set to 60 mm.

[0435] The insulator 250 was made of silicon oxynitride with a film thickness of 10 nm. Titanium nitride with a thickness of 10 nm was used as the conductor 260a. A marten was used.

[0436] The insulator 274 is a 40 nm thick oxide film formed by RF sputtering. Aluminum was used. An Al2O3 target was used for the insulator 274, and the deposition gas was Argon gas 25sccm, oxygen gas 25sccm, and film formation pressure 0.4Pa were used. The deposition power was set to 2500 W, the substrate temperature was set to 250°C, and the distance between the target and the substrate was set to It was set to 60mm.

[0437] The transistor 200_1 and the transistor 200_2 of the sample 1 having the above-described configuration Sample 1 was designed with a channel length of 360 nm and a channel width of 360 nm. The transistor 200_1 and the transistor 200_2 are the same as the transistor 200. In addition to the above configuration, a conductor 240, an insulator 241, an insulator 281, etc. Has.

[0438] Since the transistor 200_2 is fabricated on the transistor 200_1, The thermal budget for the fabrication of transistor 200_2 is also applied to transistor 200_1. However, in the manufacturing process of the transistor 200_2, the heat treatment after the formation of the insulator 224 After the insulator 274 was deposited, the sample was heat-treated at 400°C for 1 hour in a nitrogen atmosphere. After the fabrication of No. 1, a heat treatment was further carried out in a nitrogen atmosphere at 400° C. for 4 hours.

[0439] Next, a part of the prepared sample was analyzed using Hitachi High-Technologies Corporation's "HD-2300." The cross-sectional STEM image was taken at an accelerating voltage of 200 kV. Figure 23 shows a magnification of 15,000. 24(A) is a cross-sectional STEM image of the transistor 200_1 of FIG. Figure 24(B) is a cross-sectional STEM image of the transistor in Figure 23, taken at a magnification of 100,000 times. This is a cross-sectional STEM image of 200_2 taken at 100,000x magnification.

[0440] As shown in FIG. 23, in the sample 1, a transistor 200_2 are stacked.

[0441] As shown in FIG. 24A, in the transistor 200_1, the insulator 280 , the insulator 274, the oxide 230c2, and the insulator 254, the conductor 260, the conductor 24(B), the conductive body 242a is separated from the conductive body 242b. In the transistor 200_2, the insulator 280 is made of the insulator 274, the oxide 230c, 2, and insulator 254 separates conductor 260, conductor 242a, and conductor 242 It is separated from b.

[0442] Next, 13 elements of the transistor 200_1 of the sample 1 and 13 elements of the transistor 200_2 Motoko's I d -V g Measurements were taken. d -V g The measurement is performed at the drain potential V of the transistor. d of +0.1V, +3.3V, and the source potential V s is set to 0V, and the top gate potential V G -3 The bottom gate potential V was swept from +0.3V to +3.3V. bg was performed at 0V. Also, I d -V g For the measurements, a Keysight Technologies semiconductor parameter analyzer was used. was used.

[0443] FIG. 25(A) shows the I d -V g The curve is shown in Figure 25(B). The I of the 13 elements of transistor 200_2 d -V gThe curve is shown.

[0444] As shown in FIGS. 25(A) and 25(B), the transistor 200_1 and the transistor 200 Both _2 showed good switching characteristics.

[0445] As described above, the semiconductor device in which the transistor 200 according to one embodiment of the present invention is stacked can be repeatedly It was also shown that the material retains good electrical properties even after heat treatment.

[0446] The configurations, methods, etc. shown in this example may be at least partially similar to other examples described in this specification. The present invention can be implemented in appropriate combination with the embodiments and examples. [Explanation of symbols]

[0447] 10: layer, 10_n: layer, 10_1: layer, 10_2: layer, 20: transistor, 22: acid oxide, 22a: oxide, 22b: oxide, 22bP: layer, 22bX: c-axis, 24: insulator , 26: conductor, 28a: conductor, 28b: conductor, 30: insulator, 32: insulator, 34 : insulator, 36: insulator, 38: insulator, 40: insulator, 50: oxygen, 100: capacitor , 100_1: capacitance element, 100_2: capacitance element, 100a: capacitance element, 100b: capacitance Element, 110: conductor, 112: conductor, 120: conductor, 130: insulator, 150: insulator Element, 200: transistor, 200_1: transistor, 200_2: transistor, 200a: transistor, 200b: transistor, 205: conductor, 210: insulator, 212: insulator, 214: insulator, 216: insulator, 218: conductor, 220: insulator, 222: insulator, 224: insulator, 230: oxide, 230a: oxide, 230b: oxide substance, 230c: oxide, 230c1: oxide, 230c1P: layer, 230c1X: c axis, 230c2: Oxide, 230c2P: Layer, 230c2X: c axis, 230C1: Oxide film, 2 30C2: Oxide film, 231: Region, 231a: Region, 231b: Region, 232B: Oxide film , 234: area, 240: conductor, 240a: conductor, 240b: conductor, 241: insulation body, 241a: insulator, 241b: insulator, 242: conductor, 242a: conductor, 242 A: Conductor layer, 242b: Conductor, 243: Region, 243a: Region, 243b: Region, 2 46: conductor, 250: insulator, 250A: insulating film, 254: insulator, 254A: insulating film , 260: conductor, 260a: conductor, 260Aa: conductive film, 260Ab: conductive film, 26 0b: conductor, 273: insulator, 274: insulator, 276: insulator, 280: insulator, 2 80A: insulator, 281: insulator, 283: insulator, 290: oxygen, 290_1: layer, 2 90_2: layer, 291: layer, 291_1: layer, 291_2: layer

Claims

[Claim 1] a first layer and a second layer on the first layer; the first layer and the second layer each have a transistor; The first layer and the second layer transistors are a first oxide; and a first conductor and a second conductor on the first oxide; a first insulator disposed over the first conductor, the second conductor, and the first oxide; a second insulator on the first insulator; a second oxide disposed on the first oxide between the first conductor and the second conductor; a third insulator on the second oxide; a third conductor on the third insulator; and a fourth insulator in contact with an upper surface of the second insulator, an upper surface of the second oxide, an upper surface of the third insulator, and an upper surface of the third conductor; The semiconductor device according to claim 1, wherein the first insulator and the fourth insulator are less permeable to oxygen than the second insulator.

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