Semiconductor device

Abstract

To provide a semiconductor device with a novel structure.SOLUTION: A semiconductor device includes: a first transistor including a channel formation region provided for a substrate including a semiconductor material, impurity regions provided to have the channel formation region therebetween, a first gate insulating layer on the channel formation region, a first gate electrode on the first gate insulating layer, and a first source electrode and a first drain electrode electrically connected to the impurity regions; and a second transistor including a second gate electrode on the substrate including the semiconductor material, a second gate insulating layer on the second gate electrode, an oxide semiconductor layer on the second gate insulating layer, and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technical field of the present invention relates to a semiconductor device and a manufacturing method thereof. It refers to all elements and devices that function by utilizing the properties of semiconductors. [Background technology]

[0002] Metal oxides exist in a wide variety of forms and are used for a variety of purposes. Indium oxide is well known as It is a material that has been developed and is used as a transparent electrode material for liquid crystal displays and other devices. do.

[0003] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: For example, tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin film transistors using various metal oxides in the channel formation region are already known (for example, , Patent Documents 1 to 4, Non-Patent Document 1, etc.).

[0004] Incidentally, metal oxides include not only single-component oxides but also multi-component oxides. For example, InGaO3(ZnO) with homologous phase m (m: natural number) is In, Ga and It is known as a multi-component oxide semiconductor containing Zn and Zn (for example, Non-Patent Documents 2 and 3, (See patent document 4, etc.).

[0005] The oxide semiconductors made of the above-mentioned In-Ga-Zn oxides are also thin-film transistors. It has been confirmed that the method can be applied to the channel forming region of a transistor (for example, Patent Document 5, Non-Patent Document 5 and Non-Patent Document 6). [Prior art documents] [Patent documents]

[0006] [License 1] Special Announcement No. 60-198861 [License 2] Special Announcement No. 8-264794 [License 3] Special Notice No. 11-505377 [License 4] Special Announcement No. 2000-150900 [Patent Document 5] Special Announcement No. 2004-103957 [Non-licensed literature]

[0007] [Non-licensed Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-licensed Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-licensed Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-patent document 4] Masaaki Nakamura, Noboru Kimizuka, Takahiko Mohri, Mitsumasa Isobe, "Synthesis and Crystal Structure of Homologous Phase, InFeO3(ZnO)m (m: natural number) and Its Isomorphic Compounds," Solid State Physics, 1993, Vol. 28, No. 5, pp. 317-327 [Non-patent document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-patent document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 Summary of the Invention [Problem to be solved by the invention]

[0008] Incidentally, field effect transistors, which are a typical example of semiconductor devices, use materials such as silicon. However, semiconductor devices that use silicon or other materials are generally constructed using However, the switching characteristics are not high enough, and for example, when constructing a CMOS inverter circuit, In some cases, a very large through current may destroy the semiconductor device. There was also the problem of increased power consumption due to through current. .

[0009] In addition, in semiconductor devices that use silicon or other materials, off-state current (also called leakage current) The difference between the two is not so small that it can be said to be practically zero. However, a small amount of current flows, causing problems with charge-retaining semiconductor devices such as memory devices and liquid crystal displays. When constructing a semiconductor device, it is difficult to ensure a sufficient charge retention period. However, there is also a problem that the power consumption of the semiconductor device increases due to the off-state current.

[0010] Therefore, one embodiment of the disclosed invention provides a semiconductor device having a new structure that solves the above-described problems. One of the objectives is to [Means for solving the problem]

[0011] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a transistor formed using other materials. The semiconductor device has a stacked structure with a transistor formed using the above-mentioned method. Such a configuration can be adopted.

[0012] One embodiment of the present invention is a semiconductor device including a channel formation region provided in a substrate including a semiconductor material, and a channel-type impurity regions provided so as to sandwich the channel formation region, and a first gate insulating layer on the channel formation region; a first gate electrode on the first gate insulating layer; and a first gate electrode electrically connected to the impurity region. a first transistor having a source electrode and a first drain electrode; a second gate electrode on the substrate; a second gate insulating layer on the second gate electrode; an oxide semiconductor layer on the gate insulating layer; and a second source electrode electrically connected to the oxide semiconductor layer. a first transistor having a first electrode and a second drain electrode; be.

[0013] In the above, the first gate electrode and the second gate electrode are electrically connected to each other. a source electrode or a first drain electrode, a second source electrode or a second drain electrode, Preferably, the first transistor is a p-type transistor. The first transistor is a p-channel transistor, and the second transistor is an n-channel transistor. (n-channel transistor) is preferable.

[0014] In the above, the first gate electrode and the second source electrode or the second drain electrode It is preferable that the and are electrically connected.

[0015] In the above, the substrate containing a semiconductor material may be a single crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate, and it is particularly preferable that the semiconductor material is silicon.

[0016] In the above, the oxide semiconductor layer is made of an In-Ga-Zn-O based oxide semiconductor material. In particular, the oxide semiconductor layer preferably contains In2Ga2ZnO7 crystals. Furthermore, the hydrogen concentration in the oxide semiconductor layer is preferably 5×10 19 ato ms / cm 3 The off-state current of the second transistor is preferably 1× or less. 10 -13 It is preferable to set it to A or less.

[0017] In the above, the second transistor is provided in a region overlapping with the first transistor. It can be configured as follows.

[0018] The first source electrode or the first drain electrode and the second source electrode or the second drain electrode The drain electrode may be formed integrally with the second source electrode or A part of the second drain electrode functions as the first source electrode or the first drain electrode. A part of the first source electrode or the first drain electrode may be The second electrode may function as the source electrode or the second drain electrode.

[0019] In this specification, the terms "above" and "below" refer to the positional relationship of the components "directly above" and "below." For example, the term "the first layer on the gate insulating layer" is not limited to "directly under" the first layer. If the expression "gate electrode" is used, other components are provided between the gate insulating layer and the first gate electrode. The terms "upper" and "lower" are used for the convenience of explanation. Unless otherwise specified, the terms "top" and "bottom" are interchangeable.

[0020] In addition, in this specification, the terms "electrode" and "wiring" are used to refer to these components functionally. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wire" are used interchangeably to refer to the plural "electrodes." This also includes cases where "wires" and "circuits" are formed integrally.

[0021] Generally, an "SOI substrate" is a substrate with a silicon semiconductor layer on an insulating surface. However, in this specification and the like, a semiconductor layer made of a material other than silicon is provided on an insulating surface. In other words, the semiconductor that "SOI substrate" has is used as a concept that includes the substrate with the structure. The layer is not limited to a silicon semiconductor layer. Not only semiconductor substrates such as silicon wafers, but also glass substrates, quartz substrates, sapphire substrates, and metal substrates In other words, it includes a conductive substrate with an insulating surface and a semiconductor substrate on an insulator substrate. The term "SOI substrate" broadly includes those having a layer made of a silicon material. In this document, "semiconductor substrate" does not only refer to a substrate made of semiconductor material, but also to a substrate made of semiconductor material. In other words, in this specification, the term "SOI substrate" is also used broadly. "Semiconductor substrate" is included in the category. [Effects of the Invention]

[0022] In one embodiment of the present invention, a transistor including a material other than an oxide semiconductor is provided in a lower portion, and A semiconductor device including a transistor including an oxide semiconductor is provided.

[0023] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor with an oxide semiconductor, Semiconductors that require different electrical properties (e.g., different carriers involved in the operation of the device) The device can be realized.

[0024] In addition, transistors using oxide semiconductors have good switching characteristics; For example, in a CMOS inverter circuit, Since the through current can be sufficiently suppressed, the power consumption of the semiconductor device can be reduced. The semiconductor device can be prevented from being damaged by a large current. Since the off-state current of a transistor is extremely small, the use of such a transistor reduces the power consumption of a semiconductor device. can be reduced. [Brief explanation of the drawings]

[0025] [Figure 1] 1A and 1B are cross-sectional and plan views illustrating a semiconductor device; [Figure 2] Circuit diagram for explaining a semiconductor device [Figure 3] 1A and 1B are cross-sectional and plan views illustrating a semiconductor device; [Figure 4] 1A and 1B are cross-sectional views illustrating a manufacturing process of a semiconductor device; [Figure 5] 1A and 1B are cross-sectional views illustrating a manufacturing process of a semiconductor device; [Figure 6] 1A and 1B are cross-sectional views illustrating a manufacturing process of a semiconductor device; [Figure 7] 1A and 1B are cross-sectional and plan views illustrating a semiconductor device; [Figure 8] Circuit diagram for explaining a semiconductor device [Figure 9] 1A and 1B are cross-sectional and plan views illustrating a semiconductor device; [Figure 10] Circuit diagram for explaining a semiconductor device [Figure 11] FIG. 1 is a diagram illustrating an electronic device using a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0026] An example of an embodiment of the present invention will be described below with reference to the drawings. and the present invention is not limited to the above description, and may be modified in various forms and forms without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the embodiments shown below.

[0027] In addition, the position, size, range, etc. of each component shown in the drawings etc. are for ease of understanding. Therefore, the actual position, size, range, etc. may not necessarily be shown in the drawings. The present invention is not limited to the position, size, range, etc. disclosed therein.

[0028] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0029] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. This will be described with reference to FIGS.

[0030] <Configuration of semiconductor device> FIG. 1A is a cross-sectional view of a semiconductor device according to this embodiment, and FIG. 1B is a cross-sectional view of the semiconductor device according to this embodiment. 1A and 1B show plan views of semiconductor devices according to the embodiments. These correspond to the cross sections taken along lines A1-A2 and D1-D2 in Figures 1(A) and 1(B). The semiconductor device shown in FIG. 1 has a p-type transistor 160 in the lower part and an oxide semiconductor in the upper part. An n-type transistor 162 is used.

[0031] The p-type transistor 160 includes a channel forming region provided in a substrate 100 containing a semiconductor material. 116, and the impurity regions 114 and high concentration The impurity region 120 (collectively referred to as the impurity region) and the channel forming region A gate insulating layer 108a is provided on the gate insulating layer 116, and a gate insulating layer 108b is provided on the gate insulating layer 108a. The gate electrode 110a and the impurity region 114 provided on one side of the channel forming region 116 a source or drain electrode 130a electrically connected to the channel forming region 116; The source electrode or drain electrode electrically connected to the impurity region 114 provided on the other side of the It has an electrode 130b.

[0032] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110a. In addition, the substrate 100 is provided with a sidewall insulating layer 118 sandwiched therebetween in a plan view. , a high concentration impurity region 120, and a metal compound region 124 on the high concentration impurity region 120. In addition, on the substrate 100, an element isolation insulating film is formed to surround the p-type transistor 160. The layer 106 is provided, and the interlayer insulating layer 126 and the and an interlayer insulating layer 128 are provided. Through the opening, the source electrode or drain electrode 130a is connected to the channel forming region 1 16 is electrically connected to a metal compound region 124 provided on one side of the The drain electrode 130b is made of a metal compound semiconductor layer provided on the other side of the channel forming region 116. The source or drain electrode 130a is electrically connected to the region 124. The channel is formed through a metal compound region 124 on one side of the channel forming region 116. A high concentration impurity region 120 and a channel forming region 116 are provided on one side of the channel forming region 116. The region 116 is electrically connected to the impurity region 114 provided on one side thereof, and is connected to the source electrode. The drain electrode 130b is formed on the other side of the channel forming region 116 by a metal compound. A high concentration impurity region is provided on the other side of the channel forming region 116 via the impurity region 124. 120 and the impurity region 114 provided on the other side of the channel forming region 116. is connected to.

[0033] The n-type transistor 162 includes a gate electrode 136c provided on the interlayer insulating layer 128 and a gate A gate insulating layer 138 is provided on the gate electrode 136c, and a gate insulating layer 138 is provided on the gate electrode 136c. and an oxide semiconductor layer 140 formed on the oxide semiconductor layer 140. 0, a source electrode or drain electrode 142a electrically connected to and a drain electrode 142b.

[0034] Here, the gate electrode 136c of the n-type transistor 162 is formed on the interlayer insulating layer 128. The gate electrode 136c is provided so as to be embedded in the insulating layer 132. Similarly, on the source electrode or drain electrode 130a, 130b of the p-type transistor 160 Electrodes 136a and 136b are formed in contact with the substrate.

[0035] In addition, on the n-type transistor 162, a layer is formed so as to be in contact with a part of the oxide semiconductor layer 140. A protective insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 are provided with a source electrode or a drain electrode. The openings reach the source or drain electrode 142a and the source or drain electrode 142b. The electrodes 150c and 150d are connected to the source electrode or the drain electrode through the openings. The gate electrode 142a is formed in contact with the source electrode or the drain electrode 142b. , electrodes 150c and 150d, as well as the gate insulating layer 138, the protective insulating layer 144, the interlayer The electrode 15 contacting the electrode 136a and the electrode 136b is inserted through an opening provided in the insulating layer 146. 0a and electrode 150b are formed.

[0036] Here, the oxide semiconductor layer 140 is highly purified by sufficiently removing impurities such as hydrogen. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 is preferably 5×10 19 atoms / cm 3 Below 5×10 18 atoms / cm 3 Below, more hope Preferably 5 x 10 17 atoms / cm 3 In addition, the hydrogen concentration is sufficiently reduced. By using the oxide semiconductor layer 140 that has been highly purified, the n-type transistor 162 For example, when the drain voltage Vd is +1 V or In the case of +10V, when the gate voltage Vg is in the range of -5V to -20V, the off-state current is 1×10 -13 In this way, the hydrogen concentration is sufficiently reduced and the product is highly purified. By using the oxide semiconductor layer 140, the off-state current of the n-type transistor 162 can be reduced. As a result, a semiconductor device with excellent characteristics can be obtained. The concentration is determined by secondary ion mass spectrometry (SIMS). The measurements were taken using spectroscopic techniques.

[0037] An insulating layer 152 is provided on the interlayer insulating layer 146, and a semiconductor device is embedded in the insulating layer 152. Electrodes 154a, 154b, and 154c are provided so that the electrodes The electrode 154a is in contact with the electrode 150a, and the electrode 154b is in contact with the electrode 150b and the electrode 150 Electrode 154c is in contact with electrode 150d.

[0038] That is, in the semiconductor device shown in FIG. 1, the source electrode or drain electrode of the p-type transistor 160 the drain electrode 130b and the source or drain electrode 142 of the n-type transistor 162 a are electrically connected to each other via electrodes 136b, 150b, 154b, and 150c. is connected to.

[0039] Also, the gate electrode 110a of the p-type transistor 160 and the gate electrode 110b of the n-type transistor 162 The electrode 136c is also electrically connected via electrodes formed on the interlayer insulating layer 126 and the interlayer insulating layer 128. electrically connected.

[0040] The source electrode or drain electrode 130a of the p-type transistor 160 is connected to the electrode 154 a, the electrode 150a, the electrode 136a, and the power supply line that supplies the first potential. The source electrode or drain electrode 142b of the n-type transistor 162 is The electrode 154c is electrically connected to a power supply line that supplies a second potential via the electrode 150d. .

[0041] A CMOS inverter in which a p-type transistor 160 and an n-type transistor 162 are connected in a complementary manner The equivalent circuit of the capacitor circuit is shown in FIG. 2. FIG. 2 shows the semiconductor device shown in FIG. 1(A) and FIG. 1(B). In this case, when the electrode 154a is set to a positive potential VDD and the electrode 154c is set to a ground potential GND, In this example, the ground potential may be replaced by a negative potential VDL.

[0042] Next, an n-type transistor or a p-type transistor is formed on the same substrate as the above-mentioned semiconductor device. The configuration when the capacitor is used alone will be described with reference to FIG. 3. Cross section of a p-type transistor 164 and an n-type transistor 166 using an oxide semiconductor thereon 3(A) is a diagram, and FIG. 3(B) is a plan view thereof. Note that FIG. 3(A) is a diagram of the line B1 in FIG. 3(B). 3 corresponds to a cross-sectional view taken along line C1-C2. The same reference numerals will be used to describe the configuration of each of the above.

[0043] First, the configuration and electrical connection relationship of the p-type transistor 164 will be described. The source or drain electrode 130c of the transistor 164 The electrode 130d includes an electrode 136d formed so as to be embedded in the insulating layer 132, an electrode 136b formed so as to be embedded in the insulating layer 132, and an electrode 136c formed so as to be embedded in the insulating layer 132. Electrodes 136d and 136e are electrically connected to each other. The gate insulating layer 138, the protective insulating layer 144, and the interlayer insulating layer 146 are formed so as to be embedded therein. The electrodes 150e and 150f are electrically connected to each other. 50e, and the electrode 150f includes an electrode 154d formed to be embedded in the insulating layer 152. , and electrodes 154e are electrically connected to each other. The source or drain electrode 130c of 64 is connected to the electrode 136d, the electrode 150e, and the electrode 1 54d, and the source electrode or drain electrode 130d are electrically connected to predetermined wiring via electrodes 136e, 150f, and 154e. Therefore, the p-type transistor 164 can be used alone.

[0044] Next, the structure and electrical connection relationship of the n-type transistor 166 will be described. Element separation On the isolation insulating layer 106, a gate insulating layer 108b is provided. Also, on the gate insulating layer 1 08b, a gate wiring 110b is provided. An electrode 130e formed so as to be embedded in the interlayer insulating layer 126 and the interlayer insulating layer 128 is electrically connected to the gate wiring 110b. The electrode 130e is electrically connected to a gate electrode 136f formed so as to be embedded in the insulating layer 132. As a result, the gate electrode 136f of the n-type transistor 16 6 is electrically connected to the gate wiring 110b via the electrode 130e, so that the n-type transistor 166 can be used alone.

[0045] <Method for fabricating a semiconductor device> Next, an example of the method for fabricating the semiconductor device will be described. Hereinafter, first, the method for fabricating the lower p-type transistor will be described, and then the method for fabricating the upper n-type transistor will be described.

[0046] <Method for fabricating a p-type transistor> First, a substrate 100 including a semiconductor material is prepared (see Fig. 4(A)). As the substrate 100 including a semiconductor material, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc. can be applied. Here, an example in the case of using a single crystal silicon substrate as the substrate 100 including a semiconductor material will be shown. In general, the "SOI substrate" refers to a substrate having a configuration in which a silicon semiconductor layer is provided on an insulating surface, but in this specification, etc., silicon on an insulating surface ​​​​​​​​​​The concept also includes substrates having semiconductor layers made of materials other than those mentioned above. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate has a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This includes those made up of:

[0047] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 4(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride oxide or the like can be used. In order to control the threshold voltage of the transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or a metal element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity include phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Sodium, gallium, etc. can be used.

[0048] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor substrate 100 is not exposed is removed. The conductive region 104 is formed (see FIG. 4(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0049] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 4(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. The insulating layer can be removed by polishing such as CMP or etching. Either method may be used. After the semiconductor region 104 is formed or after the element isolation insulating layer is formed, After the edge layer 106 is formed, the protective layer 102 is removed.

[0050] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0051] The insulating layer will later become the gate insulating layer and is obtained using a CVD method, sputtering method, etc. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. The surface of the semiconductor region 104 is oxidized or nitrided by plasma treatment or thermal oxidation treatment. The insulating layer may be formed by the high density plasma treatment. Using a mixture of rare gases such as Xe and oxygen, nitrogen oxide, ammonia, nitrogen, and hydrogen The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 10 nm or less. It can be 0 nm or less.

[0052] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, the insulating film can be formed using a semiconductor material such as polycrystalline silicon containing a conductive material. The method for forming the conductive material is not particularly limited, and examples thereof include vapor deposition, C Various film formation methods such as VD method, sputtering method, and spin coating method can be used. In this embodiment mode, the layer containing a conductive material is formed using a metal material. The following information will be provided.

[0053] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. 4(C) , a gate electrode 110a is formed (see FIG. 4(C)). A port wiring 110b can also be formed at the same time.

[0054] Next, an insulating layer 112 is formed to cover the gate electrode 110a (see FIG. 4(C)). Boron (B) or aluminum (Al) is added to the semiconductor region 104 to form a shallow junction. The impurity region 114 is formed (see FIG. 4C). The portion of the semiconductor region 104 below the gate insulating layer 108a becomes a channel forming region 116 (see FIG. 4(C)). The concentration of the added impurities can be set appropriately. It is desirable to increase the concentration in accordance with the degree of miniaturization of the element. The process of forming the impurity region 114 after forming the edge layer 112 is adopted. The insulating layer 112 may be formed after the region 114 is formed.

[0055] Next, a sidewall insulating layer 118 is formed (see FIG. 4(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, it can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110a and the impurity region 110b. The top surface of 114 is exposed.

[0056] Next, a layer is formed so as to cover the gate electrode 110a, the impurity region 114, the sidewall insulating layer 118, etc. Then, boron is doped in the region where the insulating layer contacts the impurity region 114. (B) or aluminum (Al) is added to form a high-concentration impurity region 120 (Fig. 4(E)). After that, the insulating layer is removed, and the gate electrode 110a and the sidewall insulating layer are removed. A metal layer 122 is formed so as to cover the edge layer 118, the high concentration impurity region 120, etc. (FIG. 4(E) The metal layer 122 can be formed by various methods such as vapor deposition, sputtering, and spin coating. The metal layer 122 can be formed by a film forming method. It is desirable to form the insulating layer using a metal material that reacts with the semiconductor material to form a low-resistance metal compound. Such metal materials include, for example, titanium, tantalum, tungsten, and nickel. , cobalt, platinum, etc.

[0057] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 4(F)). When polycrystalline silicon or the like is used as the gate electrode 110a, the metal layer 12 A metal compound region is also formed in the area in contact with 2.

[0058] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize a very short time of heat treatment. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. Since the metal compound region is formed by the metal compound, the region has a sufficiently high conductivity. By doing so, the electrical resistance can be sufficiently reduced and the device characteristics can be improved. After forming the alloy region 124, the metal layer 122 is removed.

[0059] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxide nitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as palladium. The interlayer insulating layer 126 may be formed using an organic insulating material such as acrylic. and interlayer insulating layer 128, the configuration of the interlayer insulating layer is not limited to this. After the interlayer insulating layer 128 is formed, its surface is planarized by a method such as CMP or etching. It is desirable to keep it flat.

[0060] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. The source or drain electrode 130a, the source or drain electrode 130b ( Either of these can be called a source wiring or a drain wiring) is formed (FIG. 4(H) (See reference to the source or drain electrode 130a, source or drain electrode 130 b is, for example, a conductive layer formed in the region including the opening by using a PVD method, a CVD method, or the like, and then The insulating layer is formed by removing a part of the conductive layer using a method such as etching or CMP. It is possible.

[0061] The conductive layer is partially removed to form the source or drain electrode 130a, the source electrode Alternatively, when forming the drain electrode 130b, the surface thereof is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. It removes the necessary tungsten film, titanium film, titanium nitride film, etc., and also maintains the flatness of the surface. In this way, the source electrode or drain electrode 130a, By planarizing the surface of the source or drain electrode 130b, It becomes possible to form good electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0062] Here, the source electrode or drain electrode 130 in contact with the metal compound region 124 In Fig. 1a, only the source electrode or the drain electrode 130b is shown, but in this process, Wiring and the like that come into contact with the port electrode 110a can also be formed. 3. In this way, a connection electrode 130e can be formed that contacts the gate wiring 110b shown in FIG. The source or drain electrode 130a and the source or drain electrode 130b are There are no particular limitations on the materials that can be used, and various conductive materials can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, Conductive materials such as zinc and scandium can be used.

[0063] In this way, a p-type transistor is formed using the substrate 100 containing a semiconductor material. After the process, wiring or the like may be further formed. By adopting a multilayer wiring structure having a laminated structure of conductive layers, a highly integrated semiconductor device can be provided.

[0064] <Method for fabricating an n-type transistor> Next, a process of fabricating an n-type transistor on the interlayer insulating layer 128 will be described using FIGS. 5 and 6. In FIGS. 5 and 6, since the fabrication process of the n-type transistor in the cross sections of the lines A1-A2 and D1-D2 shown in FIG. 1 is shown, the p-type transistor formed below the n-type transistor is omitted. First, an insulating layer 132 is formed on the interlayer insulating layer 128, the source electrode or drain electrode 130a, and the source electrode or drain electrode 130b (see FIG. 5(A)). The insulating layer 132 can be formed using a method such as the PVD method or the CVD method. Further, it can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc.

[0065] Next, openings reaching the source electrode or drain electrode 130a and openings reaching the source electrode or drain electrode 130b are formed in the insulating layer 132. At this time, an opening is also formed in the region where the gate electrode 136c will be formed later. Then, a conductive layer 134 is formed so as to be embedded in the above openings (see FIG. 5(B)). The above openings can be formed by a method such as etching using a mask. The mask can be formed by a method such as exposure using a photomask. As the etching, either wet etching or dry etching may be used, but from the viewpoint of microfabrication, dry etching

[0066] is preferably used.​​​​​​​​​​​​​ The conductive layer 134 is preferably formed by etching. The conductive layer 134 can be formed by a film formation method. are molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Examples include conductive materials such as aluminum and scandium, as well as their alloys and compounds (e.g., nitrides). It can be obtained.

[0067] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then a CVD method is applied. After forming a thin titanium nitride film by this method, a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method is Electrode (here, source electrode or drain electrode 130a, source electrode or drain electrode 130b) and has the function of reducing the oxide film at the interface with the lower electrode, thereby reducing the contact resistance with the lower electrode. In addition, the titanium nitride film formed afterwards acts as a barrier to prevent the diffusion of conductive materials. Prepare.

[0068] After the conductive layer 134 is formed, the conductive layer 134 is removed by a method such as etching or CMP. The insulating layer 132 is exposed by removing a part of the insulating layer 132, and the electrodes 136a, 136b, and the gate electrode 136 are formed. 5C. In addition, a part of the conductive layer 134 is removed to form an electrode 136c. When forming the electrode 136a, the electrode 136b, and the gate electrode 136c, the surfaces are made flat. In this way, it is desirable to process the insulating layer 132, the electrode 136a, the electrode 136b, By planarizing the surface of the gate electrode 136c, it is possible to obtain a good electrode and wiring in the subsequent process. It is possible to form lines, insulating layers, semiconductor layers, etc.

[0069] Next, the insulating layer 132, the electrode 136a, the electrode 136b, and the gate electrode 136c are covered with The gate insulating layer 138 is formed (see FIG. 5(D)). The gate insulating layer 138 is formed by a CVD method or The gate insulating layer 138 can be formed by a sputtering method or the like. Formed to contain silicon, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. Note that the gate insulating layer 138 may have a single layer structure or a stacked layer structure. For example, a plasma using silane (SiH4), oxygen, and nitrogen as raw material gases may be used. The gate insulating layer 138 made of silicon oxynitride can be formed by the CVD method. The thickness of the gate insulating layer 138 is not particularly limited, but is, for example, 20 nm or more and 500 nm or less. In the case of a laminated structure, for example, a first layer having a film thickness of 50 nm or more and 200 nm or less can be used. a first gate insulating layer and a second gate insulating layer having a thickness of 5 nm to 300 nm on the first gate insulating layer; It is preferable to use a laminate of insulating layers.

[0070] Note that an oxide semiconductor (high-temperature oxide semiconductor) that has been made i-type or substantially i-type by removing impurities is Since the purified oxide semiconductor is extremely sensitive to the interface states and the interface charges, When such an oxide semiconductor is used for the oxide semiconductor layer, the interface with the gate insulating layer is important. That is, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer has a high-quality oxide semiconductor layer. Quality will be required.

[0071] For example, the high density plasma CVD method using microwaves (2.45GHz) produces dense and high dielectric strength materials. This is advantageous in that a high quality gate insulating layer 138 can be formed. The close contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. Because it can be made into a good one.

[0072] Of course, if it can form a good insulating layer as a gate insulating layer, highly purified Even when an oxide semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and the acidity of the gate insulating layer can be improved by heat treatment after film formation. Alternatively, an insulating layer may be formed to improve the interface characteristics with the oxide semiconductor layer. The film quality as a gate insulating layer is good, and the interface state density with the oxide semiconductor layer is reduced. Any material that can form a good interface may be used.

[0073] Furthermore, at 85°C, 2 × 10 6 V / cm, 12-hour gate bias thermal stress test (B In the T test, when impurities are added to an oxide semiconductor, the impurities and the oxide semiconductor The bond with the main component of is broken by a strong electric field (B: bias) and high temperature (T: temperature), and The dangling bonds induce a shift in the threshold voltage (Vth).

[0074] In contrast, in one embodiment of the disclosed invention, impurities, particularly hydrogen and water, in an oxide semiconductor are removed. By eliminating as much as possible and improving the interface characteristics with the gate insulating layer as described above, the BT test This makes it possible to obtain a transistor that is stable even under high voltages.

[0075] Next, an oxide semiconductor layer is formed over the gate insulating layer 138 and etched using a mask. The oxide semiconductor layer is processed by the above method to form an island-shaped oxide semiconductor layer 140. (See FIG. 5(E)).

[0076] The oxide semiconductor layer includes In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn—O-based oxide semiconductor layer, and particularly an amorphous oxide semiconductor layer. In this embodiment, an In—Ga—Zn—O-based oxide semiconductor target is used as the oxide semiconductor layer. An amorphous oxide semiconductor layer is formed by a sputtering method using a non- By adding silicon to an crystalline oxide semiconductor layer, the crystallization of the layer can be suppressed. Therefore, for example, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used to form an oxide film. A semiconductor layer may be formed.

[0077] Examples of targets for forming an oxide semiconductor layer by sputtering include oxide A target for forming an oxide semiconductor film containing zinc as a main component can be used. A target for forming oxide semiconductor films containing Ga and Zn (composition ratio: In2O3:G It is also possible to use In As a target for forming oxide semiconductor films containing In2O3:Ga2O 3:ZnO=1:1:2 [molar ratio], or In2O3:Ga2O3:ZnO=1: A target having a composition ratio of 1:4 (molar ratio) may also be used. The target filling rate is 90% to 100%, preferably 95% to 99.9%. By using a target for oxide semiconductor film formation with a high filling rate, it is possible to form a dense oxide semiconductor. A conductor layer is formed.

[0078] The film formation atmosphere is a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas ( Typically, a mixed atmosphere of argon and oxygen is preferred. The concentration of impurities such as hydrogen, water, hydroxyl groups, and hydrides is on the order of several ppm (preferably several ppb It is preferable to use a high purity gas in which the concentration has been reduced to about 100 ppm.

[0079] When forming the oxide semiconductor layer, the substrate is held in a treatment chamber kept in a reduced pressure state. The temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By depositing the oxide semiconductor layer while heating, the concentration of impurities contained in the deposited oxide semiconductor layer can be reduced. In addition, damage caused by sputtering can be reduced. While removing moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and a metal oxide is sintered. An oxide semiconductor layer is formed as a get. To remove residual moisture in the processing chamber, an adsorption It is preferable to use a vacuum pump of this type. For example, a cryopump, an ion pump, a titanium It is preferable to use a sublimation pump. A cryopump with a cold trap may be used. The film formation chamber contains, for example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably Since the exhaust gas (including compounds containing carbon atoms) is exhausted, the oxide semiconductor layer formed in the deposition chamber The concentration of impurities contained can be reduced.

[0080] The formation conditions are, for example, a distance of 100 mm between the substrate and the target, a pressure of 0.6 Pa, DC power 0.5kW, oxygen atmosphere (oxygen flow rate 100%), The following conditions can be applied. When a pulsed direct current (DC) power supply is used, film formation can be performed. This reduces the amount of powdery material (also called particles or dust) that is generated at times, and the film thickness distribution is uniform. The oxide semiconductor layer has a thickness of 2 nm to 200 nm, preferably 5 nm or more. The thickness is set to 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material used. Therefore, the thickness may be appropriately selected depending on the material used.

[0081] Before forming the oxide semiconductor layer by sputtering, argon gas was introduced to Reverse sputtering is performed to generate a smear, and dust adhering to the surface of the gate insulating layer 138 is removed. Here, reverse sputtering refers to the process of removing the sputtering layer in a normal sputtering process. Instead of bombarding the target with ions, the treatment surface is bombarded with ions. The method of bombarding the treated surface with ions is as follows: A high frequency voltage is applied to the surface to be treated in an argon atmosphere to generate plasma near the substrate. In addition, nitrogen atmosphere, helium atmosphere, oxygen atmosphere, etc. can be used instead of argon atmosphere. An atmosphere or the like may also be used.

[0082] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. To enable etching, the etching conditions (etching gas, etching solution, etc.) are adjusted to suit the material. The etching time, temperature, etc. are set appropriately.

[0083] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas). Chlorides such as chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride Fluorine-containing gases (fluorine-based gases, etc.) can also be used. fluoride, such as carbon tetrafluoride (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluoride (CHF3, etc.), hydrogen bromide (HBr), oxygen (O2), and A gas to which a rare gas such as helium (He) or argon (Ar) is added may also be used.

[0084] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are set appropriately.

[0085] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) or the like may be used.

[0086] Next, the oxide semiconductor layer is subjected to first heat treatment. The conductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 300°C. The temperature is set to 750°C or higher, preferably 400°C or higher but lower than the distortion point of the substrate. The substrate is placed in an electric furnace using a furnace or the like, and the oxide semiconductor layer 140 is heated to 450 ... Heat treatment is performed at 0° C. for 1 hour. During this time, the oxide semiconductor layer 140 is not exposed to the air. This will prevent the re-incorporation of water or hydrogen.

[0087] The heat treatment device is not limited to an electric furnace, and may be any other device that uses heat conduction from a medium such as heated gas, or The heating element may be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0088] For example, as the first heat treatment, a base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The plate is moved and placed in the oven, heated for several minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. GRTA processing can be used to process the product after it has been removed from the oven. In addition, since the heat treatment is short, the temperature condition is above the distortion point of the substrate. It can be applied even if

[0089] Note that the first heat treatment is performed using a gas containing nitrogen or a rare gas (helium, neon, argon, or the like) as a main component. It is desirable to carry out the process in an atmosphere that is free from water, hydrogen, etc. For example, the purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device. is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. It is preferable to keep the impurity concentration at 1 ppm or less, preferably 0.1 ppm or less.

[0090] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer In some cases, the crystallization rate is 90% or more, or the crystallization rate is 90% or more. In some cases, the oxide semiconductor layer is microcrystalline or 80% or more. Depending on the condition or the material of the oxide semiconductor layer, an amorphous oxide semiconductor containing no crystalline components may be used. It may be layered.

[0091] In addition, microcrystals (grain size of 1 nm or less) are formed on the amorphous oxide semiconductor (for example, on the surface of the oxide semiconductor layer). The oxide semiconductor layer is a mixture of the upper 20 nm or less (typically 2 nm to 4 nm). For example, an In-Ga-Zn-O oxide semiconductor film formation target is used. When forming an oxide semiconductor layer, the crystal of In2Ga2ZnO7, which has electrical anisotropy, is used. By providing a microcrystalline portion in which grains are oriented, the electrical characteristics of the oxide semiconductor layer can be changed. In this way, the crystal grains of In2Ga2ZnO7 are aligned in the microcrystalline part, and the oxide semiconductor By forming the oxide semiconductor layer on the surface of the oxide semiconductor layer, for example, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved. This can improve the insulating properties in the direction perpendicular to the surface of the oxide semiconductor layer. The microcrystalline portion has a function of suppressing the penetration of impurities such as water and hydrogen into the oxide semiconductor layer. Note that the oxide semiconductor layer described above has a surface treatment by GRTA treatment. It can be formed by heat. Also, the Zn content is smaller than the In or Ga content. By using a small sputtering target, it is possible to form the film more suitably.

[0092] The first heat treatment on the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In that case, the first heat treatment may be performed on the oxide semiconductor layer before the first heat treatment. The substrate is then removed from the device and subjected to a photolithography process.

[0093] Note that the first heat treatment has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called dehydration treatment, dehydrogenation treatment, etc. The dehydrogenation treatment is carried out after the oxide semiconductor layer is formed. After laminating the drain electrode, a protective insulating layer is formed on the source electrode or drain electrode. Such dehydration treatment can be carried out at any time, such as after the treatment. The dehydrogenation treatment may be carried out not only once but also multiple times.

[0094] Next, a source electrode or drain electrode 142a, The source or drain electrode 142b is formed (see FIG. 5(F)). The drain electrode 142a and the source or drain electrode 142b are formed on the oxide semiconductor layer 1 After forming a conductive layer to cover 40, the conductive layer is selectively etched. It can be formed.

[0095] The conductive layer is formed using PVD methods such as sputtering or CVD methods such as plasma CVD. The conductive layer may be made of aluminum, chromium, copper, or tantalum. , titanium, molybdenum, tungsten, or a compound containing the above elements. Gold, etc. can be used. Manganese, magnesium, zirconium, beryllium, tritium Alternatively, one or more materials selected from aluminum may be used. , titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium A material containing a single or multiple selected elements may be used. For example, aluminum containing silicon may be used. a single layer structure of titanium film, a two-layer structure with titanium film laminated on aluminum film, and a titanium film and aluminum film Examples include a three-layer structure in which an aluminum film and a titanium film are laminated.

[0096] Here, the exposure to light when forming the mask used for etching is ultraviolet light, KrF laser light, or ArF It is preferable to use laser light. The lower end of the electrode 142a and the source or drain electrode 14 on the oxide semiconductor layer 140 The channel length (L) of the transistor is determined by the distance from the bottom end of 2b. When exposure is performed with a channel length (L) of less than 25 nm, the channel length is extremely small, ranging from several nm to several tens of nm. Extreme ultraviolet light with extremely short wavelengths is used to create a mask-shaped Extreme ultraviolet light exposure provides high resolution and a large depth of focus. The channel length (L) of the formed transistor is set to 10 nm or more and 1000 nm or less. Furthermore, the off-state current is extremely small, Even with miniaturization, power consumption does not increase.

[0097] Note that when the conductive layer is etched, the oxide semiconductor layer 140 is not removed. The material and etching conditions are adjusted as appropriate. In this step, the oxide semiconductor layer 140 is partially etched to form a groove (a recess). ) may be formed as an oxide semiconductor layer.

[0098] In addition, between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142a, An oxide conductive layer is formed between the conductive layer 140 and the source or drain electrode 142b. The oxide conductive layer and the source or drain electrode 142a or the source or drain electrode 142b may be The metal layer for forming the drain electrode 142b is formed continuously (continuous film formation). The oxide conductive layer can function as a source region or a drain region. By providing such an oxide conductive layer, it is possible to reduce the resistance of the source region or the drain region. This allows the transistor to operate at high speed.

[0099] In order to reduce the number of masks used and the number of processes, an exposure method is used in which the transmitted light has multiple intensities. The etching process is performed using a resist mask formed by a multi-tone mask. The resist mask formed using the multi-tone mask may have a shape having a plurality of film thicknesses. The shape can be further deformed by ashing, resulting in different patterns. It can be used for multiple etching processes. Thus, a resist mask corresponding to at least two different patterns is formed. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can be performed more efficiently. This also reduces the number of steps, simplifying the process.

[0100] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. It is preferable that the plasma treatment is performed on the exposed surface of the oxide semiconductor layer. Adhered water and other substances are removed. In addition, plasma treatment is performed using a mixture of oxygen and argon gas. You may go.

[0101] Next, the protective insulating layer 14 in contact with a part of the oxide semiconductor layer 140 is removed without being exposed to the air. 4 is formed (see Figure 5(G)).

[0102] The protective insulating layer 144 has a thickness of 1 nm or more, and is formed by applying water, The protective insulating layer 14 can be formed by using an appropriate method that does not mix impurities such as hydrogen. Materials that can be used for 4 include silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide. The structure may be a single layer structure or a laminated structure. The substrate temperature when forming the protective insulating layer 144 is preferably set to be equal to or higher than room temperature and equal to or lower than 300°C. The atmosphere may be a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically A mixed atmosphere of nitrogen (e.g., argon) and oxygen is preferred.

[0103] If hydrogen is contained in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer or the oxide semiconductor layer may be damaged by the hydrogen. Oxygen is extracted from the oxide semiconductor layer by the oxide semiconductor layer. Therefore, the protective insulating layer 1 may have a low resistance and a parasitic channel may be formed. It is important to avoid using hydrogen in the formation method so that 44 does not contain as much hydrogen as possible. is.

[0104] In addition, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The compound semiconductor layer 140 and the protective insulating layer 144 are formed so as not to contain hydrogen, hydroxyl groups, or water. This is because.

[0105] To remove residual moisture from the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. The exhaust means is preferably a turbo pump with a cold trap added. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms and water (H2 O) and other compounds containing hydrogen atoms are removed, The concentration of impurities contained in the layer 144 can be reduced.

[0106] The sputtering gas used when forming the protective insulating layer 144 is hydrogen, water, a hydroxyl group, or The concentration of impurities such as hydrides is reduced to a few ppm (preferably a few ppb). It is preferable to use a high purity gas.

[0107] Next, a second heat treatment (preferably 2 It is desirable to carry out the heating at a temperature between 00°C and 400°C, for example, between 250°C and 350°C. For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. This can reduce variations in the electrical characteristics of the transistors.

[0108] In addition, heat treatment is carried out in the atmosphere at 100°C to 200°C for 1 hour to 30 hours. This heat treatment may be carried out by maintaining a constant heating temperature, or by heating from room temperature to 10 Repeat the heating process from 0°C to 200°C and then cooling it down to room temperature several times. Alternatively, this heat treatment may be performed under reduced pressure before forming the protective insulating layer. If the heating treatment is performed under reduced pressure, the heating time can be shortened. The treatment may be carried out in place of the second heat treatment or after the second heat treatment. stomach.

[0109] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see FIG. 6(A)). The edge layer 146 can be formed by using a PVD method, a CVD method, or the like. silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide The interlayer insulating layer 146 can be formed using a material containing an inorganic insulating material such as silica. After that, it is desirable to flatten the surface by a method such as CMP or etching. It's nice.

[0110] Next, the electrode 1 is formed on the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138. 36a, electrode 136b, source or drain electrode 142a, source or drain electrode An opening is formed that reaches the inner electrode 142b, and the conductive layer 148 is formed so as to fill the opening. The opening is formed by etching using a mask or the like (see FIG. 6(B)). The mask can be formed by a method such as exposure using a photomask. Etching can be either wet etching or dry etching. However, from the viewpoint of fine processing, it is preferable to use dry etching. The conductive layer 148 can be formed by a film formation method such as a PVD method or a CVD method. Materials that can be used to form the conductive layer 148 include molybdenum, titanium, chromium, Conductive materials such as tantalum, tungsten, aluminum, copper, neodymium, and scandium and alloys and compounds (for example, nitrides) thereof.

[0111] Specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then a CVD method is applied. After forming a thin titanium nitride film by this method, a tungsten film is formed so as to fill the opening. Here, the titanium film formed by the PVD method is Electrodes (here, electrodes 136a, 136b, source or drain electrodes 142a, The oxide film at the interface with the source electrode or drain electrode 142b is reduced, and the contact with the lower electrode is The titanium nitride formed thereafter has the function of reducing the resistance of the conductive material. It has a barrier function that suppresses diffusion.

[0112] After the conductive layer 148 is formed, the conductive layer 148 is removed by a method such as etching or CMP. 150a, 150b, and 150c are removed to expose the interlayer insulating layer 146. 50c and an electrode 150d are formed (see FIG. 6(C)). When forming the electrodes 150a, 150b, 150c, and 150d by removing the layers, It is desirable to process the surface so that it is flat. By planarizing the surfaces of the electrodes 150a, 150b, 150c, and 150d, In subsequent processes, it becomes possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc. do.

[0113] Furthermore, an insulating layer 152 is formed, and the electrodes 150a, 150b, and 150c are attached to the insulating layer 152. 50c, an opening reaching the electrode 150d is formed, and a conductive layer is formed so as to be embedded in the opening. After the formation of the insulating layer 15, a part of the conductive layer is removed by a method such as etching or CMP. 2 is exposed to form electrodes 154a, 154b, and 154c (see FIG. 6(D)). This step is the same as that for forming the electrodes 150a and the like, and therefore the details will be omitted.

[0114] When the n-type transistor 162 is fabricated by the above-described method, the water content of the oxide semiconductor layer 140 is The element concentration is 5 x 10 19 atoms / cm 3 The following is true: Off-state current is 1×10 -13 A or less, and preferably 100zA / μm or less. By using such an oxide semiconductor layer 140 in which the hydrogen concentration is sufficiently reduced and which is highly purified, As a result, an n-type transistor 162 with excellent characteristics can be obtained. The semiconductor has excellent characteristics, with an n-type transistor using an oxide semiconductor on top. A conductor device can be fabricated.

[0115] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor with an oxide semiconductor, Semiconductors that require different electrical properties (e.g., different carriers involved in the operation of the device) The device can be realized.

[0116] Transistors using oxide semiconductors have good switching characteristics. For example, in a CMOS inverter circuit, Since the current can be sufficiently suppressed, the power consumption of the semiconductor device can be reduced and a large current can be In addition, a transistor using an oxide semiconductor can be prevented from being damaged by the damage. Since the off-state current is extremely small, the use of this reduces the power consumption of semiconductor devices. It is possible.

[0117] In this embodiment, the p-type transistor 160 and the n-type transistor 162 are stacked. However, the present invention is not limited to this example. The p-type transistor 162 and the n-type transistor 163 may be formed on the same substrate. In the example, the channel length directions of the n-type transistor 160 and the n-type transistor 162 are perpendicular to each other. However, the positional relationship between the p-type transistor 160 and the n-type transistor 162 is Furthermore, the p-type transistor 160 and the n-type transistor 16 2 may be provided overlapping each other.

[0118] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0119] (Embodiment 2) In this embodiment, a structure of a semiconductor device according to another embodiment of the disclosed invention will be described with reference to FIGS. 8. In this embodiment, the semiconductor device can be used as a memory element. Possible configurations of semiconductor devices are shown.

[0120] FIG. 7A is a cross-sectional view of a semiconductor device according to this embodiment, and FIG. 7B is a cross-sectional view of the semiconductor device according to this embodiment. 7A and 7B show plan views of semiconductor devices according to the embodiments. These correspond to cross sections taken along lines E1-E2 and F1-F2. The semiconductor device shown in FIG. 1 includes a transistor 260 using a material other than an oxide semiconductor in the lower part. The transistor 262 includes an oxide semiconductor in the upper portion.

[0121] The transistor 260 using a material other than an oxide semiconductor is formed on a substrate 200 containing a semiconductor material. The channel forming region 216 is provided between the first and second electrodes 216a and 216b. The impurity region 214 and the high-concentration impurity region 220 (collectively referred to simply as the impurity region) ) and a gate insulating layer 208a provided on the channel forming region 216, and a gate insulating layer A gate electrode 210a is provided on the layer 208a, and a channel forming region 216 is provided on one side of the gate electrode 210a. A source electrode or drain electrode 230a electrically connected to the impurity region 214 is provided. and the impurity region 214 provided on the other side of the channel forming region 216. The source electrode or drain electrode 230b is connected to the source electrode or drain electrode 230a. The electrode 230a is formed by connecting the metal compound region 224 provided on one side of the channel forming region 216. The impurity region 214 is electrically connected to the channel forming region 216 via the impurity region 214. The source or drain electrode 230b is connected to the other side of the channel forming region 216. The metal compound region 224 is formed on the other side of the channel forming region 216. It is preferable that the transistor is electrically connected to the impurity region 214. The configuration of the p-type transistor 260 is the same as that of the p-type transistor 160 described in the previous embodiment. Therefore, for other details, the previous embodiment can be referred to. The polarity of the transistor 260 does not have to be limited to p-type, but may be n-type.

[0122] The transistor 262 using an oxide semiconductor has a gate electrode 2 provided over an insulating layer 228. 36c, a gate insulating layer 238 provided on the gate electrode 236c, and a gate insulating layer 23 8, and an oxide semiconductor layer 240 provided on the oxide semiconductor layer 240. A source electrode or drain electrode 242a electrically connected to the semiconductor layer 240, The transistor 262 has a source or drain electrode 242b. Since the configuration is the same as that of the n-type transistor 162 described in the previous embodiment, For details of the transistor 262, the above embodiment can be referred to. The polarity of the layer is not limited to n-type, but may be p-type.

[0123] Next, the electrical connection relationship between the transistor 260 and the transistor 262 will be described. The source or drain electrode 230a of the transistor 260 is connected to the electrode 236a, 250a, and the electrode 254a are electrically connected to predetermined wiring. The source or drain electrode 230b of the transistor 260 is connected to the electrode 236b, the electrode 25 0b, and is electrically connected to predetermined wiring via electrodes 254b and the like.

[0124] The source or drain electrode 242a of the transistor 262 is connected to the electrode 250d, the electrode 2 54c, electrode 250c, electrode 236b, and electrode 230c. The source electrode 210a of the transistor 262 is electrically connected to the source electrode 210b of the transistor 262. The drain electrode 242b is connected to a predetermined wiring via an electrode 250e, an electrode 254d, etc. are electrically connected.

[0125] In FIG. 7, the element isolation insulating layer 206 is the same as the element isolation insulating layer 106 of the first embodiment. The sidewall insulating layer 218 is formed on the sidewall insulating layer 118 of the first embodiment by using an interlayer insulating layer. The layer 226 corresponds to the interlayer insulating layer 126 of the first embodiment, and the insulating layer 232 corresponds to the insulating layer 1 of the first embodiment. 32, the protective insulating layer 244 corresponds to the protective insulating layer 144 of the first embodiment, and the interlayer insulating layer 246 corresponds to the actual The insulating layer 252 corresponds to the interlayer insulating layer 146 in the first embodiment, and the insulating layer 252 corresponds to the insulating layer 152 in the first embodiment. do.

[0126] FIG. 8 shows an example of a circuit diagram in which the semiconductor device is used as a memory element.

[0127] The source electrode of the transistor 260 using a material other than an oxide semiconductor is connected to the first source wiring (Source 1). The drain electrode of the transistor 260 is electrically connected to the drain wiring (Drain). In addition, the gate electrode of the transistor 260 using a material other than an oxide semiconductor is formed using an oxide semiconductor. The gate electrode is electrically connected to the drain electrode of the transistor 262 using a nitride semiconductor.

[0128] The source electrode of the transistor 262 using an oxide semiconductor is connected to the second source wiring (Source ce2). In addition, the transistor 262 using an oxide semiconductor The gate electrode is electrically connected to a gate wiring (Gate).

[0129] Here, the transistor 262 including an oxide semiconductor has a feature of having an extremely low off-state current. Therefore, when the transistor 262 is turned off, It is possible to maintain the potential of the gate electrode of 260 for an extremely long period of time.

[0130] By utilizing the feature of maintaining the potential of the gate electrode, for example, First, the potential of the gate wiring (Gate) is The transistor 262 is turned on as a potential at which the transistor 262 is turned on. As a result, the potential of the second source wiring (Source2) becomes the gate of the transistor 260. Then, the potential of the gate line is applied to the gate electrode (write operation). The potential at which the transistor 262 is turned off is set to turn the transistor 262 off.

[0131] Since the off-state current of the transistor 262 is extremely small, the gate electrode of the transistor 260 The potential is maintained for a long time. More specifically, for example, If the potential of the gate electrode is such that transistor 260 is turned on, transistor 26 The ON state of transistor 260 is maintained for a long time. If the potential of the gate electrode is such that the transistor 260 is in the off state, the transistor 26 The off state of 0 is maintained for a long period of time.

[0132] Therefore, according to the potential held at the gate electrode of the transistor 260, the drain wiring For example, the potential of the gate electrode of transistor 260 is If the potential is a potential that turns on the transistor 260, the transistor 260 is turned on. Therefore, the potential of the drain wiring (Drain) is maintained at the same level as the first source wiring In this way, the potential of the drain wiring (Drain) The potential will take on different values ​​depending on the potential held at the gate electrode of transistor 260. By reading this (read operation), it functions as a memory element.

[0133] The semiconductor device according to this embodiment can be used for a very long time due to the off-state current characteristics of the transistor 262. Since it is possible to retain information for a long period of time, it can be used as a substantially nonvolatile memory element. It is possible to do so.

[0134] In this embodiment, for ease of understanding, only the minimum unit of a memory element has been explained. However, the configuration of the semiconductor device is not limited to this. For example, a more advanced semiconductor device can be constructed by using a plurality of the memory elements. It is possible to configure a NAND type or NOR type semiconductor device by using the same wiring configuration as shown in FIG. It is not limited to this and can be changed as appropriate.

[0135] As described above, in one embodiment of the present invention, the off-state current characteristics of the transistor 262 are used to Thus, according to one aspect of the present invention, a new non-volatile memory element is formed. Thus, a semiconductor device having such a configuration is provided.

[0136] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0137] (Embodiment 3) In this embodiment, a structure of a semiconductor device according to another embodiment of the disclosed invention will be described with reference to FIGS. 10. In this embodiment, the semiconductor device is used as a memory element. The structure of a semiconductor device that can achieve this will be described.

[0138] FIG. 9A is a cross-sectional view of a semiconductor device according to this embodiment, and FIG. 9B is a cross-sectional view of the semiconductor device according to this embodiment. 9A and 9B show plan views of semiconductor devices according to the embodiments. These correspond to cross sections taken along lines G1-G2 and H1-H2. The semiconductor device shown in FIG. 1 has a p-type transistor 46 made of a material other than an oxide semiconductor at the bottom. 0 and an n-type transistor 464, and a transistor 46 using an oxide semiconductor thereon. It has 2.

[0139] A p-type transistor 460 and an n-type transistor 464 using a material other than an oxide semiconductor This configuration is the same as the p-type transistor 160 and the transistor 260 in the previous embodiment. The structure of the transistor 462 including an oxide semiconductor is the same as that of the transistor 462 in the above embodiment. This is similar to the n-type transistor 162 and the transistor 262 in the Each component of the transistor is also similar to that of the transistor of the previous embodiment. For details, the above embodiments can be referred to.

[0140] In FIG. 9, the substrate 400 is the substrate 100 of the first embodiment, with an element isolation insulating layer 406 corresponds to the element isolation insulating layer 106 of the first embodiment, and the gate insulating layer 408a corresponds to the gate insulating layer 106 of the first embodiment. The gate electrode 410a is formed on the gate insulating layer 108a, and the gate electrode 410a is formed on the gate electrode 110a of the first embodiment. The gate wiring 410b corresponds to the gate wiring 110b of the first embodiment, and the impurity region 414 corresponds to the gate wiring 110b of the first embodiment. The channel forming region 416 is the same as the channel forming region 1 of the first embodiment. 16, the sidewall insulating layer 418 is the same as the sidewall insulating layer 118 of the first embodiment, The high concentration impurity region 420 is the high concentration impurity region 120 of the first embodiment, and the metal compound region 4 24 corresponds to the metal compound region 124 of the first embodiment, and the interlayer insulating layer 426 corresponds to the interlayer insulating layer 124 of the first embodiment. The insulating layer 126 is connected to the interlayer insulating layer 428 of the first embodiment. The source or drain electrode 430a is the same as the source or drain electrode 130a of the first embodiment. The source or drain electrode 430b is the source or drain electrode of the first embodiment. 130b, the source electrode or drain electrode 430c is the electrode 130e of the second embodiment, Each corresponds to.

[0141] The insulating layer 432 corresponds to the insulating layer 132 of the first embodiment, and the electrode 436a corresponds to the electrode 132 of the first embodiment. The electrode 136a corresponds to the electrode 136b of the first embodiment, and the gate electrode 436c corresponds to the electrode 136b of the first embodiment. The gate electrode 136c of the first embodiment has a gate insulating layer 438. 138, the oxide semiconductor layer 440 is the oxide semiconductor layer 140 of the first embodiment, and the source electrode Alternatively, the drain electrode 442a may be the same as the source electrode or drain electrode 142a of the first embodiment. The source electrode or drain electrode 442b is the same as the source electrode or drain electrode of the first embodiment. The protective insulating layer 444 is formed on the electrode 142b in the same manner as the protective insulating layer 144 of the first embodiment. 6 corresponds to the interlayer insulating layer 146 of the first embodiment, and the electrode 450a corresponds to the electrode 150a of the first embodiment. Electrode 450b corresponds to electrode 150b of the first embodiment, and electrode 450c corresponds to electrode 150b of the first embodiment. 50b, electrode 450d corresponds to electrode 150c of the first embodiment, and electrode 450e corresponds to electrode 150c of the first embodiment. The insulating layer 452 corresponds to the insulating layer 152 of the first embodiment, and the electrode 454a corresponds to the The electrode 154a of the first embodiment is the electrode 154b of the first embodiment, and the electrode 454 The electrode 454c corresponds to the electrode 154b of the first embodiment, the electrode 454d corresponds to the electrode 154c of the first embodiment, and Each will be handled accordingly.

[0142] The semiconductor device according to the present embodiment has a drain electrode of a transistor 462 and a p-type transistor The gate electrode of the n-type transistor 460 and the gate electrode of the n-type transistor 464 are electrically connected to each other. This differs from the semiconductor device according to the previous embodiment in that it is connected (see FIG. 9). By using this configuration, the input signal (INPU T) can be temporarily held.

[0143] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0144] (Fourth embodiment) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the above embodiment will be described. The semiconductor device obtained in the above embodiment has a switching characteristic Since the device has a transistor using an oxide semiconductor with high performance, it can reduce the power consumption of each electronic device. Furthermore, new semiconductor devices utilizing the characteristics of oxide semiconductors (for example, memory Since various electronic devices (such as semiconductor devices) are provided, it is possible to provide electronic devices with new configurations. The semiconductor device according to the above embodiment may be mounted on a circuit board or the like as a single unit or integrated. These will be installed inside each electronic device.

[0145] The integrated circuit in which the semiconductor device is incorporated and integrated is the semiconductor device described in the previous embodiment. In addition, they are often constructed by incorporating various circuit elements such as resistors, capacitors, and coils. Examples of integrated circuits include arithmetic circuits, conversion circuits, amplifier circuits, memory circuits, and combinations of these. MPUs and CPUs are among the most highly integrated circuits. It can be said that this is the case.

[0146] The semiconductor device can also be used as a switching element in a display device. In this case, it is preferable to provide a driving circuit on the same substrate. The semiconductor device may be used only for the driver circuit of the device.

[0147] FIG. 11A shows a notebook personal computer including the semiconductor device according to the above embodiment. The computer is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. It has been completed.

[0148] FIG. 11B shows a personal digital assistant (PDA) including the semiconductor device according to the above embodiment. The main body 311 includes a display unit 313, an external interface 315, an operation button 314, etc. Also, a stylus 312 is provided as an accessory for operation.

[0149] FIG. 11C shows an example of electronic paper including the semiconductor device according to the above embodiment. The electronic book 320 is shown. The electronic book 320 is made up of two housings, housing 321 and housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337. The opening and closing operation can be performed around the shaft portion 337. It can be used like this:

[0150] The housing 321 incorporates a display unit 325, and the housing 323 incorporates a display unit 327. The display unit 325 and the display unit 327 may be configured to display a continuous screen, or may be configured to display different screens. By configuring to display different screens, for example, The text is displayed on the right display unit (display unit 325 in FIG. 11(C)), and the text is displayed on the left display unit (display unit 325 in FIG. 11(C)). In (C), an image can be displayed on the display unit 327).

[0151] FIG. 11C shows an example in which an operation unit and the like are provided on the housing 321. The body 321 includes a power supply 331, operation keys 333, a speaker 335, and the like. The page can be turned by using the operation keys 333. The device may be configured to include a keyboard, a pointing device, etc. , external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable) A configuration including a terminal that can be connected to various cables such as a recording medium insertion section, Furthermore, the electronic book 320 may be configured to have the function of an electronic dictionary. .

[0152] The electronic book 320 may also be configured to be able to send and receive information wirelessly. It is also possible to purchase and download desired book data from the child book server. It is possible.

[0153] Electronic paper can be applied to any field that displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as gift cards.

[0154] FIG. 11D shows a mobile phone including the semiconductor device according to the above embodiment. The handset is composed of two housings, housing 340 and housing 341. Housing 341 contains: Display panel 342, speaker 343, microphone 344, pointing device 346, a camera lens 347, and an external connection terminal 348. 0 includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. The antenna is built into the housing 341.

[0155] The display panel 342 is equipped with a touch panel, and in FIG. 11(D) multiple images are displayed. The number of operation keys 345 is indicated by dotted lines. A boost circuit is implemented to boost the output voltage to the voltage required for each circuit. In addition to the above configuration, it is also possible to incorporate a contactless IC chip, a small recording device, etc. Cut.

[0156] The display direction of the display panel 342 changes appropriately depending on the usage mode. The camera lens 347 is located on the same surface as the camera 42, making it possible to make video calls. The speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, playback Furthermore, the housing 340 and the housing 341 can be slid to each other, and the housing 340 and the housing 341 can be slid to each other, as shown in FIG. It can be folded from the unfolded state to the stacked state, making it compact and suitable for portability. It is possible.

[0157] The external connection terminal 348 can be connected to various cables such as an AC adapter or a USB cable. It is possible to charge the battery and to communicate data with a personal computer. A recording medium can be inserted into the slot 350 to accommodate the storage and transfer of larger amounts of data. In addition to the above functions, it may also have infrared communication functions, television reception functions, etc. stomach.

[0158] FIG. 11E shows a digital camera including the semiconductor device according to the previous embodiment. The digital camera comprises a main body 361, a display unit (A) 367, an eyepiece 363, and an operation switch 364. , a display unit (B) 365, a battery 366, etc.

[0159] FIG. 11F shows a television set including the semiconductor device according to the above embodiment. The vision device 370 has a display unit 373 built into a housing 371. In addition, the stand 375 supports the housing 3. The configuration shown supports 71.

[0160] The television device 370 can be operated using an operation switch provided on the housing 371 or a separate remote control. This can be done by operating the operating device 380. The remote control operating device 380 has an operating key 379. This allows you to control the channel and volume, and to operate the image displayed on the display unit 373. In addition, the remote control operation device 380 can receive the output from the remote control operation device 380. A display unit 377 for displaying the information may be provided.

[0161] It is preferable that the television device 370 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, The purpose of this communication is to communicate information between two parties (one party) or two-way (between a sender and a receiver, or between receivers). It is possible to do this.

[0162] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. Can be used in combination [Explanation of symbols]

[0163] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108a Gate insulating layer 108b Gate insulating layer 110a gate electrode 110b Gate wiring 110c wiring 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c Source or drain electrode 130d Source or drain electrode 130e electrode 132 Insulating layer 134 Conductive Layer 136a electrode 136b Electrode 136c Gate electrode 136d electrode 136e electrode 136f gate electrode 138 Gate insulating layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective Insulation Layer 146 Interlayer insulation layer 148 Conductive Layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 150f electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 154e electrode 160 p-type transistors 162 n-type transistor 164 p-type transistors 166 n-type transistor 200 boards 206 Element isolation insulating layer 208a Gate insulating layer 210a gate electrode 214 Impurity region 216 Channel formation region 218 Sidewall insulating layer 220 High concentration impurity region 224 Metal compound area 226 Interlayer insulation layer 228 Insulating Layer 230a Source electrode or drain electrode 230b Source electrode or drain electrode 230c electrode 232 Insulating layer 236a Electrode 236b Electrode 236c Gate electrode 238 Gate insulating layer 240 Oxide semiconductor layer 242a Source electrode or drain electrode 242b Source or drain electrode 244 Protective Insulation Layer 246 Interlayer Insulation Layer 250a electrode 250b electrode 250c electrode 250d electrode 250e electrode 252 Insulating layer 254a electrode 254b electrode 254c electrode 254d electrode 260 transistors 262 transistors 301 Main Unit 302 Case 303 Display section 304 keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Button 315 External Interface 320 e-books 321 Case 323 Case 325 Display section 327 Display section 331 Power supply 333 Operation Key 335 Speaker 337 Shaft 340 Case 341 Case 342 Display Panel 343 Speaker 344 Microphone 345 Operation Key 346 Pointing Device 347 Camera Lenses 348 External connection terminal 349 Solar Cells 350 external memory slot 361 Main Unit 363 Eyepiece 364 Operation Switch 365 Display section (B) 366 Battery 367 Display section (A) 370 Television Equipment 371 Case 373 Display section 375 Stand 377 Display section 379 Operation Key 380 Remote Controlled Device 400 boards 406 Element isolation insulating layer 408a Gate insulating layer 410a gate electrode 410b Gate wiring 414 Impurity region 416 Channel formation region 418 Sidewall insulating layer 420 High concentration impurity region 424 Metal compound area 426 Interlayer Insulation Layer 428 Interlayer Insulation Layer 430a Source electrode or drain electrode 430b Source electrode or drain electrode 430c Source or drain electrode 432 Insulating layer 436a electrode 436b Electrode 436c Gate electrode 438 Gate insulating layer 440 Oxide semiconductor layer 442a Source or drain electrode 442b Source or drain electrode 444 Protective Insulation Layer 446 Interlayer Insulation Layer 450a electrode 450b electrode 450c electrode 450d electrode 450e electrode 452 Insulation Layer 454a electrode 454b electrode 454c electrode 454d electrode 460 p-type transistors 462 transistors 464 n-type transistor

Claims

1. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor in its second channel formation region. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. A semiconductor device in which two or more potentials are input to the gate of the first transistor via the second channel formation region, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film and a region in contact with the oxide semiconductor film, A fourth insulating film having a region positioned above the third insulating film, A third conductive film having a region positioned above the fourth insulating film, The first conductive film is electrically connected to the oxide semiconductor film via the third conductive film. The first insulating film comprises nitrogen and silicon, The second insulating film has a laminated structure of an insulating film having nitrogen and silicon and an insulating film having oxygen and silicon. The third insulating film comprises oxygen and silicon, The fourth insulating film comprises nitrogen and silicon, A semiconductor device wherein, in a plan view, the first conductive film does not have a region that overlaps with the oxide semiconductor film.

2. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor in its second channel formation region. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. A semiconductor device in which two or more potentials are input to the gate of the first transistor via the second channel formation region, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film and a region in contact with the oxide semiconductor film, A fourth insulating film having a region positioned above the third insulating film, A third conductive film having a region positioned above the fourth insulating film, The first conductive film is electrically connected to the oxide semiconductor film via the third conductive film. The first insulating film comprises nitrogen and silicon, The second insulating film has a laminated structure of an insulating film having nitrogen and silicon and an insulating film having oxygen and silicon. The third insulating film comprises oxygen and silicon, The fourth insulating film comprises nitrogen and silicon, In a plan view, the first conductive film does not have a region that overlaps with the oxide semiconductor film. In a plan view, the maximum length of the oxide semiconductor film in the channel length direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. In a plan view, the maximum length of the third conductive film in the channel length direction of the second transistor is greater than the maximum length of the third conductive film in the channel width direction of the second transistor. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the region in the channel width direction of the second transistor in which the third conductive film overlaps with the first conductive film. A semiconductor device wherein, in a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor.

3. In claim 1 or claim 2, The present invention provides a fourth conductive film having a region located above the fourth insulating film and electrically connected to the silicon semiconductor layer having the first channel-forming region, A constant potential is applied to the fourth conductive film. When the constant potential is applied to either the source or the drain of the first transistor, the potential of the other source or drain of the first transistor is controlled according to the charge held at least at the gate of the first transistor. A semiconductor device wherein the third conductive film and the fourth conductive film have regions in contact with the upper surface of the fourth insulating film.

4. In any one of claims 1 to 3, A semiconductor device in which, in a plan view, the channel formation region of the first transistor has a region through which current flows in a direction intersecting the channel length direction of the second transistor.

5. In any one of claims 1 to 4, The second transistor has an off-current of 1 × 10⁻⁶ －１９ A semiconductor device with a density of A / μm or less.

Images