Semiconductor light emitting device and manufacturing method of the semiconductor light emitting device

Abstract

To provide a semiconductor light emitting device and a manufacturing method of the semiconductor light emitting device, in which a columnar semiconductor layer is buried with an n-type buried semiconductor layer to reduce resistance.SOLUTION: A semiconductor light emitting device (100) includes: a growth substrate (10); a mask (20) formed on the growth substrate (10); and a columnar semiconductor layer grown from an opening provided in the mask (20). An n-type nanowire layer (12) is formed at a center of the columnar semiconductor layer, an active layer (13) is formed on the outer periphery of the n-type nanowire layer (12), and a p-type semiconductor layer (14) is formed on an outer periphery of the active layer (13). A metal layer (15) is formed on the outer periphery of the p-type semiconductor layer (14), and an n-type buried semiconductor layer (16) is formed to cover the metal layer (15).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor light-emitting device and a method for manufacturing the same. [Background technology]

[0002] In recent years, rapid advances have been made in crystal growth methods for nitride-based semiconductors, leading to the practical application of high-brightness light-emitting devices using these materials. It is desirable for such semiconductor light-emitting devices using nitride semiconductors to achieve high energy conversion efficiency and high optical output in high current density regions, and to have stable light distribution characteristics for the emitted light. To address these issues, Patent Document 1 proposes a semiconductor light-emitting device in which an n-type nanowire core, an active layer, and a p-type layer are grown on a semiconductor substrate.

[0003] The semiconductor light-emitting device disclosed in Patent Document 1, in which an active layer is formed on the outer periphery of a nanowire core, has fewer crystal defects and threading dislocations than one in which the active layer is formed on the entire surface of a sapphire substrate, allowing for higher quality crystals and, because m-plane growth is possible, improved external quantum efficiency at high current densities can be achieved. Furthermore, in the semiconductor light-emitting device using the nanowire core of Patent Document 1, the active layer can be formed from high quality crystals, which is expected to enable the In composition of the active layer to be increased, thereby achieving longer wavelengths. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-040676 Summary of the Invention [Problem to be solved by the invention]

[0005] In Cited Document 1, a tunnel junction layer is formed around the outer periphery of the nanowire, and the side and top surfaces of the nanowire are covered with an n-type buried semiconductor layer to reduce resistance. However, it is very difficult to form a high-quality tunnel junction layer on the side surface of the nanowire.

[0006] Therefore, the present invention has been made in consideration of the above-mentioned conventional problems, and aims to provide a semiconductor light-emitting element that can achieve low resistance by burying a columnar semiconductor layer with an n-type buried semiconductor layer, and a method for manufacturing the semiconductor light-emitting element. [Means for solving the problem]

[0007] In order to solve the above problem, the semiconductor light-emitting element of the present invention is a semiconductor light-emitting element comprising a growth substrate, a mask formed on the growth substrate, and a columnar semiconductor layer grown from an opening provided in the mask, wherein the columnar semiconductor layer has an n-type nanowire layer formed in the center, an active layer formed on the outer periphery of the n-type nanowire layer, a p-type semiconductor layer formed on the outer periphery of the active layer, a metal layer formed on the outer periphery of the p-type semiconductor layer, and an n-type buried semiconductor layer formed covering the metal layer.

[0008] In such a semiconductor light-emitting element of the present invention, a metal layer is formed on the outer periphery of the p-type semiconductor layer, and an n-type buried semiconductor layer is formed covering the metal layer, so that the columnar semiconductor layer can be buried with the n-type buried semiconductor layer to achieve low resistance.

[0009] In one embodiment of the present invention, the metal layer is made of Al or Mg.

[0010] In one aspect of the present invention, the metal layer is formed in a dotted or mesh pattern on the surface of the p-type semiconductor layer, and the p-type semiconductor layer and the buried semiconductor layer are in contact with each other at least partially.

[0011] In one embodiment of the present invention, the metal layer has a thickness of 3 nm or less and transmits light from the active layer.

[0012] In one embodiment of the present invention, the metal layer has a thickness of 10 nm or more and reflects light from the active layer.

[0013] In one aspect of the present invention, a transparent electrode is formed on the buried semiconductor layer.

[0014] In order to solve the above problem, the method for manufacturing a semiconductor light-emitting element of the present invention includes a masking step of forming a mask layer having an opening on a growth substrate, and a growth step of forming a columnar semiconductor layer in the opening using selective growth, wherein the growth step includes a nanowire growth step of forming an n-type nanowire layer, an active layer growth step of forming an active layer outside the n-type nanowire layer, a p-type layer growth step of forming a p-type semiconductor layer outside the active layer, a metal layer formation step of forming a metal layer outside the p-type semiconductor layer, and a buried semiconductor layer formation step of forming an n-type buried semiconductor layer covering the metal layer.

[0015] In one aspect of the present invention, the metal layer forming step is performed by MOCVD in the same manufacturing apparatus as the p-type layer growing step. [Effects of the Invention]

[0016] The present invention can provide a semiconductor light emitting device capable of achieving low resistance by burying a columnar semiconductor layer with an n-type buried semiconductor layer, and a method for manufacturing the semiconductor light emitting device. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a schematic diagram showing a semiconductor light emitting device 100 according to a first embodiment. [Figure 2] 2A and 2B are schematic diagrams showing a method for manufacturing a semiconductor light-emitting element 100 according to the first embodiment, in which FIG. 2A shows a mask formation process, FIG. 2B shows a nanowire growth process, an active layer growth process, a p-type layer growth process, and a metal layer growth process, FIG. 2C shows a burying process, and FIG. 2D shows an electrode formation process. [Figure 3] 1 is a schematic diagram showing light extraction from the semiconductor light emitting device 100 according to the first embodiment. [Figure 4] 10 is a schematic diagram showing light extraction from the semiconductor light emitting device 100 according to the second embodiment. FIG. [Figure 5] FIG. 10 is a schematic cross-sectional view showing the structure of a columnar semiconductor layer and a metal layer 15a in a semiconductor light emitting device 100 according to a third embodiment. [Figure 6] 6A and 6B are schematic diagrams showing examples of the shape of the metal layer 15a in the third embodiment, where FIG. 6A shows an example in which the metal layer 15a is formed in a dotted pattern, and FIG. 6B shows an example in which the metal layer 15a is formed in a mesh pattern.

[0018] (First embodiment) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant explanations will be omitted where appropriate. Figure 1 is a schematic diagram showing a semiconductor light emitting device 100 according to this embodiment.

[0019] 1, the semiconductor light emitting element 100 includes a growth substrate 10, an underlayer 11, a mask 20, an n-type nanowire layer 12, an active layer 13, a p-type semiconductor layer 14, a metal layer 15, a buried semiconductor layer 16, a transparent electrode 17, a cathode electrode 18, and an anode electrode 19. The n-type nanowire layer 12, the active layer 13, and the p-type semiconductor layer 14 are selectively grown in a direction perpendicular to the growth substrate 10 to form a columnar shape, which constitutes the columnar semiconductor layer of the present invention.

[0020] The growth substrate 10 is a substantially flat plate-shaped member made of a material suitable for growing semiconductor crystals, with a mask 20 formed on its main surface. The growth substrate 10 may be made of a single material, or may be a single-crystal substrate with multiple semiconductor layers, such as a buffer layer, grown on it. The growth substrate 10 may be any single-crystal substrate made of a material suitable for growing a semiconductor single-crystal layer via a buffer layer. When the semiconductor light-emitting device 100 is made of a nitride-based semiconductor, a c-plane sapphire substrate is preferred, but other heterogeneous substrates, such as Si, may also be used. Furthermore, a c-plane GaN substrate, which allows for easy formation of cavity planes by cleavage, may also be used for laser oscillation. The buffer layer is a layer formed between the single-crystal substrate and the underlayer 11 to reduce lattice mismatch between them. When a c-plane sapphire substrate is used as the single-crystal substrate, GaN is preferably used as the material, but AlN, AlGaN, or other materials may also be used. Although FIG. 1 illustrates an example in which the growth substrate 10 is included in the semiconductor light-emitting device 100, the growth substrate 10 may be removed by grinding or lift-off.

[0021] The underlayer 11 is a single-crystal semiconductor layer formed on the growth substrate 10 or buffer layer, and is preferably composed of multiple layers, with an undoped GaN layer formed to a thickness of several μm and an n-type semiconductor layer such as an n-type contact layer formed thereon. The n-type contact layer is a semiconductor layer doped with n-type impurities, such as Si-doped n-type Al. 0.05 Ga 0.95 1, a cathode electrode 18 is formed on a part of the underlayer 11.

[0022] The mask 20 is a layer made of a dielectric material formed on the surface of the underlayer 11. The material constituting the mask 20 is selected from those that make it difficult for semiconductor crystals to grow, such as SiO2 or SiN. x A plurality of openings 21 (described later) are formed in the mask 20, and a semiconductor layer can be grown on the base layer 11 in the openings 21.

[0023] The pillar-shaped semiconductor layer is a semiconductor layer crystal-grown in the openings 21 formed in the mask 20, and is formed as a substantially pillar-shaped semiconductor layer standing vertically relative to the main surface of the growth substrate 10. Such a pillar-shaped semiconductor layer is obtained by setting appropriate growth conditions according to the semiconductor material to be used and performing selective growth that grows a specific crystal plane orientation. Since the mask 20 has a plurality of openings 21 formed periodically in a two-dimensional manner, the pillar-shaped semiconductor layer is also formed periodically in a two-dimensional manner on the growth substrate 10.

[0024] The n-type nanowire layer 12 is a columnar semiconductor layer selectively grown on the underlayer 11 exposed through the opening 21 in the mask 20. The n-type nanowire layer 12 is made of, for example, GaN doped with n-type impurities. When GaN is used as the n-type nanowire layer 12, the n-type nanowire layer 12 selectively grown on the c-plane of the underlayer 11 has a roughly hexagonal columnar shape with six m-planes formed as facets. In FIG. 1, the n-type nanowire layer 12 appears to grow only in the region where the opening 21 is formed. However, in reality, crystal growth also progresses on the mask 20 due to lateral growth, resulting in the formation of an enlarged hexagonal columnar structure around the opening 21. For example, if the opening 21 is formed as a circle with a diameter of approximately 150 nm, the n-type nanowire layer 12 can be formed as a hexagonal columnar structure with a height of approximately 1 to 2 μm, with a base that is a hexagon inscribed in a circle with a diameter of approximately 240 nm.

[0025] The active layer 13 is a semiconductor layer grown on the outer periphery of the n-type nanowire layer 12, and may be, for example, a multi-quantum well active layer formed by stacking five periods of 5-nm-thick GaInN quantum well layers and 10-nm-thick GaN barrier layers. While a multi-quantum well active layer is used here, it may also have a single quantum well structure or a bulk active layer. Since the active layer 13 is formed on the side and top surfaces of the n-type nanowire layer 12, the area of ​​the active layer 13 can be secured.

[0026] The p-type semiconductor layer 14 is a semiconductor layer grown on the outer periphery of the active layer 13, and is made of, for example, GaN doped with p-type impurities. Because the p-type semiconductor layer 14 is formed on the side and top surfaces of the active layer 13, a double heterostructure is formed by the n-type nanowire layer 12, the active layer 13, and the p-type semiconductor layer 14, which can effectively confine carriers in the active layer 13 and improve the probability of radiative recombination.

[0027] Metal layer 15 is a layer made of a metal material grown on the outer periphery of p-type semiconductor layer 14. There are no limitations on the material that makes up metal layer 15, but in order to inject current into p-type semiconductor layer 14, it is preferable that the material be in ohmic contact with p-type semiconductor layer 14, such as Pt, Pd, Ni, Au, Cu, W, Ag, Mo, Pb, Al, Ti, or Mg. There are no limitations on the method for forming metal layer 15, and examples that can be used include sputtering, EB (Electron-Beam) deposition, MBE (Molecular Beam Epitaxy), PLD (Pulsed Laser Deposition), and MOCVD (Metal Organic Chemical Vapor Deposition).

[0028] Preferably, the metal layer 15 can be formed by MOCVD in the same apparatus as the p-type semiconductor layer 14, consecutively, and examples thereof include Al and Mg. The metal layer 15 may be formed to a thickness of 3 nm or less to transmit light from the active layer 13. The metal layer 15 may be formed to a thickness of 10 nm or more to reflect light from the active layer 13.

[0029] The buried semiconductor layer 16 is a semiconductor layer formed to cover the top and side surfaces of the pillar-shaped semiconductor layer and the metal layer 15, and to cover all the way down to the mask 20. As shown in FIG. 1, the buried semiconductor layer 16 also covers the metal layer 15 above the pillar-shaped semiconductor layer. The buried semiconductor layer 16 is also formed between adjacent pillar-shaped semiconductor layers. The buried semiconductor layer 16 is in ohmic contact with the transparent electrode 17 and is an n-type semiconductor layer in order to inject carriers via the metal layer 15. Although the buried semiconductor layer 16 is shown here as a single layer, it may be composed of multiple semiconductor layers with different materials, compositions, and impurity concentrations.

[0030] The transparent electrode 17 is an electrode that is in ohmic contact with the buried semiconductor layer 16 and transmits light emitted from the active layer 13, and can be made of, for example, ITO or a metal multilayer film. The transparent electrode 17 can be formed by a known sputtering method or EB deposition method. Here, an example is shown in which the transparent electrode 17 is formed over the entire upper surface of the buried semiconductor layer 16, but if the buried semiconductor layer 16 can sufficiently diffuse current, the transparent electrode 17 may not be provided. Furthermore, if the semiconductor light emitting element 100 is mounted by flip-chip connection and the light emitted from the active layer 13 is extracted from the growth substrate 10 side, a reflective electrode that reflects light may be formed instead of the transparent electrode 17.

[0031] The cathode electrode 18 is an electrode formed in an area where the underlayer 11 is exposed, and is composed of a laminated structure of a pad electrode and a metal material that is in ohmic contact with the outermost surface of the underlayer 11. The anode electrode 19 is an electrode formed on a portion of the buried semiconductor layer 16, and is composed of a laminated structure of a pad electrode and a metal material that is in ohmic contact with the outermost surface of the buried semiconductor layer 16. If necessary, a known structure may be applied, such as covering the surface of the semiconductor light emitting element 100 with a protective film.

[0032] 2A and 2B are schematic diagrams showing a method for manufacturing a semiconductor light-emitting element 100 according to this embodiment, in which FIG. 2A shows a mask formation process, FIG. 2B shows a nanowire growth process, an active layer growth process, a p-type layer growth process, and a metal layer growth process, FIG. 2C shows a burying process, and FIG. 2D shows an electrode formation process.

[0033] First, in the mask formation process shown in FIG. 2(a), a GaN buffer layer and an underlayer 11 made of GaN and AlGaN are grown on a growth substrate 10 made of a single crystal sapphire using metalorganic chemical vapor deposition (MOCVD). Next, a SiO2 mask 20 is deposited on the underlayer 11 to a thickness of approximately 30 nm using a sputtering method, and multiple openings 21 with a diameter of approximately 150 nm are formed using a fine pattern formation method such as nanoimprinting lithography. The buffer layer is grown under the following conditions: source gases include TMA (TriMethyl Aluminum), TMG (TriMethyl Gallium), and ammonia; a growth temperature of 1100°C; a V / III ratio of 1000; and a pressure of 10 hPa using hydrogen as a carrier gas. The growth conditions for the underlayer 11 and the n-type semiconductor layer are, for example, a growth temperature of 1050°C; a V / III ratio of 1000; and a pressure of 500 hPa using hydrogen as a carrier gas.

[0034] 2(b), an n-type nanowire layer 12 made of GaN is grown by selective growth using the MOCVD method on the base layer 11 exposed from the opening 21. The growth conditions for the n-type nanowire layer 12 are, for example, TMG and ammonia as source gases, a growth temperature of 1050°C, a V / III ratio of 10, hydrogen as carrier gas, and a pressure of 100 hPa.

[0035] In the active layer growth step, MOCVD is used to grow active layer 13, which consists of five periods of 5-nm-thick GaInN quantum well layers and 10-nm-thick GaN barrier layers, on the side and top surfaces of n-type nanowire layer 12. The growth conditions for active layer 13 are, for example, a growth temperature of 800°C, a V / III ratio of 3000, a pressure of 1000 hPa using nitrogen as the carrier gas, and raw material gases of TMG, TMI (TriMethylIndium), and ammonia.

[0036] In the p-type layer growth step, a p-type semiconductor layer 14 made of GaN doped with p-type impurities is grown. The growth conditions for the p-type semiconductor layer 14 are, for example, a growth temperature of 950°C, a V / III ratio of 1000, a pressure of 300 hPa using hydrogen as a carrier gas, and TMG, Cp2Mg (bisCycropentadienylMagnesium), and ammonia as source gases. As a result, a columnar semiconductor layer is formed from the n-type nanowire layer 12, the active layer 13, and the p-type semiconductor layer 14.

[0037] Next, in the metal layer growth process, the MOCVD apparatus used in the p-type layer growth process is used to form the metal layer 15 by MOCVD, continuing from the p-type layer growth process. When Al is used for the metal layer 15, TMA can be used as the source gas. When Mg is used for the metal layer 15, CpMg can be used as the source gas. The growth conditions for the metal layer 15 are, for example, a growth temperature in the range of 600°C to 1300°C, more preferably a temperature range of 800°C to 1300°C. In the metal layer growth process, the supply of TMG is stopped to supply only the material for the metal layer 15, and hydrogen, nitrogen, or a mixture of hydrogen and nitrogen is used as the carrier gas. An example of the metal layer growth process is a temperature of 950°C, a carrier gas flow rate of hydrogen 46 slm, nitrogen 46 slm, a source gas flow rate of TMA 10 sccm, and a film formation time of 10 seconds.

[0038] Next, in the burying step shown in FIG. 2(c), a buried semiconductor layer 16 made of n-type GaN is grown to fill the periphery and top surface of the metal layer 15. The buried semiconductor layer 16 must be grown on the mask 20 provided between the columnar semiconductor layers. During growth of the buried semiconductor layer 16, voids may form beneath the columnar semiconductor layers. Therefore, the buried semiconductor layer 16 is preferably grown using TMG, silane, and ammonia as source gases at a low temperature and a low V / III ratio to promote lateral m-plane growth in the initial stage. Examples of low temperatures and low V / III ratios include a V / III ratio of 100 or less at 800°C or below, a hydrogen carrier gas, and a pressure of 200 hPa. After the lateral growth of the buried semiconductor layer 16 completely fills the mask 20 beneath the columnar semiconductor layers, it is preferable to grow the buried semiconductor layer 16 at a high temperature and a high V / III ratio to promote vertical c-plane growth. An example of a high temperature and a high V / III ratio is a temperature of 1000°C or higher, a V / III ratio of 2000 or higher, and a pressure of 500 hPa using hydrogen as a carrier gas.

[0039] 2(d), the region where the element isolation region and the cathode electrode 18 are to be formed is selectively dry etched, and the buried semiconductor layer 16 and the columnar semiconductor layer are removed down to the mask 20, exposing the upper surface of the base layer 11. After that, annealing is performed in an air atmosphere at 600°C to remove the hydrogen absorbed in the p-type semiconductor layer 14 and activate the p-type semiconductor layer 14. Although annealing in an air atmosphere is shown here, any atmosphere that does not contain atomic hydrogen that can activate the p-type semiconductor layer 14 may be used.

[0040] Finally, a transparent electrode 17 and an anode electrode 19 are formed on the buried semiconductor layer 16, and a cathode electrode 18 is formed on the surface of the base layer 11. If necessary, annealing after electrode formation, formation of a protective film, and element division are performed to obtain a semiconductor light-emitting element 100.

[0041] In the semiconductor light emitting device 100 of this embodiment, when a voltage is applied between the anode electrode 19 and the cathode electrode 18, a current flows through the buried semiconductor layer 16, the metal layer 15, the p-type semiconductor layer 14, the active layer 13, the n-type nanowire layer 12, and the underlayer 11 in that order, and light is generated by radiative recombination in the active layer 13. The light emitted from the active layer 13 is extracted to the outside of the semiconductor light emitting device 100.

[0042] 3 is a schematic diagram showing light extraction from the semiconductor light emitting device 100 according to this embodiment. The arrows in the figure schematically show the path of light emitted in the active layer 13. In the example shown in FIG. 3, the metal layer 15 is formed with a thickness of 3 nm or less that allows light to pass through. The light emitted in the active layer 13 passes through the p-type semiconductor layer 14 and the metal layer 15 and is extracted to the buried semiconductor layer 16 side.

[0043] Furthermore, in the semiconductor light emitting device 100 of this embodiment, the active layer 13 is formed on the outer periphery of the n-type nanowire layer 12, and a metal layer 15 is further formed on the outer periphery thereof and buried with a buried semiconductor layer 16. Therefore, current injected from the anode electrode 19 is injected from the buried semiconductor layer 16 through the metal layer 15 to the active layer 13 from the top surface and sidewalls of the p-type semiconductor layer 14. Current injection via the metal layer 15 has low resistance, allowing for good current injection. Furthermore, because the buried semiconductor layer 16, which is an n-type semiconductor layer, allows current to diffuse more easily than a p-type semiconductor layer, current can be diffused well on the side surfaces of the columnar semiconductor layer to the vicinity of the bottom surface, allowing for good current injection from the entire metal layer 15.

[0044] As a result, the current injected from the anode electrode 19 is effectively injected into the p-type semiconductor layer 14 from the entire side surface of the pillar-shaped semiconductor layer rather than from the top surface thereof, thereby enabling effective current injection into the active layer 13, realizing a high current density and improving external quantum efficiency. In addition, by forming a metal layer 15 on the outer periphery of the pillar-shaped semiconductor layer and burying it with an n-type buried semiconductor layer 16, it is possible to reduce the resistance of the semiconductor light-emitting element 100.

[0045] Furthermore, because the side surfaces of the n-type nanowire layer 12 are m-planes formed by selective growth, the active layer 13 and p-type semiconductor layer 14 formed on the outer periphery are also in contact with each other at the m-plane. The m-plane is a nonpolar plane and does not generate polarization, so the light emission efficiency of the active layer 13 is high, and since all the side surfaces of the hexagonal prism are m-planes, the light emission efficiency of the semiconductor light emitting device 100 can be improved. Furthermore, because the film thickness of the active layer 13 can be increased, the volume of the active layer 13 can be increased by approximately 3 to 10 times that of conventional semiconductor light emitting devices, which reduces the injected carrier density and significantly reduces efficiency droop.

[0046] As described above, in the semiconductor light-emitting element 100 and the manufacturing method thereof of this embodiment, the metal layer 15 is formed on the outer periphery of the p-type semiconductor layer 14, and the n-type buried semiconductor layer 16 is formed to cover the metal layer 15, so that the columnar semiconductor layer can be buried with the n-type buried semiconductor layer 16 to achieve low resistance.

[0047] (Second embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. 4. Descriptions of content that overlap with the first embodiment will be omitted. FIG. 4 is a schematic diagram showing light extraction from a semiconductor light emitting device 100 according to this embodiment. The arrows in the figure schematically indicate the path of light emitted in the active layer 13. In the example shown in FIG. 4, a metal layer 15 is formed with a thickness of 10 nm or more that reflects light. Light emitted in the active layer 13 passes through the p-type semiconductor layer 14 and reaches the metal layer 15, is reflected by the metal layer 15, and travels again toward the p-type semiconductor layer 14. The light passes through the active layer 13, the n-type nanowire layer 12, and the underlayer 11, and is finally extracted from the growth substrate 10 side.

[0048] In this embodiment, since light emitted from the active layer 13 is extracted from the growth substrate 10 side, an electrode may be formed with a material and thickness that blocks light, rather than forming the transparent electrode 17 on the buried semiconductor layer 16. Furthermore, in order to extract light from the growth substrate 10 side, the semiconductor light emitting element 100 may be mounted on a submount or a circuit board by flip-chip connection.

[0049] In the semiconductor light-emitting element 100 and the manufacturing method thereof of this embodiment, the metal layer 15 is formed on the outer periphery of the p-type semiconductor layer 14, and the n-type buried semiconductor layer 16 is formed covering the metal layer 15, so that the columnar semiconductor layer can be buried with the n-type buried semiconductor layer 16 to achieve low resistance.

[0050] (Third embodiment) Next, a third embodiment of the present invention will be described with reference to FIGS. 5 and 6. Description of content overlapping with the first embodiment will be omitted. FIG. 5 is a schematic cross-sectional view showing the structure of the columnar semiconductor layer and the metal layer 15a in the semiconductor light emitting device 100 according to this embodiment. In this embodiment, the metal layer 15a is formed in a dotted or mesh-like pattern on the surface of the p-type semiconductor layer 14, and at least a portion of the p-type semiconductor layer 14 and the buried semiconductor layer 16 are in contact with each other. In this embodiment, the formation of the metal layer 15a is stopped before the entire surface of the p-type semiconductor layer 14 is covered, and the buried semiconductor layer 16 is formed in a state in which a portion of the p-type semiconductor layer 14 is exposed between the metal layers 15a.

[0051] FIG. 6 is a schematic diagram showing an example of the shape of the metal layer 15a in this embodiment. FIG. 6(a) shows an example in which the metal layer 15a is formed in a dotted pattern, and FIG. 6(b) shows an example in which the metal layer 15a is formed in a mesh pattern. In the example shown in FIG. 6(a), the metal layer 15a is separated into multiple regions, and the metal layers 15a are formed in dotted or island-like patterns on the surface of the p-type semiconductor layer 14. This represents a state in which the metal material precipitated as growth nuclei when the metal layer 15a is formed using the MOCVD method grows over time. In the example shown in FIG. 6(b), the metal layer 15a is formed by connecting multiple regions, and the surface of the p-type semiconductor layer 14 is exposed in dotted or island-like patterns between the metal layers 15a. This represents a state in which the metal material precipitated as growth nuclei when the metal layer 15a is formed using the MOCVD method grows over time, connecting adjacent metal layers 15a, but not covering the entire surface of the p-type semiconductor layer 14.

[0052] In this embodiment, the buried semiconductor layer 16 is in partial contact with the p-type semiconductor layer 14, but is also in contact with the metal layer 15a. Therefore, current can be effectively injected from the buried semiconductor layer 16 to the p-type semiconductor layer 14 via the metal layer 15a, thereby reducing the resistance of the semiconductor light emitting device 100. Furthermore, because the metal layer 15a is formed in a dotted or mesh-like pattern, light emitted in the active layer 13 passes through the region where the buried semiconductor layer 16 and the p-type semiconductor layer 14 are in contact and is extracted. Therefore, even if the thickness of the metal layer 15a is greater than 3 nm, light can be extracted from the buried semiconductor layer 16 side, as in the example shown in FIG. 3.

[0053] In the semiconductor light-emitting element 100 and the manufacturing method thereof of this embodiment, the metal layer 15 is formed on the outer periphery of the p-type semiconductor layer 14, and the n-type buried semiconductor layer 16 is formed covering the metal layer 15, so that the columnar semiconductor layer can be buried with the n-type buried semiconductor layer 16 to achieve low resistance.

[0054] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. [Explanation of symbols]

[0055] 100...Semiconductor light emitting element 10...Growth substrate 11…base layer 12...n-type nanowire layer 13…Active layer 14...p-type semiconductor layer 15,15a...metal layer 16...Buried semiconductor layer 17...Transparent electrode 18...Cathode electrode 19...Anode electrode 20...Mask 21...Opening

Claims

1. A semiconductor light emitting device comprising: a growth substrate; a mask formed on the growth substrate; and a pillar-shaped semiconductor layer grown from an opening provided in the mask, the pillar-shaped semiconductor layer has an n-type nanowire layer formed at the center thereof and an active layer formed on an outer periphery of the n-type nanowire layer; a p-type semiconductor layer is formed on the outer periphery of the active layer; a metal layer is formed on the outer periphery of the p-type semiconductor layer, A semiconductor light emitting device comprising: an n-type buried semiconductor layer formed to cover the metal layer.

2. The semiconductor light emitting device according to claim 1 , The semiconductor light-emitting element is characterized in that the metal layer is made of Al or Mg.

3. The semiconductor light emitting device according to claim 1 , the metal layer is formed in a dotted or mesh-like pattern on the surface of the p-type semiconductor layer, The semiconductor light-emitting device is characterized in that the p-type semiconductor layer and the buried semiconductor layer are at least partially in contact with each other.

4. The semiconductor light emitting device according to claim 1 , The metal layer has a thickness of 3 nm or less and transmits light from the active layer.

5. The semiconductor light emitting device according to claim 1 , The metal layer has a thickness of 10 nm or more and reflects light from the active layer.

6. 6. The semiconductor light emitting device according to claim 1, A semiconductor light-emitting device characterized in that a transparent electrode is formed on the buried semiconductor layer.

7. a masking step of forming a mask layer having an opening on a growth substrate, and a growth step of forming a pillar-shaped semiconductor layer in the opening by using selective growth; the growth step includes a nanowire growth step of forming an n-type nanowire layer, an active layer growth step of forming an active layer outside the n-type nanowire layer, a p-type layer growth step of forming a p-type semiconductor layer outside the active layer, and a metal layer formation step of forming a metal layer outside the p-type semiconductor layer, A method for manufacturing a semiconductor light emitting device, comprising the step of forming an n-type buried semiconductor layer covering the metal layer.

8. 8. The method for manufacturing a semiconductor light-emitting device according to claim 7, 2. A method for manufacturing a semiconductor light-emitting device, wherein the metal layer forming step is carried out by MOCVD in the same manufacturing equipment as the p-type layer growing step.

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