Semiconductor growth substrate, semiconductor light emitting device, and method for manufacturing semiconductor light emitting device

Abstract

To provide a semiconductor growth substrate, a semiconductor light emitting device, and a method for manufacturing semiconductor light emitting device capable of preventing exposure of an active layer in a pillar-shaped semiconductor layer and suppressing reduction in light emission efficiency.SOLUTION: A semiconductor growth substrate includes a GaN layer (11) having a c-plane as its main surface, and a mask layer (12) formed on the GaN layer (11). The mask layer (12) has a nanowire growth region (12c) formed by a two-dimensional arrangement of a plurality of first openings (12a), and an alignment growth region formed with second openings (12b) larger than the first openings (12a).SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor growth substrate, a semiconductor light-emitting device, and a method for manufacturing a semiconductor light-emitting device. [Background technology]

[0002] In recent years, rapid advances have been made in crystal growth methods for nitride-based semiconductors, leading to the practical application of high-brightness light-emitting devices using these materials. It is desirable for such semiconductor light-emitting devices using nitride semiconductors to achieve high energy conversion efficiency and high optical output in high current density regions, and to have stable light distribution characteristics for the emitted light. To address these issues, Patent Document 1 proposes a semiconductor light-emitting device in which an n-type nanowire core, an active layer, and a p-type layer are grown on a semiconductor substrate.

[0003] The semiconductor light-emitting device disclosed in Patent Document 1, in which an active layer is formed on the outer periphery of a nanowire core, has fewer crystal defects and threading dislocations than one in which the active layer is formed on the entire surface of a sapphire substrate, allowing for higher quality crystals and, because m-plane growth is possible, improved external quantum efficiency at high current densities can be achieved. Furthermore, in the semiconductor light-emitting device using the nanowire core of Patent Document 1, the active layer can be formed from high quality crystals, which is expected to enable the In composition of the active layer to be increased, thereby achieving longer wavelengths. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-040676 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in semiconductor light-emitting devices using nanowire cores, the nanowire core and active layer are grown on the entire surface of the growth substrate, so when the buried semiconductor layer is etched to form a mesa for forming an n-type electrode or for device isolation, part of the active layer may be exposed from the side of the mesa. The active layer exposed from the side of the mesa can cause problems, such as reduced light-emitting efficiency due to the generation of leakage current and non-radiative recombination via surface states.

[0006] Therefore, the present invention has been made in consideration of the above-mentioned conventional problems, and aims to provide a semiconductor growth substrate, a semiconductor light-emitting device, and a method for manufacturing a semiconductor light-emitting device that can prevent exposure of an active layer in a columnar semiconductor layer and suppress a decrease in light-emitting efficiency. [Means for solving the problem]

[0007] In order to solve the above problems, the semiconductor growth substrate of the present invention is a semiconductor growth substrate comprising a GaN layer having a c-plane as its main surface and a mask layer formed on the GaN layer, wherein the mask layer has a nanowire growth region in which a plurality of first openings are two-dimensionally arranged, and an alignment growth region in which second openings larger than the first openings are formed.

[0008] In such a semiconductor growth substrate of the present invention, a mask layer is formed in which a plurality of first openings are arranged two-dimensionally in the nanowire growth region and a second opening larger than the first opening is formed in the alignment growth region. This makes it possible to accurately align the nanowire growth region and the cathode electrode using the alignment semiconductor layer during mesa formation, preventing exposure of the active layer from the side of the mesa and suppressing a decrease in light-emitting efficiency.

[0009] In one embodiment of the present invention, the second opening has at least a portion of a side along the m-plane or the a-plane of the GaN layer.

[0010] In order to solve the above problem, the semiconductor light-emitting element of the present invention is characterized by comprising the above semiconductor growth substrate, a columnar semiconductor layer grown from the first opening, and an alignment semiconductor layer grown from the second opening.

[0011] In one aspect of the present invention, a buried semiconductor layer is formed to cover the side surfaces and top surfaces of the plurality of pillar-shaped semiconductor layers.

[0012] In one aspect of the present invention, the alignment semiconductor layer has at least a portion of a surface parallel to the m-plane or the a-plane of the GaN layer.

[0013] In one aspect of the present invention, the columnar semiconductor layer has an n-type nanowire layer formed in the center, an active layer formed on the outer periphery of the n-type nanowire layer, and a p-type semiconductor layer formed on the outer periphery of the active layer.

[0014] In order to solve the above-mentioned problems, the manufacturing method of the semiconductor light-emitting element of the present invention is characterized by comprising a mask formation step of forming a mask layer on a GaN layer having a c-plane, the mask layer having a nanowire growth region in which a plurality of first openings are two-dimensionally arranged and an alignment growth region having a second opening larger than the first openings, and a growth step of using selective growth to form a columnar semiconductor layer in the first openings and an alignment semiconductor layer in the second openings. [Effects of the Invention]

[0015] The present invention can provide a semiconductor growth substrate, a semiconductor light-emitting device, and a method for manufacturing a semiconductor light-emitting device that can prevent exposure of the active layer in the columnar semiconductor layer and suppress a decrease in light-emitting efficiency. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic diagram showing a semiconductor light emitting device 100 according to a first embodiment. [Figure 2]2A and 2B are schematic diagrams illustrating the electrode pattern and mask layer 12 of the semiconductor light-emitting element 100, where FIG. 2A shows the shapes of the anode electrode 17 and the cathode electrode 18 included in one semiconductor light-emitting element 100, and FIG. 2B shows the pattern of the mask layer 12 formed on the semiconductor growth substrate. [Figure 3] 3A and 3B are schematic diagrams showing a mask formation process, in which FIG. 3A shows a top view and FIG. 3B shows a cross-sectional view. [Figure 4] 4A and 4B are schematic diagrams showing the growth process, where FIG. 4A shows a top view and FIG. 4B shows a cross-sectional view. [Figure 5] 5A and 5B are schematic diagrams showing a first resist coating step, in which FIG. 5A is a top view and FIG. 5B is a cross-sectional view. [Figure 6] FIG. 2 is a schematic diagram showing the procedure of a first alignment step. [Figure 7] 7A and 7B are schematic diagrams showing a first resist exposure step, in which FIG. 7A shows a top view and FIG. 7B shows a cross-sectional view. [Figure 8] 8A and 8B are schematic diagrams showing a first resist removal step, in which FIG. 8A is a top view and FIG. 8B is a cross-sectional view. [Figure 9] 9A and 9B are schematic diagrams showing a third opening forming step, in which FIG. 9A is a top view and FIG. 9B is a cross-sectional view. [Figure 10] 10A and 10B are schematic diagrams showing a second resist coating step, in which FIG. 10A shows a top view and FIG. 10B shows a cross-sectional view. [Figure 11] 11A and 11B are schematic diagrams showing a second resist exposure step, in which FIG. 11A shows a top view and FIG. 11B shows a cross-sectional view. [Figure 12] 12A and 12B are schematic diagrams showing an electrode formation step, in which FIG. 12A is a top view and FIG. 12B is a cross-sectional view. [Figure 13] 13A and 13B are schematic diagrams showing a second resist removal step, in which FIG. 13A is a top view and FIG. 13B is a cross-sectional view. [Figure 14] 10A and 10B are schematic diagrams showing examples of the shapes of a second opening 12b and an alignment semiconductor layer 14 of a semiconductor light emitting device 100 according to a second embodiment.

[0017] (First embodiment) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant explanations will be omitted where appropriate. Figure 1 is a schematic diagram showing a semiconductor light emitting device 100 according to this embodiment.

[0018] As shown in Fig. 1, the semiconductor light emitting device 100 includes a growth substrate 10, a GaN layer 11, a mask layer 12, a columnar semiconductor layer 13, an alignment semiconductor layer 14, embedded semiconductor layers 15 and 16, an anode electrode 17, a cathode electrode 18, and a dummy electrode 19. Fig. 1 shows an example in which the dummy electrode 19 is provided in the semiconductor light emitting device 100, but the dummy electrode 19 may be omitted. Also, Fig. 1 shows a state in which the region in which the columnar semiconductor layer 13 is formed and the region in which the alignment semiconductor layer 14 is formed are formed simultaneously, but only the region in which the columnar semiconductor layer 13 is formed may be divided and used as a light emitting device.

[0019] The growth substrate 10 is a substantially flat plate-shaped member made of a material that allows for crystal growth of semiconductor materials, and a mask layer 12 is formed on the main surface side. The growth substrate 10 may be made of a single material, or may be a single-crystal substrate on which multiple semiconductor layers, such as a buffer layer, are grown. The growth substrate 10 may be any single-crystal substrate made of a material that allows for the growth of a semiconductor single-crystal layer via a buffer layer. When the semiconductor light-emitting device 100 is made of a nitride-based semiconductor, a c-plane sapphire substrate is preferred, but other heterogeneous substrates such as Si may also be used. Furthermore, for laser oscillation, a c-plane GaN substrate may be used, which allows for the cavity plane to be easily formed by cleavage. The buffer layer is formed between the single-crystal substrate and the GaN layer 11 to reduce lattice mismatch between them. When a c-plane sapphire substrate is used as the single-crystal substrate, GaN is preferably used as the material, but AlN, AlGaN, etc. may also be used.

[0020] The GaN layer 11 is a single-crystal semiconductor layer formed on the growth substrate 10 or a buffer layer, and functions as a base layer for growing the columnar semiconductor layer 13. An example of the GaN layer 11 is undoped GaN formed to a thickness of several micrometers. Alternatively, the GaN layer 11 may have a multi-layer structure, with the top layer serving as an n-type contact layer. The n-type contact layer is a semiconductor layer doped with n-type impurities, such as Si-doped n-type GaN. As shown in FIG. 1, a cathode electrode 18 is formed on a portion of the GaN layer 11.

[0021] The mask layer 12 is a layer made of a dielectric material formed on the surface of the GaN layer 11. The material for the mask layer 12 is selected from those that make it difficult for semiconductor crystal growth to occur, such as SiO2 or SiN. x and Al2O3 are suitable. A plurality of first openings 12a and second openings 12b, which will be described later, are formed in the mask layer 12, and a semiconductor layer can be grown on the GaN layer 11 in the first openings 12a and second openings 12b.

[0022] The pillar-shaped semiconductor layer 13 is a semiconductor layer grown from the first openings 12a in the mask layer 12, and is formed as a substantially pillar-shaped semiconductor layer standing vertically relative to the primary surface of the GaN layer 11. Although not shown, the specific configuration of the pillar-shaped semiconductor layer 13 is not limited, and examples include a conventionally known n-type nanowire layer, active layer, and p-type semiconductor layer. The pillar-shaped semiconductor layer 13 may also include a tunnel junction layer. Such a pillar-shaped semiconductor layer 13 is obtained by setting appropriate growth conditions according to the semiconductor material and performing selective growth that grows a specific crystal plane orientation. In the example shown in FIG. 1, multiple first openings 12a are formed two-dimensionally and periodically in the mask layer 12, and therefore the pillar-shaped semiconductor layer 13 is also formed two-dimensionally and periodically on the growth substrate 10. When the width and height of one pillar-shaped semiconductor layer 13 are w1 and h1, respectively, the aspect ratio h1 / w1 is 1 or greater.

[0023] The n-type nanowire layer is a columnar semiconductor layer selectively grown on the GaN layer 11 exposed through the first opening 12a of the mask layer 12. It is composed of, for example, GaN doped with n-type impurities. When GaN is used as the n-type nanowire layer, the n-type nanowire layer selectively grown on the c-plane of the GaN layer 11 has a roughly hexagonal columnar shape with six m-planes formed as facets. In Figure 1, the n-type nanowire layer appears to grow only in the region where the opening is formed. However, in reality, crystal growth proceeds on the mask layer 12 due to lateral growth, resulting in the formation of an enlarged hexagonal columnar structure around the opening. For example, if the opening is formed as a circle with a diameter of approximately 150 nm, an n-type nanowire layer can be formed as a hexagonal columnar structure with a height of approximately 1 to 2 μm, with a base that is a hexagon inscribed in a circle with a diameter of approximately 240 nm.

[0024] The active layer is a semiconductor layer grown on the outer periphery of the n-type nanowire layer, and can be, for example, a multi-quantum well active layer consisting of five periods of 5-nm-thick GaInN quantum well layers and 10-nm-thick GaN barrier layers. While a multi-quantum well active layer is used here, it can also be a single quantum well structure or a bulk active layer. Because the active layer is formed on the side and top surfaces of the n-type nanowire layer, a sufficient area for the active layer can be secured.

[0025] The p-type semiconductor layer is a semiconductor layer grown on the outer periphery of the active layer, and is made of, for example, GaN doped with p-type impurities. Because the p-type semiconductor layer is formed on the side and top surfaces of the active layer, a double heterostructure is formed by the n-type nanowire layer, the active layer, and the p-type semiconductor layer, which effectively confines carriers in the active layer and improves the probability of radiative recombination.

[0026] The tunnel junction layer is a semiconductor layer grown on the outer periphery of the p-type semiconductor layer, and has a two-layer structure in which, for example, a p+ layer doped with a high concentration of p-type impurities on the inside and an n+ layer doped with a high concentration of n-type impurities on the outside are grown in this order. The p+ layer is a semiconductor layer doped with a high concentration of p-type impurities, and for example, it has a thickness of 5 nm and an Mg concentration of 2×10 20 cm -3The n+ layer can be made of GaN with a thickness of, for example, 10 nm and a Si concentration of 2×10 20 cm -3 Since a tunnel junction is formed by the p+ layer and the n+ layer, the two layers of the p+ layer and the n+ layer constitute the tunnel junction layer in the present invention.

[0027] The alignment semiconductor layer 14 is a semiconductor layer crystal-grown from the second opening 12b formed in the mask layer 12, and has side surfaces perpendicular to the main surface of the GaN layer 11. When the width and height of the alignment semiconductor layer 14 are w2 and h2, respectively, the aspect ratio h2 / w2 is less than 1. The height h2 of the alignment semiconductor layer 14 is smaller than the height h1 of the columnar semiconductor layer 13. The width w2 of the alignment semiconductor layer 14 is not limited and may be larger or smaller than the width w1 of the nanowire growth region 12c. To prevent the buried semiconductor layers 15 and 16 from contacting or integrating with each other due to lateral growth, the first opening 12a and the second opening 12b are preferably spaced apart by at least 10 μm.

[0028] As will be described later, the alignment semiconductor layer 14 is formed simultaneously and in the same process as the pillar-shaped semiconductor layer 13, and therefore may have a stacked structure similar to that of the pillar-shaped semiconductor layer 13. However, since the active layer, p-type semiconductor layer, tunnel junction layer, and other layers included in the pillar-shaped semiconductor layer 13 are thinner than the n-type nanowire layer, and the surface area of ​​the alignment semiconductor layer 14 is significantly larger than that of the n-type nanowire layer, the alignment semiconductor layer 14 may be made of the same material as the n-type nanowire layer.

[0029] The buried semiconductor layers 15 and 16 are semiconductor layers formed to cover the top and side surfaces of the columnar semiconductor layer 13 and the alignment semiconductor layer 14, respectively, and to cover all the way down to the mask layer 12. An anode electrode 17 and a dummy electrode 19 are formed on the top surfaces of the buried semiconductor layers 15 and 16, respectively. While the buried semiconductor layers 15 and 16 are shown as single layers here, they may be composed of multiple semiconductor layers with different materials, compositions, and impurity concentrations. The buried semiconductor layer 16 is selectively grown from the second opening 12b, and thus undergoes crystal growth in a shape corresponding to the outer shape of the second opening 12b. Furthermore, if the second opening 12b includes an edge parallel to the m-plane or a-plane of the GaN layer 11, an m-plane or a-plane facet is formed in the buried semiconductor layer 16 at the edge parallel to the m-plane or a-plane.

[0030] As will be described later, the buried semiconductor layers 15 and 16 are formed simultaneously in the same process, and therefore may be made of the same material, impurity concentration, stacked structure, etc. When the outermost periphery of the pillar-shaped semiconductor layer 13 is a p-type semiconductor layer, it is preferable to use a p-type semiconductor for the buried semiconductor layer 15. When the outermost periphery of the pillar-shaped semiconductor layer 13 is a tunnel junction layer, it is preferable to use an n-type semiconductor for the buried semiconductor layer 15.

[0031] The anode electrode 17 is an electrode formed on a part of the buried semiconductor layer 15, and is composed of a laminated structure of a pad electrode and a metal material that is in ohmic contact with the outermost surface of the buried semiconductor layer 15. When light is extracted from the buried semiconductor layer 15 side, a transparent electrode that transmits light is preferably used as the anode electrode 17, and for example, ITO (Indium Tin Oxide) can be used. When light is extracted from the growth substrate 10 side, a reflective electrode that reflects light is preferably used as the anode electrode 17, and for example, Al, Ag, etc. can be used.

[0032] The cathode electrode 18 is an electrode formed in an exposed region of the GaN layer 11, and is composed of a laminated structure of a pad electrode and a metal material that makes ohmic contact with the outermost surface of the GaN layer 11. The dummy electrode 19 is an electrode formed on a portion of the buried semiconductor layer 16, and is composed of a laminated structure of a pad electrode and a metal material that makes ohmic contact with the outermost surface of the buried semiconductor layer 16. The cathode electrode 18 and the dummy electrode 19 may be formed simultaneously in the same process as the anode electrode 17, as described below, and may be made of the same material as the anode electrode 17. Furthermore, a known structure, such as covering the surface of the semiconductor light emitting element 100 with a protective film, may be applied as needed.

[0033] 1, when a voltage is applied between the anode electrode 17 and the cathode electrode 18, a current flows from the buried semiconductor layer 15 to the columnar semiconductor layer 13 and the GaN layer 11 in this order, and light is generated by radiative recombination in the active layer included in the columnar semiconductor layer 13. The light emitted from the active layer is extracted to the outside of the semiconductor light emitting device 100.

[0034] Furthermore, because the side surfaces of the n-type nanowire layer are m-planes formed by selective growth, the active layer and p-type semiconductor layer formed around the periphery are also in contact with each other at the m-plane. The m-plane is a nonpolar plane and does not generate polarization, so the light emission efficiency of the active layer is high. Moreover, because all of the side surfaces of the hexagonal prism are m-planes, the light emission efficiency of the semiconductor light-emitting device 100 can be improved. Furthermore, because the film thickness of the active layer can be increased, the volume of the active layer can be increased by approximately 3 to 10 times compared to conventional semiconductor light-emitting devices, reducing the injected carrier density and significantly reducing efficiency droop.

[0035] 2A and 2B are schematic diagrams illustrating the electrode pattern and mask layer 12 of a semiconductor light-emitting device 100. FIG. 2A shows the shapes of the anode electrode 17 and cathode electrode 18 included in one semiconductor light-emitting device 100, and FIG. 2B shows the pattern of the mask layer 12 formed on a semiconductor growth substrate. FIG. 2B shows an enlarged view of a portion of the growth substrate 10. A plurality of first openings 12a and second openings 12b are formed in the mask layer 12. The plurality of first openings 12a are densely arranged two-dimensionally in a predetermined region surrounded by a dashed line, constituting a nanowire growth region 12c.

[0036] The anode electrode 17 shown in FIG. 2(a) is formed on the entire or almost entire top surface of the buried semiconductor layer 15 shown in FIG. 1, and is formed within the nanowire growth region 12c. The cathode electrode 18 is formed in a region where the buried semiconductor layer 15 has been removed to expose the GaN layer 11, and is formed in a region where the nanowire growth region 12c has been cut out. Here, the anode electrode 17 and the nanowire growth region 12c have a quadrilateral shape with one corner cut out, but the planar shape is not limited. Furthermore, when the anode electrode 17 is formed only on a portion of the buried semiconductor layer 15, the anode electrode 17 and the nanowire growth region 12c do not need to have similar shapes.

[0037] 2(b), only one region indicated by a dashed line representing nanowire growth region 12c is shown, but all regions in which multiple first openings 12a are formed are nanowire growth regions 12c, and multiple nanowire growth regions 12c are formed in a two-dimensional array on growth substrate 10. Nanowire growth region 12c corresponds to a mesa shape used when isolating semiconductor light emitting element 100, and substantially coincides with the side surface of buried semiconductor layer 15.

[0038] Second opening 12b is formed with an area approximately equal to that of one nanowire growth region 12c and has substantially the same shape as the periphery of alignment semiconductor layer 14. Therefore, the region where second opening 12b is formed corresponds to the alignment growth region in the present invention. Second opening 12b also has a side along the m-plane or a-plane of GaN layer 11 in at least a part of its outer shape. More specifically, the left-right direction in FIG. 2(b) is the direction that includes the m-plane or a-plane of GaN layer 11, and the sides extending in the left-right direction are oriented along the m-plane or a-plane, respectively.

[0039] 2(b) shows an example in which second opening 12b has a quadrilateral shape with four corners cut out at right angles, but the specific shape is not limited as long as the relative position and shape with respect to nanowire growth region 12c can be specified in order to specify the position and orientation of nanowire growth region 12c. Also, while FIG. 2(b) shows an example in which only one second opening 12b is formed in mask layer 12, if multiple nanowire growth regions 12c are formed, multiple second openings 12b may be formed at regular intervals one-dimensionally or two-dimensionally.

[0040] Next, a method for manufacturing the semiconductor light-emitting device 100 of this embodiment will be described with reference to Figures 3 to 13. Figures 3(a) to 13(a) show only one pair of regions for forming the nanowire growth region 12c and the alignment semiconductor layer 14, but multiple nanowire growth regions 12c and alignment semiconductor layers 14 are formed within the surface of the growth substrate 10. Figures 3(b) to 13(b) also show schematic cross sections taken along the line A-A' shown in the plan views.

[0041] 3A and 3B are schematic diagrams showing the mask formation process, where Fig. 3A is a top view and Fig. 3B is a cross-sectional view. First, a GaN layer 11 is formed on a growth substrate 10, a mask layer 12 is formed on the GaN layer 11, and a plurality of first openings 12a and second openings 12b are formed in the mask layer 12.

[0042] As an example, a buffer layer and GaN layer 11 are grown on a growth substrate 10 made of a sapphire single crystal using metal organic chemical vapor deposition (MOCVD). The buffer layer is grown under conditions such as a growth temperature of 1100°C, a V / III ratio of 1000, hydrogen as a carrier gas, and a pressure of 10 hPa, using TMA (TriMethyl Aluminum), TMG (TriMethyl Gallium), and ammonia as source gases. The GaN layer 11 is grown under conditions such as a growth temperature of 1050°C, a V / III ratio of 1000, hydrogen as a carrier gas, and a pressure of 500 hPa.

[0043] Mask layer 12 is formed, for example, by depositing mask layer 12 made of SiO2 to a thickness of about 30 nm by sputtering on GaN layer 11. First opening 12a and second opening 12b are formed, for example, by using a fine pattern formation method such as nanoimprinting lithography to form first opening 12a with a diameter of about 150 nm and large-area second opening 12b in mask layer 12.

[0044] 4A and 4B are schematic diagrams showing the growth process, with FIG. 4A showing a top view and FIG. 4B showing a cross-sectional view. In the growth process, a pillar-shaped semiconductor layer 13 and an alignment semiconductor layer 14 are selectively grown in the first opening 12a and the second opening 12b, respectively. In addition, buried semiconductor layers 15 and 16 are grown so as to cover the side and top surfaces of the pillar-shaped semiconductor layer 13 and the alignment semiconductor layer 14.

[0045] More specifically, an n-type nanowire layer made of GaN is grown by selective growth using the MOCVD method on the GaN layer 11 exposed from the first opening 12a, and an alignment semiconductor layer 14 made of GaN is simultaneously selectively grown on the GaN layer 11 exposed from the second opening 12b. In addition, an active layer and a p-type semiconductor layer are grown on the side and top surfaces of the n-type nanowire layer. If a tunnel junction layer is included in the columnar semiconductor layer 13, the tunnel junction layer is grown on the periphery of the p-type semiconductor layer.

[0046] Growth conditions for the n-type nanowire layer and alignment semiconductor layer 14 include, for example, TMG and ammonia as source gases, a growth temperature of 1050°C, a V / III ratio of 10, hydrogen as carrier gas, and a pressure of 100 hPa. The active layer may be a multi-quantum well active layer consisting of five periods of 5 nm-thick GaInN quantum well layers and 10 nm-thick GaN barrier layers. Growth conditions for the active layer include, for example, a growth temperature of 800°C, a V / III ratio of 3000, nitrogen as carrier gas, and a pressure of 1000 hPa, using TMG, TMI (TriMethylIndium), and ammonia as source gases.

[0047] The growth conditions for the p-type semiconductor layer include, for example, a growth temperature of 950° C., a V / III ratio of 1000, a pressure of 300 hPa using hydrogen as a carrier gas, and the use of TMG, Cp2Mg (bisCycropentadienylMagnesium), and ammonia as source gases.

[0048] The pillar-shaped semiconductor layer 13 and the alignment semiconductor layer 14 are grown simultaneously under the same conditions in the same MOCVD apparatus, but because the areas of the first opening 12a and the second opening 12b are different, more raw material that was not used for crystal growth in the surrounding mask layer 12 is supplied to the smaller-diameter first opening 12a, and the amount of raw material supplied per unit area is greater than that of the second opening 12b. As a result, the height h1 of the pillar-shaped semiconductor layer 13 is greater than the height h2 of the alignment semiconductor layer 14.

[0049] The buried semiconductor layer 15 must be grown on the mask layer 12 between the pillar-shaped semiconductor layers 13. During growth of the buried semiconductor layer 15, voids may form beneath the pillar-shaped semiconductor layer 13. Therefore, the buried semiconductor layers 15 and 16 are preferably grown using TMG, silane, and ammonia as source gases at a low temperature and a low V / III ratio, which promotes lateral m-plane growth in the initial stage. Examples of low temperatures and low V / III ratios include a temperature of 800°C or lower, a V / III ratio of 100 or less, and a pressure of 200 hPa using hydrogen as a carrier gas. After the lateral growth of the buried semiconductor layers 15 and 16 completely fills the mask layer 12 beneath the pillar-shaped semiconductor layers 13, the buried semiconductor layers 15 and 16 are preferably grown at a high temperature and a high V / III ratio, which promotes vertical c-plane growth. Examples of high temperatures and high V / III ratios include a temperature of 1000°C or higher, a V / III ratio of 2000 or more, and a pressure of 500 hPa using hydrogen as a carrier gas.

[0050] 5A and 5B are schematic diagrams showing the first resist coating step, with FIG. 5A showing a top view and FIG. 5B showing a cross-sectional view. In the first resist coating step, a first resist layer 20 is coated on the entire surface of the growth substrate 10 so as to cover the mask layer 12 and the buried semiconductor layers 15 and 16. The method for coating the first resist layer 20 is not limited, and a known spin coating method or the like can be used.

[0051] FIG. 6 is a schematic diagram showing the procedure of the first alignment step. In the first alignment step, as shown in FIG. 6(a), a cathode mask 21a corresponding to the shape of the cathode electrode 18 and an alignment mask 21b corresponding to the shape of the buried semiconductor layer 16 are first prepared. At this stage, the positions and orientations of the cathode mask 21a and the alignment mask 21b do not properly correspond to the buried semiconductor layers 15 and 16. Next, while comparing the shape of the alignment mask 21b with the shape of the buried semiconductor layer 16, as shown in FIG. 6(b), the growth substrate 10 is rotated in the in-plane direction so that the orientations of the alignment mask 21b and the buried semiconductor layer 16 are aligned. Next, as shown in FIG. 6(c), the growth substrate 10 is translated in the in-plane direction so that the positions of the alignment mask 21b and the buried semiconductor layer 16 along the X axis (the left-right direction in the figure) are aligned. Next, as shown in FIG. 6(d), the growth substrate 10 is translated in the in-plane direction so that the alignment mask 21b and the buried semiconductor layer 16 are aligned in the Y-axis (vertical direction in the figure).

[0052] As shown in Figures 6(a) to 6(d), the cathode mask 21a and the alignment mask 21b can be positioned at predetermined positions on the growth substrate 10 by rotating and translating the growth substrate 10 while comparing the shape of the alignment mask 21b with the shape of the buried semiconductor layer 16. The order of the translation in the X-axis direction in Figure 6(c) and the translation in the Y-axis direction in Figure 6(d) may be reversed, or may be repeated to improve alignment accuracy. Both the cathode mask 21a and the alignment mask 21b are made of a light-blocking material.

[0053] In this embodiment, alignment mask 21b used in the first alignment step has straight sides corresponding to second openings 12b, which improves the accuracy of identifying the position and orientation of alignment mask 21b by image recognition. Furthermore, when second openings 12b include straight lines parallel to the m-plane or a-plane of GaN layer 11, buried semiconductor layer 16 also has an m-plane or a-plane facet formed therein, which improves the accuracy of identifying the position and orientation of buried semiconductor layer 16 by image recognition.

[0054] 7A and 7B are schematic diagrams showing the first resist exposure step, in which Fig. 7A shows a top view and Fig. 7B shows a cross-sectional view. In the first resist exposure step, UV (Ultra Violet) light is irradiated from an exposure device 22 using a cathode mask 21a and an alignment mask 21b that have been aligned to a predetermined position and orientation on the growth substrate 10 in the alignment step, exposing the first resist layer 20 in areas where the cathode mask 21a and the alignment mask 21b are not present.

[0055] 8A and 8B are schematic diagrams showing the first resist removal step, where Fig. 8A shows a top view and Fig. 8B shows a cross-sectional view. In the first resist removal step, the first resist layer 20 is left in the areas exposed in the first resist exposure step, and the first resist layer 20 is removed in the areas not exposed to light, thereby forming an anode pattern portion 23a and an alignment pattern portion 23b at positions corresponding to the cathode mask 21a and the alignment mask 21b.

[0056] 9A and 9B are schematic diagrams showing the third opening formation step, with FIG. 9A showing a top view and FIG. 9B showing a cross-sectional view. In the third opening formation step, the mask layer 12 exposed from the anode pattern portion 23a formed in the first resist layer 20 in the first resist removal step is etched to form a third opening 24 in the mask layer 12. The GaN layer 11 is exposed from the third opening 24. After the third opening 24 is formed, the exposed first resist layer 20 is removed. The method for forming the third opening 24 is not limited, but if SiO2 is used as the mask layer 12, dry etching using CF4 gas can be used.

[0057] 10A and 10B are schematic diagrams showing the second resist coating step, with FIG. 10A showing a top view and FIG. 10B showing a cross-sectional view. In the second resist coating step, a second resist layer 25 is coated on the entire surface of the growth substrate 10 so as to cover the mask layer 12, the buried semiconductor layers 15 and 16, and the third opening 24. The method for coating the second resist layer 25 is not limited, and a known spin coating method or the like can be used.

[0058] Although not shown, after the second resist application step, a second alignment step is performed using the anode mask 26a, the cathode mask 26b, and the alignment mask 26c, similar to the first alignment step described with reference to Fig. 6. In the second alignment step, the growth substrate 10 is rotated and translated while comparing the shape of the alignment mask 26c with the shape of the embedded semiconductor layer 16, thereby positioning the anode mask 26a, the cathode mask 26b, and the alignment mask 26c at predetermined positions on the growth substrate 10.

[0059] 11A and 11B are schematic diagrams showing the second resist exposure step, in which FIG. 11A shows a top view and FIG. 11B shows a cross-sectional view. In the first resist exposure step, UV light is irradiated from an exposure device 27 using an anode mask 26a, a cathode mask 26b, and an alignment mask 26c that have been aligned to predetermined positions and orientations on the growth substrate 10 in the second alignment step, to expose the second resist layer 25 in areas where the anode mask 26a, the cathode mask 26b, and the alignment mask 26c are not present.

[0060] Although not shown, after the second resist exposure step, a second resist removal step is performed in which the second resist layer 25 is left in the area exposed in the second resist exposure step and the second resist layer 25 is removed in the unexposed area, similar to the first resist removal step described with reference to Fig. 8. In the second resist removal step, a cathode pattern portion 28a, an anode pattern portion 28b, and an alignment pattern portion 28c are formed at positions corresponding to the anode mask 26a, the cathode mask 26b, and the alignment mask 26c. The buried semiconductor layer 15, the GaN layer 11, and the buried semiconductor layer 16 are exposed from the cathode pattern portion 28a, the anode pattern portion 28b, and the alignment pattern portion 28c, respectively.

[0061] 12A and 12B are schematic diagrams showing the electrode formation step, with Fig. 12A showing a top view and Fig. 12B showing a cross-sectional view. In the electrode formation step, an anode electrode 17, a cathode electrode 18, and a dummy electrode 19 are formed on the buried semiconductor layer 15, the GaN layer 11, and the buried semiconductor layer 16. A known sputtering method or the like can be used to form each electrode.

[0062] 13A and 13B are schematic diagrams showing the second resist removal step, with FIG. 13A showing a top view and FIG. 13B showing a cross-sectional view. In the second resist removal step, the second resist layer 25 is removed, leaving behind the anode electrode 17, the cathode electrode 18, and the dummy electrode 19 formed in the electrode formation step, thereby obtaining the semiconductor light emitting device 100. After the second resist layer 25 is removed, an annealing step, formation of a protective film, etc. may be performed.

[0063] As described above, in the semiconductor growth substrate and semiconductor light-emitting element 100 of this embodiment, a plurality of first openings 12a are formed in a two-dimensional arrangement in the nanowire growth region 12c, and the mask layer 12 has second openings 12b larger than the first openings 12a formed in the alignment growth region. This makes it possible to accurately align the nanowire growth region 12c and the cathode electrode 18 using the alignment semiconductor layer 14, prevent exposure of the active layer from the mesa side, and suppress a decrease in light-emitting efficiency.

[0064] Furthermore, in the method for manufacturing a semiconductor light-emitting device of this embodiment, in the first alignment step and the second alignment step, alignment masks 21b, 26c and alignment semiconductor layer 14 are used to align third opening 24 for forming cathode electrode 18 with nanowire growth region 12c. This eliminates the need for etching nanowire growth region 12c, prevents columnar semiconductor layer 13 and active layer from being exposed from the mesa side surface, and makes it possible to suppress a decrease in light-emitting efficiency.

[0065] (Second embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. 14. Description of content overlapping with the first embodiment will be omitted. FIG. 14 is a schematic diagram showing examples of the shape of the second opening 12b and alignment semiconductor layer 14 of the semiconductor light emitting device 100 according to this embodiment. Each of the example shapes includes multiple straight sides so that the position and orientation can be specified, and the shape is asymmetric with respect to rotational movement. Furthermore, in each example shape, it is preferable that at least one of the straight sides is a side along the m-plane or a-plane of the GaN layer.

[0066] The example shown in Figure 14(a) is a rectangular shape with one corner cut out. The example shown in Figure 14(b) is a rectangular shape with both sides of one side cut out. The example shown in Figure 14(c) is a shape obtained by translating a regular hexagon twice along two sides. The example shown in Figure 14(d) is a shape in which multiple rectangles are arranged in the shape of the letter H.

[0067] In the example shown in Figure 14(e), one corner of a rectangle is cut out in a rectangular shape to form an L-shape, and a similar small L-shape is provided separately at the corner of the cutout. In the example shown in Figure 14(f), one corner of a rectangle is cut out in a rectangular shape to form an L-shape, and a small rectangle is provided separately at the corner of the cutout. In the example shown in Figure 14(g), four corners of a rectangle are cut out in a rectangular shape to form a cross shape, and a small L-shape is provided separately at one corner of the cutout.

[0068] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. [Explanation of symbols]

[0069] 100...Semiconductor light emitting element 10...Growth substrate 11...GaN layer 12...Mask layer 12a...first opening 12b…Second opening 12c…Nanowire growth region 13...Columnar semiconductor layer 14...Alignment semiconductor layer 15, 16...Buried semiconductor layer 17...Anode electrode 18...Cathode electrode 19...Dummy electrode 20...First resist layer 26a...Anode mask 21a, 26b...Cathode mask 21b, 26c...Alignment mask 22, 27...Exposure equipment 28a...Cathode pattern section 23a, 28b...Anode pattern section 23b, 28c...Alignment pattern section 24...Third opening 25...Second resist layer

Claims

1. a GaN layer having a c-plane as its principal surface; a mask layer formed on the GaN layer, The mask layer has a nanowire growth region in which a plurality of first openings are arranged two-dimensionally, and an alignment growth region in which second openings larger than the first openings are formed.

2. The semiconductor growth substrate according to claim 1, The semiconductor growth substrate, wherein the second opening has at least a portion of a side aligned with the m-plane or the a-plane of the GaN layer.

3. A semiconductor growth substrate according to claim 1, a pillar-shaped semiconductor layer grown from the first opening; and an alignment semiconductor layer grown from the second opening.

4. The semiconductor light emitting device according to claim 3, The semiconductor light-emitting element is characterized in that the alignment semiconductor layer is lower in height than the pillar-shaped semiconductor layer.

5. The semiconductor light emitting device according to claim 3, A semiconductor light emitting device comprising: a buried semiconductor layer formed to cover the side surfaces and top surfaces of the plurality of pillar-shaped semiconductor layers.

6. The semiconductor light emitting device according to claim 3, The semiconductor light-emitting device is characterized in that the alignment semiconductor layer has at least a portion of a surface parallel to the m-plane or a-plane of the GaN layer.

7. 7. The semiconductor light emitting device according to claim 3, The columnar semiconductor layer has an n-type nanowire layer formed in the center, an active layer formed on the outer periphery of the n-type nanowire layer, and a p-type semiconductor layer formed on the outer periphery of the active layer.

8. a mask forming step of forming a mask layer on a GaN layer having a c-plane, the mask layer having a nanowire growth region in which a plurality of first openings are two-dimensionally arranged and an alignment growth region having second openings larger than the first openings; and growing a semiconductor light-emitting element by selective growth to form a pillar-shaped semiconductor layer in the first opening and an alignment semiconductor layer in the second opening.

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