Image sensor

Abstract

To provide a hybrid image sensor having a heterogeneous pixel such as a CIS pixel and a DVS pixel.SOLUTION: An image sensor includes: a first region parallel to an upper surface of a substrate and disposed along a first direction and a second direction intersecting each other; a second region disposed along the first direction and the second direction; a first photodiode in the first region; a second photodiode in the second region; an image sensing pixel circuit generating a first electrical signal based on charges generated by the first photodiode; an event sensing pixel circuit that generates a second electrical signal based on a change in amount of charge generated by the second photodiode; and a logic circuit electrically coupled to the image sensing pixel. The first region is disposed in a third direction with respect to the second region, and the third direction is parallel to a top surface of the substrate and is different from the first and second directions.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present invention relates to an image sensor. [Background technology]

[0002] An image sensor is a semiconductor-based sensor that receives light and generates an electrical signal, and may include a pixel array having a plurality of pixels, a circuit for driving the pixel array to generate an image, etc. The plurality of pixels may include a photodiode that generates an electric charge in response to external light, and a pixel circuit that converts the electric charge generated by the photodiode into an electric signal.

[0003] There are various types of image sensors depending on the signal they output, such as CIS (CMOS Image Sensor) which outputs a grayscale image signal, and DVS (Dynamic Vision Sensor) which detects changes in light brightness and outputs an event signal.

[0004] Conventional methods of mixing CIS and DVS pixels can introduce noise due to various parasitic capacitances, which can require color reconstruction. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 11,848,338 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention aims to provide a hybrid image sensor having heterogeneous pixels such as CIS pixels and DVS pixels.

[0007] The present invention aims to provide an image sensor that can prevent fixed pattern noise from occurring in image data, effectively perform motion deblur of the image data, and minimize the amount of calculation required for color reconstruction. [Means for solving the problem]

[0008] An image sensor according to an embodiment of the present invention includes a first region arranged along a first direction and a second direction that are parallel to a top surface of a substrate and intersect with each other; a second region arranged along the first direction and the second direction; a first photodiode in the first region; a second photodiode in the second region; an image sensing pixel circuit that generates a first electrical signal based on charges generated by the first photodiode; an event sensing pixel circuit that generates a second electrical signal based on changes in the amount of charges generated by the second photodiode; and a logic circuit electrically connected to the image sensing pixel, wherein the first region is arranged in a third direction with the second region, and the third direction is parallel to the top surface of the substrate and different from the first and second directions.

[0009] An image sensor according to an embodiment of the present invention includes a substrate, a first photodiode in a first region of the substrate, a second photodiode in a second region of the substrate, a third photodiode in a third region of the substrate, a fourth photodiode in a fourth region of the substrate, a transfer transistor, a reset transistor, and an event sensing pixel circuit that generates an electrical signal based on a change in an amount of charge generated by the second photodiode, wherein the third region is disposed adjacent to the first region in the first direction of a plane, the fourth region is disposed adjacent to the first region in a second direction of the plane perpendicular to the first direction, and the second region is disposed relative to the first region in the third direction different from the first and second directions of the plane, a light receiving area of ​​each of the first, third, and fourth photodiodes is larger than a light receiving area of ​​the second photodiode, and the transfer transistor and the reset transistor are shared by the first, third, and fourth photodiodes.

[0010] An image sensor according to an embodiment of the present invention includes a substrate having a first surface and a second surface opposite to the first surface, a first photodiode in a first region of the substrate, a second photodiode in a second region of the substrate, a first microlens on the first photodiode, a second microlens on the second photodiode, an image sensing pixel circuit that generates a first electrical signal based on charges generated in the first photodiode, an event sensing pixel circuit that generates a second electrical signal based on changes in the amount of charges generated in the second photodiode, a deep trench isolation (DTI) between the first region and the second region, and a circuit electrically connected to the image sensing pixel circuit, wherein the first region is adjacent to the second region and the DTI is in contact with the first surface and the second surface, and a width of the first microlens in a first direction in a plane is greater than a width of the second microlens in the first direction. [Effects of the Invention]

[0011] An image sensor according to an embodiment of the present invention may include a first pixel and a second pixel that are heterogeneous pixels, and may effectively perform motion deblurring of image data acquired from the first pixel using a signal acquired from the second pixel.

[0012] Although the image sensor according to the embodiment of the present invention includes first and second pixels that are heterogeneous, the first pixels can be uniformly distributed, thereby minimizing color loss in image data acquired from the first pixels and minimizing the amount of calculation required for color reconstruction.

[0013] In an image sensor according to an embodiment of the present invention, the first pixel and the second pixel, which are different types of pixels, can be electrically isolated, so that the parasitic capacitance of the column line and the row line can be made uniform, and fixed pattern noise in the image acquired from the first pixel can be reduced.

[0014] The problems to be solved by the present invention are not limited to those described above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a simplified block diagram of an image sensor according to an embodiment of the present invention; [Figure 2] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 3A] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 3B] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 3C] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 4] 1 is a plan view showing a simplified pixel array included in an image sensor according to an embodiment of the present invention; [Figure 5] 1 is a plan view showing a simplified pixel array included in an image sensor according to an embodiment of the present invention; [Figure 6] 1 is a plan view showing a simplified pixel array included in an image sensor according to an embodiment of the present invention; [Figure 7] 1 is a plan view showing a simplified pixel array included in an image sensor according to an embodiment of the present invention; [Figure 8A] FIG. 2 is a circuit diagram illustrating a pixel circuit of the image sensor according to the embodiment of the present invention. [Figure 8B] FIG. 2 is a circuit diagram illustrating a pixel circuit of the image sensor according to the embodiment of the present invention. [Figure 9] FIG. 1 is a diagram illustrating a simplified layout of an image sensor according to an embodiment of the present invention. [Figure 10] FIG. 2 is a simplified diagram illustrating a pixel included in an image sensor according to an embodiment of the present invention. [Figure 11] FIG. 2 is a simplified diagram illustrating a pixel included in an image sensor according to an embodiment of the present invention. [Figure 12] FIG. 2 is a simplified diagram illustrating a pixel included in an image sensor according to an embodiment of the present invention. [Figure 13] FIG. 2 is a simplified diagram illustrating a pixel included in an image sensor according to an embodiment of the present invention. [Figure 14] FIG. 2 is a simplified diagram illustrating a pixel included in an image sensor according to an embodiment of the present invention. [Figure 15] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 16] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 17] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 18A]FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 18B] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 19] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 20] FIG. 2 is a circuit diagram illustrating a pixel circuit of the image sensor according to the embodiment of the present invention. [Figure 21] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 22A] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 22B] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 23] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 24] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 25A] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 25B] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 26] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 27] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 28A] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 28B] FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 29]FIG. 1 is a plan view showing a simplified configuration of a pixel included in an image sensor according to an embodiment of the present invention. [Figure 30] FIG. 2 is a diagram illustrating an example layout of an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

[0017] This description explains the principles of the present disclosure. A person of ordinary skill in the art can devise one or more arrangements incorporating the principles of the present disclosure, even if not explicitly disclosed. Furthermore, all examples cited in this specification are provided solely for the purpose of illustration, primarily to aid the reader in understanding the principles of the disclosure and the concepts that the inventors have contributed to the development of the technology, and should be construed as having no limitations on such specifically cited examples and conditions. Furthermore, all statements in this specification that refer to the principles, aspects, embodiments, and embodiments of the disclosure are intended to encompass equivalents of the embodiments.

[0018] The terms used in this disclosure may be used only to describe certain embodiments and may not be intended to limit the scope of other embodiments. A single expression may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by a person with ordinary knowledge in the technical field described in this disclosure. Among the terms used in this disclosure, terms defined in common dictionaries may be interpreted to have the same or similar meaning as the contextual meaning in the related art, and unless clearly defined in this disclosure, they should not be interpreted in an ideal or overly formal sense. In some cases, even terms defined in this disclosure cannot be interpreted to exclude embodiments of the present disclosure.

[0019] In one or more embodiments of the present disclosure described below, a hardware approach is described as an example, however, various embodiments of the present disclosure do not exclude a software-based approach, as one or more embodiments of the present disclosure include techniques that use both hardware and software.

[0020] Furthermore, in this disclosure, expressions such as "more than" or "less than" may be used to determine whether a particular condition is satisfied or not, but this is merely an explanation for expressing an example and does not exclude an explanation such as "more than" or "less than." A condition described as "more than or equal to" may be replaced with "more than," and a condition described as "less than or equal to" may be replaced with "less than."

[0021] The phrase "at least one" used in conjunction with a list of items means that different combinations of one or more of the listed items can be used, and that only one item in the list may be required. For example, "one or more of A, B, and C" includes A, B, and C, A and C, B and C, and all variations of A, B, and C. As a further example, the phrase "one or more of A, B, and C" can refer to a, b, and c only, both a and c, a and c only, both a and c, a, b, and c only, all of a, b, and c, or c only. Similarly, the term "set" means one or more. Thus, a set of items can be a single item or a collection of two or more items.

[0022] FIG. 1 is a block diagram showing a simplified configuration of an image sensor according to an embodiment of the present invention.

[0023] Referring to FIG. 1, an image sensor 1 according to an embodiment of the present invention may include a pixel array 10, a first logic circuit 20, and a second logic circuit 30.

[0024] The pixel array 10 may include a unit pixel array UPA arranged in an array along a plurality of rows and a plurality of columns. The unit pixel array UPA may include a plurality of image sensing pixels PX1 and one or more event sensing pixels PX2. For example, the unit pixel array UPA in FIG. 1 includes four image sensing pixels (black dots) and one event sensing pixel (white dot).

[0025] The image sensing pixel PX1 includes at least one photoelectric conversion element and may include a first pixel circuit including a transfer transistor, a drive transistor, a selection transistor, and a reset transistor. In an exemplary embodiment, multiple image sensing pixels included in each unit pixel array UPA may share a portion of the first pixel circuit. The event sensing pixel PX2 includes at least one photoelectric conversion element and may include a second circuit including a conversion circuit CKT1, an amplification circuit CKT2, and a comparison circuit CKT3 as shown in FIG. 8B.

[0026] According to an embodiment of the present invention, the image sensing pixel PX1 and the event sensing pixel PX2 may be heterogeneous pixels that output different types of electrical signals. For example, the image sensing pixel PX1 may be a CIS (CMOS Image Sensor) pixel that outputs an image signal having a gradation that indicates the degree of brightness of light in a predetermined wavelength range. The event sensing pixel PX2 may be a DVS (Dynamic Vision Sensor) that detects changes in the brightness of light and outputs an event signal that indicates whether the light has become brighter or darker.

[0027] The CIS pixel can output an image signal containing grayscale information corresponding to multiple bits of data. Since each CIS pixel included in the pixel array 10 can generate and output an image signal in one frame period, the frame period of the CIS pixel can be relatively long.

[0028] In contrast, the event signal output by the DVS pixel may include information on whether or not there is a change in the brightness of light and the direction of the change in the brightness of light, and may include a relatively small number of bits of data, such as 1 or 2. Furthermore, since only those DVS pixels in the pixel array 10 that detect a change in the brightness of light can generate and output an event signal, the frame period of the DVS pixel may be relatively short.

[0029] If an object moves during a frame period of a CIS pixel, an afterimage called motion blur may occur in the image generated from the image signal acquired from the CIS pixel. Because DVS pixels have a shorter frame period than CIS pixels, they can output an event signal corresponding to the position where a change in light brightness occurs during the frame period of the CIS pixel. If CIS pixels and DVS pixels are mixed in the pixel array 10 and the image signal acquired from the CIS pixel can be corrected using the event signal acquired from the DVS pixel, motion deblur, a calculation to remove motion blur, can be easily performed.

[0030] If a pixel array is constructed by replacing some of the CIS pixels connected to row and column lines with DVS pixels, the quality of the image signal obtained from the pixel array may be degraded.

[0031] For example, the parasitic capacitance between row lines and column lines may differ depending on whether DVS pixels are connected to the row lines and column lines. The difference in parasitic capacitance between row lines and column lines may cause differences in the settling time of CIS pixels. Image signals generated by pixels with different settling times may induce noise at fixed positions in the image. This noise may be called fixed pattern noise.

[0032] In addition, the locations replaced by DVS pixels may not generate gradation information corresponding to the wavelength band, i.e., color information. Therefore, color reconstruction operations may be required to estimate the color of the locations where color information is missing in order to generate an image.

[0033] According to an embodiment of the present invention, the pixel array 10 may include a plurality of image sensing pixels PX1 connected to a first row line R1 and a first column line C1, and a plurality of event sensing pixels PX2 connected to a second row line R1 and a second column line C2.

[0034] The plurality of image sensing pixels PX1 may be arranged at uniform intervals (or substantially uniform intervals) based on the first row line R1 and the first column line C1. The plurality of event sensing pixels PX2 may be arranged between the plurality of image sensing pixels PX1 at uniform intervals (or substantially uniform intervals) based on the second row line R2 and the second column line C2. For example, each of the plurality of event sensing pixels PX2 may be arranged adjacent to at least one image sensing pixel PX1.

[0035] According to an embodiment of the present invention, an event sensing pixel PX2 can be arranged between image sensing pixels PX1, so that an event signal obtained from the event sensing pixel PX2 can be used to effectively perform motion deblurring of an image obtained from the image sensing pixel PX1.

[0036] Furthermore, although the pixel array 10 includes the image sensing pixel PX1 and the event sensing pixel PX2, the image sensing pixel PX1 can be uniformly distributed in the pixel array 10. Therefore, color loss in the image data acquired from the image sensing pixel PX1 can be minimized, and the amount of calculation required for color reconstruction can be minimized.

[0037] Furthermore, the first row line R1 and the first column line C1 may be connected to pixels of the same type. Since the parasitic capacitance of the first row line R1 and the parasitic capacitance of the first column line C1 may be uniform (or substantially uniform), the settling time of the image sensing pixel PX1 may be uniform (or substantially uniform). Therefore, fixed pattern noise in the image acquired from the image sensing pixel PX1 may be mitigated.

[0038] The first logic circuit 20 may include circuits for controlling the image sensing pixels PX1 of the pixel array 10. For example, the first logic circuit 20 may include a row driver 21, a readout circuit 22, a column driver 23, and first control logic 24.

[0039] The row driver 21 may drive the image sensing pixels PX1 row by row. For example, the row driver 21 may generate a transmission control signal for controlling a transmission transistor of the first pixel circuit, a reset control signal for controlling a reset transistor, and a selection control signal for controlling a selection transistor, and may input the generated signals row by row to the pixel array 10. For example, the control signals generated by the row driver 21 may be input to one of the first row lines R1.

[0040] The readout circuit 22 may include a correlated double sampler (CDS), an analog-to-digital converter (ADC), etc. The correlated double sampler may be connected to the image sensing pixel PX1 via a column line C1. The correlated double sampler may perform correlated double sampling by receiving an image signal from the image sensing pixel PX1 connected to a row line selected by a row line selection signal of the row driver 21. The image signal may be received via the column line C1. The analog-to-digital converter may convert the image signal detected by the correlated double sampler into a digital image signal and transmit it to the column driver 23.

[0041] The column driver 23 may include a latch or buffer circuit for temporarily storing a digital image signal, an amplifier circuit, etc., and may process the digital image signal received from the readout circuit 22. The row driver 21, the readout circuit 22, and the column driver 23 may be controlled by a first control logic 24. The first control logic 24 may include a timing controller for controlling the operation timing of the row driver 21, the readout circuit 22, and the column driver 23.

[0042] Among the image sensing pixels PX1, pixel groups arranged at the same vertical position may share the same first column line C1. For example, the image sensing pixels PX1 arranged at the same vertical position may be selected in sequence by the row driver 21 and output pixel signals via the first column line C1.

[0043] The second logic circuit 30 may include circuits for controlling the event sensing pixels PX2 of the pixel array 10. For example, the second logic circuit 30 may include a row address event processor 31, a column address event processor 32, and second control logic 33.

[0044] The second control logic 33 may transmit a first selection signal for selecting one of the plurality of second column lines C2 to the column address event processor 32. In response to (or based on) the first selection signal, the event sensing pixels PX2 connected to the selected second column line C2 may be simultaneously turned on.

[0045] The second control logic 33 may transmit a second selection signal to the row address event processor 31. In response to the second selection signal, the row address event processor 31 may be connected to at least one of the plurality of second row lines R2. For example, in response to the second selection signal, the row address event processor 31 may acquire event signals from at least some of the plurality of event sensing pixels PX2 connected to the selected second row line R2.

[0046] At least some of the event sensing pixels PX2 that are turned on simultaneously (or substantially simultaneously) in response to the first selection signal may output an ON event signal or an OFF event signal to the row address event processor 31. For example, among the event sensing pixels PX2, pixels whose change in light brightness is greater than a reference value in a positive direction may output an ON event signal, and among the event sensing pixels PX2, pixels whose change in light brightness is greater than a reference value in a negative direction may output an OFF event signal. Among the event sensing pixels PX2, pixels whose change in light brightness is less than the reference value may not output an ON event signal or an OFF event signal.

[0047] The row address event processor 31 may include handshake logic corresponding to a plurality of second row lines R2, which may receive an event signal from an event sensing pixel PX2 connected to a selected second column line C2, and transmit a reset signal to the event sensing pixel PX2 in response to the event signal.

[0048] The second control logic 33 receives an event signal from the row address event processor 31 and can provide a reset signal to the row address event processor 31 to reset the row address event processor 31 .

[0049] 1, the image sensing pixel PX1 is a CIS pixel and the event sensing pixel PX2 is a DVS pixel, but the present invention is not limited to this. The event sensing pixel PX2 can form a ToF (Time of Flight) sensor.

[0050] Image sensors according to embodiments of the present invention will be described in detail below with reference to FIGS.

[0051] FIG. 2 is a plan view showing a simplified unit pixel array of an image sensor according to an embodiment of the present invention.

[0052] According to an embodiment of the present invention, the unit pixel array UPA1 may include a plurality of first regions A1 and a plurality of second regions A2. The plurality of first regions A1 may be parallel to an upper surface of the substrate and may be arranged along a first direction X and a second direction Y that intersect with each other. The plurality of second regions A2 may also be arranged along the first direction X and the second direction Y.

[0053] In one embodiment, each of the plurality of first regions A1 may have an octagonal shape including two first sides extending in a first direction X, two second sides extending in a second direction Y, and four third sides. Each of the plurality of first regions A1 may be adjacent to at least one other first region A1 on at least one of the first sides and at least one of the second sides.

[0054] Each of the second regions A2 may have a rectangular shape. The second regions A2 may be disposed between the first regions A1. For example, the second regions A1 may be adjacent to at least one second region A2 along at least one of the third sides.

[0055] A deep trench isolation (DTI) may be formed at the boundary between the first regions A1 and the second regions A2. The DTI may prevent crosstalk between the regions. The DTI may include an insulating material such as oxide, and sidewalls of the DTI may be formed of a highly reflective material.

[0056] At least one photodiode of the image sensing pixel described with reference to Fig. 1 may be arranged in each of the plurality of first regions A1, and at least one second photodiode of the event sensing pixel described with reference to Fig. 1 may be arranged in each of the plurality of second regions A2. In one embodiment, the size of the first region A1 may be larger than the size of the second region A2. The sum of the light receiving areas of the first photodiodes arranged in the first region A1 may be larger than the sum of the light receiving areas of the second photodiodes arranged in the second region A2.

[0057] 3A to 3C are plan views each showing a pixel included in a unit pixel array according to an embodiment of the present invention.

[0058] 3A to 3C, the unit pixel arrays UPA1a, UPA1b, and UPA1c may include a plurality of image sensing pixels PX1 and one or more event sensing pixels PX2. The unit pixel arrays UPA1a, UPA1b, and UPA1c may correspond to the unit pixel array UPA1 described with reference to FIG.

[0059] Each of the first regions A1 may include one or more photodiodes. In the example of Figures 3A to 3C, each of the first regions A1 may include four photodiodes PD11 to PD14 arranged in a 2x2 pattern in the first direction X and the second direction Y. The photodiodes PD11 to PD14 may constitute four image sensing pixels PX11 to PX14, and the four image sensing pixels PX11 to PX14 may share one floating diffusion node FD.

[0060] Each of the second regions A2 may include one or more photodiodes. In the examples of Figures 3A to 3C, each of the second regions A2 may include one photodiode PD2a, PD2b, PD2c, and PD2d. In one embodiment, each of the photodiodes PD2a, PD2b, PD2c, and PD2d included in the unit pixel arrays UPA1a, UPA1b, and UPA1c may constitute one event-sensing pixel PX2.

[0061] The photodiodes PD2a, PD2b, PD2c, and PD2d can convert incident light into electric charges through a microlens disposed above them. A current corresponding to the amount of electric charge generated in the photodiodes PD2a, PD2b, PD2c, and PD2d can flow to the pixel circuit of the event sensing pixel PX2 through the contacts CT connected to each of the photodiodes PD2a, PD2b, PD2c, and PD2d. The event sensing pixel PX2 can generate an event signal based on the amount of current flowing through the contacts CT.

[0062] In the unit pixel array UPA1, the microlenses disposed on the first area A1 and the second area A2 may have various sizes and shapes.

[0063] 3A, the first region A1 may include one microlens ML1a disposed above the four photodiodes PD11 to PD14. For example, the center point of the microlens ML1a may overlap the floating diffusion node FD in the vertical direction Z perpendicular to the top surface of the substrate. The second region A2 may include one microlens ML2 disposed above one second photodiode.

[0064] However, the present invention is not limited to this. For example, each of the image sensing pixels PX11 to PX14 may have one microlens in the first area A1.

[0065] 3B, the first region A1 may include two second microlenses ML1b, each of which may be disposed above two photodiodes PD11 and PD12 and two photodiodes PD13 and PD14. The second region A2 may include one second microlens ML2 disposed above one photodiode.

[0066] 3C, the first region A1 may include four microlenses ML1a disposed above the four photodiodes PD11 to PD14, respectively, and the second region A2 may include one microlens ML2 disposed above one second photodiode.

[0067] Unit pixel arrays such as the unit pixel array UPA1 described with reference to FIGS. 2, 3A, 3B, and 3C can be arranged in the first direction X and the second direction Y to form the pixel array 10 described with reference to FIG. 1.

[0068] 4 to 7 are plan views each showing a simplified pixel array included in an image sensor according to an embodiment of the present invention.

[0069] 4, a plurality of unit pixel arrays UPA may be arranged in a first direction X and a second direction Y to form a pixel array 10a. In the example of FIG. 4, the unit pixel array UPA is shown to have the same shape as the unit pixel array UPA1a described with reference to FIG. 3A, but the shape of the unit pixel array UPA is not limited to the shape of the unit pixel array UPA1a.

[0070] The unit pixel array UPA may include a plurality of first regions A1 and a plurality of second regions A2. In FIG. 4, an image sensing pixel PX1 arranged in the first region A1 and an event sensing pixel PX2 including four second regions A2 are exemplarily shown.

[0071] The unit pixel array UPA may include color filters. The color filters receive light that has passed through the microlenses and transmit light corresponding to a predetermined range of wavelengths from the received light. For example, each color filter may transmit light corresponding to the wavelength of a single color from the received light, for example, light corresponding to the wavelength of one color from red (R), green (G), and blue (B).

[0072] 4, the first region A1 of the unit pixel array UPA may include a color filter, and the second region A2 may not include a color filter. For example, the second region A2 may transmit light of at least all wavelengths in the visible light range, and the second photodiode PD2 may generate charges based on light of at least all wavelengths in the visible light range.

[0073] In the first region A1, the color filters may be arranged in a tetra pattern, which refers to a color pattern in which a pixel group including four pixels arranged in a 2x2 configuration includes color filters that transmit light of the same wavelength.

[0074] For example, in a first region A1 arranged in a 2x2 format in the unit pixel array UPA, red, green, and blue filters may be arranged in a Bayer pattern, and each of the color filters may be shared by four image sensing pixels PX1 included in the first region A1.

[0075] However, the present invention is not limited thereto. As a first example, the first region A1 may include only one single color filter selected from red, green, and blue. As a second example, the first region A1 may include other color filters that transmit light of other colors, such as cyan, magenta, or yellow. As a third example, at least a portion of the first region A1 may not include a color filter.

[0076] In the pixel array 10a, the first region A1 in the middle portion excluding the peripheral first regions A1 may be adjacent to four first regions A1 in the first direction X and the second direction Y. The first region A1 in the middle portion may be adjacent to four second regions A2 in third and fourth directions that are parallel to the top surface of the substrate and intersect with the first direction X and the second direction Y. The second region A2 in the middle portion excluding the peripheral second regions A2 may be adjacent to four first regions A1.

[0077] 5, a plurality of unit pixel arrays UPA may be arranged in a first direction X and a second direction Y to form a pixel array 10b. The pixel array 10b of FIG. 5 may have a structure similar to that of the pixel array 10a of FIG. 4. However, in the pixel array 10b of FIG. 5, some of the image sensing pixels PX1 may be phase difference detection pixels PX1b.

[0078] 5, each of the phase difference detection pixels PX1b may include two photodiodes having a first relative position in the first direction X and two photodiodes having a second relative position different from the first relative positions in the first direction X. Each of the phase difference detection pixels PG1b may detect a phase difference in the first direction X based on the amount of charge accumulated in the photodiodes having the first relative positions and the amount of charge accumulated in the photodiodes having the second relative positions, thereby providing an autofocus function. However, the present invention is not limited thereto, and the phase difference detection pixel PX1b may also be a pixel that detects a phase difference in the second direction Y.

[0079] 6, a plurality of large unit pixel arrays LUPA may be arranged in a first direction X and a second direction Y to form a pixel array 10c. The pixel array 10c of FIG. 6 may have a structure similar to that of the pixel array 10a of FIG. 4. However, the pattern of color filters arranged in the pixel array 10c of FIG. 6 may be different from the pattern of color filters arranged in the pixel array 10a of FIG. 4.

[0080] For example, the large unit pixel array LUPA shown in Fig. 6 may have a structure in which the unit pixel arrays UPA shown in Fig. 4 are arranged in a 2x2 pattern in the first direction X and the second direction Y. In the large unit pixel array LUPA of Fig. 6, the color filters may be arranged in a hexadeca pattern. For example, in the plurality of first regions A1 arranged in a 4x4 pattern included in the large unit pixel array LUPA, green filters, red filters, and blue filters may be arranged in a Bayer pattern as units of four first regions A1 arranged in a 2x2 pattern.

[0081] 7, a plurality of large unit pixel arrays LUPA may be arranged in a first direction X and a second direction Y to form a pixel array 10d. The pixel array 10d of FIG. 7 may have a structure similar to that of the pixel array 10c of FIG. 6. However, the pattern of color filters arranged in the pixel array 10d of FIG. 7 may be different from the pattern of color filters arranged in the pixel array 10c of FIG. 6.

[0082] For example, some of the image sensing pixels PX1 in the pixel array 10d may provide an autofocus function AF. The image sensing pixels PX1 providing the autofocus function AF may include color filters that transmit the same color. For example, eight image sensing pixels PX1 included in two first regions A1 adjacent to each other in the first direction X and including color filters that transmit the same color may detect a phase difference in the first direction X and provide the autofocus function in the first direction X. However, the present invention is not limited thereto. For example, the pixel array 10d may also include image sensing pixels PX1 adjacent to each other in the second direction Y and providing the autofocus function in the second direction Y.

[0083] As described with reference to FIG. 1, the image sensing pixel PX1 including the first photodiode arranged in the first region A1 of the pixel array 10a, 10b, 10c, 10d may be a CIS pixel, and the event sensing pixel PX2 including the second photodiode arranged in the second region A2 may be a DVS pixel.

[0084] 8A and 8B are circuit diagrams illustrating pixel circuits of an image sensor according to an embodiment of the present invention.

[0085] FIG. 8A shows the first pixel circuit PXC1.

[0086] 8A, the first pixel circuit PXC1 of the image sensing pixels PX11, PX12, PX13, and PX14 can output an electrical signal using charges generated by a plurality of photodiodes PD1 (PD11, PD12, PD13, and PD14). The operation of the active element included in the first pixel circuit PXC1 can be controlled by the first logic circuit 20 included in the image sensor 1 described with reference to FIG.

[0087] The first pixel circuit PXC1 may include a reset transistor RX, a plurality of first transfer transistors TX1 (TX11, TX12, TX13, TX14), a drive transistor DX, and a selection transistor SX. The image sensing pixels PX11, PX12, PX13, and PX14 may include a dedicated photodiode PD1 and a dedicated first transfer transistor TX1. The plurality of image sensing pixels PX1 may share the reset transistor RX, the drive transistor DX, and the selection transistor SX.

[0088] The photodiodes PD1 may be respectively connected to the first floating diffusion node FD1 via the first transfer transistors TX1, and the first photodiodes PD1 may share the first floating diffusion node FD1.

[0089] The first transmission transistors TX1 can transfer charges accumulated in the photodiodes PD1 to the first floating diffusion node FD1 based on the first transmission control signals TG1 (TG11, TG12, TG13, and TG14) respectively transmitted from the row driver. The photodiodes PD1 can generate electrons as the main charge carriers. The drive transistor DX can operate as a source follower buffer amplifier using the charges accumulated in the first floating diffusion node FD1. The drive transistor DX can amplify the charges accumulated in the first floating diffusion node FD1 and transfer the amplified charges to the selection transistor SX.

[0090] The reset transistor RX can reset the voltage of the first floating diffusion node FD1 to a reset voltage based on a reset control signal RG transmitted from the row driver.

[0091] The selection transistor SX may be operated by a selection control signal SEL input from a row driver to perform switching and addressing operations. When the selection control signal SEL is applied from the row driver, a voltage may be output to a column line Col connected to the selection transistor SX. The voltage may be detected by a column driver and a readout circuit connected to the column line Col. The column driver and readout circuit may detect a reset voltage when no charge is accumulated in the first floating diffusion node FD1 and detect a pixel voltage when charge is accumulated in the first floating diffusion node FD1. In one embodiment, the image sensor may generate an image signal by calculating the difference between the reset voltage and the pixel voltage.

[0092] FIG. 8B shows the second pixel circuit PXC2.

[0093] 8B, the second pixel circuit PXC2 of the event sensing pixel PX2 can output an electrical signal using charges generated by the multiple photodiodes PD2a to PD2d. The operation of the active element included in the second pixel circuit PX2 can be controlled by the second logic circuit 30 included in the image sensor 1 described with reference to FIG.

[0094] The second pixel circuit PX2 may include a conversion circuit CKT1, an amplifier circuit CKT2, a comparison circuit CKT3, a first switch SW1, and a second switch SW2. The photodiodes PD2a to PD2d generate charges in response to light, and currents Ia, Ib, Ic, and Id can flow through the photodiodes PD2a to PD2d depending on the amount of generated charges.

[0095] The photodiodes PD2a to PD2b may be connected to a common node. A current I corresponding to the total amount of charges generated by the photodiodes PD2a to PD2b may be input to the conversion circuit CKT1.

[0096] The conversion circuit CKT1 senses a current I flowing due to charges generated by the photodiodes PD2a to PD2d, and outputs a first voltage Vin corresponding to the current I. The conversion circuit CKT1 may include a first transistor TR1, a second transistor TR2, a first amplifier AMP1, a first bias circuit BI1, and a second bias circuit BI2. The first amplifier AMP1, the first bias circuit BI1, and the second bias circuit BI2 may be realized by transistors.

[0097] The first transistor TR1 may be connected in series to the plurality of second photodiodes PD2 connected in parallel. The first bias circuit BI1 and the first amplifier AMP1 may be connected in series. The gate of the first transistor TR1 may be connected between the gate of the second transistor TR2, the first bias circuit BI1, and the first amplifier AMP1.

[0098] The second transistor TR2 may be connected in series with the second bias circuit BI2 and may operate as a source follower. The second transistor TR2 may output a first voltage Vin corresponding to the magnitude of the current I.

[0099] The amplifier circuit CKT2 may include a first capacitor C1, a second capacitor C2, a second amplifier AMP2, and a reset switch SWR. The reset switch SWR may be turned on in response to a reset control signal RESET received from the row address event processor, and may reset the second voltage Vout output by the amplifier circuit CKT2. Through the reset operation, the second voltage Vout may be reset to a constant voltage.

[0100] The amplifier circuit CKT2 can output a second voltage Vout based on the first voltage Vin, which is related to the amount of change in the first voltage Vin over time. In other words, the amplifier circuit CKT2 can amplify the first voltage Vin and output the second voltage Vout to indicate changes in light intensity.

[0101] The comparator circuit CKT3 may include a first comparator COMP1 and a second comparator COMP2. The comparator circuit CKT3 may output an on-event signal ON_EVENT or an off-event signal OFF_EVENT depending on a change in the second voltage Vout. For example, the first comparator COMP1 may compare the second voltage Vout with an on-threshold voltage and generate the on-event signal ON_EVENT according to the comparison result. The second comparator COMP2 may compare the second voltage Vout with an off-threshold voltage and generate the off-event signal OFF_EVENT according to the comparison result.

[0102] The comparator circuit CKT3 may generate an on-event signal ON_EVENT or an off-event signal OFF_EVENT when the change in the intensity of light incident on the second pixel PX2 is equal to or greater than a predetermined reference range. For example, the on-event signal ON_EVENT may have a high logic value when the brightness of light incident on the photodiodes PD2a to PD2d increases above the reference range. The off-event signal OFF_EVENT may have a high logic value when the brightness of light incident on the photodiodes PD2a to PD2d decreases above the reference range.

[0103] The second pixel circuit PXC2 may receive a first select signal SEL1 from the digital address event processor via the column address event processor. The first switch SW1 and the second switch SW2 may be turned on in response to the first select signal SEL1. When the first switch SW1 and the second switch SW2 are turned on, the generated on event signal ON_EVENT or off event signal OFF_EVENT may be output to the row address event processor.

[0104] For example, if the brightness of light incident on the photodiodes PD2a to PD2d increases above a reference range, the second pixel circuit PXC2 may output an on-event signal ON_EVENT to the row address event processor via the first switch SW1 turned on in response to the first select signal SEL1. If the brightness of light incident on the photodiodes PD2a to PD2d decreases above the reference range, the second pixel circuit PXC2 may output an off-event signal OFF_EVENT to the row address event processor via the second switch SW2 turned on in response to the second select signal SEL2. If the change in the brightness of light incident on the photodiodes PD2a to PD2d is smaller than the reference range, the second pixel circuit PXC2 may not output the on-event signal ON_EVENT or the off-event signal OFF_EVENT.

[0105] After the comparison circuit CKT3 outputs the on-event signal ON_EVENT or the off-event signal OFF_EVENT, the amplifier circuit CKT2 can receive a reset signal RESET from the row address event processor, which can reset the second voltage Vout output by the amplifier circuit CKT2.

[0106] In one embodiment, the second pixel circuit PXC2 may occupy a larger area on the substrate than the first pixel circuit PXC1. In the example of Figures 8A and 8B, the first pixel circuit PXC1 may include only seven transistor elements, while the second pixel circuit PXC2 may include a circuit with a relatively complex structure, such as a comparator circuit. According to an embodiment of the present invention, in the image sensor, the first pixel circuit PXC1 and the second pixel circuit PXC2 may be vertically stacked, allowing the first pixel circuit PXC1 and the second pixel circuit PXC2 to be efficiently arranged.

[0107] FIG. 9 is a diagram showing a simplified layout of an image sensor according to an embodiment of the present invention.

[0108] 9, the image sensor 100 may include an upper semiconductor chip 200, a middle semiconductor chip 300, and a lower semiconductor chip 400. Each of the upper semiconductor chip 200, the middle semiconductor chip 300, and the lower semiconductor chip 400 may include a main region and a peripheral region.

[0109] For example, a photodiode PD1 and a second photodiode PD2 may be arranged in the main region of the upper semiconductor chip 200. Figure 9 shows a first region A1 where the photodiode PD1 may be arranged and a second region A2 where the photodiode PD2 may be arranged.

[0110] According to an embodiment of the present invention, the upper semiconductor chip 200 may further include a first pixel circuit formed below the photodiode PD1. For example, one first area A1 in the upper semiconductor chip 200 may include four photodiodes PD1 constituting image sensing pixels and the first pixel circuit. The first pixel circuit may correspond to that described with reference to FIG. 8A.

[0111] According to an embodiment of the present invention, a second pixel circuit PXC2 may be arranged in the main region of the middle semiconductor chip 300. The four photodiodes of the upper semiconductor chip 200 and the second pixel circuit PXC2 of the middle semiconductor chip 300 may be electrically connected by signal pads PAD or metal-to-metal bonding such as Cu-Cu hybrid bonding.

[0112] 9, the second pixel circuit PXC2 may occupy areas corresponding to four first areas A1 and four second areas A2. In one embodiment, the photodiodes PD2 arranged in the four second areas A2 may be connected to one second pixel circuit PXC2 by a signal pad PAD or Cu-Cu hybrid bonding. For example, the four photodiodes PD2 may be electrically connected to one another via a wiring pattern in the upper semiconductor chip 200, and the four photodiodes PD2 may be connected to the second pixel circuit PXC2 via one signal pad PAD.

[0113] According to an embodiment of the present invention, since the second pixel circuit PXC2 is arranged on the intermediate semiconductor chip 300, even if the area occupied by one second pixel circuit PXC2 is larger than the size of the second area A2 in which the photodiode PD2 is arranged, the area of ​​the image sensor 100 in the XY plane may not increase.

[0114] In one embodiment, by using four photodiodes PD2 to form one event sensing pixel, the area of ​​the image sensor 100 in the XY plane may not increase even if the area occupied by one second pixel circuit PXC2 is larger than the size of the first area A1 in which the image sensing pixel PX1 is arranged.

[0115] The main region of the lower semiconductor chip 400 may include a logic circuit LOGIC for the image sensing pixel PX1 and the event sensing pixel PX2. For example, the logic circuit LOGIC may include the first logic circuit 20 and the second logic circuit 30 described with reference to FIG. 1. In one embodiment, the logic circuit LOGIC may further include an image signal processor (ISP) that processes an image signal to generate an image, an event signal processor (ESP) that processes an event signal, etc.

[0116] Peripheral circuits connected to circuits in the main region may be arranged in the peripheral regions of the upper semiconductor chip 200, the middle semiconductor chip 300, and the lower semiconductor chip 400, respectively.

[0117] The image sensor 100 may include through-via TSVs that penetrate the peripheral region. For example, Figure 9 illustrates through-via TSVs that connect the peripheral circuits of the upper semiconductor chip 200, the middle semiconductor chip 300, and the lower semiconductor chip 400 to each other.

[0118] The structure of the image sensor according to the embodiment of the present invention will be specifically described below with reference to FIGS.

[0119] 10 to 14 are diagrams simply showing pixels included in an image sensor according to one embodiment of the present invention.

[0120] 10 illustrates pixels included in a unit pixel array UPA1a. The unit pixel array UPA1a of FIG. 10 may correspond to the unit pixel array UPA1a described with reference to FIG. 3A. However, the unit pixel array UPA1a of FIG. 10 further includes a device isolation layer DTI formed between the first region A1 and the second region A2, and a color filter disposed in the first region A1.

[0121] 11 is a cross-sectional view taken along line II' in FIG. 10, FIG. 12 is a cross-sectional view taken along line II-II' in FIG. 10, and FIG. 13 is a cross-sectional view taken along line III-III' in FIG. 10.

[0122] 11 to 13, the image sensor 100 may include an upper semiconductor chip 200, a middle semiconductor chip 300, and a lower semiconductor chip 400 as described with reference to Fig. 9. However, the lower semiconductor chip 400 is omitted in Figs. 11 to 13.

[0123] In the image sensor 100 according to an embodiment of the present invention, a pixel circuit may be disposed below the plurality of photodiodes PD1 arranged in the first region A1 and the plurality of photodiodes PD2 arranged in the second region A2.

[0124] For example, the first pixel circuit may be disposed on the first surface of the first substrate 201. The first pixel circuit may include a plurality of first elements 230, a first wiring pattern 231 connected to the plurality of first elements 230, and a first insulating layer 232 covering the plurality of first elements 230 and the first wiring pattern 231.

[0125] The first pixel circuit may include a first floating diffusion node FD1. For example, as shown in FIG. 10, the first pixels PX1 included in the first region may share one first floating diffusion node.

[0126] The first floating diffusion node FD1 may be disposed near the intra-pixel isolation layer 212. For example, the first floating diffusion node FD1 may be disposed at a position overlapping the intra-pixel isolation layer 212 in a direction perpendicular to the first surface of the first substrate 201. The first element 230 adjacent to the first floating diffusion node FD1 may correspond to a plurality of first transfer transistors. Gates of the plurality of first transfer transistors may have a vertical structure in which at least a portion of the gate is embedded in the substrate 201, and charges generated in the first photodiode PD1 may move to the first floating diffusion node FD1 via the transfer transistor.

[0127] Each of the image sensing pixels PX1 may include a color filter 203, a light transmission layer 204, and a microlens 205 disposed on a second surface opposite to the first surface of the first substrate 201. For example, each of the image sensing pixels PX1 may include a first microlens 205 disposed on top of a plurality of first photodiodes PD1. Of the light passing through the first microlens 205, light of a wavelength component transmitted by the color filter 203 may be incident on the first photodiode PD1 disposed below the first microlens 205.

[0128] 11, the pixel isolation layer 211 may have a first width W1 and a first length L1, and the intra-pixel isolation layer 212 may have a second width W2 and a second length L2. For example, the second width W2 of the intra-pixel isolation layer 212 may be smaller than the first width W1, thereby allowing the pixel isolation layer 211 and the intra-pixel isolation layer 212 to be formed simultaneously in a single process. However, the present invention is not limited thereto, and the first width W1 and the second width W2 may be the same depending on the embodiment.

[0129] In addition, the first length L1 may be greater than the second length L2. However, the present invention is not limited thereto, and the first length L1 and the second length L2 may each have various values. Meanwhile, the pixel isolation layer 211 may completely penetrate from the first surface to the second surface of the first substrate 201.

[0130] In one embodiment, the intra-pixel isolation layer 212 may have a length in the first direction that is shorter than the plurality of photodiodes PD1, thereby allowing charges to move between the plurality of photodiodes PD1 across the intra-pixel isolation layer 212. For example, if excessive charges are generated in one of the plurality of photodiodes PD1, the charge movement can prevent saturation of the photodiode PD1.

[0131] The second pixel circuit may be disposed on a first surface of the second substrate 301 of the middle semiconductor chip 300. The second pixel circuit may include a plurality of second elements 330, a second wiring pattern 331 connected to the plurality of second elements 330, and a second insulating layer 332 covering the plurality of second elements 330 and the second wiring pattern 331.

[0132] The upper semiconductor chip 200 may include contacts CT for connecting one or more photodiodes PD2 to a second pixel circuit, and charges generated in the pixel circuit may be transferred to the second pixel circuit through the contacts CT.

[0133] The contacts CT may penetrate a region in which the photodiode PD2 is formed on the first substrate 201. The insulating layer 332 may include a first signal pad 233 for electrically connecting circuit elements in the main region of the upper semiconductor chip 200 and the main region of the middle semiconductor chip 300. The contacts CT may be connected to the first signal pads 233 via the first wiring patterns 231.

[0134] The event sensing pixel PX2 may include a light-transmitting layer and a second microlens 206 disposed on the second surface of the first substrate 201. For example, the event sensing pixel PX2 may include a second microlens 206 disposed above each of the second photodiodes PD2. Light passing through the second microlens 206 may be incident on the second photodiode PD2 disposed below the second microlens 206.

[0135] In one embodiment, the event-sensing pixel PX2 may not include a color filter. For example, a light-transmitting layer 206 having the same thickness as the color filter 203 disposed on the first photodiode PD2 may be disposed on the second photodiode PD2.

[0136] According to an embodiment of the present invention, the upper semiconductor chip 200 and the middle semiconductor chip 300 may be bonded by C2C (Chip to Chip) bonding. That is, the insulating layer 232 of the upper semiconductor chip 200 may be in contact with the insulating layer 332 of the middle semiconductor chip 300, and the signal pad 233 of the upper semiconductor chip 200 may be in contact with the signal pad 333 of the middle semiconductor chip 300. The second photodiode PD2 may be electrically connected to a second pixel circuit formed on the middle semiconductor chip 300 via the signal pads 233 and 333.

[0137] 11 to 13, the upper semiconductor chip 200 and the middle semiconductor chip 300 are bonded by C2C bonding, but the present invention is not limited to this. For example, the upper semiconductor chip 200 and the middle semiconductor chip 300 may be bonded by direct bonding.

[0138] 14 illustrates a cross-sectional view taken along line III-III' in FIG. 10 when upper semiconductor chip 200 and middle semiconductor chip 300 are bonded by direct bonding. In FIG. 14, lower semiconductor chip 400 as described with reference to FIG. 9 is omitted.

[0139] The semiconductor device 100a of Fig. 14 may include an upper semiconductor chip 200 and a middle semiconductor chip 300a. The upper semiconductor chip 200 and the middle semiconductor chip 300a of Fig. 14 may have structures similar to those of the upper semiconductor chip 200 and the middle semiconductor chip 300 described with reference to Figs. 11 to 13. For example, the second substrate 301a, the plurality of second elements 330a, the second wiring pattern 331a, and the second insulating layer 332a of the middle semiconductor chip 300a may have structures similar to those of the second substrate 301, the second elements 330, the second wiring pattern 331, and the second insulating layer 332 described with reference to Figs. 11 to 13.

[0140] 11 to 13, the middle semiconductor chip 300a of FIG. 14 can be bonded to the upper semiconductor chip 200 by direct bonding. That is, the insulating layer 232 of the upper semiconductor chip 200 can be bonded to the second substrate 301a of the middle semiconductor chip 300a. The middle semiconductor chip 300a can include a through via 334a that penetrates the second substrate 301a and at least a portion of the insulating layer 332a to connect the photodiode PD2 to the second pixel circuit. The through via 334a can be in contact with the pad 233 and the wiring pattern 331a of the upper semiconductor chip 200.

[0141] 3A to 14, the embodiments of the present invention have been described using an example in which four photodiodes PD2 are connected to one second pixel circuit to form one event sensing pixel PX2. However, the present invention is not limited to this. For example, if the area occupied by one second pixel circuit is equal to or smaller than the sum of the first area A1 and the second area A2, one second pixel circuit may be electrically connected to one photodiode PD2 and arranged to overlap one first area A1.

[0142] FIG. 15 is a plan view showing a simplified view of a pixel included in an image sensor according to an embodiment of the present invention.

[0143] The top surface of the unit pixel array UPA2 of Fig. 15 may have the same structure as the top surface of the unit pixel array UPA1a described with reference to Fig. 3A. However, in the unit pixel array UPA2 of Fig. 15, each of the plurality of photodiodes PD21 to PD24 may constitute one second pixel. For example, the unit pixel array UPA2 may include four event sensing pixels PX21 to PX24.

[0144] According to an embodiment of the present invention, the second pixel circuits of the event sensing pixels PX21-PX24 may overlap the first pixel circuits of the image sensing pixels PX11-PX14 in the vertical direction Z. For example, the photodiodes PD11-PD14, the photodiodes PD21-PD24, and the first pixel circuits may be included in the upper semiconductor chip, and the second pixel circuits may be included in the second region A2 and the first region A1 adjacent to the second region A2 in the middle semiconductor chip.

[0145] The present invention is not limited to the case where one first region A1 in which image sensing pixels are arranged includes four photodiodes PD1, for example, the first region A1 may include one first photodiode PD1, nine first photodiodes PD1, or any other number of first photodiodes.

[0146] FIG. 16 is a plan view showing a simplified view of a pixel included in an image sensor according to an embodiment of the present invention.

[0147] The top surface of the unit pixel array UPA3 of Figure 16 may have a structure similar to the top surface of the unit pixel array UPA1a described with reference to Figure 3A. However, the unit pixel array UPA3 of Figure 16 may include nine first photodiodes PD1 arranged in a 3x3 pattern in the first direction X and the second direction Y in one first region A1. The photodiodes PD1 included in one first region A1 may constitute one pixel group PG1.

[0148] 16, the unit pixel array UPA3 may include an event-sensing pixel PX2 including four photodiodes PD2a to PD2d included in four second regions A2. However, the present invention is not limited to this. As a first example, the unit pixel array UPA3 may include four event-sensing pixels PX2 each including one photodiode PD2. As a second example, the unit pixel array UPA3 may include nine first regions A1 and nine second regions A2 each arranged in a 3x3 configuration, and may include one event-sensing pixel PX2 each including photodiodes PD2 included in the nine second regions A2.

[0149] According to an embodiment of the present invention, the image sensing pixel may have a split photodiode structure. The image sensing pixel having the split photodiode structure may include a small photodiode having a small light receiving area and a large photodiode having a larger light receiving area than the small photodiode.

[0150] For example, a large photodiode can generate pixel signals mainly in low-light conditions. The large photodiode can operate in high-conversion gain (HCG) mode in the lowest light conditions and in low-conversion gain (LCG) mode in general low-light conditions. The small photodiode can operate in high-light conditions by extending the exposure time.

[0151] Hereinafter, with reference to FIGS. 17 to 20, examples of structures that the image sensor according to the embodiment of the present invention may have when the first pixel group PG1 has a split photodiode structure will be described. FIG.

[0152] 17 to 19 are plan views each showing a simplified pixel included in an image sensor according to an embodiment of the present invention.

[0153] 17, the unit pixel array UPA4 may include a plurality of first regions A1, a plurality of second regions A2, and a plurality of third regions A3, each of which may be parallel to an upper surface of the substrate and arranged along a first direction X and a second direction Y that intersect with each other.

[0154] Specifically, the unit pixel array UPA4 may include a plurality of octagonal regions and a plurality of third regions A3. Each of the octagonal regions may have an octagonal shape including two first sides extending in a first direction X, two second sides extending in a second direction Y, and four third sides. Each of the third regions A3 may have a quadrangular shape.

[0155] Each of the plurality of octagonal regions may be adjacent to at least one other octagonal region along at least one of the first sides and at least one of the second sides. Each of the plurality of third regions A3 may be disposed between the plurality of octagonal regions. For example, each of the plurality of octagonal regions may be adjacent to at least one other third region A3 along at least one of the third sides.

[0156] Each of the multiple octagonal regions may include a first region A1 and a second region A2. In one embodiment, the area of ​​the first region A1 may be larger than the area of ​​the second region A2. For example, the first region A1 may be adjacent to three of the four third sides, and the second region A2 may be adjacent to one of the four third sides.

[0157] An isolation film DTI may be formed at the boundaries between the plurality of first regions A1, the plurality of second regions A2, and the plurality of third regions A3.

[0158] According to an embodiment of the present invention, each of the plurality of first regions A1 includes a large photodiode, and each of the plurality of second regions A2 includes a small photodiode. The large photodiode and the small photodiode can form a plurality of image sensing pixels. And, each of the plurality of third regions A3 can include a photodiode that forms an event sensing pixel.

[0159] 18A and 18B, the unit pixel arrays UPA4a and UPA4b may include a plurality of image sensing pixels PX1 and one or more second pixels PX2. The unit pixel arrays UPA4a and UPA4b may correspond to the unit pixel array UPA4 described with reference to FIG.

[0160] Each of the first regions A1 may include one or more photodiodes PD1 (PD11, PD12, PD13). Each of the second regions A2 may include one or more photodiodes PD2 (PD21). The total light-receiving area of ​​the photodiodes PD1 may be larger than the light-receiving area of ​​the photodiode PD2. The photodiodes PD1 may be collectively referred to as a large photodiode, and the photodiode PD2 may be collectively referred to as a small photodiode. The first region A1 and the second region A2 may share a first pixel circuit. That is, the image sensing pixel PX1 may have a split photodiode structure.

[0161] Each of the first regions A1 may include one or more first floating diffusion nodes FD1. For example, the photodiodes PD1 included in one first region A1 may share one first floating diffusion node FD1. Each of the second regions A2 may include a second floating diffusion node FD2.

[0162] The first and second regions A1 and A2 included in one octagonal region may include a plurality of image sensing pixels sharing one first pixel circuit, and the image sensing pixel PX1 may generate an image signal using at least some of the charges accumulated in the first floating diffusion node FD1 and the second floating diffusion node FD2.

[0163] Each of the third regions A3 may include one or more third photodiodes. In the examples of Figures 18A and 18B, each of the third regions A3 may include one photodiode PD3a-PD3d. In one embodiment, the photodiodes PD3a-PD3d included in the plurality of third regions A3 included in the unit pixel arrays UPA4a and UPA4b may form one second pixel PX2. Each of the third regions A3 may include a contact CT for transferring charges generated in the photodiodes PD3a-PD3d to the second pixel PX2.

[0164] In the unit pixel array UPA4, the microlenses included in the upper portions of the first to third regions A1 to A3 may have various sizes and shapes.

[0165] 18A, the first region A1 may include one first microlens ML1 disposed above three first photodiodes PD1, the second region A2 may include one second microlens ML2 disposed above one photodiode PD2, and the third region A3 may include one third microlens ML3 disposed above one photodiode PD3a-PD3d.

[0166] In the example of FIG. 18B, the first region A1 may include three first microlenses ML1b disposed above three photodiodes PD11, PD12, and PD13, respectively.

[0167] 19, the unit pixel array UPA4c may have a structure similar to the unit pixel array UPA4a of FIG. 18A. However, in the unit pixel array UPA4c of FIG. 19, one first region A1 may include eight photodiodes PD1. In one octagonal region, eight photodiodes PD1 and one photodiode PD2 may be arranged in a 3×3 pattern.

[0168] The photodiodes PD1 and PD2 included in one octagonal region may share the first pixel circuit. The total light-receiving area of ​​the eight photodiodes PD1 may be greater than the total light-receiving area of ​​the eight photodiodes PD2.

[0169] The event sensing pixel PX2 described with reference to Figures 18A, 18B, and 19 may include a second pixel circuit as described with reference to Figure 8B. However, the first pixel circuit shared by the first image sensing pixel described with reference to Figures 18A, 18B, and 19 may be different from the first pixel circuit described with reference to Figure 8A. Hereinafter, the circuit structure of the first pixel group PG1 having a split photodiode structure will be described with reference to Figure 20.

[0170] FIG. 20 is a circuit diagram showing a pixel circuit of an image sensor according to an embodiment of the present invention.

[0171] 20, the first pixel circuit PXC1 can output an electrical signal using charges generated by a plurality of photodiodes PD11 to PD13 included in the first region A1 and a photodiode PD2 included in the second region A2. The operation of the active elements included in the first pixel circuit PXC1 can be controlled by the first logic circuit 20 included in the image sensor 1 described with reference to FIG.

[0172] The first pixel circuit PXC1 may include a reset transistor RX, a plurality of first transmission transistors TX1 (TX11, TX12, TX13), a second transmission transistor TX2, a storage capacitor SC, a first switch transistor SWX1, a second switch transistor SWX2, a driving transistor DX, and a selection transistor SX.

[0173] The photodiodes PD11 to PD13 may be respectively connected to a first floating diffusion node FD1 via a plurality of first transfer transistors TX1. The photodiodes PD11 to PD13 may share the first floating diffusion node FD1. The photodiode PD2 may be connected to a second floating diffusion node FD2 via a second transfer transistor TX2.

[0174] The storage capacitor SC may be an element for storing charges generated by the second photodiode PD2. The storage capacitor SC may be implemented as a metal-insulator-metal (MIM) capacitor, an active capacitor, or the like. Meanwhile, the second power supply voltage VSC connected to the storage capacitor SC may be smaller than the first power supply voltage VDD of the entire pixel circuit. However, this is merely an example and is not limiting. The first power supply voltage VDD and the second power supply voltage VSC may be the same.

[0175] The storage capacitor SC stores charges in response to the amount of charges generated by the photodiode PD2 and the operation of the second transfer transistor TX2. A first switch transistor SWX1 is connected between the storage capacitor SC and a third floating diffusion node FD3, and the charges of the storage capacitor SC can be transferred to the third floating diffusion node FD3 by the on / off operation of the first switch transistor SWX1.

[0176] Meanwhile, the second switch transistor SWX2 may be connected between the third floating diffusion node FD3 and the first floating diffusion node FD1. That is, the third floating diffusion node FD3 may be connected to the reset transistor RX1, the first switch transistor SWX1, and the second switch transistor SWX2. Charges accumulated in the third floating diffusion node FD3 may be transferred to the first floating diffusion node FD1 in response to the operation of the second switch transistor SWX2.

[0177] 20 , the photodiodes PD1 and PD2 may share a column line Col. Therefore, while a first pixel voltage corresponding to the charges of the photodiodes PD1 is output to the column line Col, the photodiode PD2 may be isolated from the column line Col. For example, while the first pixel voltage is output to the column line Col, if at least one of the first switch transistor SWX1 and the second switch transistor SWX2 is turned off, the second photodiode PD2 may be isolated from the column line Col. To generate the first pixel voltage using the charges of the photodiodes PD1 and output it to the column line Col, the first transfer transistor TX1 is turned on, and the charges generated in the photodiode PD1 may be accumulated in the first floating diffusion node FD1.

[0178] Similarly, while a second pixel voltage corresponding to the charge of photodiode PD2 is output to the column line Col, the photodiodes PD11-PD13 may be isolated from the column line Col. For example, while the second pixel voltage is output to the column line Col, the first transfer transistor TX1 is turned off, thereby isolating the photodiodes PD11-PD13 from the column line Col. To generate and output the second pixel voltage to the column line Col, the first switch transistor SWX1 and the second switch transistor SWX2 are turned on, thereby connecting the third floating diffusion node FD3 to the first floating diffusion node FD1. The charge generated by the second photodiode PD2 and stored in the storage capacitor SC is accumulated in the first floating diffusion node FD1, the second floating diffusion node FD2, and the third floating diffusion node FD3 and converted into a voltage by the drive transistor DX.

[0179] An image sensor in which the image sensing pixel has a split photodiode structure may have various structures other than the structures described with reference to FIGS.

[0180] 21 to 23 are plan views each showing a pixel included in an image sensor according to an embodiment of the present invention.

[0181] 21, the unit pixel array UPA5 may include a plurality of first regions A1, a plurality of second regions A2, and a plurality of third regions A3. The unit pixel array UPA5 of FIG. 21 may have regions with shapes similar to those of the unit pixel array UPA4 described with reference to FIG. 17. However, the unit pixel array UPA5 may have a structure in which the shapes and positions of the second regions A2 and the third regions A3 are different from those of the unit pixel array UPA4.

[0182] For example, the unit pixel array UPA5 may include a plurality of octagonal regions, each of which is adjacent to two first sides extending in a first direction X, two second sides extending in a second direction Y, and four third sides. Each of the octagonal regions may be adjacent to at least one of the octagonal regions along at least one of the first sides and at least one of the second sides. Each of the octagonal regions may include a first region A1 and a third region A3.

[0183] The second regions A2 may be disposed between the octagonal regions, and for example, at least one of the third sides of the octagonal regions may be adjacent to at least one of the second regions A2.

[0184] 22A and 22B, the unit pixel arrays UPA5a and UPA5b may include a plurality of image sensing pixels PX1 and one or more event sensing pixels PX2. The unit pixel arrays UPA5a and UPA5b may correspond to the unit pixel array UPA5 described with reference to FIG.

[0185] Each of the first regions A1 may include one or more photodiodes PD1 (PD11, PD12, PD13), and each of the second regions A2 may include one or more photodiodes PD2 (PD21). The total light receiving area of ​​the first photodiodes PD1 may be larger than the light receiving area of ​​the second photodiode PD2.

[0186] In one embodiment, a first region A1 and a second region A2 separated by a third region A3 may share a first pixel circuit, and color filters that transmit the same color may be disposed in the first region A1 and the second region A2 that share a first pixel circuit.

[0187] Each of the third regions A3 may include one photodiode PD3a to PD3d. In one embodiment, the third photodiodes PD3 included in the plurality of third regions A3 included in the unit pixel arrays UPA4a and UPA4b may configure one event sensing pixel PX2.

[0188] In the unit pixel array UPA5, the microlenses included in the upper portions of the first to third regions A1 to A3 may have various sizes and shapes.

[0189] 22A, the first region A1 may include one first microlens ML1 disposed above three photodiodes PD1, the second region A2 may include one second microlens ML2 disposed above one photodiode PD2, and the third region A3 may include one third microlens ML3 disposed above one photodiode PD3.

[0190] In the example of FIG. 22B, the first region A1 may include three first microlenses ML1b disposed above the three photodiodes PD1, respectively.

[0191] 23, the unit pixel array UPA5c may have a structure similar to the unit pixel array UPA5a of FIG. 21A. However, the unit pixel array UPA5c of FIG. 23 may include eight photodiodes PD1. In one octagonal region, eight first photodiodes PD1 and one photodiode PD3 may be arranged in a 3×3 pattern.

[0192] A first region A1 and a second region A2 separated by a third region A3 may share a first pixel circuit. The total light receiving area of ​​the eight photodiodes PD1 may be greater than the total light receiving area of ​​the eight photodiodes PD2.

[0193] 24 to 26 are plan views each showing a simplified pixel included in an image sensor according to an embodiment of the present invention.

[0194] 24, the unit pixel array UPA6 may include a plurality of first regions A1, a plurality of second regions A2, and a plurality of third regions A3. The unit pixel array UPA6 may include a plurality of rectangular regions. Each of the rectangular regions may include one first region A1, one second region A2, and one third region A3.

[0195] 24, the first region A1 may be arranged adjacent to the second region A2 and the third region A3 in the first direction X, and the second region A2 and the third region A3 may be arranged adjacent to each other in the second direction Y. The third regions A3 may be spaced apart from each other in the first direction X and the second direction Y.

[0196] An isolation film DTI may be formed at the boundaries of the first regions A1, the second regions A2, and the third regions A3.

[0197] According to an embodiment of the present invention, each of the plurality of first regions A1 includes a large photodiode, each of the plurality of second regions A2 includes a small photodiode, the large photodiode and the small photodiode can share a first pixel circuit, and each of the plurality of third regions A3 includes a photodiode constituting an event sensing pixel.

[0198] 25A and 25B, the unit pixel arrays UPA6a and UPA6b may include a plurality of image sensing pixels PX1 and one or more event sensing pixels PX2. The unit pixel arrays UPA6a and UPA6b may correspond to the unit pixel array UPA6 described with reference to FIG.

[0199] In the examples of Figures 25A and 25B, each of the first regions A1 includes two first photodiodes PD1, each of the second regions A2 includes one second photodiode PD2, and each of the third regions A3 includes one third photodiode PD3a to PD3d.

[0200] 18A, 18B, 22A, and 22B, the first photodiode PD1 and the second photodiode PD2 included in one rectangular region may share one first pixel circuit. Image sensing pixels sharing one first pixel circuit may include color filters that transmit the same color. In addition, the third photodiodes PD3 included in the plurality of third regions A3 included in the unit pixel arrays UPA6a and UPA6b may form one event sensing pixel PX2.

[0201] In the unit pixel array UPA6, the microlenses included in the upper portions of the first to third regions A1 to A3 may have various sizes and shapes.

[0202] 25A, the first region A1 may include one first microlens ML1 disposed above two first photodiodes PD1, the second region A2 may include one second microlens ML2 disposed above one photodiode PD2, and the third region A3 may include one third microlens ML3 disposed above one photodiode PD3.

[0203] In the example of FIG. 25B, the first region A1 may include two first microlenses ML1b disposed above the two first photodiodes PD1, respectively.

[0204] 26, the unit pixel array UPA6c may have a structure similar to that of the unit pixel array UPA6a of FIG. 25A. However, in the unit pixel array UPA6c of FIG. 26, one first region A1 may include six photodiodes PD1, and one second region A2 may include two photodiodes PD2. In one rectangular region, the photodiodes PD1, PD2, and PD3 may be arranged in a 3×3 pattern.

[0205] 27 to 29 are plan views each showing a simplified pixel included in an image sensor according to an embodiment of the present invention.

[0206] 27, the unit pixel array UPA7 may include a plurality of first regions A1, a plurality of second regions A2, and a plurality of third regions A3. The unit pixel array UPA7 may include a plurality of rectangular regions. Each of the rectangular regions may include one first region A1, one second region A2, and one third region A3.

[0207] Unlike the unit pixel array UPA6 described in Fig. 24, the relative positions of the first region A1, the second region A2, and the third region A3 in one rectangular region of the unit pixel array UPA7 in Fig. 27 may be different. For example, in rectangular regions adjacent to each other in the first direction X and the second direction Y of the unit pixel array UPA6, the third regions A4 may be disposed adjacent to each other.

[0208] 28A and 28B, the unit pixel arrays UPA7a and UPA7b may include a plurality of image sensing pixels PX1 and one or more event sensing pixels PX2. The unit pixel arrays UPA7a and UPA7b may correspond to the unit pixel array UPA7 described with reference to FIG.

[0209] 25A and 25B, the first photodiode PD1 and the second photodiode PD2 included in one rectangular region may share one first pixel circuit. Image sensing pixels sharing one first pixel circuit may include color filters that transmit the same color. In addition, the third photodiodes PD3 included in the plurality of third regions A3 included in the unit pixel arrays UPA7a and UPA7b may form one event sensing pixel PX2.

[0210] In the unit pixel array UPA7, the microlenses included in the upper portions of the first to third regions A1 to A3 may have various sizes and shapes.

[0211] 28A, the first region A1 may include one first microlens ML1 disposed above two photodiodes PD1, the second region A2 may include one second microlens ML2 disposed above one photodiode PD2, and the third region A3 may include one third microlens ML3 disposed above one photodiode PD3.

[0212] In the example of FIG. 28B, the first region A1 may include two first microlenses ML1b disposed above the two first photodiodes PD1, respectively.

[0213] 29, the unit pixel array UPA7c may have a structure similar to that of the unit pixel array UPA7a of FIG. 28A. However, in the unit pixel array UPA7c of FIG. 29, one first region A1 may include six photodiodes PD1, and one second region A2 may include two photodiodes PD2. In one rectangular region, the photodiodes PD1, PD2, and PD3 may be arranged in a 3×3 pattern.

[0214] Examples of image sensors having various structures according to embodiments of the present invention have been described with reference to Figures 17 to 29. Below, an example of a vertical structure that the image sensor may have, including a lower semiconductor chip, will be described.

[0215] FIG. 30 is a side cross-sectional view showing an image sensor according to an embodiment of the present invention, in which a main region and a peripheral region are cut away.

[0216] The image sensor 1100 may include a first semiconductor chip 1200, a second semiconductor chip 1300, and a third semiconductor chip 1400. The first semiconductor chip 1200, the second semiconductor chip 1300, and the third semiconductor chip 1400 may correspond to the upper semiconductor chip 200, the middle semiconductor chip 300, and the lower semiconductor chip 400 described with reference to Fig. 9. A main region MAIN and a peripheral region PERI may be defined in each of the first semiconductor chip 1200, the second semiconductor chip 1300, and the third semiconductor chip 1400.

[0217] The first semiconductor chip 1200 may include a first semiconductor substrate 1210 and a first wiring structure 1220 disposed on the first semiconductor substrate 1210 .

[0218] The first semiconductor substrate 1210 may be a semiconductor substrate such as a silicon substrate or a silicon germanium substrate. In the first semiconductor substrate 1210, a surface on which a semiconductor device is formed may be referred to as an upper surface or front side, and a surface of the first semiconductor substrate 1210 opposite to the upper surface may be referred to as a lower surface or back side.

[0219] The first semiconductor substrate 1210 includes a plurality of photodiodes PD1 and PD2 and a pixel separating structure 1280. In one embodiment, the plurality of first photodiodes PD1 may share a first pixel circuit PXC1, and the photodiode PD2 may be connected to a second pixel circuit PXC2. The bottom surface of the first semiconductor substrate 1210 may be a light-receiving surface onto which light is incident.

[0220] The pixel separating structure 1280 may be disposed between a plurality of pixels arranged in a matrix to define a plurality of pixels. In one embodiment, the pixel separating structure 1280 may physically and electrically separate the first photodiode PD1 and the second photodiode PD2. The pixel separating structure 1280 may have an FDTI structure penetrating the semiconductor substrate 1210 from the upper surface to the lower surface of the semiconductor substrate 1210. A deep trench for the pixel separating structure 1280 is formed in the semiconductor substrate 1210. The pixel separating structure 1280 includes an insulating layer 1281 conformally formed on the inner surface of the trench and a conductive layer 1285 filling the trench on the insulating layer 1281. For example, the insulating layer 1281 may include silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or tantalum oxide. The conductive layer 1285 may include at least one of doped polysilicon, metal, metal silicide, metal nitride, or metal-containing film.

[0221] 8A may be disposed on the upper surface of the first semiconductor substrate 1210. The isolation pattern ISO may be formed in the first semiconductor substrate 1201 to define an active region in which the first semiconductor device will be formed. For example, the isolation pattern ISO may be formed by filling an insulating material in a shallow trench formed by patterning the first semiconductor substrate 1210.

[0222] The first semiconductor element includes a part of an element that constitutes the first pixel circuit, and may include a transistor having a gate electrode, a gate insulating film, and source / drain regions.

[0223] The first semiconductor device may include transistors such as the first transfer transistor TX1, the reset transistor RX, the drive transistor DX, and the select transistor SX as described with reference to FIG. 8A.

[0224] At least a portion of the gate electrode of the first transfer transistor TX1 may extend vertically and be buried in the first semiconductor substrate 1210. A first floating diffusion node FD1 may be formed to be connected to one end of the first transfer transistor TX1. When the first transfer transistor TX1 is turned on, charges generated from the first photodiode PD1 may be stored in the first floating diffusion node FD1.

[0225] The first wiring structure 1220 disposed on the upper surface of the first semiconductor substrate 1210 may include a first insulating layer 1221 and a first wiring layer 1225 disposed in the first insulating layer 1221. The first wiring layer 1225 may be connected to the first semiconductor device to form a first pixel circuit. The first wiring layer 1225 may include a plurality of wiring lines 1222 located at multiple levels in the first insulating layer 1221 and wiring vias 1223 connected to the plurality of wiring lines 1222. For example, the first wiring layer 1225 may include copper or a copper alloy.

[0226] The second semiconductor chip 1300 may include a second wiring structure 1320 disposed on the first wiring structure 1220 and having a capacitor 1380, and a second semiconductor substrate 1310 disposed on the second wiring structure 1320. According to an embodiment of the present invention, a second pixel circuit may be formed on the second semiconductor chip 1300.

[0227] A second semiconductor chip 1300 may be disposed on the first semiconductor chip 1200. The first and second semiconductor chips may be bonded such that the first and second wiring structures 1220 and 1320 face each other.

[0228] 8B may be disposed on the upper surface of the second semiconductor substrate 1310. The second semiconductor element 1350 may include a part of the element constituting the second pixel circuit, and may include a transistor having a gate electrode 1352, a gate insulating film 1351, and source / drain regions 1355a and 1355b.

[0229] Similar to the first wiring structure 1220, the second wiring structure 1320 may include a second insulating layer 1321 and a second wiring layer 1325 disposed in the second insulating layer 1321. The second wiring layer 1325 may include a plurality of wiring lines 1322 and wiring vias 1223.

[0230] According to an embodiment of the present invention, the second photodiode PD2 formed inside the first semiconductor substrate 1210 may be connected to the second pixel circuit formed on the second semiconductor chip 1300 via the first metal pad 1225P.

[0231] The first wiring structure 1220 may include a first bonding insulating layer 1221B disposed on the uppermost part of the first wiring structure 1220 and a first metal pad 1225P disposed in the first bonding insulating layer 1221B and connected to the first wiring layer 1225. Similarly, the second wiring structure 1320 may include a second bonding insulating layer 1321B disposed on the lowermost part of the second wiring structure 1320 and a second metal pad 1325P disposed in the second bonding insulating layer 1321B. The first metal pad 1225P may have an upper surface substantially planar with an upper surface of the first bonding insulating layer 1221B, and the second metal pad 1325P may have an upper surface substantially planar with an upper surface of the first bonding insulating layer 1221B.

[0232] The first and second metal pads 1225P and 1352P may be directly bonded to form a metal-to-metal bond, and the first and second bonding insulating layers 1221B and 1321B may be directly bonded to form a dielectric-to-dielectric bond, which may also be called hybrid bonding.

[0233] The first wiring layer 1225 and the second redistribution layer 1325 may be electrically connected by bonding between the first and second metal pads 1225P and 1352P. The bonding between the first and second metal pads 1225P and 1352P may electrically connect not only the peripheral region PERI but also the main region MAIN. Figure 30 illustrates a first path P1 (P1a, P1b) for electrically connecting the second pixel circuit and the second photodiode PD2.

[0234] Meanwhile, a first through via 1510 may be further included in the peripheral region PERI to electrically connect the first semiconductor chip 1200 and the second semiconductor chip 1300.

[0235] The third semiconductor chip 1400 may include a third wiring structure 1420 disposed on the second semiconductor substrate 1310, and a third semiconductor substrate 1410 on which a logic element is implemented and disposed on the third wiring structure 1420. The third semiconductor chip 1400 may include a logic circuit.

[0236] Similar to the first and second wiring structures 1210 and 1320, the third wiring structure 1420 may include a third insulating layer 1421 and a third wiring layer 1425 disposed in the third insulating layer 1421. The third wiring layer 1425 may include a plurality of wiring lines 1422 and wiring vias 1423.

[0237] A third semiconductor device 1450 may be formed in an active region defined by an isolation pattern ISO on the bottom surface of the third semiconductor substrate 1410. The third semiconductor device 1450 may include logic circuits, such as the first logic circuit 20 and the second logic circuit 30 described with reference to FIG.

[0238] In this embodiment, the third semiconductor chip 1400 is illustrated as being electrically connected to the first and second semiconductor chips 1200 and 1300 by the second through via 1520, but similar to the connection between the first and second semiconductor chips 1200 and 1300, the connection between the second and third semiconductor chips 1300 and 1400 can also be achieved by bonding using metal pads, similar to the connection between the second and third semiconductor chips 1300 and 1400, instead of or in parallel with the second through via 1520.

[0239] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the scope of the appended claims. Therefore, various substitutions, modifications, and changes can be made by a person skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and these also fall within the scope of the present invention.

Claims

1. An image sensor, a first region arranged along a first direction and a second direction that are parallel to an upper surface of the substrate and intersect with each other; a second region arranged along the first direction and the second direction; a first photodiode in the first region; a second photodiode in the second region; an image sensing pixel circuit that generates a first electrical signal based on the charge generated by the first photodiode; an event sensing pixel circuit that generates a second electrical signal based on a change in the amount of charge generated by the second photodiode; a logic circuit electrically connected to the image sensing pixel; the first region is disposed in a third direction relative to the second region; The third direction is parallel to the top surface of the substrate and is different from the first and second directions.

2. The image sensor according to claim 1 , wherein a light receiving area of ​​the first photodiode is larger than a light receiving area of ​​the second photodiode.

3. the first region has an octagonal shape including two first sides extending in the first direction, two second sides extending in the second direction, and four third sides; The image sensor of claim 1 , wherein the second region has a rectangular shape.

4. the first and second photodiodes are disposed on a first chip; The image sensor of claim 1 , wherein the event sensing pixel circuit is disposed on a second chip stacked on the first chip.

5. the logic circuit is disposed on a third chip stacked on the second chip; The image sensor according to claim 4 , wherein the second chip is disposed between the first chip and the third chip.

6. The image sensor includes: a third photodiode in the first region; further comprising a floating diffusion node; The image sensor of claim 5 , wherein the first photodiode and the third photodiode share the floating diffusion node.

7. The image sensor includes: a floating diffusion node; a reset transistor that resets the voltage of the floating diffusion node; a transfer transistor that transfers the charge generated in the first photodiode to the floating diffusion node, The image sensor of claim 5 , wherein the floating diffusion node, the reset transistor, and the transfer transistor are disposed on the first chip.

8. 8. The image sensor of claim 7, wherein the first chip is connected to the second chip by Cu-Cu bonding.

9. The image sensor includes: a third photodiode in the first region; The image sensor of claim 8 , further comprising a microlens disposed over the first and third photodiodes.

10. The image sensor of claim 1 , wherein the first chip is coupled to the third chip through a through via.

11. The image sensor includes: a third region adjacent to the first region in the first direction; a third diode in the third region, The image sensor of claim 10 , wherein a light receiving area of ​​the third photodiode is larger than a light receiving area of ​​the second photodiode.

12. The image sensor includes: a first microlens on the first photodiode; a second microlens over the second photodiode; The image sensor of claim 11 , wherein a width of the first microlens in the second direction is greater than a width of the second microlens in the second direction.

13. The image sensor includes: a fourth photodiode in the first region; a fifth photodiode in the first region; The image sensor of claim 9 , wherein the microlenses are disposed over the first, third, fourth, and fifth photodiodes.

14. The image sensor includes: Further comprising a deep trench isolation (DTI) between the first region and the second region, The image sensor of claim 11 , wherein the DTI contacts a top surface of the substrate.

15. the DTI contacts the underside of the substrate; The image sensor of claim 14 , wherein the bottom surface of the substrate faces the top surface of the substrate.

16. The image sensor of claim 8 , wherein the transfer transistor extends into the substrate.

17. An image sensor, A substrate; a first photodiode in a first region of the substrate; a second photodiode in a second region of the substrate; a third photodiode in a third region of the substrate; a fourth photodiode in a fourth region of the substrate; a transfer transistor; A reset transistor; an event sensing pixel circuit that generates an electrical signal based on a change in the amount of charge generated by the second photodiode; the third region is disposed adjacent to the first region in the first direction of a plane, the fourth region is disposed adjacent to the first region in a second direction perpendicular to the first direction of the plane, the second region is disposed in a third direction different from the first region and the first and second directions of the plane, the first, third, and fourth photodiodes each have a light receiving area larger than the light receiving area of ​​the second photodiode; The image sensor, wherein the transfer transistor and the reset transistor are shared by the first, third, and fourth photodiodes.

18. the first to fourth photodiodes, the transfer transistor, and the reset transistor are disposed on a first chip; the event sensing pixel circuit is disposed on a second chip; the first chip is stacked on the second chip; 18. The image sensor of claim 17, wherein the first chip is connected to the second chip by Cu-Cu bonding.

19. The image sensor includes: a first microlens on the first photodiode; a second microlens over the second photodiode; The image sensor of claim 17 , wherein a width of the first microlens in the first direction is greater than a width of the second microlens in the first direction.

20. An image sensor, a substrate including a first surface and a second surface opposite to the first surface; a first photodiode in a first region of the substrate; a second photodiode in a second region of the substrate; a first microlens on the first photodiode; a second microlens on the second photodiode; an image sensing pixel circuit that generates a first electrical signal based on the charge generated by the first photodiode; an event sensing pixel circuit that generates a second electrical signal based on a change in the amount of charge generated by the second photodiode; a deep trench isolation (DTI) between the first region and the second region; and a circuit electrically coupled to the image sensing pixel circuit; the first region is adjacent to the second region; the DTI is in contact with the first surface and the second surface; An image sensor, wherein a width of the first microlens in a first direction in a plane is greater than a width of the second microlens in the first direction.

Images