Semiconductor memory device and method for forming the semiconductor memory device

Abstract

To provide a semiconductor memory device and a method for forming the semiconductor memory device.SOLUTION: Aspects of the present disclosure provide a semiconductor device comprising a first die. The first die comprises a first layer stack comprising a semiconductor layer on a backside of the first die. A second layer stack comprising gate-gate layers and a first insulating layer alternately stacked on a front side of the first die is formed. The front side is located on an opposite side of the back side. A vertical structure part comprises a first portion disposed in the first layer stack and a second portion extending through the second layer stack. The first portion has a different dimension than the second portion in a direction parallel to a major surface of the first die.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] This application describes embodiments generally relating to semiconductor memory devices and methods for forming semiconductor memory devices. [Background technology]

[0002] Semiconductor manufacturers have deployed vertical device technologies, such as three-dimensional (3D) NAND flash memory technology, to achieve ever-increasing data storage densities without the need for smaller memory cells. In some examples, a 3D NAND memory device includes a core region (also known as an array region) and a staircase region. The core region includes an array of channel structures extending through a stack of gate layers and insulating layers. The gate layers and channel structures can form vertical NAND memory cell strings. The staircase region is used to form connections for controlling the vertical NAND memory cell strings. Summary of the Invention [Means for solving the problem]

[0003] Aspects of the present disclosure provide semiconductor devices and methods of forming semiconductor devices.

[0004] According to a first aspect, a semiconductor device is provided. The semiconductor device includes a first die. The first die includes a first layer stack including semiconductor layers on a backside of the first die. A second layer stack including alternating gate layers and first insulating layers is formed on a front side of the first die. The front side is located opposite the backside. A vertical structure includes a first portion disposed in the first layer stack and a second portion extending through the second layer stack. The first portion has a different dimension from the second portion in a direction parallel to a major surface of the first die.

[0005] In some embodiments, the vertical structure comprises a channel structure in the core region. The channel structure comprises a channel layer extending through the first portion and the second portion. In some embodiments, the second portion comprises a tunnel layer surrounding the channel layer, a charge trapping layer surrounding the tunnel layer, and a barrier layer surrounding the charge trapping layer. In some embodiments, the channel layer is in contact with the semiconductor layer in the first portion.

[0006] In some embodiments, the first lateral perimeter of the first portion extends from the second perimeter of the second portion by 10 to 100 nm.

[0007] In some embodiments, the first portion has a larger dimension than the second portion in a direction parallel to a major surface of the first die.

[0008] In some embodiments, the semiconductor device further comprises a first conductive structure disposed on a backside of the first die, the first conductive structure being conductively connected to the semiconductor layer, and a second conductive structure disposed on the backside of the first die, the second conductive structure being conductively connected to a contact structure disposed on the front side of the first die.

[0009] In some embodiments, the vertical structures comprise at least one of gate line slit (GLS) structures or dummy channel structures.

[0010] In some embodiments, the semiconductor device further comprises memory cells on a front side of the first die, and a second die bonded face-to-face to the first die, the second die comprising a substrate and peripheral circuitry formed on the front side of the substrate for the memory cells.

[0011] According to a second aspect of the present disclosure, a memory system includes a semiconductor device having a die. The die includes a first layer stack including a semiconductor layer on a backside of the die. A second layer stack includes alternating gate layers and insulating layers on a front side of the die. The front side is located opposite the backside. A vertical structure includes a first portion disposed in the first layer stack and a second portion extending through the second layer stack. The first portion has a different dimension from the second portion in a direction parallel to a major surface of the die. The memory system also includes a controller configured to control operation of the semiconductor device. The controller is connected to the semiconductor device.

[0012] According to a third aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device. The method includes forming an etch stop structure in an initial first layer stack comprising a sacrificial semiconductor layer on a first substrate. The etch stop structure extends into the sacrificial semiconductor layer. A second layer stack is formed on the initial first layer stack. Holes are formed extending through the second layer stack. The holes expose respective etch stop structures having dimensions different from the holes in a direction parallel to a major surface of the first substrate. Each etch stop structure is removed through the holes such that the holes extend into the sacrificial semiconductor layer. Vertical structures are formed within the holes. In some embodiments, the first portion has a dimension larger than the second portion in a direction parallel to the major surface of the first substrate.

[0013] In some embodiments, the etch stop structure has different etching characteristics than the second layer stack.The etch stop structure has different etching characteristics than the sacrificial semiconductor layer.

[0014] In some embodiments, the vertical structure comprises a channel structure, and forming the vertical structure includes forming a second insulating layer on the exposed surface along the channel hole, and the channel layer is formed along the second insulating layer.

[0015] In some embodiments, the first substrate and sacrificial semiconductor layer of the first die are removed from the backside of the first die such that a channel structure is exposed from the backside of the first die. The exposed portion of the second insulating layer is removed such that the channel layer is exposed from the backside of the first die. A semiconductor layer is formed covering the channel structure from the backside of the first die. A first conductive structure is formed that is conductively connected to the semiconductor layer. A contact structure is formed from the front side of the first die. The front side is located opposite the backside. A second conductive structure is formed from the backside of the first die. The second conductive structure is conductively connected to the contact structure.

[0016] In some embodiments, each channel structure is formed using a respective etch stop structure.

[0017] In some embodiments, the second layer stack comprises a sacrificial gate layer and a first insulating layer alternately stacked on top of the initial first layer stack. A dummy channel structure is formed in the staircase region. A gate line (GL) cut trench is formed extending through the second layer stack. The sacrificial gate layer is replaced with a gate layer via the GL cut trench. A gate line slit (GLS) structure is formed in the GL cut trench.

[0018] In some embodiments, forming the vertical structures includes forming at least one of a dummy channel structure or a GLS structure.

[0019] In some embodiments, the first substrate is included in the first die, the peripheral circuitry is formed on the front side of the second die, and the first die and the second die are bonded face-to-face.

[0020] According to a fourth aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device. The method includes forming a first layer stack including semiconductor layers on a backside of a first die. A second layer stack including alternating gate layers and first insulating layers is formed on a front side of the first die. The front side is located opposite the backside. A channel structure is formed including a first portion disposed in the first layer stack and a second portion extending through the second layer stack. The first portion has a larger dimension than the second portion in a direction parallel to a major surface of the first die.

[0021] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to common practice in the industry, various features have not been drawn to scale. In fact, the dimensions of various features may be expanded or reduced for clarity of presentation. [Brief explanation of the drawings]

[0022] [Figure 1A] 1 is a vertical cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 1B] FIG. 1B is an enlarged view of box 100B in FIG. 1A, according to an exemplary embodiment of the present disclosure. [Figure 1C] FIG. 1B illustrates a layout design of the semiconductor device in FIG. 1A according to an exemplary embodiment of the present disclosure. [Figure 2] 1 is a flow diagram of an example process for manufacturing an example semiconductor device, according to an example embodiment of the present disclosure. [Figure 3A] 1A-1C are cross-sectional views of a semiconductor device at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure. [Figure 3B] 1A-1C are cross-sectional views of a semiconductor device at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure. [Figure 3C] 1A-1C are cross-sectional views of a semiconductor device at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure. [Figure 3D]1A-1C are cross-sectional views of a semiconductor device at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure. [Figure 3E] 1A-1C are cross-sectional views of a semiconductor device at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure. [Figure 3F] 1A-1C are cross-sectional views of a semiconductor device at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure. [Figure 3G] 1A-1C are cross-sectional views of a semiconductor device at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure. [Figure 3H] 1A-1C are cross-sectional views of a semiconductor device at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure. [Figure 3I] 1A-1C are cross-sectional views of a semiconductor device at various intermediate manufacturing steps according to exemplary embodiments of the present disclosure. [Figure 4] FIG. 1 is a block diagram of a memory system device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0023] The following disclosure presents numerous different embodiments or examples for implementing various features of the presented subject matter. Specific examples of components and configurations are described below to facilitate understanding of the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, when a first feature is formed over or on a second feature in the following description, this may include embodiments in which the first and second features may be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, where the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purposes of clarity and does not in itself indicate a relationship between the various embodiments and / or components discussed.

[0024] Additionally, spatially relative terms such as "below," "lower," "lower," "upper," and "above" may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations) and the spatially relative terms used herein may be similarly interpreted accordingly.

[0025] According to some aspects of the present disclosure, vertical features, such as channel features in a three-dimensional (3D) NAND flash memory device, are formed in holes etched into a semiconductor layer by front-side processing. This etching process for forming the holes in the semiconductor layer can affect the depth uniformity of the holes into the semiconductor layer. Poor hole depth uniformity results in poor edge profile uniformity of the vertical features in the semiconductor layer. Some semiconductor technologies utilize back-side processing to form features, such as connection features, on the backside of a semiconductor device. In some examples, a semiconductor layer is removed by back-side processing, and further back-side processing can be performed. Poor edge profile uniformity of the vertical features can make back-side processing difficult.

[0026] The present disclosure provides methods for forming vertical features with well-controlled profiles, including sidewall and edge profiles. The techniques herein include forming an etch-stop structure below the additional vertical feature. In some examples, the etch-stop structure has a larger horizontal dimension than the additional vertical feature so that a hole (for the additional vertical feature) with some tolerance for alignment errors can be formed on top of the etch-stop structure. The etch-stop structure can include a material with an etch selectivity that allows the hole etching process to stop at the etch-stop structure without significant gouging or uniformity problems. The etch-stop structure can then be removed through the hole, and further processing, such as to form a vertical feature within the hole, can be performed.

[0027] According to some aspects of the present disclosure, multiple etch stop structures may be formed below various additional vertical structures. In some embodiments, the etch stop structures are formed below the additional channel structures to achieve a controlled etch profile for the corresponding channel holes. In some embodiments, the etch stop structures are formed below the additional gate line slit (GLS) structures to achieve a controlled etch profile for the corresponding gate line (GL) cut trenches. In some embodiments, the etch stop structures may be formed below the dummy channel structures to achieve a controlled etch profile for the corresponding dummy channel holes.

[0028] According to some aspects of the present disclosure, the pattern of etch stop features can be included in an alignment mask, which is the first mask to form alignment features that can be used for alignment by subsequent masks, thus eliminating the need for redundant masks.

[0029] FIG. 1A shows a vertical cross-sectional view of a semiconductor device 100A according to an exemplary embodiment of the present disclosure. FIG. 1B shows an enlarged view of box 100B in FIG. 1A according to an exemplary embodiment of the present disclosure. FIG. 1C shows several layers in a layout design 100C for the semiconductor device 100A in FIG. 1A according to an exemplary embodiment of the present disclosure. It should be noted that, for illustrative purposes, a channel structure is used as an example of a vertical structure.

[0030] As shown in FIGS. 1A-1B, the semiconductor device 100A includes a first die D1. The first die D1 includes a first layer stack 110 including a semiconductor layer 111 on a backside of the first die D1. Furthermore, the first die D1 includes a second layer stack 120 including alternating gate layers 123 and first insulating layers 121 on a front side of the first die D1. The front side is located opposite the backside. The first die D1 further includes a channel structure 130 disposed in the core region 101 (also referred to as the array region). The channel structure 130 may include a first portion 131 disposed in the first layer stack 110 and a second portion 132 extending through the second layer stack 120. The first portion 131 of the channel structure 130 has a larger dimension than the second portion 132 of the channel structure 130 in a direction parallel to a major surface (e.g., the XY plane) of the first die D1. For example, the first portion 131 can be wider than the second portion 132 in the X direction in the XZ cross section as shown in FIG. 1B . Furthermore, the first portion 131 may be wider than the second portion 132 in any direction within the XY plane such that the first portion 131 extends horizontally beyond the second portion 132. For example, the first lateral periphery of the first portion 131 may extend 10 to 100 nm from the second periphery of the second portion 132.

[0031] In some embodiments, the second portion 132 of the channel structure 130 comprises a channel layer 135 (e.g., polysilicon) and a second insulating layer 134 surrounding the channel layer 135. For example, the second insulating layer 134 may comprise a tunnel layer 134i (e.g., silicon oxide) surrounding the channel layer 135, a charge trapping layer 134ii (e.g., silicon nitride) surrounding the tunnel layer 134i, and a barrier layer 134iii (e.g., silicon oxide) surrounding the charge trapping layer 134ii.

[0032] In some embodiments, the first portion 131 of the channel structure 130 comprises a channel layer 135, which is surrounded by a semiconductor layer 111 (e.g., polysilicon) and covered by the semiconductor layer 111 from the backside of the first die D1. As a result, the first portion 131 is in contact with and conductively connected to the semiconductor layer 111. In some embodiments, the semiconductor layer 111 is configured to function as a source connection layer connecting the channel layer 135 to an array common source (ACS). In one example, the semiconductor layer 111 comprises a bulk portion 112 and a liner portion 113 (e.g., a conformal portion). The liner portion 113 is in contact with the channel layer 135 and may have a different doping profile than the bulk portion 112. In another example, the semiconductor layer 111 comprises only the bulk portion 112 in contact with the channel layer 135.

[0033] In some embodiments, the channel structure 130 may further comprise a dielectric layer 136 located within and surrounded by the channel layer 135. The dielectric layer 136 may comprise one or more voids 137.

[0034] In some embodiments, the first portion 131 of the channel structure 130 has a lateral dimension of 80 to 200 nm in a direction parallel to the major surface of the first die D1 (e.g., the XY plane) and a thickness of 10 to 500 nm in a direction perpendicular to the major surface of the first die D1 (e.g., the Z direction). The second portion 132 may have a lateral dimension of 60 to 150 nm in a direction parallel to the major surface of the first die. Furthermore, the first portion 131 and the second portion 132 may have various shapes. For example, the first portion 131 and the second portion 132 may have a circular, elliptical, or polygonal shape in the XY plane, and may have a columnar shape in the XZ and YZ planes.

[0035] 1C shows a layout pattern 131′ corresponding to a first portion 131 of the channel structure 130 and a layout pattern 132′ corresponding to a second portion 132 of the channel structure 130. In some examples, the lateral periphery of the layout pattern 131′ extends from the lateral periphery of the layout pattern 132′ by a layout size corresponding to an actual product size (e.g., semiconductor device 100A) of 10 nm to 100 nm.

[0036] In some embodiments, the second stack 120 of the gate layer 123 and the first insulating layer 121 and the channel structure 130 may form a transistor stack, such as an array of vertical memory cell strings. In some embodiments, the transistor stack may comprise memory cells stacked in the Z direction on the front side of the first die D1. In some embodiments, the transistor stack may further comprise select transistors, such as one or more bottom select transistors and one or more top select transistors. In some embodiments, the transistor stack may further comprise one or more dummy select transistors.

[0037] 1A-1B, the first die D1 may further include a plurality of gate line slit (GLS) structures 140 (also referred to as gate line cut structures in some examples) extending through the second layer stack 120. FIG. 1C shows a layout pattern 140′ corresponding to the GLS structures 140. The GLS structures 140 may be used to facilitate sacrificial layer replacement with the gate layer 123 in a gate-last process. In one embodiment (not shown), the GLS structures 140 may include a semiconductor material (not shown) and may be configured to function as an ACS. The ACS is conductively connected to the channel layer 135 via a source connection layer, such as the semiconductor layer 111.

[0038] In another embodiment, such as that shown in FIG. 1A , the GLS structures 140 include one or more dielectric materials. In some examples, the GLS structures 140 extend through the second layer stack 120, and the GLS structures 140 are configured to partition the vertical memory cell strings (corresponding to the channel structures 130) into separate blocks. In some examples, the vertical memory cell strings are configured to be erased in blocks. Additionally, the amount and configuration of the channel structures 130 between the GLS structures 140 can vary.

[0039] 1A , the GLS structure 140 is shown with a continuous sidewall profile. In another example (not shown), the GLS structure 140 may have a configuration similar to the channel structure 130. That is, the GLS structure 140 may include a first portion disposed within the first layer stack 110 and a second portion extending through the second layer stack 120. The first portion of the GLS structure 140 may have a larger dimension in a direction parallel to the major surface of the first die D1 than the second portion of the GLS structure 140. Thus, the sidewall of the first portion has a larger perimeter than the second portion.

[0040] In some embodiments, the first die D1 includes a staircase region 102 in which pairs of gate layers 123 and first insulating layers 121 are configured in the form of staircase steps, e.g., one pair of first insulating layer 121 and gate layer 123 is present on each staircase step. Accordingly, gate contact structures (not shown) may be disposed on the staircase steps and connected to each gate layer 123. The gate contact structures are used to connect drive circuits to each gate layer 123 for controlling stacked memory cells and select gates.

[0041] In some embodiments, the first die D1 further includes a plurality of dummy channel structures 150. These dummy channel structures 150 can prevent the second layer stack 120 from collapsing during replacement of the sacrificial layer with the gate layer 123 in a gate-last process. The dummy channel structures 150 can include one or more dielectric materials. In one example, an array of the dummy channel structures 150 can be disposed in the staircase region 102 between the GLS structures 140. In another example, one or more dummy channel structures 150 can also be disposed in the core region 101.

[0042] 1A , the dummy channel structure 150 has a continuous sidewall. For example, the dummy channel structure 150 has a rectangular or trapezoidal shape in the XZ plane. In another example (not shown), the dummy channel structure 150 may have a configuration similar to the channel structure 130. That is, the dummy channel structure 150 may include a first portion disposed in the first layer stack 110 and a second portion extending through the second layer stack 120. The first portion of the dummy channel structure 150 may have a larger dimension in a direction parallel to the major surface of the first die D1 than the second portion of the dummy channel structure 150. Thus, the sidewall of the first portion has a larger perimeter than the second portion.

[0043] In some embodiments, the first die D1 may further include at least one contact structure 161 extending from the front side of the first die D1 to the back side of the first die D1. In one example, the at least one contact structure 161 extends through the capping layer 125, the third insulating layer 163, and the etch stop layer 115 and extends into the semiconductor layer 111. In another example (not shown), the contact structure 161 may extend through the first insulating layer 121 and the third insulating layer 163 and stop at the etch stop layer 115.

[0044] In some embodiments, the first die D1 further includes a spacer layer 165 (e.g., silicon oxide) covering the semiconductor layer 111 from the backside of the first die D1. A first conductive structure 167a is disposed on the backside of the spacer layer 165, and the first conductive structure 167a is conductively connected to the semiconductor layer 111 through an opening in the spacer layer 165. Furthermore, a second conductive structure 167b is disposed on the backside of the first die D1, and the second conductive structure 167b is conductively connected to the contact structure 161 through a contact called a through-silicon contact. In one example, the through-silicon contact is formed in the opening in the semiconductor layer 111. The opening in the semiconductor layer 111 may be lined with the spacer layer 165 on its sidewalls. Although not shown, it should be understood that the first conductive structure 167a and the second conductive structure 167b may be conductively connected to an external circuit.

[0045] As described above, the memory cells may be vertically stacked on the front side of the first die D1. In some embodiments, a second die D2 (not shown) may be bonded face-to-face to the first die D1 (the side having the majority of the circuitry is the face, and the side opposite the face is the backside). In some examples, the second die D2 includes a substrate and peripheral circuitry (e.g., address decoders, driver circuits, sense amplifiers, etc.) for the memory cells formed on the front side of the substrate. It should be noted that the first die D1 initially includes a substrate on which the memory cells are formed, and in some examples, the first conductive structure 167a and the second conductive structure 167b are formed after the substrate of the first die D1 is removed.

[0046] In general, the peripheral circuitry of the second die D2 can connect the memory cells to external circuits. In some embodiments, the contact structures 161 are conductively connected to the peripheral circuitry of the second die D2. As a result, the peripheral circuitry can receive commands from the external circuitry, send control signals to the memory cells, receive data from the memory cells, and output data to the external circuitry via the contact structures 161 and the second conductive structures 167b.

[0047] In some embodiments, semiconductor device 100A may include multiple array dies (e.g., a first die D1) and a CMOS die (e.g., a second die D2). The multiple array dies and CMOS dies may be stacked and bonded together. Each array die is coupled to a CMOS die, and the CMOS die may drive the array dies individually or together in a similar manner. Furthermore, in some embodiments, semiconductor device 100A includes at least a first wafer and a second wafer bonded face-to-face. The first die D1 is disposed on the first wafer with other array dies, such as D1, and the second die D2 is disposed on the second wafer with other CMOS dies, such as D2. The first wafer and the second wafer are bonded together such that the array dies on the first wafer are bonded to corresponding CMOS dies on the second wafer.

[0048] FIG. 2 shows a flow chart of a process 200 for fabricating an example semiconductor device, such as semiconductor device 100A, according to an exemplary embodiment of the present disclosure. Process 200 begins in step S210, where an etch-stop structure is formed in an initial first layer stack comprising a sacrificial semiconductor layer on a first substrate of a first die. The etch-stop structure extends into the sacrificial semiconductor layer. In step S220, a second layer stack is formed. The second layer stack comprises a sacrificial gate layer and a first insulating layer alternately stacked on the initial first layer stack. In step S230, holes (e.g., channel holes) are formed that extend through the second layer stack and stop at the etch-stop structure. The holes expose respective etch-stop structures having dimensions larger than the holes in a direction parallel to the major surface of the first die. In step S240, each etch-stop structure is removed through the holes so that the holes extend into the sacrificial semiconductor layer. In step S250, vertical structures (e.g., channel structures 130) are formed in these holes. Note that additional steps may be performed before, during, and after this process 200, and that some of the steps described may be substituted, eliminated, or performed in a different order for other embodiments of process 200.

[0049] In some embodiments, the initial first layer stack can be replaced with a first layer stack (e.g., first layer stack 110) comprising, for example, semiconductor layer 111, for example, by processing the backside of semiconductor device 100A.

[0050] 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, and 3I are cross-sectional views of a semiconductor device 300 at various intermediate manufacturing stages, according to exemplary embodiments of the present disclosure. In some embodiments, the semiconductor device 300 may ultimately become the semiconductor device 100A in FIGS. 1A-1B. It should be noted that, for illustrative purposes, a channel structure is used as an example of a vertical structure.

[0051] As shown in FIG. 3A , the semiconductor device 300 includes a first die D3 having a first substrate 371. An oxide layer 373 may be disposed on the first substrate 371. The first die D3 includes an initial first layer stack 310 including a sacrificial semiconductor layer 375 and an etch stop layer 315. The etch stop layer 315 may be sandwiched between an oxide layer 377 and an oxide layer 379. In some embodiments, an etch stop structure 381 is formed in the initial first layer stack 310 and extends into the sacrificial semiconductor layer 375. In the example of FIG. 1A , the etch stop structure 381 is formed in the core region 301. For example, the etch stop structure 381 may be formed by forming an opening in the initial first layer stack 310 based on a first mask having a pattern corresponding to the layout pattern 131′. An etch stop material, such as tungsten, may then be deposited to fill the opening, and excess etch stop material may be removed, such as by chemical-mechanical polishing. As will be discussed below, etch stop structures 381 may also be formed in other regions, such as, for example, staircase regions.

[0052] 1A 。 Note that in some examples, the first die D3 may ultimately become the first die D1 of FIG. 1A . Thus, the initial first layer stack 310 may ultimately become the first layer stack 110. The etch stop layer 315 may correspond to the etch stop layer 115. The core region 301 may correspond to the core region 101. Similarly, the first die D3 may have a front side and a back side (the side having the majority of the circuitry is the face, and the side opposite the front side is the back side).

[0053] 3B , a second layer stack 320 is formed on the initial first layer stack 310. The second layer stack 320 may include first insulating layers 321 and sacrificial gate layers 322 alternately stacked in the Z direction. A capping layer 325 may further be formed on the second layer stack 320. Channel holes 383 may then be formed by etching through the second layer stack 320. In some examples, the channel holes 383 are formed based on a second mask having a pattern corresponding to the layout pattern 132′. Each channel hole 383 may expose a respective etch stop structure 381 having a dimension larger than that of the corresponding channel hole 383 in a direction parallel to a major surface (e.g., the XY plane) of the first die D3. In this example, the etch stop structure 381 may extend horizontally beyond the periphery of each channel hole 383.

[0054] In some embodiments, the etch stop structure 381 has a lateral dimension of 80 to 200 nm in a direction parallel to the major surface of the first die D3 (e.g., the XY plane) and a thickness of 10 to 500 nm in a direction perpendicular to the major surface of the first die D3 (e.g., the Z direction). Each channel hole 383 has a lateral dimension of 60 to 150 nm in a direction horizontal to the major surface of the first die D3.

[0055] In some embodiments, the etch stop structure 381 is configured to have different etching characteristics than the sacrificial semiconductor layer 375 and the second layer stack 320 such that the etching process for forming the channel hole 383 can be stopped at the etch stop structure 381. In non-limiting examples, the etch stop structure 381 comprises tungsten. The first insulating layer 321 comprises silicon oxide. The sacrificial gate layer 322 comprises silicon nitride. The etch stop layer 315 comprises polysilicon. The sacrificial semiconductor layer 375 comprises polysilicon.

[0056] Additionally, in some embodiments, the second layer stack 320 may ultimately become the second layer stack 120. The first insulating layer 321 may correspond to the first insulating layer 121. The capping layer 325 may correspond to the capping layer 125.

[0057] 3C, the etch stop structure 381 is removed, for example, by dry etching. As a result, the channel hole 383 extends into the initial first layer stack 310, specifically into the sacrificial semiconductor layer 375. The channel hole 383 therefore has a width that varies in height (e.g., in the Z direction). More importantly, the channel hole 383 can have a uniform edge profile at the bottom of the hole.

[0058] 3D , the channel structure 330 is formed in the channel hole 383. For example, a second insulating layer 334 of the channel structure 330 may be formed on the exposed surface along the channel hole 383. The second insulating layer 334 may include a tunneling layer, a charge trapping layer, and a barrier layer. Then, a channel layer 335 of the channel structure 330 may be formed along the second insulating layer 334, and a dielectric layer 336 of the channel structure 330 may be formed surrounded by the channel layer 335. The dielectric layer 336 may include one or more voids 337.

[0059] As shown, the channel structure 330 comprises a first portion 331 disposed within the initial first layer stack 310 and a second portion 332 extending through the second layer stack 320. The first portion 331 of the channel structure 330 has a larger dimension than the second portion 332 of the channel structure 330 in a direction parallel to a major surface (e.g., the XY plane) of the first die D3.

[0060] In some embodiments, channel structure 330 may ultimately become channel structure 130. Thus, first portion 331 may ultimately become first portion 131. Second portion 332 may correspond to second portion 132. Channel layer 335 may correspond to channel layer 135. Second insulating layer 334 may correspond to second insulating layer 134. Dielectric layer 336 may correspond to dielectric layer 136. One or more voids 337 may correspond to one or more voids 137.

[0061] In some embodiments, although not shown, the semiconductor device 300 may further include a third layer stack on the second layer stack 320. The third layer stack includes first insulating layers 121 and sacrificial gate layers 122 alternately stacked in the Z direction. Furthermore, channel holes may be formed by etching through the third stack, and are referred to as upper channel holes (UCHs). Accordingly, the channel holes 383 may be referred to as lower channel holes (LCHs). Each UCH may be aligned with a respective LCH such that a respective channel structure extending through the second stack 230 and the third stack may be formed. Each channel structure may include a first portion 331 of the channel structure 330 and another portion corresponding to the second portion 332 of the channel structure 330. In one embodiment, each channel structure may be formed simultaneously in the UCH and the LCH. In another embodiment, a portion of each channel structure may be first formed in the LCH, followed by forming a third stack, which may be etched to form the UCH, followed by forming another portion of each channel structure in the UCH.

[0062] 3E, a staircase region 302 is formed in which pairs of first insulating layers 321 and sacrificial gate layers 322 are arranged in the form of staircase steps, e.g., one pair of first insulating layer 321 and sacrificial gate layer 322 is present on each step of the staircase. The staircase region 302 may be covered by a third insulating layer 363. A plurality of dummy channel structures 350 may be formed, for example, in the staircase region 302. One or more gate line (GL) cut trenches 385 may be formed, for example, in the core region 301. The one or more GL cut trenches 385 may be used to replace the sacrificial gate layer 322 with a gate layer in a later step, and the plurality of dummy channel structures 350 may prevent the second layer stack 320 from collapsing during such a later replacement step.

[0063] In some embodiments, the multiple dummy channel structures 350 are formed by etching dummy channel holes (DCHs, not shown) through the second layer stack 320 and filling the DCHs with one or more dielectric materials. In some embodiments, etch-stop structures 381 may be formed in the staircase region 302 and used to form the dummy channel structures 350. Each DCH may expose a respective etch-stop structure 381 having a dimension larger than the corresponding DCH in a direction parallel to a major surface (e.g., the XY plane) of the first die D3. For example, the etch-stop structure 381 may extend horizontally beyond the periphery of each DCH. As a result, the dummy channel structures 350 may have a configuration similar to that of the channel structure 330.

[0064] In some embodiments, the etch stop structures 381 may be further formed and used to form GL cut trenches 385. Each GL cut trench 385 may expose a respective etch stop structure 381 having a dimension larger than that of the corresponding GL cut trench 385 in a direction parallel to a major surface (e.g., the XY plane) of the first die D3. For example, the etch stop structure 381 may extend horizontally beyond the periphery of each GL cut trench 385. As a result, the GL cut trenches 385 (and subsequent gate line slit structures formed in the GL cut trenches 385) may have a configuration similar to that of the channel structure 330.

[0065] In some embodiments, the staircase region 302 may correspond to the staircase region 102. The dummy channel structure 350 may correspond to the dummy channel structure 150. The third insulating layer 363 may correspond to the third insulating layer 163.

[0066] 3F , the sacrificial gate layer 322 is replaced with the gate layer 323 via the GL-cut trench 385 by etching away the sacrificial gate layer 322 and forming the gate layer 323. Then, a gate line slit (GLS) structure 340 is formed in the GL-cut trench 385. Next, at least one contact structure 361 is formed, extending from the front side of the first die D3 to the back side of the first die D3. Although not shown, further gate contact structures may be formed on the steps of the staircase and connected to each gate layer 323. The gate contact structures may be used to connect drive circuits to each gate layer 323.

[0067] In some embodiments, gate layer 323 may correspond to gate layer 123. GLS structure 340 may correspond to GLS structure 140. At least one contact structure 361 may correspond to at least one contact structure 161. Similarly, second stack 320 of gate layer 323 and first insulating layer 321 and channel structure 330 may form a transistor stack, such as an array of vertical memory cell strings. In some embodiments, the transistor stack may comprise memory cells stacked in the Z direction.

[0068] Additionally, in some embodiments, a second die D4 (not shown) may be bonded face-to-face to the first die D3 (the side having the majority of the circuitry is the face, and the side opposite the face is the backside). The second die D4 corresponds to the second die D2. Thus, the second die D4 may include a second substrate and peripheral circuitry formed on the face side of the second substrate for the memory cells of the first die D3, which has been described in detail above and is omitted here for brevity.

[0069] 3G, the first substrate 371, the oxide layer 373, and the sacrificial semiconductor layer 375 are removed from the backside of the first die D3, thereby exposing the channel structure 330 from the backside of the first die D3. Specifically, the first substrate 371 may be removed by chemical mechanical polishing (CMP). The oxide layer 373 may be etched. The sacrificial semiconductor layer 375 may be selectively etched. As a result, the GLS structure 340 and the dummy channel structure 350 may also be exposed from the backside of the first die D1. In this example, the contact structure 361 is exposed. In another example, where the contact structure 361 extends through the third insulating layer 363 and stops at the etch stop layer 315, the contact structure 361 remains covered by the etch stop layer 315.

[0070] 3H, the exposed portion of the second insulating layer 334 is removed, thereby exposing the channel layer 335 from the backside of the first die D3. As a result, the channel structure 330 may become the channel structure 130. Specifically, the first portion 331 may become the first portion 131. This has been described in detail above and will be omitted here for brevity.

[0071] In some examples, second insulating layer 334 comprises a silicon oxide layer surrounded by a silicon nitride layer surrounded by another silicon oxide layer, and therefore, during an etching process to remove exposed portions of second insulating layer 334, oxide layer 377 may also be removed.

[0072] In FIG. 3I, a semiconductor layer 311 is formed covering the channel structure 330 from the backside of the first die D3. In some embodiments, the semiconductor layer 311 may correspond to the semiconductor layer 111. In one embodiment, the semiconductor layer 311 comprises a bulk portion 312 and a liner portion 313 (e.g., a conformal portion). The liner portion 313 may be formed on the channel layer 335 and may be doped by ion implantation. The bulk portion 312 may then be formed, for example, by chemical vapor deposition (CVD) and planarized by CMP. The bulk portion 312 may be doped in situ during CVD or by ion implantation after CVD. A post-annealing step, for example, laser annealing, may be performed to activate the dopants and / or repair crystal damage. In another embodiment, the semiconductor layer 311 comprises only the bulk portion 312 in contact with the channel layer 335. Therefore, the semiconductor layer 311 can be formed by a single deposition process before planarization, and may further undergo a doping process and an annealing process.

[0073] Furthermore, an opening 387 may be formed in the semiconductor layer 311 to expose the contact structure 361 from the backside of the first die D1. Although not shown, a spacer layer corresponding to the spacer layer 165 may be formed from the backside of the first die D3. A portion of this spacer layer is removed from the bottom of the opening 387, leaving the remaining portion of the spacer layer covering the sidewalls of the opening 387 and exposing the contact structure 361. Next, a conductive layer may be formed from the backside of the first die D3 and segmented to form individual conductive structures. In one example, a first conductive structure corresponding to the first conductive structure 167a is formed. This first conductive structure is conductively connected to the semiconductor layer 311 through the opening in the spacer layer. In another example, a second conductive structure corresponding to the second conductive structure 167b is formed. The second conductive structure is formed from the backside of the first die D3 and is conductively connected to the contact structure 361 through an opening 387 in the semiconductor layer 311. The second conductive structure is separated from the semiconductor layer 311 by a remaining portion of the spacer layer disposed on the sidewalls of the opening 387.

[0074] It is noted that the semiconductor device 100A may be suitably used in a memory system.

[0075] 4 shows a block diagram of a memory system device 400 according to an example embodiment of the present disclosure. Memory system device 400 includes one or more semiconductor memory devices, such as those shown by semiconductor memory devices 411, 412, 413, and 414, each configured similarly to semiconductor device 100A. In some examples, memory system device 400 is a solid-state drive (SSD).

[0076] Memory system device 400 may include other suitable components. For example, memory system device 400 may include an interface 401 and a master controller 402 coupled together, as shown in FIG. 4. Memory system device 400 may include a bus 420 coupling master controller 402 to semiconductor memory devices 411-414. Furthermore, master controller 402 is connected to each of semiconductor memory devices 411-414 by, for example, control lines 421, 422, 423, and 424, respectively.

[0077] The interface 401 is appropriately configured mechanically and electrically to connect between the memory system device 400 and a host device, and can be used to transfer data between the memory system device 400 and the host device.

[0078] The master controller 402 is configured to connect each of the semiconductor memory devices 411-414 to the interface 401 for data transfer. For example, the master controller 402 is configured to send enable / disable signals to the semiconductor memory devices 411-414, respectively, to activate / deactivate one or more of the semiconductor memory devices 411-414 for data transfer.

[0079] The master controller 402 is responsible for the completion of various commands within the memory system device 400. For example, the master controller 402 may perform bad block management, error checking and correction, garbage collection, and the like.

[0080] In some embodiments, the master controller 402 is implemented using a processor chip. In some examples, the master controller 402 is implemented using multiple microcontroller units (MCUs).

[0081] As used herein, "device" or "semiconductor device" generally refers to any suitable device, such as, for example, a memory circuit, a semiconductor chip (or die) having a memory circuit formed thereon, a semiconductor wafer having multiple semiconductor dies formed thereon, a semiconductor chip stack, and a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0082] As used herein, "substrate" or "target substrate" generally refers to an object to be processed by the present invention. The substrate may comprise any material portion or substrate of a device, particularly a semiconductor or other electronic device, or may be a base substrate structure, such as a semiconductor wafer, reticle, or layer that resides on or overlies a base substrate structure, such as a thin film. Thus, the substrate is not limited to any particular patterned or unpatterned base structure, underlayer, or overlying layer, but rather is contemplated to comprise any such layer or base structure, and any combination of layers and / or base structures. While the description may refer to particular types of substrates, this is for illustrative purposes only.

[0083] The substrate can be any suitable substrate, such as, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate can include a semiconductor material, such as, for example, a Group IV semiconductor, a III-V compound semiconductor, or a II-VI oxide semiconductor. The Group IV semiconductor may include Si, Ge, or SiGe. The substrate can be a bulk wafer or an epitaxial layer.

[0084] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. It will be appreciated by those skilled in the art that this disclosure may be readily used as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments presented herein. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various modifications, substitutions, and alterations may be made by those skilled in the art without departing from the spirit and scope of the present disclosure.

[0085] [1] A first die, a first layer stack comprising a semiconductor layer on a backside of the first die; a second layer stack comprising alternating gate layers and first insulating layers on a front side of the first die, the front side being opposite the back side; a vertical structure having a first portion disposed in the first layer stack and a second portion extending through the second layer stack, the first portion having a different dimension than the second portion in a direction parallel to a major surface of the first die; A first die comprising: A semiconductor device comprising: [2] The vertical structure includes a channel structure within a core region; The semiconductor device according to [1], wherein the channel structure comprises a channel layer extending into the first portion and the second portion. [3] The second part is a tunnel layer surrounding the channel layer; a charge trapping layer surrounding the tunneling layer; a barrier layer surrounding the charge trapping layer; The semiconductor device according to [2], comprising: [4] The semiconductor device according to [2], wherein the channel layer is in contact with the semiconductor layer at the first portion. [5] The semiconductor device according to [1], wherein the first portion has a dimension that is larger than the second portion in a direction parallel to the main surface of the first die. [6] The semiconductor device according to [1], wherein the first lateral periphery of the first portion extends 10 to 100 nm from the second periphery of the second portion. [7] a first conductive structure disposed on the backside of the first die, the first conductive structure being conductively connected to the semiconductor layer; a second conductive structure disposed on the backside of the first die, the second conductive structure conductively connected to a contact structure disposed on the front side of the first die; The semiconductor device according to [1], further comprising: [8] The semiconductor device according to [1], wherein the vertical structure comprises at least one of a gate line slit (GLS) structure and a dummy channel structure. [9] memory cells on the front side of the first die; a second die bonded face-to-face to the first die, the second die comprising a substrate and peripheral circuitry formed on a front side of the substrate for the memory cells; The semiconductor device according to [1], further comprising:

[10] A semiconductor device, a die comprising a first layer stack comprising a semiconductor layer on a backside of the die; a second layer stack comprising alternating gate layers and insulating layers on a front side of the die, the front side being opposite the back side; a vertical structure having a first portion disposed in the first layer stack and a second portion extending through the second layer stack, the first portion having a different dimension than the second portion in a direction parallel to a major surface of the die; a semiconductor device comprising: a controller configured to control operation of the semiconductor device, the controller being connected to the semiconductor device; A memory system comprising:

[11] A method for manufacturing a semiconductor device, comprising: forming an etch stop structure in an initial first layer stack comprising a sacrificial semiconductor layer over a first substrate, the etch stop structure extending into the sacrificial semiconductor layer; forming a second layer stack over the initial first layer stack; forming holes extending through the second layer stack, the holes exposing respective etch stop structures having dimensions in a direction parallel to a major surface of the first substrate that differ from the dimensions of the holes; removing the respective etch stop structures through the holes such that the holes extend into the sacrificial semiconductor layer; forming a vertical structure in the hole; A method comprising:

[12] the etch stop structure has different etching characteristics than the second layer stack; 12. The method of claim 11, wherein the etch stop structure has different etching characteristics than the sacrificial semiconductor layer.

[13] The method according to

[11] , wherein the first portion has a dimension that is larger than the second portion in a direction parallel to the major surface of the first substrate.

[14] The vertical structure comprises a channel structure, and the step of forming the vertical structure comprises: forming a second insulating layer on the exposed surface along the channel hole; forming a channel layer along the second insulating layer; The method according to

[11] , comprising:

[15] removing the first substrate and the sacrificial semiconductor layer of a first die from a backside of the first die so that the channel structure is exposed from the backside of the first die; removing exposed portions of the second insulating layer so that the channel layer is exposed from the backside of the first die; forming a semiconductor layer covering the channel structure from the backside of the first die; forming a first conductive structure in conductive connection to the semiconductor layer; forming a contact structure from a front side of the first die, the front side being opposite the back side; forming a second conductive structure from the backside of the first die, the second conductive structure being conductively connected to the contact structure; The method according to

[14] , further comprising:

[16] The method of

[14] , wherein each channel structure is formed using a respective etch stop structure.

[17] the second layer stack comprises a sacrificial gate layer and a first insulating layer alternately stacked on the initial first layer stack; forming a dummy channel structure in the staircase region; forming a gate line (GL) cut trench extending through the second layer stack; replacing the sacrificial gate layer with a gate layer via the GL cut trench; forming a gate line slit (GLS) structure in the GL cut trench; The method according to

[11] , further comprising:

[18] The method according to

[17] , wherein the step of forming the vertical structure includes the step of forming at least one of the dummy channel structure or the GLS structure.

[19] the first substrate is included in a first die; forming peripheral circuitry on the front side of the second die; bonding the first die and the second die face-to-face; The method according to

[11] , further comprising:

[20] A method for manufacturing a semiconductor device, comprising: forming a first layer stack comprising a semiconductor layer on a backside of the first die; forming a second layer stack on a front side of the first die, the second layer stack comprising alternating gate layers and first insulating layers, the front side being opposite the back side; forming a channel structure comprising a first portion disposed in the first layer stack and a second portion extending through the second layer stack, the first portion having a larger dimension than the second portion in a direction parallel to a major surface of the first die; A method comprising: [Explanation of symbols]

[0086] 100A semiconductor device 100B Box 100C Layout Design 101 Core Area 102 Stairs area 110 First Layer Stack 111 Semiconductor layer 112 Bulk section 113 Liner part 115 Etch stop layer 120 Second Layer Stack 121 first insulating layer 122 Sacrificial Gate Layer 123 Gate Layer 125 Capping Layer 130 Channel structure 131 First Part 131' Layout Pattern 132 Second Part 132' Layout Pattern 134 Second insulating layer 134i Tunnel Layer 134ii Charge trapping layer 134iii Barrier layer 135 Channel Layer 136 Dielectric Layer 137 Void 140 Gate Line Slit (GLS) Structure 140' layout pattern 150 Dummy channel structure 161 Contact structure 163 Third insulating layer 165 spacer layer 167a first conductive structure 167b second conductive structure 200 processes 230 Second Stack 300 Semiconductor Devices 301 Core Area 302 Stairs area 310 First Layer Stack 311 Semiconductor layer 312 Bulk part 313 Liner part 315 Etch stop layer 320 Second Layer Stack 321 First insulating layer 322 Sacrificial Gate Layer 323 Gate Layer 325 Capping Layer 330 Channel structure 331 First Part 332 Second Part 334 Second insulating layer 335 Channel Layer 336 Dielectric Layer 337 Void 340 Gate Line Slit (GLS) Structure 350 Dummy channel structure 361 Contact structure 363 Third Insulation Layer 371 First Substrate 373 Oxide layer 375 Sacrificial Semiconductor Layer 377 Oxide layer 379 Oxide layer 381 Etching stop structure 383 Channel Hall 385 Gate Line (GL) Cut Trench 387 Aperture 400 Memory System Devices 401 Interface 402 Master Controller 411 Semiconductor Memory Devices 412 Semiconductor Memory Devices 413 Semiconductor Memory Devices 414 Semiconductor Memory Devices 420 Bus 421 Control Line 422 control line 423 Control Line 424 Control Line D1 First die D2 Second Die D3 First Die D4 Second Die

Claims

1. a first die, a semiconductor layer; a stack structure including gate layers and first insulating layers interleaved along a first direction; a first conductive structure, the semiconductor layer being between the first conductive structure and the stack structure in the first direction; a channel structure including a first portion in the semiconductor layer and a second portion extending into the stack structure, wherein a dimension of the first portion differs from a dimension of the second portion in a second direction, and the first direction differs from the second direction; a first die comprising: A semiconductor device comprising:

2. The channel structure portion is a channel layer; a tunnel layer surrounding the channel layer; a charge trapping layer surrounding the tunneling layer; a barrier layer surrounding the charge trapping layer; A functional layer comprising The semiconductor device of claim 1 , comprising:

3. 3. The semiconductor device of claim 2, wherein the channel layer comprises a first portion in the stack structure and a second portion in the semiconductor layer, and wherein a dimension of the first portion of the channel layer differs from a dimension of the second portion of the channel layer in the second direction, and the first direction is perpendicular to the second direction.

4. 3. The semiconductor device of claim 2, wherein the channel structure further comprises a dielectric layer surrounded by the channel layer, the dielectric layer comprising a first portion in the stack structure and a second portion in the semiconductor layer, the first portion of the dielectric layer having a dimension different from a dimension of the second portion of the dielectric layer in the second direction, and the first direction is perpendicular to the second direction.

5. 3. The semiconductor device of claim 2, wherein the functional layer has a first portion extending in the first direction and a second portion extending outward toward the channel structure in the second direction, the second portion of the functional layer being between the semiconductor layer and the stack structure.

6. The semiconductor device of claim 5 , wherein the functional layer does not extend into the semiconductor layer.

7. 3. The semiconductor device of claim 2, wherein the channel layer comprises a portion exposed from the functional layer, and at least a portion of the portion of the channel layer exposed from the functional layer is within and in contact with the semiconductor layer.

8. 2. The semiconductor device of claim 1, wherein the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer, the first semiconductor layer being between the stack structure portion and the second semiconductor layer in the first direction, the first semiconductor layer comprising a first portion extending in the first direction and a second portion extending in the second direction, and at least a portion of the first portion of the first semiconductor layer and the second portion of the first semiconductor layer being within the second semiconductor layer and connected to the second semiconductor layer.

9. 10. The semiconductor device of claim 1, further comprising a second die having peripheral circuitry, the second die being bonded to the first die, and the stack structure being between the semiconductor layer and the second die.

10. 2. The semiconductor device of claim 1, wherein the first die further comprises a contact structure extending in the first direction and a second conductive structure in contact with the contact structure, the contact structure being spaced apart from the stack structure in the second direction, a dimension of the contact structure being larger than a dimension of the stack structure in the first direction, the second conductive structure extending through the semiconductor layer, and the second conductive structure and the contact structure being spaced apart from the semiconductor layer in the second direction.

11. The semiconductor device of claim 1 , wherein the first die further comprises a dummy channel structure extending through the stack structure and into the semiconductor layer.

12. a first die, a stack structure including gate layers and first insulating layers interleaved in a first direction; a semiconductor layer located on one side of the stack structure in the first direction; A channel structure including a channel layer and a functional layer, the functional layer including a tunnel layer, a charge trapping layer, and a barrier layer, the channel layer including: a first portion extending into the stack structure and surrounded by the functional layer; a second portion in the semiconductor layer exposed from the functional layer, the second portion having a surface of the channel layer that is away from the first portion of the channel layer in the first direction and that is connected to the semiconductor layer; A channel structure comprising: a first die comprising: A semiconductor device comprising:

13. 13. The semiconductor device of claim 12, wherein a dimension of the first portion of the channel layer is smaller than a dimension of the second portion of the channel layer in a second direction perpendicular to the first direction.

14. 13. The semiconductor device of claim 12, wherein the channel structure further comprises a dielectric layer surrounded by the channel layer, the dielectric layer comprising a first portion in the stack structure and a second portion in the semiconductor layer, and a dimension of the first portion of the dielectric layer differs from a dimension of the second portion of the dielectric layer in a second direction perpendicular to the first direction.

15. 13. The semiconductor device of claim 12, wherein the functional layer has a first portion extending in the first direction and a second portion extending outward toward the channel structure in a second direction perpendicular to the first direction, the second portion of the functional layer being between the semiconductor layer and the stack structure.

16. 13. The semiconductor device of claim 12, wherein the first die further comprises a first conductive structure connected to the semiconductor layer, the semiconductor layer being between the first conductive structure and the stack structure in the first direction.

17. 13. The semiconductor device of claim 12, wherein the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer, the first semiconductor layer being between the stack structure portion and the second semiconductor layer in the first direction, the first semiconductor layer comprising a first portion extending in the first direction and a second portion extending in a second direction, and at least a portion of the first portion of the first semiconductor layer and the second portion of the first semiconductor layer being within the second semiconductor layer and connected to the second semiconductor layer.

18. 13. The semiconductor device of claim 12, wherein the semiconductor device further comprises a second die comprising peripheral circuitry, the second die being bonded to the first die, and the stack structure portion being between the semiconductor layer and the second die.

19. a first die, a stack structure including gate layers and first insulating layers interleaved in a first direction; a semiconductor layer located on one side of the stack structure in the first direction; a channel structure comprising a channel layer and a functional layer, the functional layer comprising a tunnel layer, a charge trapping layer, and a barrier layer, the functional layer having a first portion extending in the first direction and a second portion extending outward toward the channel structure in a second direction perpendicular to the first direction, the second portion of the functional layer being between the semiconductor layer and the stack structure; a first die comprising: A semiconductor device comprising:

20. The channel layer is a first portion extending into the stack structure and surrounded by the functional layer; a second portion in the semiconductor layer exposed from the functional layer; 20. The semiconductor device of claim 19, wherein the second portion of the channel layer is connected to the semiconductor layer, and wherein a dimension of the first portion of the channel layer is smaller than a dimension of the second portion of the channel layer in a second direction that is perpendicular to the first direction.

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