Semiconductor device

Abstract

To provide a transistor with favorable electrical characteristics, in a transistor including an oxide semiconductor, and a manufacturing method of the transistor.SOLUTION: A first oxide insulating film is formed over a substrate. After a first oxide semiconductor film is formed over the first oxide insulating film, heat treatment is performed, so that hydrogen contained in the first oxide semiconductor film is released and part of oxygen contained in the first oxide insulating film is diffused into the first oxide semiconductor film. Thus, a second oxide semiconductor film with reduced hydrogen concentration and reduced oxygen defect is formed. Then, the second oxide semiconductor film is selectively etched to form a third oxide semiconductor film, and a second oxide insulating film is formed. The second oxide insulating film is selectively etched to form a protective film covering an end portion of the third oxide semiconductor film. Then, a pair of electrodes, a gate insulating film, and a gate electrode are formed over the third oxide semiconductor film and the protective film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Semiconductor device having a circuit including semiconductor elements such as transistors and a manufacturing method thereof For example, power devices, memories, thyristors, converters, inverters, etc. that are mounted on power supply circuits. The present invention relates to electronic equipment that incorporates a light-emitting display device or the like having an image as a component.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices, light-emitting displays, semiconductor circuits, and electronic equipment. be. [Background technology]

[0003] As typified by liquid crystal display devices, transistors formed on glass substrates are amorphous. It is made of amorphous silicon, polycrystalline silicon, etc. Although the resulting transistor has low field-effect mobility, it can be used on large glass substrates. In addition, although the field effect mobility of a transistor using polycrystalline silicon is high, it is difficult to use a glass substrate. However, it has the drawback that it is not suitable for large areas.

[0004] For a transistor using silicon, a transistor using an oxide semiconductor is manufactured. The technology is attracting attention for its application to electronic and optical devices. Then, transistors were fabricated using zinc oxide and In-Ga-Zn-O oxides, and display devices were The technology used for the switching element of the pixel is disclosed in Patent Document 1 and Patent Document 2. do.

[0005] Incidentally, it has been pointed out that hydrogen is a carrier supply source, especially in oxide semiconductors. Therefore, it is important to take measures to prevent hydrogen from being mixed in when forming an oxide semiconductor. In addition to the oxide semiconductor, hydrogen in the gate insulating film in contact with the oxide semiconductor is also required. By reducing the threshold voltage, the fluctuation of the threshold voltage is reduced (see Patent Document 3). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2009-224479 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in a transistor using an oxide semiconductor, the side surface of the oxide semiconductor is decompressed. When exposed to the atmosphere, oxygen in the oxide semiconductor is released, causing oxygen defects (oxygen vacancies). Oxygen vacancies are formed in oxide semiconductors. The area where the carriers flow easily affects the electrical characteristics of the transistor. However, there is a problem that the leakage current between the source and drain of the transistor is high. do.

[0008] In view of this, one embodiment of the present invention is to provide a transistor including an oxide semiconductor having good electrical characteristics. An object of the present invention is to provide a good transistor and a manufacturing method thereof. [Means for solving the problem]

[0009] One embodiment of the present invention is a method for forming a first oxide insulating film over a substrate, After the oxide semiconductor film is formed, heat treatment is performed to remove hydrogen from the first oxide semiconductor film. While the oxygen is being desorbed, part of the oxygen contained in the first oxide insulating film is diffused into the first oxide semiconductor film. Then, a second oxide semiconductor film in which the hydrogen concentration and oxygen vacancies are reduced is formed. The oxide semiconductor film is selectively etched to form a third oxide semiconductor film, and then a second A second oxide insulating film is formed, and the second oxide insulating film is selectively etched to form a third oxide semiconductor. A protective film is formed to cover the end of the conductive film. After that, a first insulating film is formed on the third oxide semiconductor film and the protective film. The method is characterized by forming a pair of electrodes, a gate insulating film, and a gate electrode.

[0010] One embodiment of the present invention is a method for forming a first oxide insulating film over a substrate, An oxide semiconductor film is formed, the first oxide semiconductor film is selectively etched, and a second oxide semiconductor film is formed. Next, a second oxide insulating film is formed to cover the first oxide insulating film and the second oxide semiconductor film. After forming the oxide insulating film, a heat treatment is performed to form the first oxide insulating film and the second oxide insulating film. Part of the oxygen contained in the second oxide semiconductor film is diffused into the second oxide semiconductor film, thereby reducing the hydrogen concentration and oxygen defects. Next, the second oxide insulating film is selectively etched. Then, a protective film is formed to cover the edge of the third oxide semiconductor film. a pair of electrodes, a gate insulating film, and a gate electrode are formed on the body film and the protective film. do.

[0011] One embodiment of the present invention is a method for forming a first oxide insulating film over a substrate, An oxide semiconductor film is formed, and a pair of electrodes is formed over the first oxide semiconductor film. The first oxide semiconductor film is selectively etched to form a second oxide semiconductor film. a second oxide insulating film covering the oxide insulating film, the pair of electrodes, and the second oxide semiconductor film; Then, heat treatment is performed to remove part of the oxygen contained in the first oxide insulating film and the second oxide insulating film. into the second oxide semiconductor film to form a third oxide semiconductor film in which the hydrogen concentration and oxygen defects are reduced. Next, the second oxide insulating film is selectively etched to form a third oxide semiconductor. A protective film is formed to cover the end of the conductive film. After that, a third oxide semiconductor film and the protective film are formed on the third oxide semiconductor film and the protective film. The method is characterized by forming a gate insulating film and a gate electrode.

[0012] The first and second oxide insulating films are oxide insulating films from which part of the oxygen is released by heating. The oxide insulating film from which part of oxygen is released by heating is formed using a material having a stoichiometric ratio of It is preferable to use an oxide insulating film containing more oxygen than the oxygen that fills the insulating film. The oxide insulating film from which part of the oxide is released releases oxygen when heated, so the first oxide Oxygen can be diffused into the oxide semiconductor film or the second oxide semiconductor film. Typical examples of oxide insulating films from which some of the elements are released are silicon oxide, silicon oxynitride, and nitride. Silicon oxide, aluminum oxide, aluminum oxide nitride, gallium oxide, hafnium oxide Examples include yttrium oxide and yttrium oxide.

[0013] In one embodiment of the present invention, a first oxide semiconductor is formed in contact with at least a first oxide insulating film. The conductive film or the second oxide semiconductor film is heated to remove oxygen contained in the first oxide insulating film. into the first oxide semiconductor film or the second oxide semiconductor film, thereby reducing oxygen defects. In addition, the first oxide insulating film and the first oxide semiconductor film or the second oxide semiconductor film can be formed. As a result, the interface state at the interface with the semiconductor film can be reduced. This can reduce the negative shift of the low voltage.

[0014] In addition, after the end portions of the third oxide semiconductor film are covered with a protective film, a pair of electrodes, a gate insulating film, and Since the gate electrode is formed on the third oxide semiconductor film, the side surfaces of the third oxide semiconductor film are not exposed to a reduced-pressure atmosphere. In addition, in the process of forming the pair of electrodes, the side surfaces of the third oxide semiconductor film are Therefore, generation of oxygen defects on the side surfaces of the third oxide semiconductor film is reduced. It can be reduced.

[0015] In one aspect of the present invention, the protective film, the gate electrode, and the pair of electrodes are used as a mask to form a first By adding a dopant to the oxide semiconductor film of 3, a pair of dopants can be formed in a self-aligned manner. The dopant is hydrogen, helium, neon, etc. , argon, krypton, and xenon, and The dopant concentration in the region containing the dopant is 5×10 18 atoms / cm 3 More than 1×10 22 atoms / cm 3 Less than or equal to 5 x 10 18 atoms / cm 3 5x10 or more 19 atoms / cm 3 As a result, the first oxide semiconductor region overlapping with the gate electrode a pair of dopant-containing regions sandwiching the first oxide semiconductor region, and a pair of electrodes overlapping the first oxide semiconductor region; and forming a pair of second oxide semiconductor regions sandwiching a pair of regions containing a dopant therebetween. The first oxide semiconductor region functions as a channel region, and the second oxide semiconductor region functions as a region containing a dopant. This region functions as an electric field relaxation region, suppressing the short channel effect of the transistor. In addition, since the gate electrode and the pair of electrodes do not overlap, the parasitic capacitance can be reduced. This allows the transistor to operate at high speed.

[0016] After the addition of the dopant, a heat treatment may be carried out.

[0017] The oxide semiconductor may contain one or more elements selected from the group consisting of In, Ga, Sn, and Zn. Cut.

[0018] The oxide semiconductor is non-single-crystal and has a triangular or triangular shape when viewed from a direction perpendicular to the ab plane. Or, it has a hexagonal, equilateral triangular, or equilateral hexagonal atomic arrangement, and the direction perpendicular to the c axis From the viewpoint of the material, it is a material containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It can also be done as follows.

[0019] In this specification, a non-single crystal is defined as a crystal that is triangular or has a shape perpendicular to the ab plane. Or, it has a hexagonal, equilateral triangular, or equilateral hexagonal atomic arrangement, and the direction perpendicular to the c axis From this perspective, materials containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers, These are called c-axis aligned crystals (CAAC) oxide semiconductors.

[0020] CAAC oxide semiconductors are not single crystals, but are formed only from amorphous materials. In addition, the CAAC oxide semiconductor contains a crystallized portion (crystalline portion), but it is not a single In some cases, the boundary between the crystalline and non-crystalline regions cannot be clearly distinguished. A part or all of the oxygen constituting the CAAC oxide semiconductor may be substituted with nitrogen. The c-axis of each crystalline part that constitutes the conductor is aligned in a certain direction (for example, the CAAC oxide semiconductor is supported). The orientation may be aligned in a direction perpendicular to the surface of the substrate or the surface of the CAAC oxide semiconductor. Alternatively, the normal to the ab plane of each crystal part constituting the CAAC oxide semiconductor is in a certain direction (e.g. For example, a substrate surface supporting the CAAC oxide semiconductor, a surface of the CAAC oxide semiconductor, etc. The direction may be facing the target.

[0021] CAAC oxide semiconductors can be conductors or insulators depending on their composition. Depending on the composition of the material, it may be transparent or opaque to visible light. As an example of the AAC oxide semiconductor, it is formed in a film shape, and the film surface, the substrate surface, or the boundary When observed perpendicular to the surface, a triangular or hexagonal atomic arrangement is observed, and When observing the cross section of the film, it is possible to see layers of metal atoms, or metal atoms and oxygen atoms (or nitrogen atoms). Materials in which a crystalline arrangement is observed can also be mentioned. [Effects of the Invention]

[0022] According to one embodiment of the present invention, oxygen defects in an oxide semiconductor film can be reduced. , the negative shift of the threshold voltage of the transistor is reduced, and the source of the transistor is It is possible to reduce leakage current in the source and drain, and improve the electrical characteristics of the transistor. It can improve the performance. [Brief explanation of the drawings]

[0023] [Figure 1]1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 3] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A to 1C are top views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a semiconductor device and a manufacturing method thereof according to one embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 16] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 17] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 18]1A and 1B are a block diagram and a partial circuit diagram illustrating a semiconductor device showing a specific example of a CPU. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating a display device using a semiconductor device which is one embodiment of the present invention. [Figure 20] 1A and 1B are cross-sectional views illustrating operation modes of a liquid crystal. [Figure 21] 1A and 1B are cross-sectional views illustrating operation modes of a liquid crystal. [Figure 22] 1A and 1B are cross-sectional views illustrating operation modes of a liquid crystal. [Figure 23] 1A and 1B are a top view and a cross-sectional view illustrating an operation mode of a liquid crystal. [Figure 24] FIG. 2 is a top view illustrating the structure of a pixel electrode. [Figure 25] FIG. 2 is a top view illustrating the structure of a pixel electrode. [Figure 26] 1A and 1B are a circuit diagram and a top view illustrating one embodiment of a protection circuit. [Figure 27] FIG. 1 is a diagram illustrating a model used in calculations. [Figure 28] FIG. 1 is a diagram illustrating a model used in calculations. DETAILED DESCRIPTION OF THE INVENTION

[0024] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above embodiment, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the present invention. It should not be construed as being limited to the description of the embodiments. In the configuration, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings. These are commonly used, and repeated explanations will be omitted.

[0025] In each of the drawings described in this specification, the size of each component, the thickness of the film, or the area is not clearly indicated. The figures may be exaggerated for clarity and are not necessarily limited to that scale. .

[0026] In addition, terms such as first, second, and third used in this specification are used in order to avoid confusion of components. It is not a numerical limitation. For example, "first" can be changed to " The terms "second" or "third" can be used interchangeably to explain the present invention.

[0027] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a transistor capable of reducing leakage current will be described. This will be explained with reference to FIGS.

[0028] 1A and 1B are a top view and a cross-sectional view of the transistor described in this embodiment. 1B is a top view of a transistor shown in an embodiment, and FIG. 1B is a top view of a transistor shown in FIG. 1(C) is a cross-sectional view corresponding to the dashed line CD in FIG. 1(A). 1(D) is a cross-sectional view corresponding to the dashed line EF in FIG. 1(A). In 1(A), to avoid complexity, some of the components of the transistor (e.g., The gate insulating film 111, insulating film 125, etc. are omitted.

[0029] The transistor shown in FIG. 1 includes an oxide insulating film 102 provided on a substrate 101 and an oxide insulating film 103. The oxide semiconductor film 120 is provided on the oxide semiconductor film 102, and a protective film covering the edge of the oxide semiconductor film 120 is provided on the oxide semiconductor film 102. a pair of electrodes formed over the protective film 107 and in contact with the oxide semiconductor film 120; 109, a gate insulating film covering the protective film 107, the pair of electrodes 109, and the oxide semiconductor film 120. The insulating film 111 and the gate insulating film 112 are overlapped with the oxide semiconductor film 120. The gate electrode 113 is covered with the gate insulating film 111 and the gate electrode 113. The oxide semiconductor film 120 may have a gate electrode 113 overlapping with the oxide semiconductor film 125. an oxide semiconductor region 119 and a pair of regions containing dopants sandwiching the oxide semiconductor region 119; 115, 117, and a pair of electrodes sandwiching the regions 115, 117 containing a pair of dopants. The oxide semiconductor region 109 has a pair of oxide semiconductor regions 121 and 123 in contact with the oxide semiconductor region 109. Region 119 functions as a channel region, and regions 115 and 117 containing a pair of dopants The pair of oxide semiconductor regions 121 and 123 function as a field relaxation region. The regions in contact with the protective film 109 function as a source region and a drain region. The end of the oxide semiconductor film 120 covered by the oxide semiconductor film 120 is at least the side surface of the oxide semiconductor film 120. , and may further include a part of the surface of the oxide semiconductor film 120.

[0030] There is no particular restriction on the material of the substrate 101, but it should be strong enough to withstand the subsequent heat treatment. It must be heat resistant. For example, glass substrates, ceramic substrates, quartz substrates, and surface treatment substrates are A fiber substrate or the like may be used as the substrate 101. Also, silicon, silicon carbide, etc. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, and compound semiconductor substrates such as silicon germanium It is also possible to apply an SOI substrate, etc., and a semiconductor element is provided on such a substrate. The resulting film may be used as the substrate 101 .

[0031] Alternatively, a flexible substrate may be used as the substrate 101. A release layer may be provided between the semiconductor device and the substrate. After that, it can be separated from the substrate 101 and used for transferring to another substrate. The semiconductor device can be transferred to a substrate having poor heat resistance or a flexible substrate.

[0032] The oxide insulating film 102 is formed using an oxide insulating film from which part of oxygen is released by heating. As an oxide insulating film from which part of the oxygen is released by heat, it is necessary to use a material that contains more oxygen than the stoichiometric ratio. It is preferable to use an oxide insulating film containing oxygen. Oxygen is released from the insulating film by heating, and the oxygen diffuses into the oxide semiconductor film by heating. The oxide insulating film 102 is typically formed of silicon oxide, silicon oxynitride, or nitride. Silicon oxide, aluminum oxide, aluminum oxide nitride, gallium oxide, hafnium oxide The insulating layer can be formed of aluminum oxide, yttrium oxide, or the like.

[0033] The oxide insulating film 102 has a thickness of 50 nm or more, preferably 200 nm or more and 500 nm or less. By increasing the thickness of the oxide insulating film 102, the amount of oxygen released from the oxide insulating film 102 can be increased. At the same time, the boundary between the oxide insulating film 102 and an oxide semiconductor film to be formed later can be prevented. It is possible to reduce the surface level.

[0034] Here, "a part of the oxygen is released by heating" means that the TDS (Thermal Desorption Thermal desorption spectroscopy (TDS) analysis revealed that the oxygen atoms The converted oxygen release rate is 1.0 x 10 18 atoms / cm 3 Above, preferably 3.0 x10 20 atoms / cm 3 This means that the above is the case.

[0035] Here, the method for measuring the amount of desorbed oxygen converted into oxygen atoms in TDS analysis is as follows: will be explained.

[0036] The amount of gas desorbed during TDS analysis is proportional to the integral value of the spectrum. The amount of released gas is calculated by the ratio of the integral value of the film spectrum to the reference value of the standard sample. The reference value of the standard sample is the integral value of the spectrum of a sample containing a specific atom. is the ratio of the atomic density to the total mass.

[0037] For example, the TDS analysis results of a silicon wafer containing a predetermined density of hydrogen as a standard sample, and From the results of TDS analysis of the insulating film, the amount of oxygen molecules desorbed from the insulating film (N O2 ) is calculated using formula 1 Here, all of the spectra detected at mass number 32 obtained by TDS analysis can be It is assumed that the mass number is 32 and that CH3OH exists. It is not considered here because it has low affinity. The abundance ratio of the oxygen molecule, which contains the oxygen atom with mass number 18, in nature is Not taken into consideration as it is an extremely small amount.

[0038]

number

[0039] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the spectrum obtained when the material is subjected to TDS analysis is shown in Fig. 1. Here, the reference value of the standard sample is N H2 / S H2 Let's say S O2 is the integral value of the spectrum obtained when the insulating film is analyzed by TDS. α is a coefficient that affects the spectral intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. The amount of oxygen released from the insulating film is Using a thermal desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Corporation, 1×10 16 atoms / cm 3 measured using a silicon wafer containing hydrogen atoms .

[0040] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen molecules is included, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0041] In addition, N O2 is the amount of oxygen molecules released. In the case of an insulating film, when converted to oxygen atoms, The amount of released oxygen is twice the amount of desorbed oxygen molecules.

[0042] In the above structure, the insulating film from which oxygen is released by heating is silicon oxide (S iO X (X>2)) or silicon oxide (SiO X (X>2) It means that the number of oxygen atoms per unit volume is more than twice the number of silicon atoms. The number of silicon atoms and oxygen atoms per volume was measured by Rutherford backscattering spectroscopy. value.

[0043] Oxygen is supplied from the oxide insulating film to the oxide semiconductor film, whereby the oxide insulating film and the oxide semiconductor As a result, the charge that may be generated due to the operation of the transistor can be reduced. can be prevented from being trapped at the interface between the oxide insulating film and the oxide semiconductor film. This allows for a reduction in the negative shift of the threshold voltage, resulting in a transistor with minimal degradation of electrical characteristics. You can get the data.

[0044] Furthermore, charges may be generated due to oxygen vacancies in the oxide semiconductor film. Oxygen vacancies in the semiconductor film cause some of them to become donors, generating electrons as carriers. The threshold voltage of the transistor shifts in the negative direction. The back channel in this specification is particularly noticeable in the oxygen vacancies that occur on the hole side. In the oxide semiconductor region 119 shown in FIG. 1B, the vicinity of the interface with the oxide insulating film 102 is indicated. When oxygen is sufficiently released from the oxide insulating film to the oxide semiconductor film, the threshold voltage The oxygen vacancies in the oxide semiconductor film, which are the cause of the negative shift in .

[0045] That is, when oxygen vacancies occur in the oxide semiconductor film, It is difficult to suppress the trapping of charges in the oxide insulating film. By providing the insulating film, the interface state between the oxide semiconductor film and the oxide insulating film and the oxide insulating film can be reduced. This reduces oxygen vacancies in the oxide semiconductor film and prevents charge trapping at the interface between the oxide semiconductor film and the oxide insulating film. The influence of the

[0046] The oxide semiconductor film 120 is made of at least one material selected from the group consisting of In, Ga, Sn, and Zn. The oxide semiconductor film contains one or more elements. Sn-Ga-Zn-O based metal oxides and In-Ga-Zn-O based ternary metal oxides Metal oxides, In-Sn-Zn-O based metal oxides, In-Al-Zn-O based metal oxides, Sn-Ga-Zn-O metal oxide, Al-Ga-Zn-O metal oxide, Sn-Al- Zn-O based metal oxides, binary metal oxides such as In-Zn-O based metal oxides, Sn- Uses Zn-O based metal oxides and single-component metal oxides such as ZnO, SnO, and InO. The oxide semiconductor may contain silicon oxide. In-Ga-Zn-O materials are made of indium (In), gallium (Ga), and zinc (Z). n), and the composition ratio is not particularly limited. In this case, the oxide semiconductor film may contain an element other than gallium and zinc. In this case, it is preferable to use an excess of oxygen relative to the stoichiometric ratio. It is possible to suppress generation of carriers due to oxygen deficiency in the semiconductor film.

[0047] When an In-Zn-O-based material is used as the oxide semiconductor film, the atomic ratio is In / Zn= 0.5 to 50, preferably In / Zn=1 to 20, more preferably In / Zn=1.5 By setting the atomic ratio of In to Zn in the above-mentioned preferred range, the transistor The field effect mobility of the semiconductor can be improved. When n:O=X:Y:Z, Z>1.5X+Y.

[0048] Note that metal oxides that can be formed in the oxide semiconductor film 120 have an energy gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. In addition, by using an oxide semiconductor with a wide energy gap, the off-state current of a transistor can be reduced. can be reduced.

[0049] The oxide semiconductor film 120 may have an amorphous structure.

[0050] The oxide semiconductor film 120 is non-single-crystal and has a thickness of 100 nm when viewed from a direction perpendicular to the ab plane. It has a triangular, hexagonal, or equilateral triangular or equilateral hexagonal atomic arrangement and is perpendicular to the c-axis. When viewed from a perpendicular direction, the phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers, is called Alternatively, the layer may be formed using a material containing c-axis oriented crystals, i.e., a c-axis oriented crystal material.

[0051] The oxide semiconductor film 120 has a thickness of 5×10 18 atoms / cm 3 The following nitrogen may be present: stomach.

[0052] In the oxide semiconductor film 120, the concentration of the alkali metal or alkaline earth metal is 1×1 0 18 atoms / cm 3 or less, more preferably 2 × 10 16 atoms / cm 3 below It is desirable that the alkali metal and alkaline earth metal bond to the oxide semiconductor. This is because carriers may be generated when the gate electrode is turned on, which may cause an increase in the off-state current of the transistor. do.

[0053] The oxide semiconductor film 120 has a hydrogen concentration of 5×10 18 atoms / cm 3 Less than, preferably 1×10 18 atoms / cm 3 Less than or equal to 5 × 10 17 atoms / cm 3 or less, more preferably 1 × 10 16 atoms / cm 3 The following is preferred: By bonding with the compound semiconductor and hydrogen, some of the hydrogen becomes donors, and electrons, which act as carriers, are generated. For these reasons, the threshold voltage can be reduced by reducing the hydrogen concentration in the oxide semiconductor film. This can reduce negative pressure shifts.

[0054] Here, an amorphous oxide semiconductor film is formed as the oxide semiconductor film 120.

[0055] The thickness of the oxide semiconductor film 120 is preferably 1 nm to 50 nm, more preferably 3 nm to 30 nm. It is preferable to set it to 0 nm or less.

[0056] In the oxide semiconductor film 120, the protective film 107, the pair of electrodes 109, and the gate electrode 113 The uncovered areas are provided with a pair of dopant-containing regions 115, 117. The regions 115 and 117 containing the oxypant contain a group 15 element such as nitrogen, phosphorus, or arsenic. Alternatively, the regions 115 and 117 containing a pair of dopants may contain hydrogen, helium, It contains at least one dopant selected from neon, argon, krypton, and xenon. It is being eaten.

[0057] The concentration of the dopant contained in the pair of dopant-containing regions 115 and 117 is 5×10 1 8 atoms / cm 3 More than 1×10 22 atoms / cm 3 Less than or equal to 5 x 10 1 8 atoms / cm 3 5x10 or more 19 atoms / cm 3 Less than.

[0058] Furthermore, the regions 115 and 117 containing a pair of dopants contain dopants, and therefore the carrier density is high. Therefore, the dopant-free oxide semiconductor can be used to increase the degree of doping or defects. The conductivity can be increased compared to region 119. If the dopant is too thick, it will hinder the movement of carriers, and the region containing the pair of dopants will This will reduce the conductivity of the regions 115, 117.

[0059] The regions 115 and 117 containing the pair of dopants have a conductivity of 10 S / cm or more and 1000 S / cm or more. It is preferable that the viscosity is 100 S / cm or less and 1000 S / cm or less.

[0060] The oxide semiconductor film 120 has regions 115 and 117 containing a pair of dopants. As a result, the electric field applied to the edge of the oxide semiconductor region 119 functioning as a channel region is reduced. This makes it possible to suppress the short channel effect of the transistor.

[0061] In the oxide semiconductor film 120, the pair of electrodes 109, the gate electrode 113, and the protective layer The region covered with the film 107 is made of oxide semiconductor regions 121 and 123, which are made of nitrogen, Group 15 elements such as phosphorus or arsenic, hydrogen, helium, neon, argon, krypton, At least one dopant of xenon is introduced by ion doping, ion implantation, or the like. It is not added by methods such as plasma treatment.

[0062] The protective film 107 is a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, and a nitride film. The protective film 107 can be formed of a single layer or a multilayer of silicon films. At least in a region in contact with the oxide semiconductor film 120, It is preferable to use an oxide insulating film from which oxygen is released by heating.

[0063] The thickness of the protective film 107 is 30 nm or more and 1000 nm or less, and more preferably 100 nm or more. When the thickness is 1000 nm or less, doping of the dopant to the edge of the oxide semiconductor film 120 is prevented. In addition, insulation between the oxide semiconductor film 120 and the pair of electrodes 109 can be maintained. The distance that the protective film 107 covers the surface of the oxide semiconductor film 120 at the end is 5 If the thickness is 0 nm or less, and more preferably 20 nm or less, the oxide can be reliably formed even if the mask is misaligned. The side surfaces of the semiconductor film 120 can be covered with a protective film.

[0064] The protective film 107 covers the end portion of the oxide semiconductor film 120, and thus the side surface of the oxide semiconductor film 120 The pair of electrodes 109 do not come into contact with each other, and the occurrence of leakage current in the region is suppressed. can be done.

[0065] The pair of electrodes 109 is made of a conductive material such as aluminum, titanium, chromium, nickel, copper, or iron. Monolithic alloys consisting of tritium, zirconium, molybdenum, silver, tantalum, or tungsten The metal or alloy containing it as the main component is used as a single layer structure or a laminated structure. , a single layer structure of aluminum film containing silicon, and a two-layer structure of titanium film laminated on aluminum film. Layer structure, two-layer structure with titanium film laminated on tungsten film, copper-magnesium-aluminum A two-layer structure in which a copper film is laminated on an aluminum alloy film, a titanium film, and an aluminum film laminated on the titanium film. There are three-layer structures, such as a laminated aluminum film and a titanium film on top of that. A transparent conductive material containing indium, tin oxide, or zinc oxide may also be used. 109 also functions as wiring.

[0066] The gate insulating film 111 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide, etc. may be used. The gate insulating film 111 is formed as a stacked layer or a single layer. Alternatively, an oxide insulating film from which oxygen is released by heating may be used. By using a film from which oxygen is released, oxygen vacancies occurring in the oxide semiconductor film can be repaired. This makes it possible to suppress deterioration of the electrical characteristics of the transistor.

[0067] The gate insulating film 111 is made of hafnium silicate (HfSiO x ), nitrogen added Hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium Laminate (HfAl x O y N z ), hafnium oxide, yttrium oxide, etc. The use of k-materials can reduce gate leakage.

[0068] The thickness of the gate insulating film 111 is 1 nm or more and 300 nm or less, and more preferably 5 nm or more and 500 nm or less. It is recommended to set it to 0 nm or less.

[0069] The gate insulating film 111 is formed only on the oxide semiconductor region 119. The regions 115 and 117 containing the components may not be covered.

[0070] The gate electrode 113 may be made of aluminum, chromium, copper, tantalum, titanium, molybdenum, or titanium. or an alloy containing the above-mentioned metal elements, or It can be formed by using an alloy of a combination of metal elements. Alternatively, one or more metal elements selected from the group consisting of arsenic, gallium, arsenic ... The electrode 113 may have a single layer structure or a laminated structure of two or more layers. a single-layer structure of an aluminum film containing titanium; a two-layer structure of an aluminum film with a titanium film laminated on top; Two-layer structure in which a titanium film is laminated on a titanium film, and two-layer structure in which a tungsten film is laminated on a titanium nitride film. Layer structure, two-layer structure with tungsten film stacked on tantalum nitride film, titanium film and its titanium There are three-layer structures, such as an aluminum film on a titanium film, and an aluminum film on top of that. In addition, titanium, tantalum, tungsten, molybdenum, chromium, nickel, A film of an element selected from the group consisting of chromium, chromium, and scandium, or an alloy film of a combination of multiple elements, or A nitride film may also be used.

[0071] The gate electrode 113 is made of indium tin oxide or indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide containing titanium oxide A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element may also be used.

[0072] In addition, a material in contact with the gate insulating film 111 is provided between the gate electrode 113 and the gate insulating film 111. As the material layer, a nitrogen-containing In-Ga-Zn-O film, a nitrogen-containing In-Sn-O film, and a nitrogen-containing In-Ga-Zn-O film are used. In-Ga-O films containing nitrogen, In-Zn-O films containing nitrogen, Sn-O films containing nitrogen, It is preferable to provide an In—O film containing nitrogen or a metal nitride film (InN, ZnN, etc.) These films have a work function of 5 eV, preferably 5.5 eV or more, and are suitable for transistors. The threshold voltage of the switching element can be made positive, so that it is a so-called normally-off switching element. For example, when an In-Ga-Zn-O film containing nitrogen is used, at least In-G containing nitrogen at a higher concentration than the oxide semiconductor film 120, specifically, 7 atomic % or more of nitrogen. An a-Zn-O film is used.

[0073] The insulating film 125 is made of a material such as silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Any of these may be used, and the layer may be formed as a laminate or a single layer.

[0074] In the transistor described in this embodiment, the edge portions of the oxide semiconductor film 120 are covered with the protective film 107. Therefore, the region of the oxide semiconductor film 120 covered with the protective film 107 is doped with the dopant. Therefore, the occurrence of leakage current in this region can be reduced. In addition, since the pair of electrodes 109 and the gate electrode 113 do not overlap, The parasitic capacitance occurring between the gate electrodes 113 can be reduced. In addition, since the hydrogen concentration in the oxide semiconductor film 120 is low, The electrical characteristics and reliability of the transistor can be improved.

[0075] In this embodiment, a transistor in which the opposing regions of a pair of electrodes 109 are linear is used. However, the opposing regions of the pair of electrodes 109 may be U-shaped, C-shaped, etc. A transistor with such a structure can have a large channel width and an on-state current. The flow can be increased.

[0076] Next, a manufacturing method of the transistor illustrated in FIG. 1 will be described with reference to FIGS.

[0077] As shown in FIG. 2A, an oxide insulating film 102 is formed on a substrate 101. Next, An oxide semiconductor film 103 is formed over the film 102 .

[0078] The oxide insulating film 102 is formed by a sputtering method, a CVD method, or the like. An oxide insulating film from which part of the oxygen is released can be easily formed by sputtering. preferable.

[0079] When an oxide insulating film from which part of oxygen is released by heating is formed by a sputtering method, It is preferable that the amount of oxygen in the film forming gas is high, and oxygen or a mixed gas of oxygen and a rare gas is used. Typically, the oxygen concentration in the deposition gas is set to 6% or more and 100% or less. It is preferable.

[0080] When a silicon oxide film is formed, a part of the oxygen is released by heating. In this case, quartz (preferably synthetic quartz) is used as the target, and the substrate temperature is 30°C or more and 450°C or less. (preferably 70°C or higher and 200°C or lower), the distance between the substrate and the target (TS distance) The gap should be between 20mm and 400mm (preferably between 40mm and 200mm), and the pressure should be 0. Set the pressure to 1 Pa or higher and 4 Pa ​​or lower (preferably 0.2 Pa or higher and 1.2 Pa or lower), and turn the high-frequency power supply to 0. 5kW or more and 12kW or less (preferably 1kW or more and 5kW or less), O2 / (O 2+Ar) ratio is 1% or more and 100% or less (preferably 6% or more and 100% or less), and R It is preferable to form a silicon oxide film by F sputtering. Alternatively, a silicon target may be used in place of the silicon (or synthetic quartz) target. The deposition gas may contain only oxygen.

[0081] The oxide semiconductor film 103 can be formed by a sputtering method, a coating method, a printing method, a pulsed laser deposition method, or the like. It can be formed by:

[0082] Here, the oxide semiconductor film 103 is formed by a sputtering method to a thickness of 1 nm to 50 nm. More preferably, the thickness is 3 nm or more and 30 nm or less.

[0083] Next, a sputtering apparatus for forming an oxide semiconductor film will be described in detail below.

[0084] The treatment chamber for forming the oxide semiconductor film has a leak rate of 1×10 -10 Pa·m 3 / second or less It is preferable to set the above-mentioned condition so that impurities in the film are prevented from being introduced when the film is formed by sputtering. This can reduce the contamination.

[0085] To reduce the leak rate, it is necessary to reduce not only external leaks but also internal leaks. An external leak is when gas enters the vacuum system from outside due to a small hole or poor seal. Internal leaks are leaks from partitions such as valves in the vacuum system or leaks from internal components. Leak rate is 1×10 -10 Pa·m 3 / sec or less Therefore, measures must be taken to prevent both external and internal leaks.

[0086] To reduce external leakage, it is advisable to seal the opening and closing parts of the processing chamber with metal gaskets. Tal gaskets are coated with iron fluoride, aluminum oxide, or chromium oxide. It is preferable to use a metal material. Metal gaskets have a higher adhesion than O-rings, and they are In addition, passivation such as iron fluoride, aluminum oxide, and chromium oxide can reduce the By using a metal material coated with a fluorine-based compound, the released gas, including hydrogen, generated from the metal gasket can be prevented. This suppresses the internal leakage and reduces the internal leakage.

[0087] The inner wall of the processing chamber is made of aluminum and chromium, which emit less gas, including hydrogen. , titanium, zirconium, nickel or vanadium. It may be used by coating an alloy material containing chromium and nickel. The alloy material containing titanium is rigid, heat-resistant, and suitable for processing. To reduce the area, reducing the surface roughness of the components by polishing or other methods can reduce the amount of gas released. Alternatively, the components of the film forming apparatus may be replaced with iron fluoride, aluminum oxide, or chromium oxide. Alternatively, the metal may be coated with a passivation material such as

[0088] Furthermore, a sputtering gas refiner may be installed immediately before the sputtering gas is introduced into the processing chamber. In this case, the length of the piping from the refiner to the treatment chamber is 5 m or less, preferably 1 m or less. By keeping the length of the piping at 5m or less or 1m or less, the influence of the gas emitted from the piping can be reduced. The reverberation can be reduced depending on the length.

[0089] The exhaust from the processing chamber is performed by a roughing pump such as a dry pump, a sputter ion pump, and a turbo pump. It is advisable to use a suitable combination of a sub-pump and a high vacuum pump such as a cryopump. While the polymer pump excels at pumping large molecules, it has poor pumping ability for hydrogen and water. Therefore, a cryopump with high water pumping capacity and a sputter ion pump with high hydrogen pumping capacity are used. It is effective to combine

[0090] Adsorbates present inside the processing chamber are adsorbed to the inner wall and do not affect the pressure in the processing chamber. This causes gas emission when the processing chamber is evacuated. Although there is no correlation, a pump with high exhaust capacity is used to remove as much of the adsorbed matter as possible from the treatment chamber. It is important to evacuate the treatment chamber in advance. Baking is also possible. Baking increases the desorption rate of adsorbed substances by about 10 times. Baking can be performed at a temperature between 100°C and 450°C. By removing adsorbed substances while introducing gas, it is possible to remove water and other substances that are difficult to remove by exhausting only. The speed can be further increased.

[0091] In this way, in the step of forming the oxide semiconductor film 103, it is more preferable to form an oxide insulating film. In the membrane process, the pressure in the processing chamber, the leak rate in the processing chamber, etc. are used to minimize the inclusion of impurities. By suppressing the amount of hydrogen contained in the oxide semiconductor film, the amount of hydrogen contained in the oxide semiconductor film can be reduced. In addition, diffusion of impurities such as hydrogen from the oxide insulating film to the oxide semiconductor film can be reduced. It is possible.

[0092] The hydrogen contained in the oxide semiconductor reacts with the oxygen that bonds with the metal atoms to form water, and the oxygen Defects are formed in the lattice where atoms are removed (or in the area where oxygen is removed). Therefore, by significantly reducing impurities including hydrogen in the film formation process of the oxide semiconductor film, It is possible to reduce defects in the oxide semiconductor film. By using a highly purified oxide semiconductor film as a channel region, the signal It can increase reliability.

[0093] In the sputtering method, the power supply for generating plasma is an RF power supply, A A C power supply, a DC power supply, etc. can be used as appropriate.

[0094] As the target, a metal oxide target containing zinc can be used. Examples of oxides include quaternary metal oxides such as In-Sn-Ga-Zn-O and ternary metal oxides such as In-Sn-Ga-Zn-O. In-Ga-Zn-O based metal oxides and In-Sn-Zn-O based metal oxides compound, In-Al-Zn-O metal oxide, Sn-Ga-Zn-O metal oxide, Al- Ga-Zn-O based metal oxides, Sn-Al-Zn-O based metal oxides, and binary metal oxides In-Zn-O based metal oxides, Sn-Zn-O based metal oxides, and single-component metal oxides ZnO-based metal oxides, SnO-based metal oxides, etc. can be used as targets. .

[0095] As an example of the target, a metal oxide target containing In, Ga, and Zn is used. The composition ratio is O3:Ga2O3:ZnO=1:1:1 [molar ratio]. 3: Ga2O3: ZnO = 1: 1: 2 [molar ratio], The target has a composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [molar ratio]. The composition ratio of In2O3:Ga2O3:ZnO=2:1:8 [molar ratio] A target of In2O3:ZnO=25:1 [molar ratio] or more can also be used. A target having a composition ratio of 1:4 can also be used.

[0096] The sputtering gas may be a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. A mixed gas of hydrogen and oxygen is used as appropriate. The sputtering gas does not contain impurities including hydrogen. It is preferable to use a high purity gas from which .

[0097] Note that the oxide insulating film 102 and the oxide semiconductor film 103 are preferably formed in succession. After the oxide insulating film 102 is formed, the oxide semiconductor film 103 is formed without exposure to air. The adhesion of hydrogen to the interface between the oxide insulating film 102 and the oxide semiconductor film 103 can be reduced. Alternatively, in a multi-chamber sputtering device equipped with a heating device, oxidation can be performed. The insulating film 102 is formed, and the oxide insulating film 102 is heated in a heating device to remove hydrogen. The oxide semiconductor film 103 may be formed over the oxide insulating film 102 .

[0098] Next, the substrate 101 is subjected to heat treatment to release hydrogen from the oxide semiconductor film and to remove oxygen. The oxide insulating film 102 is partially oxidized to the oxide semiconductor film 103, the oxide insulating film 102, and the oxide semiconductor film 103. 2B, the cations of ... The oxide semiconductor film 104 in which the hydrogen concentration and oxygen defects are reduced can be formed.

[0099] The heat treatment is performed at a temperature such that hydrogen is released from the oxide semiconductor film and the oxide insulating film 102 is The temperature is preferably such that part of the oxygen contained in the oxide semiconductor film is released and diffused into the oxide semiconductor film. Typically, the temperature is 150° C. or higher and lower than the substrate strain point, preferably 250° C. or higher and 450° C. or lower, and more preferably Preferably, the temperature is 300°C or higher and 450°C or lower.

[0100] The heat treatment is carried out using an RTA (Rapid Thermal Anneal) device. By using RTA, it is possible to heat treat the substrate at a temperature above its distortion point for a short period of time. Therefore, hydrogen can be released from the oxide semiconductor film and the oxide insulating film 1 can be The time required for oxygen diffusion from the oxide semiconductor film 102 to the oxide semiconductor film 103 can be shortened.

[0101] The heat treatment can be carried out in an inert gas atmosphere, typically helium, neon, or arsenic. It is preferable to carry out the treatment in an atmosphere of a rare gas such as argon, xenon, or krypton, or in a nitrogen atmosphere. The treatment may be carried out in an oxygen atmosphere or a reduced pressure atmosphere. The treatment time is 3 minutes to 24 hours.

[0102] Oxygen vacancies in the oxide semiconductor film act as donors, generating electrons as carriers. By performing heat treatment in a state where the oxide semiconductor film 103 covers the oxide insulating film 102, the oxide insulating film 102 is A part of the oxygen contained in the insulating film 102 diffuses into the oxide semiconductor film 103, and the oxide semiconductor In addition, the oxide insulating film 102 can reduce oxygen vacancies in the oxide film 103. Since the surface of the oxide insulating film 102 is covered with the semiconductor film 103 and is not exposed, The amount of oxygen released from the insulating film 102 to the outside without diffusing into the oxide semiconductor film 103 can be reduced. Therefore, oxygen defects in the oxide semiconductor film and the oxide insulating film 102 and the oxide semiconductor film 103 are formed. The interface state density at the interface can be reduced.

[0103] In addition, in the deposition process of the oxide semiconductor film 103, the pressure of the treatment chamber and the leak rate of the treatment chamber By suppressing the inclusion of impurities as much as possible, the oxide insulating film 102 and the oxide semiconductor It is possible to reduce the amount of impurities, including hydrogen, contained in the insulating film 103. Diffusion of impurities including hydrogen from the film 102 to the oxide semiconductor film 103 can be reduced. Furthermore, the heat treatment can reduce the hydrogen concentration in the oxide semiconductor film 103. In nitride semiconductors, some of the hydrogen atoms become donors and act as carriers due to bonding with hydrogen. Therefore, electrons are generated during the oxide semiconductor film formation process and the subsequent heating process. In this case, impurities, typically hydrogen, are significantly reduced, thereby reducing defects in the oxide semiconductor film. It is possible to do this.

[0104] Next, a mask is formed over the oxide semiconductor film 104, and then the oxide semiconductor film 104 is The oxide semiconductor film 104 is selectively etched to form the oxide semiconductor film 105 (see FIG. 2(C)). (see).

[0105] The mask for etching the oxide semiconductor film 104 is formed by a photolithography process. A jet method, a printing method, or the like can be used as appropriate. Wet etching or dry etching can be used as appropriate. If a remover is used to remove the mask, the oxide semiconductor film 10 Since oxygen may be released from the side of the mask, ashing is not used to remove the mask. That's fine.

[0106] Next, as shown in FIG. 2D, an oxide insulating film 102 and an oxide semiconductor film 105 are formed on the oxide insulating film 102 and the oxide semiconductor film 105. The oxide insulating film 106 is formed by heating the oxide insulating film 106 to form an insulating film 106. As with the oxide insulating film 102, the oxide insulating film 106 is formed by heating the oxide insulating film 106 to form an insulating film 106. The insulating film is formed using an oxide insulating film from which part of the oxygen is released by heating. As the insulating film, an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric ratio is used. is preferred.

[0107] The oxide insulating film 106 may be formed by a method similar to that for forming the oxide insulating film 102. Note that when the oxide insulating film 106 is formed, the oxide semiconductor film 105 In order to reduce the amount of oxygen desorbed from the side, the deposition temperature of the oxide insulating film 106 is set as low as possible. It is desirable to form the film at a low temperature, preferably at room temperature.

[0108] Even if oxygen defects are generated on the side surfaces of the oxide semiconductor film 105 due to oxygen desorption, By using an oxide insulating film from which part of oxygen is released by heat as the oxide insulating film 106, By this heat treatment, oxygen defects on the side surfaces of the oxide semiconductor film 105 can be reduced. do.

[0109] Next, a mask is formed over the oxide insulating film 106, and then the oxide insulating film 106 is The mask is then selectively etched to form a protective film 107. After this, the mask is removed (FIG. 2 The protective film 107 covers at least the edge of the oxide semiconductor film 105. In the subsequent manufacturing steps, the side surfaces of the oxide semiconductor film 105 are not exposed to a reduced-pressure atmosphere. In addition, in a subsequent etching step, the sidewall of the oxide semiconductor film 105 is exposed to an etchant. As a result, oxygen desorption from the side surface of the oxide semiconductor film 105 and the resulting In addition, the side surface of the oxide semiconductor film 105 and the pair of electrodes can be prevented from being generated. Since the oxide semiconductor film 105 does not come into contact with the electrode 109, the leakage current in the region near the side surface of the oxide semiconductor film 105 is reduced. The occurrence of current can be suppressed.

[0110] Next, as shown in FIG. 3(A), a pair of electrodes 109 are printed by a printing method or an ink-jet method. Alternatively, after forming a conductive film by a sputtering method, a CVD method, a vapor deposition method, etc., A mask is formed over the conductive film and the conductive film is etched to form a pair of electrodes 109 . The mask formed on the conductive film is formed by a printing method, an inkjet method, or a photolithography method as appropriate. In addition, when the pair of electrodes 109 is formed using a mask, Remove the mask.

[0111] Next, as shown in FIG. 3B, the oxide semiconductor film 105, the protective film 107, and the pair of electrodes After forming a gate insulating film 111 on the substrate 109, a gate electrode 11 is formed on the gate insulating film 111. Form 3.

[0112] The gate insulating film 111 is formed by a thermal oxidation method, a CVD method, a sputtering method, or the like.

[0113] The gate electrode 113 is formed by a printing method or an ink jet method. After forming a conductive film by a deposition method, a CVD method, a vapor deposition method, or the like, a mask is formed on the conductive film. The conductive film is etched to form the gate electrode 113. The mask formed on the conductive film is Printing, inkjet printing, and photolithography can be used as appropriate. If the gate electrode 113 is formed using a mask, the mask is then removed.

[0114] Next, as shown in FIG. 3C, a process of adding a dopant to the oxide semiconductor film 105 is performed. Thus, regions 115 and 117 containing dopants are formed. By adding dopants using the electrode 109 as a mask, dopants are self-aligned. The dopant-containing regions 115, 117 and the oxide regions 118, 119 are doped with dopant. The compound semiconductor regions 119, 121, and 123 can be formed. The regions 115 and 117 function as electric field relaxation regions. A pair of dopant-containing regions 115 and 117 and a pair of oxide semiconductor regions 121 and 122 3 is an oxide semiconductor film 120.

[0115] A dopant can be added to the oxide semiconductor film 105 by ion doping or ion doping. The dopant to be added can be an on-implantation method. Group 15 elements such as nitrogen, phosphorus, or arsenic, hydrogen, helium, neon, argon, chlorine, At least one of the pair of electrodes 109 is selected from the group consisting of lipton and xenon. The gate electrode 113 serves as a mask, and the dopant regions 115 and 117 containing dopants, regions overlapping the gate electrode 113 and containing dopants; The oxide semiconductor region 119 sandwiched between the electrodes 115 and 117 overlaps with the pair of electrodes 109 and The oxide semiconductor regions 121 and 123 sandwiching the dopant-containing regions 115 and 117 are self-aligned. It can be formed in a line.

[0116] In addition, the dopant is added to the oxide semiconductor film 105. Although the insulating film and the like are formed, the oxide semiconductor film 103 is exposed. Dopants may be added in this state.

[0117] Furthermore, the dopant is added by ion doping or ion implantation. For example, a gas atmosphere containing the element to be added can be used. By generating plasma in the atmosphere and treating the material with plasma, The plasma generating device may be a dry etchant. A chipping device, a plasma CVD device, a high density plasma CVD device, etc. can be used. .

[0118] Next, the insulating film 125 is formed and subjected to a heat treatment. The insulating film 125 is formed by, for example, a thermal oxidation method, a C The heat treatment is typically performed by a VD method, a sputtering method, or the like. is 150°C or higher and 450°C or lower, preferably 250°C or higher and 325°C or lower. The temperature may be gradually increased from 250°C to 325°C.

[0119] By the heat treatment, oxygen diffuses from the protective film 107 to the oxide semiconductor film 120, and the oxide semiconductor It is possible to reduce oxygen defects on the side surfaces of the conductive film 120. The resistance of the regions 115 and 117 can be reduced. The punt-containing regions 115, 117 may be in a crystalline or amorphous state.

[0120] Here, the ease of oxygen vacancies on the top surface and side surface of the oxide semiconductor film is examined using the following model. The results of the calculations performed using the model are explained below. However, since there are multiple crystal faces on one side, the calculation becomes complicated. Therefore, here, The calculation was carried out using a ZnO single crystal with an oriented wurtzite structure. As shown in Figure 27, the crystal was cut along a plane parallel to the c-axis and a plane perpendicular to it, and the (001) surface and The (100) surface and the (110) surface were prepared.

[0121] After the surface structure was fabricated, the (100) surface, ( The calculations were carried out for oxygen escaping from the (110) and (001) surfaces, and the ease of escaping was calculated. was compared for each surface.

[0122] A model was created in which the crystal structure was cut so that the (001) plane was the surface. To perform the experiment with a three-dimensional periodic structure, a vacuum region with two (001) surfaces is formed in a slab model with a size of 1 nm. Similarly, the side surface is assumed to be perpendicular to the (001) plane. As an example, a slab model was created with the (100) and (110) planes on the surface. By calculating the surface, it is possible to see the tendency of oxygen escaping on the surface perpendicular to (001). In this case, the vacuum region is 1 nm. The number of atoms is (100) surface model, (1 10) The surface model and the (001) surface model were set to 64, 10, and 10 atoms, respectively. In addition, we created structures in which oxygen was removed from the surfaces of the above three structures.

[0123] The calculation was performed using the density functional theory program CASTEP. The plane wave basis pseudopotential method was used, and the functional was GGAPBE. The structure was optimized, including the lattice constant, in a four-atom unit cell. The surface structure was then fabricated based on the structure that had been fabricated. The structure with and without defects was optimized with the lattice constant fixed. The energy used is that after structural optimization.

[0124] The cutoff energy is 380 eV for the unit cell calculation and 500 eV for the surface structure calculation. 300 eV was used. The k-point was calculated using a unit cell of 9x9x6 and a (100) surface. 3×2×1 for the model calculation, 1×2×2 for the (110) surface model calculation, (001) The surface model calculation used 2x2x1.

[0125] Add the energy of the structure with oxygen vacancies and half the energy of the oxygen molecule to the surface structure above. The energy difference (here, the binding energy) is calculated by subtracting the energy of the structure without oxygen vacancies from the value obtained by the calculation. It can be said that oxygen escapes easily from a surface with a small binding energy. do.

[0126]

number

[0127] The binding energies of each surface obtained by Equation 2 are shown in Table 1.

[0128] [Table 1]

[0129] From the results shown in Table 1, the (100) and (110) surfaces are more constrained than the (001) surface. The energy is small and oxygen is easily released. It can be seen that oxygen escapes more easily from the side surface than from the top surface of the c-axis oriented ZnO film. ZnO, an example of an AAC oxide semiconductor, also has a mixture of various crystal planes. The side surfaces of the ZnO single crystal have the same crystal faces as those of the ZnO single crystal. It can be said that this tendency is similar to the ease with which the base comes off.

[0130] In addition, when the oxide semiconductor film is selectively etched, for example, by dry etching, When the side surface of the oxide semiconductor film is exposed to plasma containing chlorine radicals, fluorine radicals, and the like, Metal atoms exposed on the side surfaces of the oxide semiconductor film are bonded to chlorine radicals, fluorine radicals, etc. At this time, metal atoms are bonded to chlorine atoms and fluorine atoms, and then released, forming an oxide semiconductor. The oxygen atoms that are bonded to the metal atoms in the membrane become activated. Therefore, oxygen vacancies are likely to occur on the side surfaces of the oxide semiconductor film. .

[0131] For these reasons, in the transistor described in this embodiment, part of oxygen is released by heating. After an oxide semiconductor film is formed over the oxide insulating film, heat treatment is performed to form a thin film in the oxide semiconductor film. and reducing oxygen defects in the oxide insulating film and interface states at the interface between the oxide insulating film and the oxide semiconductor film. In addition, after selectively etching the oxide semiconductor film, the etched oxide As a protective film covering the edge of the semiconductor film, an oxide insulating film from which part of the oxygen is released by heating is used. As a result, the side surface of the etched oxide semiconductor film is formed in a reduced pressure atmosphere and an etching atmosphere. Since the oxide semiconductor film is not exposed to the oxygen, the generation of oxygen defects on the side surfaces of the oxide semiconductor film can be reduced. Furthermore, the subsequent heating process causes oxygen diffusion from the protective film to the oxide semiconductor film. Therefore, even if oxygen defects occur on the side surfaces of the oxide semiconductor film, the oxygen defects can be compensated for. As a result, the negative shift of the threshold voltage of the transistor can be reduced. Furthermore, it is possible to reduce leakage current at the source and drain of the transistor. This can improve the electrical characteristics of the transistor.

[0132] (Embodiment 2) In this embodiment, the transistor shown in FIG. 1 is manufactured by a manufacturing method different from that in Embodiment 1. The manufacturing method will be described with reference to FIGS.

[0133] As in the first embodiment, an oxide insulating film 102 is formed on a substrate 101 as shown in FIG. Next, the oxide semiconductor film 103 is formed over the oxide insulating film 102. The film 102 and the oxide semiconductor film 103 are preferably formed in succession. The oxide insulating film 102 is formed in a multi-chamber sputtering apparatus having a After that, the oxide insulating film 102 was heated in a heating apparatus to desorb hydrogen, and then, The oxide semiconductor film 103 may be formed on the insulating film 104.

[0134] Next, a mask is formed over the oxide semiconductor film 103, and then the oxide semiconductor film 103 is The oxide semiconductor film 103 is selectively etched to form the oxide semiconductor film 131. Next, the oxide insulating film 106 is formed on the oxide semiconductor film 131 (FIG. 4(B)). The oxide insulating films 102 and 106 are formed by oxidation, in which part of oxygen is released by heat. The oxide insulating film from which part of the oxygen is released by heating is formed using a chemical It is preferable to use an oxide insulating film containing more oxygen than the stoichiometric ratio.

[0135] Next, the substrate 101 is subjected to heat treatment to release hydrogen from the oxide semiconductor film 131. Part of oxygen contained in the oxide insulating films 102 and 106 is oxidized to the oxide semiconductor film 1 31 and the oxide semiconductor film 131 near the interface between the oxide insulating film 102 and the oxide insulating film 106. As a result, the hydrogen concentration and oxygen defects are reduced as shown in FIG. In this way, the oxide semiconductor film 105 can be formed.

[0136] In this embodiment, the oxide insulating film 102 and the oxide insulating film 106 are different from those in the first embodiment. The difference is that oxygen is diffused from the oxide semiconductor film 131 to the oxide semiconductor film 132. Not only the surface of the oxide semiconductor film 131 but also the side surface of the oxide semiconductor film 131 is covered with the oxide insulating film 106. Therefore, the heat treatment can remove oxygen defects and oxides in the oxide semiconductor film 131. The interface states at the interfaces between the semiconductor film 131 and the oxide insulating films 102 and 106 are reduced. In addition, oxygen is supplied to oxygen defects on the side surfaces of the oxide semiconductor film 131, so that the oxide semiconductor Even if oxygen defects occur on the side surfaces of the body film 131, the oxygen defects can be compensated for.

[0137] Further, by providing a blocking film over the oxide insulating film 106, the oxide insulating film 106 can be prevented from being oxidized in the heat treatment. The blocking film 106 can prevent oxygen from being released to the outside. Examples of the film include silicon nitride film, silicon nitride oxide film, aluminum oxide film, and aluminum nitride film. , aluminum oxide nitride film, aluminum nitride oxide film, diamond-like carbon, etc. be.

[0138] Next, a mask is formed over the oxide insulating film 106, and then the oxide insulating film 106 is The protective film 107 is formed by selectively etching the protective film 107 (see FIG. 4(D)). covers at least the edge of the oxide semiconductor film 105. Therefore, the side surfaces of the oxide semiconductor film 105 are not exposed to a reduced pressure atmosphere. In the etching step, the sidewall of the oxide semiconductor film 105 is not exposed to the etchant. As a result, oxygen desorption from the side surface of the oxide semiconductor film 105 and the resulting generation of oxygen defects are prevented. In addition, the side surfaces of the oxide semiconductor film 105 are not in contact with the pair of electrodes 109. Therefore, generation of leakage current in the region near the side surface of the oxide semiconductor film 105 can be suppressed. This can be done.

[0139] After this, by going through the process shown in Figure 3, the threshold voltage is shifted negatively and the Therefore, it is possible to fabricate a transistor with reduced leakage current at the source and drain. do.

[0140] (Embodiment 3) In this embodiment, a method for manufacturing a transistor different from those in Embodiments 1 and 2 will be described. 3, 5 and 6, the transistor shown in the first embodiment will be described. Although this will be described as another embodiment of the method for manufacturing a capacitor, the second embodiment can be applied as appropriate. 6A and 6B are top views of the insulating film 145 in the manufacturing process. This corresponds to the cross section of line AB.

[0141] As in the first embodiment, after the steps of FIGS. 2(A) to 2(D), the process shown in FIGS. 5(A) and 6 As shown in FIG. 5(B), an insulating film 145 having openings 141 and 143 is formed. As shown in the figure, a conductive film 147 is formed over the oxide semiconductor film 105 and the insulating film 145. The film 147 can be formed using the material and manufacturing method of the pair of electrodes 109 described in Embodiment 1 as appropriate. can be done.

[0142] Next, similarly to Embodiment 1, a mask is formed over the conductive film 147, and then the mask is used to The conductive film 147 is selectively etched to form the pair of electrodes 109. The insulating film 145 is etched to cover the end of the semiconductor film 105, thereby forming a protective film 107. Through the above steps, the protective film 107 covering the edge of the oxide semiconductor film 105 and the oxide semiconductor film 106 are formed. A pair of electrodes 109 can be formed in contact with the conductive film 105. The protective film 107 is formed by oxidation. In order to cover the edge of the oxide semiconductor film 105, the side of the oxide semiconductor film 105 is The surface is not exposed to a reduced pressure atmosphere. As a result, the sidewalls of the oxide semiconductor film 105 are not exposed to the etchant. This can prevent oxygen from being desorbed from the side and the resulting generation of oxygen defects. Since the side surfaces of the oxide semiconductor film 105 and the pair of electrodes 109 are not in contact with each other, This can suppress the occurrence of leakage current in the region near the side surface of the semiconductor device 5.

[0143] Thereafter, the same process as in the first embodiment is carried out through the process shown in FIG. A transistor is fabricated in which the voltage shift and leakage current at the source and drain are reduced. It can be manufactured.

[0144] (Fourth embodiment) In this embodiment, the structure of a transistor different from those in the first and second embodiments and The manufacturing method will be described with reference to FIGS. 2, 3, 7, and 8. Although this will be described as another embodiment of the method for manufacturing a transistor described in Embodiment 1, it will be appropriately applied to Embodiment 2. It can be used.

[0145] 7A and 7B are a top view and a cross-sectional view of the transistor described in this embodiment. 7B is a top view of a transistor shown in an embodiment, and FIG. 7B is a top view of a transistor shown in FIG. 7A is a cross-sectional view corresponding to line F. In FIG. 7A, in order to avoid complication, Some of the components of the transistor (such as the insulating film 153) are omitted.

[0146] The transistor shown in FIG. 7 includes an oxide insulating film 102 provided on a substrate 101 and an oxide insulating film 103. The oxide semiconductor film 120 provided on the insulating film 102 and the insulating film 103 covering the edge of the oxide semiconductor film 120 are a protective film 150, a part of which functions as a gate insulating film, and a a pair of electrodes 109 in contact with the oxide semiconductor film 120; The gate electrode 151 overlaps with the nitride semiconductor film 120. The insulating film 153 covers the oxide semiconductor film 120, the protective film 150, and the gate electrode 151. In addition, a pair of electrodes 109 are connected to the openings provided in the insulating film 153. The oxide semiconductor film 120 has an oxide semiconductor film 121 overlapping with the gate electrode 151. The oxide semiconductor region 119 is sandwiched between a pair of dopant-containing regions 1 15, 117, and a pair of electrodes 115, 117 sandwiching the pair of dopant-containing regions 115, 117. The pair of oxide semiconductor regions 121 and 123 are in contact with the oxide semiconductor region 09. The regions 115 and 117 including the pair of oxide semiconductor regions 121 function as electric field relaxation regions. , 123 function as source and drain regions.

[0147] In this embodiment, the protective film 150 covers the edge of the oxide semiconductor film 120 and also serves as a gate electrode. It is characterized by being used as an insulating film. As a result, the number of processes can be reduced. Since the gate electrode 151 and the pair of electrodes 109 are formed in the same layer, a part of the gate The scanning line, which is the electrode 151, and the signal line connected to the pair of electrodes 109 are arranged in a single line so as not to come into contact with each other. A pair of wirings 155 electrically connected to the pair of electrodes 109 and a part of which is the gate electrode 151 The scanning lines are intersected with an insulating film 153 interposed therebetween.

[0148] Next, a manufacturing method of the transistor shown in FIG. 7 will be described with reference to FIGS. 2A to 2C, 3A to 3C, and 8A to 8C. do.

[0149] As in the first embodiment, after the steps of FIGS. 2(A) to 2(D), as shown in FIG. After the insulating film 145 having the opening is formed, the oxide semiconductor film 105 and the insulating film 145 are A conductive film 147 is formed on the conductive film 147 .

[0150] Next, a mask is formed over the conductive film 147, and then the conductive film 147 is selectively removed using the mask. The pair of electrodes 109 and the gate electrode 151 are formed by etching. Next, a mask is applied to the pair of electrodes 109, the insulating film 145, and the gate electrode 151. After forming the pair of electrodes 109 and the insulating film 145 that is not covered with the gate electrode 151, The insulating film 145 is etched to cover the edge of the oxide semiconductor film 105. A protective film 150 is formed to cover the edge of the compound semiconductor film 105 and function as a gate insulating film. After this, the mask is removed.

[0151] Next, by the same process as in the first embodiment, the oxide semiconductor film 10 5 is subjected to a process of adding a dopant to form regions 115 and 117 containing the dopant. By adding dopants using the gate electrode 151 and the pair of electrodes 109 as a mask, As a result, the dopant-containing regions 115 and 117 are doped in a self-aligned manner. and forming oxide semiconductor regions 119, 121, and 123 to which no dopant is added. The regions 115 and 117 containing the dopant function as electric field relaxation regions. In addition, the oxide semiconductor region 119, the regions 115 and 117 containing a pair of dopants, and the The pair of oxide semiconductor regions 121 and 123 is referred to as an oxide semiconductor film 120 .

[0152] Next, the insulating film 153 is formed on the oxide semiconductor film 120, the pair of electrodes 109, and the protective film 150. After that, a mask is formed on the insulating film 153, and the insulating film 153 is selectively etched to form openings. After that, the mask is removed. Next, a pair of electrodes 10 are formed in the openings. A pair of wirings 155 in contact with the wiring 9 is formed, and heat treatment is performed (see FIG. 8(C)). By the treatment, oxygen diffuses from the protective film 150 to the oxide semiconductor film 120, The oxygen defects on the side surface of the dopant-containing region 11 can be reduced. 5, 117 can be reduced. The containing regions 115, 117 may be in a crystalline or amorphous state.

[0153] The insulating film 153 is formed using a material and a method similar to those of the insulating film 125 described in Embodiment 1, as appropriate. Alternatively, the insulating film 153 may be made of polyimide, acrylic resin, or epoxy resin. It may also be formed using an organic resin such as fat.

[0154] The pair of wirings 155 can be formed by using the same material and method as the pair of electrodes 109. Cut.

[0155] By the above process, the negative shift of the threshold voltage and the source and drain Therefore, a transistor with reduced leakage current in the drain can be manufactured.

[0156] (Embodiment 5) In this embodiment, a transistor having a structure different from those in Embodiments 1 to 4 and its The manufacturing method will be described with reference to FIGS.

[0157] 9A and 9B are a top view and a cross-sectional view of the transistor described in this embodiment. 9B is a top view of a transistor shown in an embodiment, and FIG. 9B is a top view of a transistor shown in FIG. 9(C) is a cross-sectional view corresponding to the dashed line IJ in FIG. 9(A). In FIG. 9A, the configuration elements of the transistors are not shown in order to avoid complication. Some elements (for example, the gate insulating film 211, the insulating film 225, etc.) are omitted.

[0158] The transistor shown in FIG. 9A includes an oxide insulating film 102 provided over a substrate 101 and an oxide insulating film 103. The oxide semiconductor film 220 is provided over the insulating film 102, and the oxide semiconductor film 220 is provided in contact with the oxide semiconductor film 220. The oxide semiconductor film 220 covers the pair of electrodes 209 and the end portions of the oxide semiconductor film 220. a protective film 207 covering the pair of electrodes 209 and the oxide semiconductor film 220; a gate insulating film 211 and a layer on the gate insulating film 211 that overlaps the oxide semiconductor film 220; The gate insulating film 211 and the gate electrode 213 are The oxide semiconductor film 220 may have an insulating film 225 covering the gate electrode 213. The oxide semiconductor region 219 overlaps with the pair of dopants sandwiching the oxide semiconductor region 219. and a pair of dopant-containing regions 215 and 217 sandwiched between the dopant-containing regions 215 and 217. The pair of oxide semiconductor regions 221 and 223 are in contact with the pair of electrodes 209. The semiconductor region 219 functions as a channel region, and the regions 215, 216 containing a pair of dopants The oxide semiconductor regions 221 and 223 function as a source region. and functions as a drain region.

[0159] The oxide semiconductor film 220, the pair of electrodes 209, the protective film 207, the gate insulating film 211, The gate electrode 213 and the insulating film 225 are formed by the same method as in Embodiment 1 except for the oxide semiconductor film 1 20, a pair of electrodes 109, a protective film 107, a gate insulating film 111, a gate electrode 113, and The same material as that of the insulating film 125 can be used as appropriate. The pair of dopant-containing regions 215 and 217 and the pair of oxide semiconductor regions 221 and 223 are The oxide semiconductor region 119 and the region 114 containing a pair of dopants, which are described in Embodiment 1, The oxide semiconductor regions 15 and 117 may be formed of the same material as that of the pair of oxide semiconductor regions 121 and 123. can.

[0160] Next, a manufacturing method of the transistor shown in FIG. 9 will be described with reference to FIGS. 10 and 11. .

[0161] As in the first embodiment, as shown in FIG. 10(A), an oxide insulating film 102 is formed on a substrate 101. Next, the oxide semiconductor film 103 is formed over the oxide insulating film 102. The insulating film 102 and the oxide semiconductor film 103 are preferably formed in succession. In a multi-chamber sputtering apparatus having a device, an oxide insulating film 102 is formed. Then, the oxide insulating film 102 is heated by a heating device to desorb hydrogen, and then the oxide insulating film 102 is The oxide semiconductor film 103 may be formed thereover.

[0162] Next, the substrate 101 is subjected to heat treatment to release more hydrogen from the oxide semiconductor film. Part of oxygen contained in the oxide insulating film 102 is transferred to the oxide semiconductor film and the oxide insulating film 102. As a result, as shown in FIG. 10(B), The oxide semiconductor film 104 in which the hydrogen concentration and oxygen defects are reduced can be formed.

[0163] Next, as shown in FIG. 10C, a pair of electrodes 209 is formed over the oxide semiconductor film 104. The pair of electrodes 209 is formed in the same manner as the pair of electrodes 109 described in Embodiment 1. can be done.

[0164] In this embodiment, after the oxide semiconductor film 103 is formed over the oxide insulating film 102, By performing heat treatment, part of oxygen contained in the oxide insulating film 102 is oxidized to the oxide semiconductor film and the oxide insulating film 102. The oxide semiconductor film 102 was diffused in the vicinity of the interface with the oxide semiconductor film. After forming the conductive film for forming the electrode 209, the heat treatment may be performed.

[0165] Next, a mask is formed over the oxide semiconductor film 104 and the pair of electrodes 209, and then the oxide semiconductor The oxide semiconductor film 104 is selectively etched to form an oxide semiconductor film 205 (FIG. 10(D) 9A.) Through this process, a pair of electrodes is formed as shown in the oxide semiconductor film 220 in FIG. The oxide semiconductor film 205 can be formed so as to overlap with the oxide semiconductor film 209 and be partly exposed. After that, the mask is removed. If a remover is used to remove the mask, the oxide semiconductor Since oxygen may be released from the side of the conductive film 205, assembling is recommended as a method for removing the mask. Ringing may also be used.

[0166] Next, as shown in FIG. 11A, an oxide semiconductor film 205 and a pair of electrodes 209 are formed on the oxide semiconductor film 205. An insulating film 206 is formed. The oxide insulating film 206 has the same structure as the oxide insulating film 106 described in Embodiment 1. Similarly, the insulating film is formed using an oxide insulating film from which part of oxygen is released by heating. The oxide insulating film from which part of the film is desorbed is an oxide film containing more oxygen than the stoichiometric ratio. It is preferable to use an insulating film made of silicon dioxide.

[0167] Even if oxygen defects are generated on the side surfaces of the oxide semiconductor film 205 due to oxygen desorption, the oxide semiconductor film 205 is oxidized. By using an oxide insulating film that releases part of the oxygen by heat as the insulating film 206, By this treatment, oxygen defects on the side surfaces of the oxide semiconductor film 205 can be reduced.

[0168] Next, a mask is formed over the oxide insulating film 206, and then the oxide insulating film 206 is is selectively etched to form a protective film 207. After this, the mask is removed (FIG. 1 1(B)). This step covers a part of the pair of electrodes 209 and also A protective film 207 can be formed to cover the end portion of the oxide semiconductor film 205 exposed from the surface of the insulating film 209. As a result, in a subsequent manufacturing step, the side surface of the oxide semiconductor film 205 is exposed to a reduced-pressure atmosphere. In addition, in a subsequent etching step, the sidewall of the oxide semiconductor film 205 is not etched. Furthermore, after the pair of electrodes is formed, the oxide semiconductor film 104 is The oxide semiconductor film 205 is formed by etching, and then the side surface of the oxide semiconductor film 205 is To form a covering insulating film, an oxide semiconductor film is formed to overlap with the pair of electrodes. As a result, oxygen desorption from the side surface of the oxide semiconductor film 205 and the resulting generation of oxygen defects are prevented. The side surfaces of the oxide semiconductor film 205 and the pair of electrodes 209 are prevented from coming into contact with each other. Therefore, the occurrence of leakage current in the region near the side surface of the oxide semiconductor film 205 can be suppressed. can be done.

[0169] Next, as shown in FIG. 11C, similarly to Embodiment 1, the oxide semiconductor film 205 and the protective film After forming a gate insulating film 211 on the film 207 and the pair of electrodes 209, A gate electrode 213 is formed on the layer 211 .

[0170] Next, as shown in FIG. 11(D), a process for adding a dopant to the oxide semiconductor film 205 is performed. The gate electrode 213 and a pair of dopant-containing regions 215 and 217 are formed. By adding dopants using the electrode 209 as a mask, dopants are deposited in a self-aligned manner. The dopant-containing regions 215, 217 are doped with dopant, and the oxide regions 216 are doped with dopant. The oxide semiconductor regions 219, 221, and 223 can be formed. The regions 215 and 217 function as electric field relaxation regions.

[0171] Next, an insulating film 225 is formed and subjected to heat treatment. Oxygen diffuses into the oxide semiconductor film 205, reducing oxygen defects on the side surfaces of the oxide semiconductor film. In addition, oxygen desorption from the oxide semiconductor film 205 can be reduced. The resistance of the regions 215 and 217 containing the punt can be reduced. In this case, the dopant-containing regions 215, 217 may be in a crystalline or amorphous state.

[0172] By the above steps, the negative shift of the threshold voltage and the source and drain Therefore, a transistor with reduced leakage current in the drain can be manufactured.

[0173] (Embodiment 6) In this embodiment, a transistor having a structure different from those in Embodiments 1 to 5 will be described. This will be explained using FIG.

[0174] A cross-sectional structure of the transistor described in this embodiment will be described with reference to FIG.

[0175] The transistor shown in FIG. 12 includes an oxide insulating film 102 provided on a substrate 101 and an oxide insulating film 103. One 161 of a pair of electrodes provided on the membrane 102 and an acid in contact with the one 161 of the pair of electrodes. The oxide semiconductor film 163, an end portion of the oxide semiconductor film 163, and a part of one of the pair of electrodes 161 a protective film 165 that covers the oxide semiconductor film 163; The other electrode 167, the protective film 165, the oxide semiconductor film 163, and the other electrode A gate insulating film 169 covers the side 167, and an oxide semiconductor film 16 3 and a gate electrode 171 overlapping the gate insulating film 169 and the gate electrode 1 An insulating film 173 may be provided to cover the insulating film 71 .

[0176] The oxide semiconductor film 163 includes an oxide semiconductor region 175 overlapping with the gate electrode 171 and an oxide semiconductor region 176 overlapping with the gate electrode 171. A pair of dopant-containing regions 177 and 179 sandwiching a compound semiconductor region 175; The electrodes 161 and 167 are connected to each other and sandwich the areas 177 and 179 including the conductors. The oxide semiconductor region 175 has a pair of oxide semiconductor regions 181 and 183. The regions 177 and 179 function as a channel region and contain a pair of dopants. The pair of oxide semiconductor regions 181 and 183 function as a source region and a drain region. It functions as such.

[0177] Next, a manufacturing method of the transistor described in this embodiment will be described below. This will be described as an application of the method for manufacturing a transistor shown in Embodiment 1. The present invention can be applied to the second to fifth embodiments as appropriate.

[0178] In the transistor described in this embodiment, an oxide semiconductor film 103 is formed over an oxide insulating film 102. Before that, one of the pair of electrodes 161 is formed. Next, through the same process as in the first embodiment, After forming a protective film 165 on the selectively etched oxide semiconductor film, a pair of electrodes The other 167 is then formed. After that, similarly to the first embodiment, a gate insulating film 169 and a gate The electrode 171 is formed. Next, the gate electrode, the protective film 165, and the other of the pair of electrodes 167 are formed. By adding dopants using the mask, the oxide semiconductor region 175 and the pair of dopants are formed. and a pair of oxide semiconductor regions 181 and 183. After that, the insulating film 173 is formed, and then, Heat treatment may be performed in the same manner as in the first embodiment.

[0179] Through the above steps, the transistor shown in FIG. 12 can be manufactured.

[0180] (Embodiment 7) In this embodiment mode, a method for manufacturing a protective film different from those in Embodiment Modes 1 to 6 will be described. This will be explained using FIG.

[0181] As shown in FIG. 13(A), an oxide insulating film 102 is formed on a substrate 101. An insulating oxide film 191 serving as a protective film is formed on the insulating oxide film 102. 13(D) in a region where an oxide semiconductor film 197 to be formed later is located. In this step, the oxide insulating film 102 is formed to be exposed.

[0182] Like the oxide insulating film 102, the oxide insulating film 191 is an oxide insulating film in which part of oxygen is released by heat. As an oxide insulating film from which part of the oxygen is released by heating, a stoichiometric It is preferable to use an oxide insulating film containing more oxygen than the oxygen that satisfies the ratio.

[0183] Next, as shown in FIG. 13B, an oxide semiconductor film was formed on the oxide insulating film 102 and the oxide insulating film 191. A conductive film 192 is formed. After that, similarly to the first embodiment, a heat treatment is performed to form an oxide semiconductor. Hydrogen is released from the conductive film 192, and hydrogen contained in the oxide insulating film 102 and the oxide insulating film 191 is released. The oxide semiconductor film 192, the oxide insulating film 102, and the oxide insulating film 191 13C. As described above, the oxide semiconductor film 193 in which the hydrogen concentration and oxygen defects are reduced can be formed. (See Figure 13(C)).

[0184] Next, at least the oxide semiconductor film 193 is polished to remove the influence of the thickness of the oxide insulating film 191. First, the oxide semiconductor film 197 has a flat surface, and the oxide semiconductor film 197 has a thickness similar to that of the oxide semiconductor film 197. In addition, the protective film 195 can be formed with a flat surface similar to that of the oxide semiconductor film 197. The side surfaces of the oxide semiconductor film 197 are formed with oxide insulating films from which part of oxygen is released by heating. Since the oxide semiconductor film 197 is in contact with the protective film 195, the oxide semiconductor film 197 has oxygen defects on its side surface. However, oxygen defects can be reduced by subsequent heat treatment.

[0185] As a result, the unevenness of the surface with the protective film is small, and oxygen defects on the side surfaces can be reduced. Therefore, an oxide semiconductor film that can be formed on the oxide semiconductor film 197 can be formed later. The thickness of the gate insulating film to be formed can be reduced. In this embodiment, the oxide insulating film 102 is The oxygen supply method to the oxide semiconductor film is the same as that in Embodiment 1. After forming an oxide insulating film over the oxide semiconductor film 192, heat treatment is performed to form the oxide semiconductor film Oxygen is supplied to the oxide semiconductor film 192 from the oxide insulating films sandwiching the oxide semiconductor film 192. The oxide insulating film and the oxide semiconductor film are etched to form a protective film. Therefore, an oxide semiconductor film having small unevenness on the surface and reduced oxygen defects can be formed. Cut.

[0186] (Embodiment 8) In this embodiment, the oxide semiconductor films 103 and 192 described in Embodiments 1 to 7 are A method for forming a CAAC film using an oxide semiconductor will be described. The following description will be given using the compound semiconductor film 103.

[0187] The first method for forming the oxide semiconductor film 103 using a CAAC oxide semiconductor is as follows. Explained below.

[0188] The method for forming the oxide semiconductor film 103 using a CAAC oxide semiconductor is the same as that described in Embodiment 1. In the method for forming the oxide semiconductor film 103 shown in FIG. 1, when a sputtering method is used, the substrate temperature is By setting the temperature at 150°C or higher and 450°C or lower, preferably 200°C or higher and 350°C or lower, the oxide While preventing the intrusion of moisture (including hydrogen) into the semiconductor film, A conductor can be formed.

[0189] After the oxide semiconductor film 103 is formed using the CAAC oxide semiconductor by the above-described formation method, The heat treatment allows hydrogen to be released from the oxide semiconductor film 103 and the oxide insulating film 1 The oxide semiconductor film 103, the oxide insulating film 102, and the oxide semiconductor film 104 are partially oxidized. The heat treatment can diffuse the conductor film 103 to the vicinity of the interface. The oxide semiconductor film 104 containing a CAAC oxide semiconductor with high crystallinity can be formed. do.

[0190] Next, a second method for forming the oxide semiconductor film 103 using a CAAC oxide semiconductor will be described. The following explains this.

[0191] A first oxide semiconductor film is formed over the oxide insulating film 102. The thickness is from a sublayer to 10 nm, preferably from 2 nm to 5 nm.

[0192] When the first oxide semiconductor film is formed, the substrate temperature is set to 150° C. or higher and 450° C. or lower, preferably 20 The temperature is preferably 0° C. or higher and 350° C. or lower. It is possible to reduce the amount of impurities such as moisture (including hydrogen) contained in the film. Furthermore, the crystallinity of the first oxide semiconductor film can be improved, and the CAAC oxide film with high orientation can be obtained. An oxide semiconductor film can be formed using an oxide semiconductor.

[0193] Note that first heat treatment may be performed after the first oxide semiconductor film is formed. By this mechanism, moisture (including hydrogen) can be released from the first oxide semiconductor film. Furthermore, the crystallinity can be improved. In addition, the first heat treatment can be performed for 200 °C or higher and lower than the strain point of the substrate, preferably 250°C or higher and 450°C or lower.

[0194] The first heat treatment is carried out using an RTA (Rapid Thermal Anneal) device. By using an RTA, it is possible to heat the substrate at a temperature above its strain point for a short period of time. Therefore, the ratio of crystalline regions to amorphous regions is high. The time required to form the semiconductor film can be reduced.

[0195] The first heat treatment can be carried out in an inert gas atmosphere, typically, helium, neodymium, or the like. It is preferable to carry out the treatment in an atmosphere of a rare gas such as argon, xenon, or krypton, or in a nitrogen atmosphere. The treatment may also be carried out in an oxygen atmosphere or a reduced pressure atmosphere. The treatment time is 3 minutes to 24 hours. As the treatment time increases, an oxide semiconductor film having a higher ratio of crystalline regions to amorphous regions is formed. However, heat treatment for more than 24 hours is not recommended as it reduces productivity. .

[0196] Next, a second oxide semiconductor film is formed over the first oxide semiconductor film. The film can be formed by a method similar to that for forming the first oxide semiconductor film.

[0197] When the second oxide semiconductor film is formed, the substrate is heated during the film formation, so that the first oxide semiconductor film The second oxide semiconductor film can be crystallized using the conductive film as a seed crystal. The first oxide semiconductor film and the second oxide semiconductor film are formed of the same elements and are called homo-growth. Alternatively, the first oxide semiconductor film and the second oxide semiconductor film may be made of at least one kind of oxide semiconductor. Composed of different elements is called heterogrowth.

[0198] Note that after the second oxide semiconductor film is formed, second heat treatment may be performed. The second heat treatment can be carried out in the same manner as the first heat treatment. The proportion of crystalline regions relative to amorphous regions can be increased in the oxide semiconductor film. By performing the second heat treatment, the first oxide semiconductor film is used as a seed crystal to form a second oxide semiconductor film. The semiconductor film can be crystallized. At this time, the first oxide semiconductor film and the second oxide semiconductor film The semiconductor film may be homo-grown, which is composed of the same element. The semiconductor film and the second oxide semiconductor film are composed of at least one different element. It's okay to call it terrorist growth.

[0199] By the above method, the oxide semiconductor film 103 can be formed using a CAAC oxide semiconductor. The hydrogen contained in the oxide semiconductor reacts with the oxygen that bonds with the metal atoms to form water. In addition, defects are formed in the lattice from which oxygen has been desorbed (or in the portion from which oxygen has been desorbed). Therefore, by significantly reducing the amount of impurities in the process of forming the oxide semiconductor film, It is possible to reduce defects in the semiconductor film. A channel region is formed by an oxide semiconductor film using highly purified CAAC oxide semiconductor. By creating a transistor, the change in threshold voltage before and after light irradiation and BT test can be measured. It can have stable electrical properties with a small amount.

[0200] Note that in the first heat treatment and the second heat treatment, the oxide insulating film 102 is converted into an oxide semiconductor. Oxygen may diffuse into the conductive film. In this case, the process between Fig. 2(A) and Fig. 2(B) Defects in the oxide semiconductor film 103 can be reduced without heat treatment. The number of heating steps can be reduced.

[0201] (Embodiment 9) FIG. 14A is a circuit diagram of a memory element (hereinafter also referred to as a memory cell) included in a semiconductor device. As an example, the memory cell may be made of a material other than an oxide semiconductor (e.g., silicon, germanium). , silicon carbide, gallium arsenide, gallium nitride, organic compounds, etc.) in the channel formation region Transistor 1160 using an oxide semiconductor and Transistor 1 using an oxide semiconductor for a channel formation region It consists of 162.

[0202] The transistor 1162 in which an oxide semiconductor is used for a channel formation region is The semiconductor device can be manufactured according to the method of embodiment 8. Note that when an oxide semiconductor is used for the channel formation region, The transistor is denoted as OS in the drawing.

[0203] As shown in FIG. 14A, the gate electrode of the transistor 1160 and the The first electrode is electrically connected to one of the source electrode and the drain electrode of the second electrode. The wiring SL (1st Line: also called the source line) and the source electrode of the transistor 1160 The second wiring BL (also called the bit line) and the The third wiring is electrically connected to the drain electrode of the transistor 1160. S1 (also called the 3rd Line: first signal line) and the source electrode of the transistor 1162 The other of the drain electrodes is electrically connected to a fourth line S2 (4th Line: The second signal line is electrically connected to the gate electrode of the transistor 1162. There are.

[0204] A transistor using a material other than an oxide semiconductor, such as single-crystal silicon, in the channel formation region. Since the transistor 1160 can operate at a sufficiently high speed, by using the transistor 1160, It is possible to read out stored contents at high speed. The transistor 1162 used in the formation region has a smaller off-state current than the transistor 1160. Therefore, by turning off the transistor 1162, Therefore, the potential of the gate electrode of the transistor 1160 can be maintained for a very long time. It is Noh.

[0205] By utilizing the feature that the potential of the gate electrode can be maintained, it is possible to write information, It can be stored and read.

[0206] First, writing and holding of data will be described. First, the potential of the fourth wiring S2 is set as follows: The transistor 1162 is turned on as a potential at which the transistor 1162 is turned on. As a result, the potential of the third wiring S1 is applied to the gate electrode of the transistor 1160. After that, the potential of the fourth wiring S2 is set to a value that the transistor 1162 is in an off state. By turning off the transistor 1162, the transistor The potential of the gate electrode 1160 is maintained (retained).

[0207] Since the off-state current of the transistor 1162 is extremely small, the gate voltage of the transistor 1160 For example, the potential of the gate electrode of the transistor 1160 is maintained for a long time. If the potential is a potential that turns on the transistor 1160, the transistor 1160 is turned on. The gate of transistor 1160 is maintained in the on state for a long time. If the potential of the electrode is a potential that turns off the transistor 1160, the transistor 116 The off state of 0 is maintained for a long period of time.

[0208] Next, the reading of information will be described. As described above, when the transistor 1160 is in the ON state, When the ON or OFF state is maintained, a predetermined potential (constant potential) is applied to the first wiring SL. When the transistor 1160 is turned on or off, the second wiring B For example, when the transistor 1160 is turned on, the potential of the first The potential of the first wiring SL approaches the potential of the second wiring BL. When the switch 1160 is in the off state, the potential of the second wiring BL does not change.

[0209] In this way, in the state where the information is held, the potential of the second wiring BL and a predetermined potential are By comparing, information can be read out.

[0210] Next, the rewriting of information will be explained. The rewriting of information is performed by writing and storing the above information. That is, the potential of the fourth wiring S2 is set to a value that is equal to or larger than the potential of the transistor 1162 when the transistor 1162 is turned on. The transistor 1162 is turned on by applying a potential to the third wiring The potential of S1 (the potential related to the new information) is applied to the gate electrode of transistor 1160. After that, the potential of the fourth wiring S2 is set to a potential that turns off the transistor 1162. By turning off the transistor 1162, the new data is held. become.

[0211] In this way, the memory cell according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. In other words, high-speed operation of the semiconductor device having memory cells is realized.

[0212] FIG. 14(B) shows an example of a circuit diagram of a memory cell which is an extension of the memory cell shown in FIG. 14(A). Shown below.

[0213] The memory cell 1100 shown in FIG. 14B has a first wiring SL (source line) and a second wiring BL (bit line), a third wiring S1 (first signal line), and a fourth wiring S2 (second signal line) a fifth wiring WL (word line), a transistor 1164 (first transistor), A transistor 1161 (second transistor) and a transistor 1163 (third transistor) The transistor 1164 and the transistor 1163 are A material other than an oxide semiconductor is used for a channel formation region. A compound semiconductor is used for the channel formation region.

[0214] Here, the gate electrode of the transistor 1164 and the source electrode of the transistor 1161 The first wiring SL is electrically connected to one of the drain electrodes. The source electrode of the transistor 1164 is electrically connected to the drain electrode of the transistor 1164. The electrode and the source electrode of the transistor 1163 are electrically connected to each other. The second wiring BL and the drain electrode of the transistor 1163 are electrically connected to each other. The wiring S1 and the other of the source electrode and the drain electrode of the transistor 1161 are electrically The fourth wiring S2 and the gate electrode of the transistor 1161 are electrically connected to each other. The fifth wiring WL and the gate electrode of the transistor 1163 are electrically connected. do.

[0215] Next, a specific example of the operation of the circuit will be described. The pressure and other figures may be changed as appropriate.

[0216] When writing to the memory cell 1100, the first wiring SL is set to 0 V, and the fifth wiring WL is set to The first wiring BL is set to 0V, the second wiring BL is set to 0V, and the fourth wiring S2 is set to 2V. When writing data "0", the third line S1 is set to 2V, and when writing data "0", the third line S1 is set to 0V. At this time, the transistor 1163 is in an off state and the transistor 1161 is in an on state. Note that, when writing is completed, the potential of the fourth wiring S1 is changed before the potential of the third wiring S1 is changed. The wiring S2 is set to 0 V, and the transistor 1161 is turned off.

[0217] As a result, after writing data "1", the node connected to the gate electrode of the transistor 1164 After writing data "0", the potential of node A is approximately 2V. The node A is charged according to the potential of the third wiring S1. As described above, the off-state current of the transistor 1161 is extremely small. The potential of the gate electrode is maintained for a long period of time.

[0218] Next, when reading the memory cell, the first wiring SL is set to 0V and the fifth wiring WL is set to 2V. V, the fourth wiring S2 is set to 0V, the third wiring S1 is set to 0V, and the At this time, the transistor 1163 is in an ON state, and the transistor Start 1161 is turned off.

[0219] If data is "0", that is, node A is at approximately 0V, transistor 1164 is in the off state. Therefore, the resistance between the second wiring BL and the first wiring SL is high. When the voltage at node A is "1", that is, when node A is at about 2 V, transistor 1164 is in an on state. Therefore, the resistance between the second wiring BL and the first wiring SL is low. Data "0" and "1" can be read out based on the difference in the resistance state of the recell. The second wiring BL was set to 0V when the voltage was increased, but it may be in a floating state or charged to a potential of 0V or higher. The third wiring S1 is set to 0V during readout, but it can be set to a floating state. It does not matter if the capacitor is charged to a potential above 0V.

[0220] Note that the definitions of data "1" and data "0" are for convenience, and they may be reversed. The above-mentioned operating voltage is an example. When the data is "1", the transistor 1164 is turned on. In this way, the transistor 1161 is turned on during writing and turned off during other times. Also, if the transistor 1163 is selected to be in an on state during reading, In particular, instead of 2V, the power supply potential VDD of the peripheral logic circuits may be used.

[0221] In this embodiment, for ease of understanding, a memory cell of the minimum storage unit (1 bit) will be explained. However, the configuration of the memory cells is not limited to this. For example, the memory cells can be connected in multiple ways to form a more sophisticated semiconductor device. By using these, it is possible to configure NAND type and NOR type semiconductor devices. The configuration is not limited to that shown in FIG. 14(A) or FIG. 14(B) and can be changed as appropriate.

[0222] FIG. 15 shows a block diagram of a semiconductor device according to one embodiment of the present invention having a storage capacity of m×n bits. The circuit diagram is shown.

[0223] The semiconductor device shown in FIG. 15 includes m fifth wirings WL(1) to WL(m) and m fourth wirings WL(2) to WL(m). The wirings S2(1) to S2(m), n second wirings BL(1) to BL(n), and n first wirings The wiring S1(1) to S1(n) of the three lines and the wiring S1(1) to S1(n) of the three lines arranged in a matrix of m vertical (rows) × n horizontal ( column) (m and n are natural numbers) memory cells 1100(1, 1) to 1100(m, n) The memory cell array 1110, the second wiring BL, and the third wiring S1 are connected to the driver circuit 1. 111, a driver circuit 1113 connected to the fourth wiring S2 and the fifth wiring WL, and a read circuit The circuit 1112 is also a peripheral circuit. A logic circuit or the like may be provided.

[0224] Consider memory cell 1100(i, j) as a representative of each memory cell. Rule 1100(i, j) (i is an integer between 1 and m, and j is an integer between 1 and n) is the second The wiring BL(j), the third wiring S1(j), the fifth wiring WL(i) and the fourth wiring S2(i ), and the first wiring SL. The first wiring SL is connected to the first wiring potential Vs In addition, the second wirings BL(1) to BL(n) and the third wiring S1(1) 1111 and the readout circuit 1112 connected to the second wiring BL and the third wiring S1. The fifth wirings WL(1) to WL(m) and the fourth wirings S2(1) to S2(m) are connected to the wiring circuit 1112. (m) is connected to the driving circuit 1113 via the fourth wiring S2 and the fifth wiring WL. It is being done.

[0225] The operation of the semiconductor device shown in Fig. 15 will be described. In this configuration, writing and reading for each row are performed. Make a presentation.

[0226] When writing to the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, The potential Vs of the first wiring SL is set to 0V, the potential Vs of the fifth wiring WL(i) is set to 0V, and the potential Vs of the second wiring BL(1) to BL(n) is set to 0 V, and the fourth wiring S2(i) is set to 2 V. At this time, the transistor 1161 The third wirings S1(1) to S1(n) are connected to the columns into which data "1" is written. The column to which data "0" is written is set to 2V, and the column to which data "0" is written is set to 0V. Before changing the potential of the third wiring S1(1) to S1(n), the fourth wiring S2(i) is set to 0V. The transistor 1161 is turned off. The fourth wire of the selection is set to 0V.

[0227] As a result, the gate voltage of the transistor 1164 of the memory cell in which data "1" is written is The potential of the node connected to the electrode (hereinafter referred to as node A) is about 2V, and data "0" is written. The potential of node A of the selected memory cell is approximately 0V. The position remains unchanged.

[0228] When reading out the memory cells 1100(i, 1) to 1100(i, n) in the i-th row, The potential Vs of the first wiring is set to 0 V, the potential of the fifth wiring WL(i) is set to 2 V, and the potential of the fourth wiring S2(i) is set to 0 V. V, the third wiring S1(1) to S1(n) are set to 0V, and the second wiring BL(1) to BL(n) The read circuit connected to the memory cell is set to an operating state. The difference in resistance state allows data "0" and "1" to be read out. The fifth wiring WL other than WL(i) is set to 0V, and the fourth wiring S2 other than the fourth wiring S2(i) is set to The second wiring BL is set to 0V during writing, but it can be set to a floating state or 0V. The third wiring S1 may be charged to a potential of 0 V or higher during readout. It may be in a floating state or charged to a potential of 0V or higher.

[0229] According to this embodiment, a node connected to a transistor using an oxide semiconductor for a channel region can be It is possible to maintain the voltage of the board for an extremely long period of time, so it consumes very little power. This makes it possible to manufacture a memory cell in which information can be written, held, and read.

[0230] (Embodiment 10) In this embodiment, an example of a circuit diagram of a memory cell having a capacitor is shown. The memory cell 1170 shown in FIG. 1 includes a first wiring SL, a second wiring BL, a third wiring S1, a fourth wiring S2, a The wiring S2, the fifth wiring WL, the transistor 1171 (first transistor), and the transistor The transistor 1172 (second transistor) and the capacitor element 1173 are included. The transistor 1171 uses a material other than an oxide semiconductor for a channel formation region. The transistor 1172 has a channel formation region formed using an oxide semiconductor.

[0231] The transistor 1172 in which an oxide semiconductor is used for a channel formation region is described in any one of Embodiments 1 to 8. It can be prepared according to the following.

[0232] Here, the gate electrode of the transistor 1171 and the source electrode of the transistor 1172 One of the drain electrodes is electrically connected to one of the electrodes of the capacitor 1173. The first wiring SL and the source electrode of the transistor 1171 are electrically connected. The second wiring BL and the drain electrode of the transistor 1171 are electrically connected to each other. The wiring 3 and the other of the source electrode and the drain electrode of the transistor 1172 are electrically connected to each other. The fourth wiring and the gate electrode of the transistor 1172 are electrically connected to each other. The fifth wiring and the other electrode of the capacitor 1173 are electrically connected to each other.

[0233] Next, the operation of the circuit will be specifically described.

[0234] When writing to the memory cell 1170, the first wiring SL is set to 0V, and the fifth wiring WL is set to The first wiring BL is set to 0V, the second wiring BL is set to 0V, and the fourth wiring S2 is set to 2V. When writing data "0", the third line S1 is set to 2V, and when writing data "0", the third line S1 is set to 0V. At this time, the transistor 1172 is turned on. In this case, before changing the potential of the third wiring S1, the fourth wiring S2 is set to 0 V, and the transistor START 1172 is turned off.

[0235] As a result, after writing data "1", the gate electrode of the transistor 1171 is connected to The potential of the node (hereinafter referred to as node A) is about 2V. After writing data "0", the potential of node A becomes approximately 0V.

[0236] When reading the memory cell 1170, the first wiring SL is set to 0 V, and the fifth wiring WL is set to 2V, the fourth wiring S2 is set to 0V, the third wiring S1 is set to 0V, and it is connected to the second wiring BL. The readout circuit is put into an operating state. At this time, the transistor 1172 is turned off. .

[0237] The state of the transistor 1171 when the fifth wiring WL is set to 2 V will be described. The potential of the node A that determines the state of the transistor 1171 is determined by the capacitance between the fifth wiring WL and the node A. C1 and the capacitance C2 between the gate electrode, source electrode, and drain electrode of the transistor 1171 Depends.

[0238] Although the third wiring S1 is set to 0V during reading, it may be set to a floating state or a potential of 0V or more. The definitions of data "1" and data "0" are for convenience only, and the reverse is not acceptable. It's okay if that's the case.

[0239] The potential of the third wiring S1 during writing is set to a value that is lower than the value that the transistor 1172 is turned off after writing. In addition, when the potential of the fifth wiring WL is 0V, the transistor 1171 is in an off state. The potential of the fifth line WL during reading can be selected from the range of 0 and 1. When the data is "0", the transistor 1171 is turned off, and when the data is "1", the transistor 1172 is turned off. For example, transistor 1171 may be selected so that it is turned on when The threshold voltage of the transistor 1171 may be set to the range where the state of the transistor 1171 is not changed. Any threshold voltage may be used as long as it is within this range.

[0240] Also, a selection transistor having a first gate electrode and a second gate electrode; An example of a NOR type semiconductor memory device using memory cells having the following structure will be described with reference to FIG. 16(B). I will explain.

[0241] The memory cell array shown in FIG. 16B has i rows (i is a natural number of 3 or more) and j columns (j is a natural number of 3 or more). A plurality of memory cells 1180 arranged in a matrix on the line WL (word lines WL_1 to WL_i) and i capacitance lines CL (capacitance lines CL_1 to CL_i) i), i gate lines BGL (gate lines BGL_1 to BGL_i), and j bit lines BL (bit lines BL_1 to BL_j) and source lines SL. For convenience, j is a natural number of 3 or more. The number of rows and columns is not limited to three or more. Alternatively, a memory cell array of two rows or two columns may be used.

[0242] The memory cell array shown in FIG. 16B has i rows (i is a natural number of 3 or more) and j columns (j is a natural number of 3 or more). A plurality of memory cells 1180 arranged in a matrix (a natural number of which is i) and i word lines W L (word lines WL_1 to WL_i), and i capacitance lines CL (capacitance lines CL_1 to CL_i). a capacitance line CL_i) and i gate lines BGL (gate lines BGL_1 to BGL _i), j bit lines BL (bit lines BL_1 to BL_j), and source lines SL and.

[0243] Furthermore, each of the plurality of memory cells 1180 (memory cells 1180(M,N) (where , N is a natural number between 1 and j, and M is a natural number between 1 and i) 1181(M,N), a capacitance element 1183(M,N), and a transistor 1182(M,N ) and.

[0244] In the semiconductor memory device, the capacitance element includes a first capacitance electrode, a second capacitance electrode, and The capacitance element is composed of a dielectric layer overlapping the first capacitance electrode and the second capacitance electrode. Charge is accumulated between the first and second capacitance electrodes in response to a voltage applied between the first and second capacitance electrodes.

[0245] The transistor 1181 (M, N) is an n-channel transistor, and has a source electrode, a drain electrode, and a The semiconductor device has a drain electrode, a first gate electrode, and a second gate electrode. In the semiconductor memory device, the transistor 1181 is not necessarily an n-channel transistor. You don't have to.

[0246] One of the source electrode and the drain electrode of the transistor 1181(M,N) is connected to the bit line BL _N, and the first gate electrode of the transistor 1181(M,N) is connected to the word line WL _M, and the second gate electrode of the transistor 1181(M,N) is connected to the gate line BG The source and drain electrodes of the transistor 1181(M,N) are connected to By configuring one of the terminals to be connected to the bit line BL_N, the The data can be read out.

[0247] The transistor 1181(M,N) is the selected transistor in the memory cell 1180(M,N). It functions as a register.

[0248] The transistor 1181(M,N) is a transistor using an oxide semiconductor for a channel formation region. In addition, in the transistor 1181(M, N), a source electrode, a drain electrode, a channel forming region, and a first gate electrode or a second gate electrode; The gate electrode may be formed by using any one of a pair of electrodes, an oxide semiconductor film, and a gate electrode described in any of Embodiments 1 to 8. The structure and manufacturing method of the pole can be appropriately applied.

[0249] The transistor 1182(M,N) is a P-channel transistor. In the semiconductor memory device of this embodiment, the transistor 1182 is not necessarily a p-channel transistor. It doesn't have to be star.

[0250] One of the source electrode and the drain electrode of the transistor 1182(M,N) is connected to the source line SL The other of the source electrode and the drain electrode of the transistor 1182(M,N) is connected to The gate electrode of the transistor 1182(M,N) is connected to the bit line BL_N. The other of the source electrode and drain electrode of the transistor 1181(M, N) is connected to the other of the source electrode and drain electrode of the transistor 1181(M, N).

[0251] The transistor 1182(M,N) is an output transistor in the memory cell 1180(M,N). The transistor 1182 (M, N) has a function as a single-circuit transistor. A transistor using crystalline silicon for a channel formation region can be used.

[0252] The first capacitance electrode of the capacitance element 1183(M,N) is connected to the capacitance line CL_M. The second capacitor electrode of 1183(M,N) is connected to the source electrode of the transistor 1181(M,N). The capacitor 1183(M,N) is connected to the other of the drain electrodes. It has the function as.

[0253] The voltages of the word lines WL_1 to WL_i are controlled by a driver using, for example, a decoder. It is controlled by an operating circuit.

[0254] The voltages of the bit lines BL_1 to BL_j are respectively controlled by a driver using a decoder, for example. It is controlled by an operating circuit.

[0255] The voltages of the capacitance lines CL_1 to CL_i are respectively controlled by a driving circuit using a decoder, for example. It is controlled by the path.

[0256] The voltages of the gate lines BGL_1 to BGL_i are respectively set by the gate line driving circuit, for example. It is controlled using a path.

[0257] The gate line driving circuit may be configured such that, for example, a diode and a first capacitor electrode are connected to the anode and It is configured by a circuit having a capacitance element electrically connected to the gate line BGL.

[0258] By adjusting the voltage of the second gate electrode of transistor 1181, transistor 1 Therefore, the threshold voltage of the transistor 181 that functions as a selection transistor can be adjusted. The threshold voltage of the transistor 1181 is adjusted to reduce the source voltage of the transistor 1181 in the off state. Therefore, the current flowing between the source electrode and the drain electrode can be minimized. The data retention period in the circuit can be extended. The voltage required for readout can be lower than that of conventional semiconductor devices, reducing power consumption It is possible.

[0259] According to this embodiment, a node connected to a transistor using an oxide semiconductor for a channel region can be formed. It is possible to maintain the voltage of the board for an extremely long period of time, so it consumes very little power. This makes it possible to manufacture a memory cell in which information can be written, stored, and read. In the memory cell array shown in FIG. 16B, instead of the memory cell 1180, 6(A) can be used. Wiring should be arranged appropriately to match 170.

[0260] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0261] (Embodiment 11) In this embodiment, an example of a semiconductor device including the transistor described in the above embodiment will be described. , will be described with reference to FIG.

[0262] Figure 17(A) shows a so-called DRAM (Dynamic Random Access Memory) An example of a semiconductor device having a structure corresponding to a memory cell shown in FIG. The memory cell array 1120 has a configuration in which a plurality of memory cells 1130 are arranged in a matrix. The memory cell array 1120 also includes m first wirings BL and n second wirings BL. In this embodiment, the first wiring BL is called a bit line BL. The second wiring WL is called a word line WL.

[0263] The memory cell 1130 is composed of a transistor 1131 and a capacitor element 1132. The gate electrode of the transistor 1131 is connected to the second wiring WL (word line WL). In addition, one of the source electrode and the drain electrode of the transistor 1131 is connected to the first The source electrode of the transistor 1131 is connected to the wiring BL (bit line BL). The other of the drain electrodes is connected to one of the electrodes of the capacitor element. The other electrode is connected to the capacitance line CL and is given a constant potential. The transistor described in the above embodiment is applied to the transistor.

[0264] The transistor in which an oxide semiconductor is used for a channel formation region, which is described in the above embodiment, The off-state current is smaller than that of a transistor using single crystal silicon for the channel formation region. Therefore, the so-called DRAM shown in FIG. When the transistor is applied to a semiconductor device, a substantially nonvolatile memory can be obtained. It is possible.

[0265] Figure 17(B) shows a so-called SRAM (Static Random Access Memory). An example of a semiconductor device having a structure corresponding to the memory cell shown in FIG. The array 1140 is configured such that a plurality of memory cells 1150 are arranged in a matrix. In addition, the memory cell array 1140 includes a first wiring BL and a second wiring BLB ( The memory cell has an inverted bit line, a third wiring WL, a power supply line Vdd, and a ground potential line Vss.

[0266] The memory cell 1150 includes a first transistor 1151, a second transistor 1152, and a third transistor 1153. The third transistor 1153, the fourth transistor 1154, and the fifth transistor 1155 , and a sixth transistor 1156. The transistor 1152 functions as a selection transistor. One of the first transistor 1153 and the fourth transistor 1154 is an n-channel transistor (here, The other is a p-channel transistor (here, is the third transistor 1153). That is, the third transistor 1153 and the fourth The CMOS circuit is formed by the fifth transistor 1154. The sixth transistor 1155 and the sixth transistor 1156 form a CMOS circuit.

[0267] First transistor 1151, second transistor 1152, fourth transistor 115 The fourth and sixth transistors 1156 are n-channel transistors, and in the previous embodiment, The third transistor 1153 and the transistor shown in the embodiment can be applied. The fifth transistor 1155 is a p-channel transistor made of a material other than an oxide semiconductor. A material (for example, single crystal silicon) is used for the channel formation region.

[0268] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0269] (Embodiment 12) A CPU using at least a part of a transistor in which an oxide semiconductor is used for a channel formation region (Central Processing Unit) can be configured.

[0270] FIG. 18(A) is a block diagram showing a specific configuration of the CPU. The PU is provided on a substrate 1190 with an arithmetic logic unit (ALU). nit) 1191, ALU controller 1192, instruction decoder 1193 , interrupt controller 1194, timing controller 1195, register 11 96, Register Controller 1197, Bus Interface (Bus I / F) 119 8, rewritable ROM 1199 and ROM interface (ROM I / F) 1 The substrate 1190 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM I / F 1189 may be provided on a separate chip. The CPU shown in FIG. 18(A) is merely an example of a simplified configuration, and the actual CPU U has a wide variety of configurations depending on its use.

[0271] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0272] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates signals for the CPU program. During system execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask. The register controller 1197 determines the address of the register 1196 and processes it. It generates a response and reads or writes to register 1196 depending on the state of the CPU.

[0273] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal that controls the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal C based on the reference clock signal CLK1. The internal clock signal CLK2 is generated by an internal clock generator. Supply to the seed circuit.

[0274] In the CPU shown in FIG. 18A, a register 1196 is provided with a memory cell. The memory cells of the register 1196 are the same as those described in the ninth to eleventh embodiments. A molcell can be used.

[0275] In the CPU shown in FIG. 18A, the register controller 1197 controls the ALU 1191 The holding operation in register 1196 is selected according to the instruction from register 1196. In the memory cell of the memory cell 1196, data is held by a phase inversion element or Select whether to hold data using a phase inversion element. If selected, the power supply voltage is supplied to the memory cells in the register 1196 . If data retention in the capacitor is selected, data rewriting to the capacitor is This allows the supply of power supply voltage to the memory cells in register 1196 to be stopped.

[0276] Regarding power supply shutdown, as shown in FIG. 18(B) or FIG. 18(C), A switching element is connected between nodes to which the power supply potential VDD or VSS is applied. The circuits shown in FIGS. 18(B) and 18(C) are explained below. Do the following.

[0277] In FIG. 18B and FIG. 18C, a switch for controlling the supply of a power supply potential to a memory cell is shown. A memory circuit including a transistor in which an oxide semiconductor is used for a channel formation region is also provided. An example of the configuration is shown below.

[0278] The memory device shown in FIG. 18B includes a switching element 1141 and a memory cell 1142. Specifically, each memory cell 1142 has: The memory cells described in the ninth to eleventh embodiments can be used. Each memory cell 1142 in the memory cell group 1143 is connected to a switching element 1141. A high level power supply potential VDD is supplied to the memory cell group 1143. Each memory cell 1142 has a potential of the signal IN and a potential of the low-level power supply potential VSS. The rank is given.

[0279] In FIG. 18B, a switching element 1141 is formed by using an oxide semiconductor as a channel formation region. The transistor has a gate electrode connected to the Switching is controlled by signal SigA.

[0280] In FIG. 18B, the switching element 1141 has only one transistor. However, there is no particular limitation to the configuration, and a plurality of transistors may be included. When the switching element 1141 has a plurality of transistors functioning as switching elements, The plurality of transistors may be connected in parallel or in series. Alternatively, the series and parallel connections may be combined.

[0281] In FIG. 18B, a memory cell group 1143 is enabled by a switching element 1141. The supply of a high-level power supply potential VDD to each memory cell 1142 is controlled. The supply of the low-level power supply potential VSS is controlled by the switching element 1141. That's fine.

[0282] In addition, in FIG. 18C, each memory cell 1142 included in the memory cell group 1143 is A low-level power supply potential VSS is supplied to the memory device through the switching element 1141. The switching element 1141 switches each memory cell in the memory cell group 1143. The supply of a low-level power supply potential VSS to the memory cell 1142 can be controlled.

[0283] A switch is provided between the memory cell group and a node to which the power supply potential VDD or VSS is applied. When a switching element is installed to temporarily stop CPU operation and cut off the supply of power voltage It is possible to retain data even in this state, and power consumption can be reduced. Specifically, for example, a user of a personal computer inputs information into an input device such as a keyboard. You can stop the CPU from operating while you are no longer entering information, which will save you money. Power consumption can be reduced.

[0284] Here, we have taken the CPU as an example, but the same can be said for DSP (Digital Signal Processor) processor), custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as MOS gate arrays.

[0285] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0286] (Embodiment 13) FIG. 1 shows one mode of a display device using the transistors described in any of Embodiments 1 to 8. Shown in Figure 9.

[0287] FIG. 19A shows a transistor 750 and a liquid crystal element 713 disposed between a first substrate 701 and a second substrate 702. 19(B) is a top view of a panel sealed between a substrate 706 and the panel by a sealing material 705. ) corresponds to a cross-sectional view taken along the dashed dotted line MN in FIG. 19(A).

[0288] A sealing material 705 is provided so as to surround a pixel portion 702 provided on a first substrate 701. A second substrate 706 is provided on the pixel portion 702. The first substrate 701, the sealant 705, and the second substrate 706 seal the liquid crystal layer 708 together. It has been stopped.

[0289] In addition, in an area different from the area surrounded by the sealing material 705 on the first substrate 701, , an input terminal 720, and an FPC (Flexible Printed Circuit ) 718a and FPC 718b are connected. FPC 718a is made separately on a different board. The FPC 718b is electrically connected to the signal line driver circuit 703, which is fabricated on a separate substrate. The pixel portion 702 is electrically connected to a scanning line driver circuit 704 fabricated in the Various signals and potentials are transmitted to the signal line driver circuit 718 via the FPC 718a and the FPC 718b. 03 and the scanning line driver circuit 704.

[0290] The method of connecting the drive circuit fabricated on a separate substrate is not particularly limited. , COG (Chip On Glass) method, wire bonding method, TCP (Ta pe Carrier Package) method or TAB (Tape Automa A method such as ted bonding can be used.

[0291] A liquid crystal element (also called a liquid crystal display element) is used as a display element provided in the display device. In addition, display media such as electronic ink, whose contrast changes due to electrical effects, can also be applied.

[0292] The display device shown in FIG. 19 has electrodes 715 and wirings 716. 716 is electrically connected to the terminal of the FPC 718a via an anisotropic conductive film 719. are.

[0293] The electrode 715 is formed from the same conductive film as the first electrode 730, and the wiring 716 is formed from the same conductive film as the transistor. The source electrode and drain electrode of the capacitor 750 are formed from the same conductive film.

[0294] Note that the transistor 750 provided in the pixel portion 702 is electrically connected to a display element. The display element is not particularly limited as long as it can display an image, and various display elements can be used. A child can be used.

[0295] The size of the storage capacitor provided in the liquid crystal display device is determined by the lead of the transistor arranged in the pixel portion. The transistor is set to be able to hold charge for a predetermined period, taking into consideration factors such as the current. As the transistor 750, any of the transistors using an oxide semiconductor film described in Embodiments 1 to 8 may be used. By using a transistor, the capacitance of the liquid crystal in each pixel is set to 1 / 3 or less, preferably It is sufficient to provide a storage capacitor having a size of 1 / 5 or less.

[0296] The transistor including the oxide semiconductor film used in this embodiment has a hydrogen concentration that is reduced by heat treatment. Therefore, the current value in the off state (off current value) can be reduced. Therefore, the retention time of the electric signals such as the image signals can be extended, and the power can be turned off. In the ON state, the write interval can be set longer. Therefore, the frequency of refresh operations can be reduced. In addition, the oxide semiconductor film can be used to reduce power consumption. The transistor can hold a potential applied to the liquid crystal element without providing a storage capacitor. do.

[0297] Further, the transistors including the oxide semiconductor film described in any of Embodiments 1 to 8 Since a relatively high field effect mobility can be obtained, high speed driving is possible. By using the above transistor in a pixel portion of a display device, a high-quality image can be provided. In addition, the transistors are separately formed in the driver circuit portion and the pixel portion on the same substrate. This allows the number of components in the liquid crystal display device to be reduced.

[0298] FIG. 19 shows the configuration of a display device using a liquid crystal element as a display element. The liquid crystal element 713, which is a display element, is made up of a first electrode 730, a second electrode 731, and a liquid crystal The liquid crystal layer 708 is sandwiched between insulating films 73 which function as alignment films. 2, an insulating film 733 is provided. The second electrode 731 is provided on the second substrate 706 side. The first electrode 730 and the second electrode 731 are laminated with the liquid crystal layer 708 interposed therebetween. There are.

[0299] The spacers 735 are columnar spacers formed of an insulating film on the second substrate 706. The spherical surface is provided to control the film thickness (cell gap) of the liquid crystal layer 708. A spacer may also be used.

[0300] When a liquid crystal element is used as a display element, the liquid crystal layer 708 is made of a thermotropic liquid crystal, a low molecular weight liquid crystal, a Use of polymer liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. These liquid crystal materials can be in a cholesteric phase, a smectic phase, or a cubic phase depending on the conditions. The phases shown are chiral nematic, isotropic, and nematic.

[0301] Furthermore, the liquid crystal layer 708 may be made of a liquid crystal that exhibits a blue phase without using an alignment film. is one of the liquid crystal phases, and when the temperature of cholesteric liquid crystal is increased, it changes from the cholesteric phase to the equilibrium phase. This is the phase that appears just before the transition to the rhombohedral phase. The blue phase appears only in a narrow temperature range. In order to improve the temperature range, a liquid crystal composition containing a chiral agent is used in the liquid crystal layer. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a short response time of 1 millisecond or less. Since the liquid crystal display is optically isotropic, no alignment treatment is required and the viewing angle dependency is small. Since there is no need to provide a rubbing treatment, the This can prevent electrostatic breakdown, which may occur during the manufacturing process, thereby reducing defects and damage to the liquid crystal display device. Therefore, it is possible to improve the productivity of the liquid crystal display device.

[0302] The specific resistivity of the liquid crystal material is 1×10 9 Ω·cm or more, preferably 1×10 1 1 Ω·cm or more, and more preferably 1×10 12 Ω·cm or more. The specific resistivity values ​​in the specification are those measured at 20°C.

[0303] The liquid crystal display device shown in this embodiment is a TN (Twisted Nematic) mode liquid crystal display. , IPS (In-Plane-Switching) mode, FFS (Fringe F ield Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Comp Ensulated Birefringence mode, FLC (Ferrerolect ric Liquid Crystal) mode, AFLC (AntiFerroele (electric Liquid Crystal) mode, Vertical Alignment (VA) mode, MVA (Multi-Domain Vertical Alignment) mode, ASV (Advanced Super-View) mode, PVA (Patterned V Vertical Alignment mode, TBA (Transverse Bench d Alignment) and other operating modes can be used as appropriate.

[0304] In addition, in a liquid crystal display device, a black matrix (light-shielding layer), a polarizing member, a phase difference member, Optical members (optical substrates) such as anti-reflection members are provided as appropriate. Circularly polarized light from a differential substrate may also be used. may also be used.

[0305] In addition, multiple light-emitting diodes (LEDs) are used as backlights, and a time-division display system is used. It is also possible to perform field sequential driving. By applying the color drive method, color display can be achieved without using a color filter. This can be done.

[0306] In addition, the display method in the pixel section uses the progressive method, interlace method, etc. In addition, the color elements controlled by pixels when displaying colors are RGB (R is It is not limited to the three colors (red, green, and blue). For example, RGBW (W stands for white). Or, RGB may be combined with one or more colors such as yellow, cyan, or magenta. The size of the display area may be different for each dot of the color element. This is not limited to color LCD devices, but can also be applied to monochrome LCD devices. You can also do this.

[0307] Here, several liquid crystal operation modes will be given as examples of typical driving methods for liquid crystal display devices. In the liquid crystal display device, a voltage is applied perpendicular to the substrate to drive the liquid crystal. There are two types of LCDs: a vertical electric field type in which a voltage is applied parallel to the substrate, and a horizontal electric field type in which a voltage is applied parallel to the substrate.

[0308] First, the pixel configuration of a TN mode liquid crystal display device will be explained with reference to FIGS. 20(A) and 20(B). A cross-sectional schematic diagram is shown.

[0309] A first substrate 3101 and a second substrate 3102 are arranged to face each other, and display elements are formed on the first substrate 3101 and the second substrate 3102. A layer 3100 having a polarizer is sandwiched between the first substrate 3101 and the first polarizer 3. 103 is formed on the second substrate 3102 side, and a second polarizing plate 3104 is formed on the second substrate 3102 side. The absorption axis of the first polarizing plate 3103 and the absorption axis of the second polarizing plate 3104 are in a crossed Nicol state. are arranged in

[0310] Although not shown, a backlight and the like are disposed outside the second polarizing plate 3104. The first substrate 3101 and the second substrate 3102 are provided with a first electrode 3108 and a second electrode 3109, respectively. The electrode 3109 is provided on the side opposite to the backlight, i.e., the visible side. The first electrode 3108 is formed to have light-transmitting properties.

[0311] In a liquid crystal display device having such a configuration, in the case of a normally white mode, When a voltage is applied between the electrode 3108 and the second electrode 3109 (called a vertical electric field method), As shown in FIG. 20(A), the liquid crystal molecules 3105 are aligned vertically. Light from the screen cannot pass through the first polarizer 3103, resulting in a black display.

[0312] As shown in FIG. 20(B), a voltage is applied between the first electrode 3108 and the second electrode 3109. When no pressure is applied, the liquid crystal molecules 3105 are aligned horizontally and twisted in the plane. As a result, the light from the backlight can pass through the first polarizer 3103, A white display is obtained. Furthermore, the voltage applied between the first electrode 3108 and the second electrode 3109 is By adjusting the value of the gradation, it is possible to express a desired image display. will be carried out.

[0313] The liquid crystal material used in the TN mode may be a known material.

[0314] Next, the pixel configuration of a VA mode liquid crystal display device will be explained with reference to FIGS. 20(C) and 20(D). In the VA mode, the liquid crystal molecules 3105 are perpendicular to the substrate when no electric field is applied. This is a mode oriented as follows:

[0315] As in FIGS. 20A and 20B, a first substrate 3101 and a second substrate 3102 A first electrode 3108 and a second electrode 3109 are provided on the top of the backlight. The first electrode 3108, which is the electrode on the side opposite to the light, i.e., the viewing side, is made to be transparent. A first polarizing plate 3103 is formed on the first substrate 3101 side, and a second polarizing plate 3104 is formed on the second substrate 3102 side. A second polarizing plate 3104 is formed on the 102 side. The axis and the absorption axis of the second polarizing plate 3104 are arranged in a crossed Nicol state.

[0316] In the liquid crystal display device having such a configuration, the first electrode 3108 and the second electrode 31 When a voltage is applied between the liquid crystal molecules 31 and 32 (vertical electric field method), the liquid crystal molecules 31 and 32 move in the direction of the arrows as shown in FIG. Then, the light from the backlight is polarized by the first polarizer 3103. can pass through and is displayed in white.

[0317] As shown in FIG. 20(D), a voltage is applied between the first electrode 3108 and the second electrode 3109. When no pressure is applied, the liquid crystal molecules 3105 are aligned vertically. The light from the backlight polarized by the polarizing plate 3104 is reflected by the birefringence of the liquid crystal molecules 3105. This allows the light from the polarized backlight to pass through the cell without being affected by the polarization. Light cannot pass through the first polarizing plate 3103, resulting in a black display. By adjusting the voltage applied between the first electrode 3108 and the second electrode 3109, gray scales can be displayed. In this way, a predetermined image is displayed.

[0318] Next, the pixel configuration of an MVA mode liquid crystal display device will be explained with reference to FIGS. 20(E) and 20(F). The MVA mode divides one pixel into multiple parts, and the alignment direction of each part is This is a method of compensating for the viewing angle dependency by changing the direction. In the MVA mode, a cross section is provided on the first electrode 3108 and the second electrode 3109 for orientation control. Triangular protrusions 3158 and 3159 are provided. The other configurations are VA mode and are equivalent.

[0319] When a voltage is applied between the first electrode 3108 and the second electrode 3109 (vertical electric field method), As shown in FIG. 20(E), the liquid crystal molecules 3105 are aligned with the surfaces of the protrusions 3158 and 3159. The liquid crystal molecules 3105 are aligned so that their long axes are almost vertical. The light can pass through the first polarizer 3103, resulting in a white display.

[0320] As shown in FIG. 20(F), a voltage is applied between the first electrode 3108 and the second electrode 3109. When no pressure is applied, the liquid crystal molecules 3105 are aligned vertically. Light from the backlight cannot pass through the first polarizing plate 3103, resulting in a black display. In addition, the voltage applied between the first electrode 3108 and the second electrode 3109 can be adjusted. In this way, a desired image is displayed.

[0321] Another example of the MVA mode is shown in a top view and a cross-sectional view in FIG. 23. In FIG. 23(A), The electrode is formed in a bent pattern like a dogleg, and the second electrode 3109a , the second electrode 3109b, and the second electrode 3109c. An insulating layer 3162, which is an alignment film, is formed on the second electrodes 3109a, 3109b, and 3109c. A protrusion 3158 is formed on the first electrode 3108 so as to overlap with the second electrode 3109b. An alignment film is formed on the first electrode 3108 and the protrusions 3158. An insulating layer 3163 is formed.

[0322] Next, the pixel configuration of an OCB mode liquid crystal display device will be explained with reference to FIGS. 21(A) and 21(B). In the OCB mode, the liquid crystal molecules 3105 in the liquid crystal layer exhibit viewing angle dependence. The alignment is such that it compensates for this, and this is called a bend alignment.

[0323] As in FIG. 20, the first substrate 3101 and the second substrate 3102 each have a first An electrode 3108 and a second electrode 3109 are provided. The first electrode 3108, which is the electrode on the viewing side, is formed to be light-transmitting. A first polarizing plate 3103 is formed on the 101 side, and a second polarizing plate 3104 is formed on the second substrate 3102 side. The absorption axis of the first polarizing plate 3103 and the absorption axis of the second polarizing plate 3104 are aligned. The absorption axes of the 04 are arranged in a crossed Nicol state.

[0324] In the liquid crystal display device having such a configuration, the first electrode 3108 and the second electrode 31 When a constant voltage is applied to O9 (vertical electric field method), a black display appears as shown in Figure 21(A). At this time, the liquid crystal molecules 3105 are aligned vertically. These lights cannot pass through the first polarizing plate 3103, resulting in a black display.

[0325] As shown in FIG. 21B, a first electrode 3108 and a second electrode 3109 are provided between them. When a certain voltage is applied, the liquid crystal molecules 3105 are in a bend alignment state. The light from the screen can pass through the first polarizer 3103, resulting in a white display. In addition, by adjusting the voltage applied between the first electrode 3108 and the second electrode 3109, This allows for the expression of gradation, and a desired image is displayed in this manner.

[0326] In this OCB mode, the viewing angle dependence is controlled by the arrangement of liquid crystal molecules 3105 in the liquid crystal layer. We can compensate you.

[0327] Next, FIG. 21(C) and FIG. 21(D) show liquid crystal display devices in FLC mode and AFLC mode. 1 shows a cross-sectional view illustrating the pixel configuration of the device.

[0328] As in FIG. 20, the first substrate 3101 and the second substrate 3102 each have a first An electrode 3108 and a second electrode 3109 are provided. That is, the first electrode 3108, which is the electrode on the viewing side, is formed to have light-transmitting properties. A first polarizing plate 3103 is formed on the first substrate 3101 side, and a second polarizing plate 3104 is formed on the second substrate 3102 side. The second polarizing plate 3104 is formed on the first polarizing plate 3103. The absorption axes of the second polarizing plate 3104 are arranged in a crossed Nicol state.

[0329] In the liquid crystal display device having such a configuration, the first electrode 3108 and the second electrode 31 When a voltage is applied to the liquid crystal panel 3109 (called the vertical electric field method), the liquid crystal molecules 3105 move in the direction opposite to the rubbing direction. As a result, the light from the backlight is directed in the first polarized direction. It can pass through the light plate 3103 and is displayed in white.

[0330] As shown in FIG. 21(D), a voltage is applied between the first electrode 3108 and the second electrode 3109. When no pressure is applied, the liquid crystal molecules 3105 are aligned horizontally along the rubbing direction. Then, the light from the backlight can pass through the first polarizing plate 3103. Furthermore, when a voltage is applied between the first electrode 3108 and the second electrode 3109, By adjusting the voltage, it is possible to express gradation. The display is performed.

[0331] The liquid crystal materials used in the FLC mode and AFLC mode can be any known material. That's fine.

[0332] Next, the pixel configuration of an IPS mode liquid crystal display device will be explained with reference to FIGS. 22(A) and 22(B). In the IPS mode, the liquid crystal molecules 3105 are always aligned in the plane of the substrate. This is a rotation mode, and the electrodes are provided on only one of the substrates in a horizontal electric field system.

[0333] The IPS mode is characterized by controlling the liquid crystal with a pair of electrodes on one of the substrates. For this purpose, a pair of electrodes 3150 and 3151 are provided on the second substrate 3102. The pair of electrodes 3150 and 3151 preferably have light-transmitting properties. A first polarizing plate 3103 is formed on the side of the plate 3101, and a second polarizing plate 3104 is formed on the side of the second substrate 3102. The absorption axis of the first polarizing plate 3103 and the absorption axis of the second polarizing plate The absorption axes of 3104 are arranged in a crossed Nicol state.

[0334] In the liquid crystal display device having such a configuration, a pair of electrodes 3150 and 3151 are connected to When pressure is applied, the liquid crystal molecules 3105 are displaced from the rubbing direction as shown in FIG. 22(A). Then, the light from the backlight is polarized along the lines of electric force of the first polarizer 3103. can pass through and is displayed in white.

[0335] Furthermore, as shown in FIG. 22(B), a voltage is applied between a pair of electrodes 3150 and 3151. When not rubbing, the liquid crystal molecules 3105 are aligned horizontally along the rubbing direction. As a result, the light from the backlight cannot pass through the first polarizer 3103, and a black The voltage applied between the pair of electrodes 3150 and 3151 is adjusted. In this way, a desired image is displayed. .

[0336] An example of a pair of electrodes 3150 and 3151 that can be used in IPS mode is shown in FIG. As shown in the top views of FIGS. 24(A) to 24(C), a pair of electrodes 3150 and 3151 are In FIG. 24(A), the electrodes 3150a and 3151a are formed to have different shapes. In FIG. 24(B), the electrode 3150b and the electrode 3151b In FIG. 24(C), the electrodes 3150c and 3150d are comb-shaped and partially overlap each other. 3151c is comb-shaped and has electrodes that interlock with each other.

[0337] Next, the pixel configuration of an FFS mode liquid crystal display device will be explained with reference to FIGS. 22(C) and 22(D). The FFS mode is the same horizontal electric field type as the IPS mode, but the FFS mode is As shown in FIG. 22(C) and FIG. 22(D), an electrode 3151 is formed on an electrode 3150 via an insulating film. This is the structure that is formed.

[0338] The pair of electrodes 3150 and 3151 may each have light-transmitting properties. A first polarizing plate 3103 is formed on the side of the plate 3101, and a second polarizing plate 3104 is formed on the side of the second substrate 3102. The absorption axis of the first polarizing plate 3103 and the absorption axis of the second polarizing plate The absorption axes of 3104 are arranged in a crossed Nicol state.

[0339] In the liquid crystal display device having such a configuration, a pair of electrodes 3150 and 3151 are connected to When pressure is applied, the liquid crystal molecules 3105 are displaced from the rubbing direction as shown in FIG. 22(C). Then, the light from the backlight is polarized along the lines of electric force of the first polarizer 3103. can pass through and is displayed in white.

[0340] Furthermore, as shown in FIG. 22(D), a voltage is applied between a pair of electrodes 3150 and 3151. When not rubbing, the liquid crystal molecules 3105 are aligned horizontally along the rubbing direction. As a result, the light from the backlight cannot pass through the first polarizer 3103, and a black The voltage applied between the pair of electrodes 3150 and 3151 is adjusted. In this way, a desired image is displayed. .

[0341] An example of a pair of electrodes 3150 and 3151 that can be used in FFS mode is shown in FIG. As shown in the top views of FIGS. 25(A) to 25(C), various patterns are formed on the electrode 3150. In FIG. 25(A), the electrode 3151 is formed on the electrode 3150a. 1a has a bent L-shape, and in FIG. 25(B), the electrode 3151b on the electrode 3150b In FIG. 25(C), the electrodes 3150c are comb-shaped and have a shape in which the electrodes interlock with each other. The electrode 3151c has a comb-like shape.

[0342] The liquid crystal materials used in the IPS mode and FFS mode can be any known material. Alternatively, a liquid crystal exhibiting a blue phase may be used.

[0343] In FIG. 19, the first substrate 701 and the second substrate 706 are the same as those in the first embodiment. Alternatively, the first substrate 701 and the second substrate 7 A flexible substrate can also be used as the substrate 06, for example, a light-transmitting plastic. As for plastic, FRP (Fibreglass) s-Reinforced Plastics) board, PVF (polyvinyl fl Polyurethane film, polyester film or acrylic resin film may be used. It is also possible to sandwich aluminum foil between PVF film or polyester film. A sheet with a different structure can also be used.

[0344] A liquid crystal display device transmits light from a light source or a display element to display an image. The thin films such as the substrate, insulating film, and conductive film provided in the pixel area are all irradiated with light in the visible light wavelength range. It is translucent.

[0345] A first electrode and a second electrode (such as a pixel electrode, a common electrode, and a counter electrode) that apply a voltage to the display element In this case, the direction of the extracted light, the location of the electrodes, and the pattern of the electrodes are all determined. The transparency or reflectivity can be selected depending on the structure of the film.

[0346] The first electrode 730 and the second electrode 731 are made of indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium, indium tin oxide (also called ITO), indium Conductive materials with light transmission properties, such as indium zinc oxide and indium tin oxide with added silicon oxide A material consisting of 1 to 10 graphene sheets can be used. That's fine.

[0347] The first electrode 730 and the second electrode 731 are made of a conductive polymer ( The conductive polymer may be formed using a conductive composition containing a conductive polymer. A so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or the like or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or Copolymers consisting of two or more of aniline, pyrrole and thiophene, or derivatives thereof Examples include:

[0348] In the case of a reflective liquid crystal display device, either the first electrode 730 or the second electrode 731 On the other hand, tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium ( Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium (Ti), Platinum (Pt), Aluminum (Al ), copper (Cu), silver (Ag), or other metals, or their alloys, or their nitrides, Alternatively, a plurality of types may be used.

[0349] In addition, since transistors are easily damaged by static electricity, it is preferable to provide a protection circuit. It is preferable that the protection circuit is configured using a nonlinear element. One mode of a protection circuit that can be used in a display device in this embodiment will be described with reference to FIG. .

[0350] The protection circuit 997 is composed of n-type transistors 970a and 970b. The gate terminal is connected to the drain terminal so that each exhibits the same characteristics as a diode. Note that the transistors 970a and 970b are the same as those in Embodiments 1 to 8. The transistors described in the section 1 may be used as appropriate.

[0351] The first terminal (gate) and the third terminal (drain) of the transistor 970a are connected to the first wiring 945. The first terminal (source) is connected to the second wiring 960. The first terminal (gate) and the third terminal (drain) of the transistor 970b are connected to the second wiring 960. The second terminal (source) is connected to the first wiring 945. That is, as shown in FIG. The protection circuit shown in is a circuit in which two transistors are rectified in opposite directions, and the first The first wiring 945 and the second wiring 960 are connected to each other. A transistor whose rectification direction is from the first wiring 945 to the second wiring 960 and a transistor whose rectification direction is from the second wiring 9 60 to the first wiring 945, the transistors are connected to the first wiring 945 and the second wiring 96 0.

[0352] When the second wiring 960 is positively or negatively charged due to static electricity or the like, the protection circuit For example, if the second wiring 960 is positively charged, A current flows in a direction that releases the positive charge to the first wiring 945. It is possible to prevent electrostatic damage or malfunction of circuits or elements connected to the second wiring 960. In addition, in a configuration in which the charged second wiring 960 and other wirings intersect with each other via an insulating layer, This can prevent the insulating layer from being broken down.

[0353] Note that the protective circuit is not limited to the above configuration. For example, a plurality of transistors each having a rectifying direction from the second wiring 960 to the first wiring 960; A configuration having a plurality of transistors facing the wiring 945 may also be used. A protection circuit can also be constructed using transistors.

[0354] The protection circuit shown in FIG. 26(A) can be used for various purposes. For example, The wiring 945 is a common wiring for the display device, and the second wiring 960 is one of a plurality of signal lines. The protection circuit can be applied between the image signal line and the signal line. The element transistor is protected from defects such as electrostatic breakdown due to charging of wiring and threshold voltage shift. Be protected.

[0355] The protection circuit can be applied to other circuits of the liquid crystal display device as well as to other implementations. The present invention can also be applied to the semiconductor device shown in the embodiment.

[0356] Next, a configuration in which the protection circuit 997 is formed on a substrate will be described. An example is shown in FIG. 26B. Here, the transistor described in Embodiment 1 is used. In order to avoid complication, some of the components of the transistor (e.g., the protective film) , gate insulating film, insulating film, etc.) are omitted.

[0357] The transistor 970a has a gate electrode 911a. The gate electrode 911a is connected to the first wiring 9 The source electrode of the transistor 970a is connected to the second wiring 960. The drain electrode is connected to a first wiring 945 via a first electrode 915a. The transistor 970a overlaps with the gate electrode 911a between the source electrode and the drain electrode. It includes a semiconductor layer 913 .

[0358] The transistor 970b has a gate electrode 911b, which is connected to a contact hole. The drain of the transistor 970b is connected to the second wiring 960 via a line 925b. The gate electrode is connected to the second wiring 960, and the source electrode is connected to the first electrode 915a through a contact hole. The transistor 970b is connected to the first wiring 945 via a gate 925a. A semiconductor layer 914 is provided between the source electrode and the drain electrode, overlapping with the gate electrode 911b. .

[0359] As described above, the transistors exemplified in the first to eighth embodiments are By applying this to a resistor, a highly reliable liquid crystal display device can be provided. The transistors exemplified in the first to eighth embodiments are semiconductor devices having the above-mentioned display function. In addition to the above, various semiconductor devices are also available, including those with image sensor functions that read information about the target object. The present invention can be applied to semiconductor devices having various functions.

[0360] In this embodiment, a liquid crystal display device using a liquid crystal element as a display element is used as the display device. However, the present invention is not limited to this. For example, a light-emitting element may be used as a display element. By using the display element, a light-emitting display device can be provided as one mode of the display device. Since an electrophoretic element is used as the display device, an electrophoretic display device can be used as one form of the display device. can.

[0361] This embodiment mode can be freely combined with other embodiment modes.

Claims

1. an oxide semiconductor layer having a channel formation region of a transistor; a first insulating film having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a side surface of the oxide semiconductor layer; a first conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the transistor; a second conductive layer having a region located above the first insulating film and a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; a second insulating film having a region in contact with an upper surface of the first conductive layer, a region in contact with an upper surface of the second conductive layer, and a region in contact with an upper surface of the oxide semiconductor layer; a third conductive layer having a region in contact with the second conductive layer and functioning as a wiring; the first conductive layer and the second conductive layer have the same material; the third conductive layer has a region overlapping with the oxide semiconductor layer and a region intersecting with the first conductive layer.

2. an oxide semiconductor layer having a channel formation region of a transistor; a first insulating film having a region in contact with a top surface of the oxide semiconductor layer and a region in contact with a side surface of the oxide semiconductor layer; a first conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the transistor; a second conductive layer having a region located above the first insulating film and a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; a second insulating film having a region in contact with an upper surface of the first insulating film, a region in contact with an upper surface of the first conductive layer, a region in contact with an upper surface of the second conductive layer, and a region in contact with an upper surface of the oxide semiconductor layer; a third conductive layer having a region in contact with the second conductive layer and functioning as a wiring; the first conductive layer and the second conductive layer have the same material; the third conductive layer has a region overlapping with the oxide semiconductor layer and a region intersecting with the first conductive layer.

3. In claim 1 or 2, The semiconductor device, wherein the first conductive layer and the second conductive layer have a stacked structure.

4. In any one of claims 1 to 3, The semiconductor device, wherein the third conductive layer comprises at least one of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten.

Images