Manufacturing method for semiconductor device

Abstract

To provide a semiconductor device with parasitic capacitance reduced.SOLUTION: A semiconductor device includes a first insulating layer on a substrate, a first metal oxide layer on the first insulating layer, an oxide semiconductor layer on the first metal oxide layer, a second metal oxide layer on the oxide semiconductor layer, a gate insulating layer on the second metal oxide layer, a second insulating layer on the second metal oxide layer, and a gate electrode layer on the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes a first region to a third region. The first region includes a region overlapping with the gate electrode layer. The second region includes a region overlapping with the gate insulating layer or the second insulating layer. The second region is a region between the first region and the third region. The second region and the third region include a region containing an element N (N is phosphorus, argon, or xenon).SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, relating to the manufacture or composition of matter, especially The present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, and In particular, one embodiment of the present invention relates to a semiconductor device or a driving method thereof. or a method for producing the same.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. Display devices and electronic devices may include semiconductor devices. [Background technology]

[0003] The technology of constructing a transistor using a semiconductor film formed on a substrate with an insulating surface is attracting attention. The transistor is used in devices such as integrated circuits (ICs) and image display devices (display devices). Silicon is widely used as a semiconductor thin film that can be applied to transistors. Silicon-based semiconductor materials are widely known, but oxide semiconductors are also attracting attention. There are.

[0004] For example, indium (In), gallium (Ga), and A transistor using an amorphous oxide semiconductor layer containing zinc (Zn) is disclosed in Patent Document 1. are. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-165528 Summary of the Invention [Problem to be solved by the invention]

[0006] In order to manufacture semiconductor devices with highly integrated transistors, miniaturization of transistors is required. However, as transistors are miniaturized, the parasitic capacitance of the transistors increases. The increase in volume becomes a problem.

[0007] For example, in the operation of a transistor, the vicinity of the channel (for example, the source electrode-drain electrode If there is a parasitic capacitance between the power supply and the load, time is required to charge the parasitic capacitance. This reduces the response of the transistor and, ultimately, the response of the semiconductor device.

[0008] Furthermore, as transistors become increasingly miniaturized, it becomes increasingly difficult to control the shape of the transistors. Variations that occur during the manufacturing process have a significant impact on transistor characteristics and reliability. It ends up like this.

[0009] Therefore, one object of one embodiment of the present invention is to reduce the parasitic capacitance of a transistor. Another object is to provide a semiconductor device capable of high-speed operation. One of the objects is to provide a semiconductor device having good electrical characteristics. It is an object of the present invention to provide a semiconductor device. One of the purposes is to reduce the variation in properties caused by the manufacturing process. An object of the present invention is to provide a semiconductor device including an oxide semiconductor layer with few element vacancies. Another object is to provide a semiconductor device that can be formed by a simple process. Alternatively, a semiconductor device having a structure capable of reducing the interface state density in the vicinity of an oxide semiconductor layer may be provided. Another object of the present invention is to provide a semiconductor device with low power consumption. Another object is to provide a novel semiconductor device. Another object is to provide a method for manufacturing the semiconductor device.

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] (1) One aspect of the present invention is a semiconductor device comprising a first insulating layer on a substrate, a first metal oxide layer on the first insulating layer, and a first metal oxide layer. an oxide semiconductor layer on the metal oxide layer; a second metal oxide layer on the oxide semiconductor layer; and a second metal oxide layer on the second metal oxide layer. a gate insulating layer on the oxide semiconductor layer and a gate electrode layer on the gate insulating layer; The gate electrode layer has first to third regions, and the first and second regions are regions overlapping with the gate electrode layer. The second region is a region between the first region and the third region, and the second region is a region between the first region and the third region. the third region has a region having a lower resistance than the second region, The second and third regions are regions containing the element N (N is phosphorus, argon, or xenon). The semiconductor device is characterized by having:

[0012] (2) Another aspect of the present invention is a semiconductor device comprising: a first insulating layer on a substrate; a first metal oxide layer on the first insulating layer; A first insulating layer and a second metal oxide layer on the oxide semiconductor layer. a first gate insulating layer on the second metal oxide layer; and a gate electrode layer on the first gate insulating layer. , a second metal oxide layer, and a first gate insulating layer, a region facing a side surface of the conductor layer, the oxide semiconductor layer having first to third regions; The first region and the second region have a region overlapping with the gate electrode layer, and the second region has a region overlapping with the first region. The second region has a region between the third region and has a region with a lower resistance than the first region, The third region has a region with a lower resistance than the second region, and the second region and the third region have an element A semiconductor characterized by having a region containing N (N is phosphorus, argon, or xenon). It is a device.

[0013] (3) Another aspect of the present invention is to provide a method for manufacturing a semiconductor device comprising the steps of: (1) forming a first gate insulating layer and a second gate electrode layer between the first gate insulating layer and the second gate electrode layer; The semiconductor device is characterized by having a second gate insulating layer.

[0014] (4) Another aspect of the present invention is any one of (1) to (3), wherein the second region is a first region The third region has a region where the concentration of element N is higher than that of the first region. The semiconductor device is characterized by having a high region.

[0015] (5) Another aspect of the present invention is the method for manufacturing a semiconductor device according to any one of (1) to (4), wherein the third region is an element N. Concentration is 1×10 18 atoms / cm 3 More than 1×10 22atoms / cm 3 is A semiconductor device characterized by having a region.

[0016] (6) One aspect of the present invention is a semiconductor device comprising a first insulating layer on a substrate, a first metal oxide layer on the first insulating layer, and a first metal oxide layer. an oxide semiconductor layer on the metal oxide layer; a second metal oxide layer on the oxide semiconductor layer; and a second metal oxide layer on the second metal oxide layer. a gate insulating layer on the metal oxide layer; a second insulating layer on the second metal oxide layer; and a gate insulating layer on the gate insulating layer. the gate insulating layer has a region in contact with a side surface of the gate electrode layer, and the second insulating layer The oxide semiconductor layer has a region in contact with the gate insulating layer, and the oxide semiconductor layer has first to third regions. The first region has a region overlapping with the gate electrode layer, and the second region has a region overlapping with the gate insulating layer or The second region has a region overlapping with the second insulating layer, the second region being a region between the first region and the third region, The second and third regions are regions containing the element N (N is phosphorus, argon, or xenon). The semiconductor device is characterized by having:

[0017] (7) Another aspect of the present invention is that in (6), the second region is a region having a lower resistance than the first region. and the third region has a region having a lower resistance than the second region. It is a body device.

[0018] (8) Another aspect of the present invention is that in (6) or (7), the bottom surface of the substrate and the side surface of the gate electrode layer A semiconductor device characterized in that the angle formed by the tangent line is in the range of 60 degrees to 85 degrees. Place.

[0019] (9) Another aspect of the present invention is a method for forming a first insulating layer on a substrate, and depositing a first metal oxide layer on the first insulating layer. a first metal oxide layer and a first oxide semiconductor layer; The stack of conductor layers is etched into islands using a first mask to form a second metal oxide layer. and forming a second oxide semiconductor layer on the second oxide semiconductor layer and the first insulating layer. forming a metal oxide layer, forming a second insulating layer on the third metal oxide layer, and A third insulating layer is formed by performing a planarization process, and a part of the third insulating layer is formed using a second mask. A fourth insulating layer having a groove portion reaching the third metal oxide layer is formed by etching a portion of the fourth insulating layer. forming a fifth insulating layer on the fourth insulating layer and the third metal oxide layer; and forming a first insulating layer on the fifth insulating layer. A conductive layer is formed and planarized against the first conductive layer and the fifth insulating layer until the fourth insulating layer is exposed. The gate electrode layer and the sixth insulating layer are formed by processing the gate electrode layer as a mask. The fourth insulating layer and the sixth insulating layer are etched using the same to form a gate insulating layer. and then adding ions to the second oxide semiconductor layer using the gate electrode layer as a mask. and forming a source region and a drain region by the above-mentioned method. This is the manufacturing method.

[0020] (10) Another aspect of the present invention is a method for forming a first insulating layer on a substrate, and depositing a first metal oxide layer on the first insulating layer. a first metal oxide layer and a first oxide semiconductor layer; The stack of conductor layers is etched into islands using a first mask to form a second metal oxide layer. and forming a second oxide semiconductor layer on the second oxide semiconductor layer and the first insulating layer. forming a metal oxide layer, forming a first gate insulating layer on the third metal oxide layer, and A second insulating layer is formed on the insulating layer, and a planarization process is performed on the second insulating layer to form a third insulating layer. A border layer is formed, and a portion of the third insulating layer is etched using a second mask to form the first insulating layer. A fourth insulating layer having a groove portion reaching the gate insulating layer is formed, and the fourth insulating layer and the first gate insulating layer are connected to each other. A first conductive layer is formed on the insulating layer, and a planarization process is performed on the first conductive layer until the fourth insulating layer is exposed. The gate electrode layer is then processed to form a fourth insulating layer. The edge layer is etched to expose a region of the first gate insulating layer, and a gate electrode is formed. The first insulating layer is etched using the layer as a mask to form a second gate insulating layer. The second oxide semiconductor layer is doped with ions to form a source region and a drain region. The method for manufacturing a semiconductor device is characterized by forming a gate region.

[0021] (11) Another aspect of the present invention is a method for forming a first insulating layer on a substrate, and depositing a first metal oxide layer on the first insulating layer. a first metal oxide layer and a first oxide semiconductor layer; The stack of conductor layers is etched into islands using a first mask to form a second metal oxide layer. and forming a second oxide semiconductor layer on the second oxide semiconductor layer and the first insulating layer. forming a metal oxide layer, forming a first gate insulating layer on the third metal oxide layer, and A second insulating layer is formed on the insulating layer, and a planarization process is performed on the second insulating layer to form a third insulating layer. A border layer is formed, and a portion of the third insulating layer is etched using a second mask to form the first insulating layer. A fourth insulating layer having a groove portion reaching the gate insulating layer is formed, and the fourth insulating layer and the first gate insulating layer are connected to each other. forming a fifth insulating layer on the insulating layer; forming a first conductive layer on the fifth insulating layer; The gate electrode is formed by planarizing the fourth insulating layer against the fifth insulating layer until the fourth insulating layer is exposed. a fourth insulating layer and a sixth insulating layer are formed using the gate electrode layer as a mask; 6 The insulating layer is etched to expose a region of the first gate insulating layer, and a second oxide is applied. The source and drain regions are formed by adding ions to the nitride semiconductor layer. The present invention provides a method for manufacturing a semiconductor device, characterized in that:

[0022] (12) Another aspect of the present invention is any one of (9) to (11), wherein ions are added. and using phosphorus, argon, or xenon. is.

[0023] (13) Another aspect of the present invention is any one of (9) to (12), wherein ions are added. The ion dose is 1×10 14 ions / cm 2 5x10 or more 16 ions / cm 2 A method for manufacturing a semiconductor device is characterized by the following.

[0024] (14) Another aspect of the present invention is a method for forming a first insulating layer on a substrate, and depositing a first metal oxide layer on the first insulating layer. a first metal oxide layer and a first oxide semiconductor layer; The stack of conductor layers is etched into islands using a first mask to form a second metal oxide a first oxide semiconductor layer and a second oxide semiconductor layer are formed on the second oxide semiconductor layer and the first insulating layer; forming a third metal oxide layer, forming a second insulating layer on the third metal oxide layer, and A third insulating layer is formed by performing a planarization process using a second mask. a fourth insulating layer having a groove that reaches the third metal oxide layer by etching a portion of the fourth insulating layer; forming a fifth insulating layer on the fourth insulating layer and the third metal oxide layer; and forming a fifth insulating layer on the fifth insulating layer. A first conductive layer is formed, and the first conductive layer and the fifth insulating layer are exposed until the fourth insulating layer is exposed. By performing a planarization treatment, a gate electrode layer and a sixth insulating layer are formed. The fourth and sixth insulating layers are etched using the mask to form a gate. a gate insulating layer having a region in contact with a side surface of the electrode layer; The seventh insulating layer is formed to form a second oxide semiconductor layer, and ions are added to the second oxide semiconductor layer. and forming a source region and a drain region.

[0025] (15) Another aspect of the present invention is that in (14), phosphorus, argon, or The present invention is a method for manufacturing a semiconductor device characterized in that xenon is used.

[0026] (16) Another aspect of the present invention is to provide a method for adding ions in (14) or (15). The dose is 1×10 14 ions / cm 2 5x10 or more 16 ions / cm 2 The following The present invention provides a method for manufacturing a semiconductor device, characterized in that:

[0027] (17) Another embodiment of the present invention is the method for manufacturing a semiconductor device according to any one of (14) to (16), wherein the gate electrode layer The angle between the tangent of the side surface and the bottom surface of the substrate is in the range of 60 degrees to 85 degrees. The present invention provides a method for manufacturing a semiconductor device.

[0028] (18) Another aspect of the present invention is a semiconductor device according to any one of (1) to (8), a housing, and , and a speaker. [Effects of the Invention]

[0029] Therefore, by using one embodiment of the present invention, the parasitic capacitance of a transistor can be reduced. Therefore, a semiconductor device capable of high-speed operation can be provided. It is possible to provide a semiconductor device having high reliability. Alternatively, variations in the characteristics of transistors or semiconductor devices due to the manufacturing process can be reduced. Alternatively, a semiconductor having an oxide semiconductor layer with few oxygen vacancies can be formed. Alternatively, a semiconductor device that can be formed by a simple process can be provided. Alternatively, the interface state density in the vicinity of the oxide semiconductor layer can be reduced. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device or the like can be provided. A method for manufacturing a semiconductor device can be provided.

[0030] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0031] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 2] 1A and 1B are schematic diagrams illustrating a cross-sectional view and a band diagram of a transistor. [Figure 3] FIG. 1 is a diagram illustrating the principle of ALD film formation. [Figure 4] Schematic diagram of the ALD equipment. [Figure 5] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 6] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 7] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 8] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 9] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 10] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 11] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 12] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 13] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 14] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 17] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 18] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 19] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 20] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 21]1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 22] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 23] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 24] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 25] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 26] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 27] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 28] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 29] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 30] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 31] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 32] 1A and 1B are top views and cross-sectional views illustrating a method for manufacturing a transistor. [Figure 33] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 34] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 35] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 36] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 37] 1A and 1B are diagrams illustrating structural analysis of a CAAC-OS and a single-crystal oxide semiconductor by XRD, and a selected-area electron diffraction pattern of a CAAC-OS. [Figure 38] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis. [Figure 39] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 40] Cross-sectional TEM image of a-like OS. [Figure 41] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 42] 1A and 1B are cross-sectional views and a circuit diagram of a semiconductor device. [Figure 43] 1A and 1B are cross-sectional views and a circuit diagram of a semiconductor device. [Figure 44] FIG. [Figure 45] FIG. 2 is a plan view showing pixels of the imaging device. [Figure 46] FIG. [Figure 47] FIG. [Figure 48] 1A and 1B are a circuit diagram and a timing chart illustrating a semiconductor device of one embodiment of the present invention. [Figure 49] 1A and 1B are graphs and circuit diagrams illustrating a semiconductor device of one embodiment of the present invention. [Figure 50] 1A and 1B are a circuit diagram and a timing chart illustrating a semiconductor device of one embodiment of the present invention. [Figure 51] 1A and 1B are a circuit diagram and a timing chart illustrating a semiconductor device of one embodiment of the present invention. [Figure 52] FIG. 2 is a diagram illustrating an example of the configuration of an RF tag. [Figure 53] FIG. 2 is a diagram illustrating an example of the configuration of a CPU. [Figure 54] FIG. 1 is a circuit diagram of a memory element. [Figure 55] 1A and 1B are diagrams illustrating a structural example of a display device and a circuit diagram of a pixel. [Figure 56] 1A and 1B are a top view and a cross-sectional view of a liquid crystal display device. [Figure 57] 1A and 1B are a top view and a cross-sectional view of a display device. [Figure 58] FIG. 2 is a diagram illustrating a display module. [Figure 59] 1A and 1B are perspective views showing the cross-sectional structure of a package using a lead frame type interposer and a module configuration. [Figure 60] 1A to 1C illustrate electronic devices. [Figure 61] 1A to 1C illustrate electronic devices. [Figure 62] 1A to 1C illustrate electronic devices. [Figure 63] 1A to 1C illustrate electronic devices. [Figure 64] Cross-sectional view of a measurement sample. [Figure 65] Sheet resistance measurement results of the measurement sample after ion implantation. [Figure 66] Sheet resistance measurement results of the measurement sample after ion implantation. [Figure 67] Sheet resistance measurement results of the measurement sample after ion implantation. [Figure 68] FIG. 10 is a diagram illustrating the measurement results of the XRD spectrum of a sample. [Figure 69] TEM image of the sample and a diagram explaining the electron beam diffraction pattern. [Figure 70] FIG. 1 is a diagram illustrating EDX mapping of a sample. DETAILED DESCRIPTION OF THE INVENTION

[0032] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0033] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0034] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0035] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0036] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0037] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0038] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0039] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0040] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0041] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , the second connection path does not have a second connection path, and the second connection path is a The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. The third connection path does not have the second connection path, and the third The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path, The second connection path has a connection path through a transistor, and the drain of the transistor (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , does not have a fourth electrical path, and the fourth electrical path is a drain of the transistor (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0042] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0043] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0044] <Notes regarding the description of the drawings>

[0045] In this specification, the terms "above" and "below" that indicate the positional relationship between components are used. , are used for convenience in explanation with reference to the drawings. The meaning of the wording in the specification changes depending on the direction in which the configuration is depicted. It is not limited to this and can be rephrased appropriately depending on the situation.

[0046] In addition, the terms "above" and "below" refer to the positional relationship of the components directly above or below, and directly adjacent to each other. For example, if the expression is "electrode B on insulating layer A," Electrode B does not need to be formed directly on insulating layer A, but between insulating layer A and electrode B This does not exclude the inclusion of other components.

[0047] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0048] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0049] In addition, in the drawings, the size, thickness of a layer, or area is shown arbitrarily for the convenience of explanation. Therefore, the drawings are not necessarily limited to the scale. The drawings are merely schematic illustrations for the purpose of illustration, and are not limited to the shapes or values ​​shown in the drawings.

[0050] In addition, in the drawings, top views (also called plan views or layout views) and perspective views, In order to clarify the drawings, some components may be omitted.

[0051] In addition, "the same" may mean having the same area or the same shape. Due to the manufacturing process, it is expected that the shapes will not be completely identical. This can be rephrased as being the same.

[0052] <Notes regarding possible paraphrases>

[0053] In this specification and the like, when describing the connection relationship of a transistor, one of the source and the drain is referred to as "one of the source and drain" (or the first electrode, or the first terminal), and The other side of the drain is referred to as the "other side of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because it changes depending on the conditions. Regarding the names of the source and drain of a transistor, can be appropriately rephrased as source (drain) terminal, source (drain) electrode, etc. depending on the situation. It can be done.

[0054] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0055] In this specification, a transistor includes a gate, a drain, and a source. It is an element with at least three terminals. And, the drain (drain terminal, drain A channel is formed between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode). The transistor has a channel region and allows current to flow through the drain, channel region, and source. It is possible.

[0056] Here, the source and drain vary depending on the structure or operating conditions of the transistor. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are not called source or drain. One of the source and the drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode. It may be written.

[0057] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of the elements. It should be noted that the numbers are added to avoid confusion and are not intended to be limiting.

[0058] In this specification, the substrate of the display panel is provided with, for example, an FPC (Flexible Printed Circuit). Switched Circuits) or TCP (Tape Carrier Packet ge) or COG (Chip On Glass) on the board A display device is sometimes called a display device when an IC (integrated circuit) is directly mounted on it.

[0059] Also, the words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0060] <Notes on definitions of terms> The definitions of terms used in this specification and the like are explained below.

[0061] In this specification, the term "trench" or "groove" refers to a thin, band-like depression. It refers to the

[0062] <About connection>

[0063] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to the above, it also includes those that are electrically connected. Connected means that there is an object between A and B that has some electrical effect. , which enables the transmission and reception of electrical signals between A and B.

[0064] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the context, and / or one or more other embodiments The contents (or a part of the contents) described in the embodiments may be applied, combined, or replaced. You can do things like drawing.

[0065] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0066] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining the figures (or a part thereof) described in other embodiments of the present invention, This allows for even more diagrams to be constructed.

[0067] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings. explain.

[0068] <Structure of Transistor 10> 1A, 1B, and 1C are top views and diagrams of a transistor 10 according to one embodiment of the present invention. 1(A) is a top view, and FIG. 1(B) is a cross-sectional view of the device shown in FIG. 1(A). 1(C) is a cross-sectional view taken along the line A3-A4 in FIG. 1(A). In (A), some elements have been enlarged, reduced, or omitted for clarity. The dashed line A1-A2 direction is the channel length direction, and the dashed line A3-A4 direction is the channel This may also be referred to as the width direction.

[0069] The transistor 10 comprises a substrate 100, an insulating layer 110, a metal oxide layer 121, an oxide semiconductor layer 122, and a metal oxide semiconductor layer 123. The gate insulating layer 150 is a gate insulating layer 122, a metal oxide layer 123, a low resistance region 125, and a gate insulating layer 150. The substrate 100 includes a first electrode layer 160, an insulating layer 180, a conductive layer 190, and a conductive layer 195.

[0070] An insulating layer 110 is provided on the substrate 100 .

[0071] The metal oxide layer 121 is provided on the insulating layer 110 .

[0072] The oxide semiconductor layer 122 is provided on the metal oxide layer 121. 22 has a low resistance region 125. The low resistance region can be hydrogen, nitrogen, helium, neon, or argon. Any of the following: argon, krypton, xenon, boron, phosphorus, tungsten, or aluminum The low resistance region 125 has a function as a source or a drain. .

[0073] The metal oxide layer 123 is provided over the oxide semiconductor layer 122 .

[0074] A gate insulating layer 150 is provided on the metal oxide layer 123 .

[0075] The gate electrode layer 160 is provided on the gate insulating layer 150. The gate insulating layer 150, the metal oxide layer 123, and the oxide semiconductor layer 122 are overlapped with each other. It will be established.

[0076] The insulating layer 180 is provided on the insulating layer 110 .

[0077] The conductive layer 190 is provided on the low resistance region 125. The conductive layer 190 and the low resistance region 125 , and has an area for electrical connection.

[0078] A conductive layer 195 is provided on the conductive layer 190 .

[0079] The low resistance region 125 can also be partially provided under the gate electrode layer. a first region, a region overlapping the gate electrode layer 160 and partially overlapping the gate electrode layer 160; The low resistance region 125 where the gate electrode layer 160 is not overlapped is referred to as the second region. The second region has a region with a lower resistance than the first region, and the third region is It can be said that the resistance is lower than the second region. It can be obtained by measuring the sheet resistance, for example, and can be controlled by the impurity concentration. In the third region, the concentration of the above elements is 1×10 18 atoms / cm 3 1 x10 22 atoms / cm 3 It has a region that is:

[0080] <About the metal oxide layer> The metal oxide layer (for example, the metal oxide layer 121 and the metal oxide layer 123) is basically It has insulating properties, and when the gate electric field or drain electric field becomes strong, it is A layer through which an electric current can flow.

[0081] The above structure reduces the parasitic capacitance between the gate and source or between the gate and drain. As a result, the cutoff frequency characteristics of the transistor 10 can be improved. This enables high-speed operation of the transistor.

[0082] The transistor 10 also has a self-aligned gate, source, and drain. This makes it easier to align the transistors. It is possible to manufacture it in

[0083] As shown in the cross-sectional view of FIG. 1C, the transistor 10 has a channel width direction The gate electrode layer 160 is connected to the metal oxide layer 121 and the oxide semiconductor layer 122 via the gate insulating layer 150. The conductive layer 122 has a region facing the side surface of the metal oxide layer 123. That is, the gate electrode layer When a voltage is applied to 160, the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide The layer 123 is surrounded by the electric field of the gate electrode layer 160 in the channel width direction. The structure of a transistor in which a semiconductor is surrounded by the electric field of a layer is called a surrounded channel. This is called the el (s-channel) structure.

[0084] Here, the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are combined. When the oxide is formed as a bulk oxide, the transistor 10 is in an on-state. ) and the on-state current increases. The channel region formed in the band-gap oxide semiconductor layer 122 serves as a potential barrier. The off-state current can be further reduced.

[0085] <Channel length> Note that the channel length of a transistor is, for example, The semiconductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate The source (source region) in the region where the source electrode overlaps with the source electrode or the region where the channel is formed The distance between the source electrode and the drain electrode. In addition, the channel length does not necessarily have the same value in all regions of a single transistor. That is, the channel length of a transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one of the lengths in the region where the channel is formed. The value, maximum value, minimum value or average value.

[0086] <About channel width> The channel width is the width of the semiconductor (or transistor) when it is in the on state. This refers to the length of the area where the gate electrode overlaps with the current-carrying part of a transistor. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is any one value, maximum value, minimum value or the like in the region where the channel is formed. or the average value.

[0087] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in transistors with a fine, three-dimensional structure, In some cases, the proportion of the channel region formed may be large. The effective channel width of the channel that is actually formed is larger than the apparent channel width that is The larger the

[0088] In the case of a transistor having a three-dimensional structure, the effective channel width is measured. For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0089] <SCWについて> Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel width in the region is called the "surrounding channel width (SCW)." In this specification, it is sometimes referred to as "Dedicated Channel Width." When we refer to channel width, it refers to enclosed channel width or apparent channel width. In this specification, when simply referring to the channel width, it may refer to the effective channel width. It may refer to the channel width. The upper channel width, the enclosed channel width, etc. are obtained by taking a cross-sectional TEM image. The value can be determined, such as by analysis.

[0090] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0091] <Improved characteristics through miniaturization> To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate as the channel width shrinks. When the value is reduced, the on-state current decreases.

[0092] For example, in the transistor of one embodiment of the present invention shown in FIG. 1, as described above, the channel is formed A metal oxide layer 123 is formed so as to cover an oxide semiconductor layer 122 formed on the substrate. The channel formation region and the gate insulating layer are not in contact with each other. This can suppress the scattering of carriers that occurs at the interface between the gate insulating layer and the The on-current can be increased.

[0093] In the transistor of one embodiment of the present invention, the oxide semiconductor layer 122 serving as a channel Since the gate electrode layer 160 is formed so as to electrically surround the panel in the width direction, the oxide In addition to the gate electric field acting in the vertical direction, the semiconductor layer 122 is also subjected to a gate electric field acting in the lateral direction. That is, a gate electric field is applied to the entire oxide semiconductor layer 122. As a result, the current flows through the entire oxide semiconductor layer 122, which further increases the on-state current. It can be seen.

[0094] In addition, in the transistor of one embodiment of the present invention, the metal oxide layer 123 is formed by the metal oxide layer 121 and the oxide layer 122. By forming the layer on the oxide semiconductor layer 122, it is possible to prevent the formation of interface states. By making the metal oxide layer 122 a layer positioned between the metal oxide layer 121 and the metal oxide layer 123, This can prevent impurities from entering from above and below. In addition to improving the current, the threshold voltage has been stabilized and the S value (subthreshold value) has been reduced. Therefore, it is possible to reduce Icut (current when gate voltage VG is 0V). This allows for a reduction in power consumption. This stabilizes the temperature and improves the long-term reliability of the semiconductor device.

[0095] In addition, in the transistor of one embodiment of the present invention, the oxide semiconductor layer 122 serving as a channel Since the gate electrode layer 160 is formed so as to electrically surround the gate electrode in the width direction, the oxide semiconductor In addition to the gate electric field acting in the vertical direction, the conductor layer 122 is also subjected to the gate electric field acting in the lateral direction. That is, a gate electric field is applied to the entire oxide semiconductor layer 122. This reduces the influence of the drain electric field and significantly suppresses the short channel effect. Therefore, good characteristics can be obtained even when the size is reduced. .

[0096] In addition, in the transistor of one embodiment of the present invention, the oxide semiconductor layer 122 serving as a channel has a wide By using band gap materials, the source-drain breakdown voltage characteristics are high and various The electrical characteristics are stable in a wide range of temperature environments.

[0097] In this embodiment, when an oxide semiconductor layer or the like is used for a channel or the like, However, one aspect of the embodiment of the present invention is not limited to this. or its vicinity, source region, drain region, etc., depending on the situation. , silicon (including strained silicon), germanium, silicon germanium, silicon carbide, Gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors , etc.

[0098] <Transistor components> Each structure of the transistor of this embodiment will be described below.

[0099] <<Substrate 100>> The substrate 100 may be, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a multi-crystal crystalline semiconductor substrate, compound semiconductor substrate made of silicon germanium, SOI (Silicon on Insulator) It is also possible to use a silicon-on-insulator (Si-on-insulator) substrate, and on these substrates The substrate 100 may be a substrate on which a semiconductor element is provided. It may be a substrate on which other devices such as transistors are formed. At least one of the gate, source, and drain of the transistor is electrically connected to the other devices mentioned above. It may be continued.

[0100] A flexible substrate may be used as the substrate 100. As a method for providing a transistor, a transistor is formed on a non-flexible substrate, and then a transistor is formed on the substrate. There is also a method of peeling off the substrate and transferring it to the substrate 100, which is a flexible substrate. A peeling layer may be provided between the substrate and the transistor. Alternatively, a sheet, film, or foil containing the material may be used. In addition, the substrate 100 has the property of returning to its original shape when the bending or pulling is stopped. Alternatively, the substrate 100 may have a property of not returning to its original shape. is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, and The thickness of the substrate 100 is preferably 15 μm or more and 300 μm or less. Furthermore, by making the substrate 100 thinner, it is possible to reduce the weight of the substrate 100 when using glass or the like. It has the property of being stretchable even when bent or pulled, and of returning to its original shape when bending or pulling is stopped. Therefore, the semiconductor device on the substrate 100 may be subjected to a shock due to being dropped or the like. In other words, a robust semiconductor device can be provided.

[0101] The substrate 100, which is a flexible substrate, may be made of, for example, a metal, an alloy, a resin, or glass. The substrate 100, which is a flexible substrate, has a linear expansion coefficient of The lower the temperature, the more preferable it is, since deformation due to the environment is suppressed. For example, the linear expansion coefficient is 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 The resin may be, for example, polyester or polyolefin. Polyimide, polycarbonate, acrylic Aramid, in particular, has a linear expansion coefficient of Since the resistance is low, it is suitable for the substrate 100, which is a flexible substrate.

[0102] Insulating layer 110 The insulating layer 110 is made of silicon (Si), nitrogen (N), oxygen (O), fluorine (F), hydrogen (H ), aluminum (Al), gallium (Ga), germanium (Ge), yttrium ( Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf An insulating film containing one or more of tantalum (Ta) and silicon (Si) can be used.

[0103] The insulating layer 110 serves to prevent the diffusion of impurities from the substrate 100 and also serves to prevent the oxide semiconductor from diffusing. It plays a role in supplying oxygen to the conductor layer 122 (metal oxide layer 121, metal oxide layer 123). Therefore, the insulating layer 110 is preferably an insulating film containing oxygen. It is more preferable that the insulating film contains more oxygen than the stoichiometric composition. The amount of oxygen released, converted to oxygen atoms, is 1.0 x 10 19 atoms / cm 3 That's all The surface temperature of the film during the TDS analysis was 100°C to 700°C. The temperature is preferably in the range of 100° C. or higher and 500° C. or lower. When the substrate 10 is a substrate on which other devices are formed, the insulating layer 110 functions as an interlayer insulating film. In this case, CMP (Chemical Mechanical Polishing) is used to make the surface flat. It is preferable to perform a planarization process using a method such as an anical polishing method.

[0104] Furthermore, since the insulating layer 110 contains fluorine, the gasified fluorine can be easily removed from the insulating layer. Fluorine can stabilize oxygen vacancies in the oxide semiconductor layer 122.

[0105] <<Metal oxide layer 121, oxide semiconductor layer 122, metal oxide layer 123>> The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are made of In or Zn. The oxide semiconductor film includes, for example, an In-Ga oxide, an In-Zn oxide, or an In -Mg oxide, Zn-Mg oxide, In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd).

[0106] The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 can be formed by The oxide preferably contains at least indium (In) or zinc (Zn). Alternatively, it is preferable that both In and Zn are contained. To reduce the variation in the electrical characteristics of the transistors, stabilizers are included along with them. It is preferable.

[0107] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Aluminum (Al) or zirconium (Zr). Also, other stabilizers The lanthanides are lanthanum (La), cerium (Ce), and praseodymium (P r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Er, Thulium, Ytterbium, Lutetium, etc. .

[0108] Indium and gallium in the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 The content of ammonium and other elements was measured using time-of-flight secondary ion mass spectrometry (TOF-SIMS) and X-ray electron spectroscopy. Comparison can be made using X-ray photoelectron spectroscopy (XPS) and inductively coupled plasma mass spectrometry (ICP-MS).

[0109] The oxide semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more. More preferably, the voltage is 3 eV or more, so that the off-state current of the transistor 10 can be reduced. can.

[0110] The thickness of the oxide semiconductor layer 122 is 3 nm to 200 nm, preferably 3 nm to 100 nm. 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0111] The thickness of the oxide semiconductor layer 122 is at least thinner than that of the metal oxide layer 121. For example, an oxide semiconductor When the layer 122 is thickened, the on-state current of the transistor can be increased. The oxide layer 121 is formed to a degree that does not impair the effect of suppressing the generation of interface states in the oxide semiconductor layer 122. For example, the thickness of the oxide semiconductor layer 122 may be set to be equal to or greater than that of the metal oxide layer 121. More than 1 time, or 2 times or more, or 4 times or more, or 6 times or more of the thickness In addition, when it is not necessary to increase the on-state current of the transistor, a metal oxide The thickness of the oxide semiconductor layer 121 may be equal to or greater than the thickness of the oxide semiconductor layer 122. For example, When oxygen is added to the insulating layer 180, the oxide semiconductor layer 1 The amount of oxygen vacancies contained in 22 can be reduced, and the electrical characteristics of the semiconductor device can be stabilized. This can be done.

[0112] The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, each combination When the composition is different, the interface is observed by scanning transmission electron microscope (STEM). It can be observed using a transmission electron microscope (SEM). It may be possible.

[0113] The oxide semiconductor layer 122 is more insulating than the metal oxide layer 121 and the metal oxide layer 123. In the oxide semiconductor layer, the s orbital of the heavy metal is the carrier. By increasing the In content, more s orbitals overlap, which contributes to the conductivity. Therefore, oxides with a composition in which In is greater than M are oxides with a composition in which In is equal to or less than M. Therefore, when the oxide semiconductor layer 122 has a high indium content, the oxide semiconductor layer 122 has a high indium content. By using oxides with a high content of ZnO, it is possible to realize transistors with high field-effect mobility. do.

[0114] The oxide semiconductor layer 122 is an In-M-Zn oxide (wherein M is Al, Ti, Ga, Y, or Sn). , Zr, La, Ce, Mg, Hf, or Nd), oxide semiconductors can be obtained by sputtering. In the target used to form the metal layer 122, the atomic ratio of the metal elements is In:M :If Zn=x2:y2:z2, then x2 / (x2+y2+z2) is 1 / 3 or more. The oxide semiconductor layer 122 also has a similar composition ratio of metal atoms. Furthermore, x2 / y2 is 1 / 3 or more and 6 or less, and further 1 or more and 6 or less, and z2 / y2 is It is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. The conductor layer 122 is made of CAAC-OS (C-Axis Aligned Crystalline This makes it easier for a thin film of oxide semiconductor to form on the target. Typical examples of atomic ratios of metal elements are In:M:Zn=1:1:1, In:M:Z n=1:1:1.2, 2:1:1.5, 2:1:2.3, 2:1:3, 3:1:2, 4: Examples include 2:3, 4:2:4.1, etc.

[0115] The metal oxide layer 121 and the metal oxide layer 123 may include Al, Ti, Ga, Y, Zr, Sn, By having La, Ce, Mg, Hf or Nd in a higher atomic ratio than In, the following effects can be achieved: (1) The energy gain of the metal oxide layer 121 and the metal oxide layer 123 may be increased. (2) The electron affinity of the metal oxide layer 121 and the metal oxide layer 123 is reduced. (3) It blocks impurities from the outside. (4) It is smaller than the oxide semiconductor layer 122. , and the insulating properties improve. (5) Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, H Since f or Nd is a metal element with a strong bond with oxygen, it is difficult to bond with Al, Ti, Ga, Y, Having Zr, Sn, La, Ce, Mg, Hf, or Nd in a higher atomic ratio than In This makes it difficult for oxygen deficiency to occur.

[0116] The metal oxide layer 121 and the metal oxide layer 123 constitute the oxide semiconductor layer 122. Therefore, the oxide semiconductor layer 122 and the gold At the interfaces with the metal oxide layer 121 and the metal oxide layer 123, interfacial scattering is unlikely to occur. Therefore, the movement of carriers is not hindered at the interface, and the transistor 10 The field effect mobility is increased.

[0117] The metal oxide layer 121 and the metal oxide layer 123 are typically made of In-Ga oxide or In-Z n-oxide, In-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-M-Zn oxide oxides (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd) and the energy level of the conduction band minimum is closer to the vacuum level than that of the oxide semiconductor layer 122. Typically, the energy levels at the bottom of the conduction band of the metal oxide layer 121 and the metal oxide layer 123 are and the energy level of the oxide semiconductor layer 122 is 0.05 eV or more; 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less, 1 eV or more That is, the metal oxide layer 121, the metal oxide layer 122, the metal oxide layer 123, the metal oxide layer 124, the metal oxide layer 125, the metal oxide layer 126, the metal oxide layer 127, the metal oxide layer 128, the metal oxide layer 129, the metal oxide layer 130, the metal oxide layer 131, the metal oxide layer 132, the metal oxide layer 133, the metal oxide layer 134, the metal oxide layer 135, the metal oxide layer 136, the metal oxide layer 137, the metal oxide layer 138, the metal oxide layer 139 ... The difference between the electron affinity of the oxide semiconductor layer 123 and the electron affinity of the oxide semiconductor layer 122 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.2 eV or more and 2 eV or less , 1 eV or less, 0.5 eV or less, or 0.4 eV or less. This indicates the difference between the empty energy level and the energy level at the bottom of the conduction band.

[0118] Also, when the metal oxide layers 121 and 123 are In-M-Zn oxides (M is Al, T i, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), compared with the oxide semiconductor layer 122 formed by sputtering, the atomic ratio of M (Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd) contained in the metal oxide layers 121 and 123 is high, and the element represented by M above binds more strongly to oxygen than indium. Therefore, it has the function of suppressing the occurrence of oxygen deficiency in the metal oxide layers 121 and 123. That is, the metal oxide layers 121 and 123 are oxide semiconductor films in which oxygen deficiency is less likely to occur than in the oxide semiconductor layer 122. The metal oxide layers 121 and 123 also have a similar composition in terms of the atomic ratio of metal atoms. Also, when the metal oxide layer 121 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), in the target used to form the metal oxide layer 121, if the atomic ratio of metal elements is In:M:Zn = x1:y1:z 1, then x1 / y1 < z1 / y1, and z1 / y1 is preferably 1 / 10 or more and 6 or less, and further preferably 0.2 or more and 3 or less. Also, since the metal oxide layers 121 and 123 have higher insulating properties compared to the oxide semiconductor layer 122, they can have the same function as the gate insulating layer. Also, the metal oxide layer 123 can be replaced with a metal oxide such as aluminum oxide, gallium oxide, hafnium oxide, silicon oxide, germanium oxide, or zirconia. The metal oxide layers 121 and 123 have a similar composition in terms of the atomic ratio of metal atoms.

[0119] Also, when the metal oxide layer 121 is an In-M-Zn oxide (M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), in the target used to form the metal oxide layer 121, if the atomic ratio of metal elements is In:M:Zn = x1:y1:z 1, then x1 / y1 < z1 / y1, and z1 / y1 is preferably 1 / 10 or more and 6 or less, and further preferably 0.2 or more and 3 or less. 1, then x1 / y1 < z1 / y1, and z1 / y1 is preferably 1 / 10 or more and 6 or less, and further preferably 0.2 or more and 3 or less. Furthermore, it is preferable that z1 / y1 is 0.2 or more and 3 or less.

[0120] Also, since the metal oxide layers 121 and 123 have higher insulating properties compared to the oxide semiconductor layer 122, they can have the same function as the gate insulating layer.

[0121] Also, the metal oxide layer 123 can be replaced with a metal oxide, for example, aluminum oxide, gallium oxide, hafnium oxide, silicon oxide, germanium oxide, or zirconia. ​​Alternatively, the metal oxide may be present on the metal oxide layer 123.

[0122] In addition, the metal oxide layer 123 has the effect of suppressing the generation of interface states in the oxide semiconductor layer 122. For example, the thickness may be equal to or less than the thickness of the metal oxide layer 121. If the metal oxide layer 123 is thick, the electric field generated by the gate electrode layer 160 may cause oxidation. Therefore, the metal oxide layer 123 is formed thinly. For example, the thickness of the metal oxide layer 123 is preferably thinner than that of the oxide semiconductor layer 122. However, the thickness of the metal oxide layer 123 is not limited to this, and may be the same as the thickness of the gate insulating layer 150 The value may be appropriately set according to the voltage at which the transistor is driven, taking into consideration the breakdown voltage of the transistor.

[0123] For example, the thickness of the metal oxide layer 123 is 1 nm or more and 20 nm or less, or 3 nm or more and 10 nm or less. It is preferable to set it to nm or less.

[0124] The metal oxide layer 121 and the metal oxide layer 123 are made of In-M-Zn oxide (M is Al, T i, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd), metal oxide In the target used for depositing the metal oxide layer 121 and the metal oxide layer 123, If the atomic ratio is In:M:Zn=x3:y3:z3, then x3 / y3 <x2 / y2であっ Therefore, z3 / y3 is preferably 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. By setting z3 / y3 to 1 or more and 6 or less, the metal oxide layer 121 and the metal oxide layer 123 The CAAC-OS film is easily formed as a result of the atomic ratio of the target metal elements. Examples include In:M:Zn=1:3:2, 1:3:4, 1:3:6, 1:3:8, 1: 4:4, 1:4:5, 1:4:6, 1:4:7, 1:4:8, 1:5:5, 1:5:6, Examples include 1:5:7, 1:5:8, 1:6:8, 1:6:4, 1:9:6, etc. The ratio is not limited to these, and any suitable atomic ratio may be used depending on the required semiconductor characteristics. good.

[0125] The atomic ratio of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 is Each of these may contain a margin of error of ±40% from the atomic ratios listed above.

[0126] For example, when an oxide semiconductor film that becomes the oxide semiconductor layer 122 is formed, In the target, the atomic ratio of metal elements is In:Ga:Zn=1:1:1. When the oxide semiconductor film is formed, the atomic ratio of metal elements is In:Ga:Zn=1:1:0.6. The atomic ratio of zinc may be the same or may decrease. When the atomic ratio is described, the vicinity of the atomic ratio is included.

[0127] <About hydrogen concentration> Hydrogen contained in the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 reacts with oxygen bonded to metal atoms to form water, and the lattice (or acid) from which oxygen is released When hydrogen enters the oxygen vacancy, the carrier In some cases, electrons are generated. Also, some of the hydrogen atoms bond with oxygen atoms that bond with metal atoms. Therefore, the acid containing hydrogen may generate electrons as carriers. A transistor using a nitride semiconductor layer tends to have a normally-on characteristic.

[0128] Therefore, the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and the At each interface, it is preferable that oxygen vacancies and hydrogen are reduced as much as possible. For example, the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and Secondary ion mass spectrometry (SIMS) was performed at each interface. The hydrogen concentration obtained by mass spectrometry was 1×10 16 at oms / cm 3 Over 2×10 20 atoms / cm 3 Less than 1 × 10 16 at oms / cm 3 5x10 or more 19 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below, more preferably 1 × 1 0 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 It is desirable to do the following: As a result, the transistor 10 has electrical characteristics in which the threshold voltage is positive (normal This is also called an off characteristic.

[0129] <Carbon and silicon concentrations> In addition, the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and If silicon or carbon, which is one of the group 14 elements, is included at the interface, the metal oxide The oxygen vacancies increase in the layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123. Therefore, the metal oxide layer 121 and the oxide semiconductor layer 122 are not uniformly doped with the metal oxide layer 121 and the oxide semiconductor layer 122. The silicon and carbon concentrations at the metal oxide layer 123 and their respective interfaces are low. For example, the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide The silicon and carbon concentrations obtained by SIMS at the interface between the silicon layer 123 and ... Degrees are 1 x 10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below, I prefer Or 1 x 10 16 atoms / cm 3 5x10 or more 18 atoms / cm 3 Below, further Preferably 1 x 10 16 atoms / cm 3 Over 2×10 18 atoms / cm 3 below As a result, the transistor 10 has a voltage whose threshold voltage is positive. It has temperamental properties.

[0130] <Alkali metal and alkaline earth metal concentrations> In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and their respective interfaces It is preferable to reduce the concentration of alkali metals or alkaline earth metals in the For example, a metal oxide layer 121, an oxide semiconductor layer 122, a metal oxide layer 123, and At the interface of the alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry The metal concentration is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atom s / cm 3 This allows the transistor 10 to have a threshold voltage of It can have electrical properties in which the

[0131] <Regarding nitrogen concentration> In addition, the metal oxide layer 121, the oxide semiconductor layer 122, the metal oxide layer 123, and If nitrogen is present at the interface, electrons acting as carriers are generated, increasing the carrier density. As a result, an n-type region is formed. Therefore, the metal oxide layer 121 and the oxide semiconductor Nitrogen is preferably as low as possible in the conductor layer 122, the metal oxide layer 123, and their interfaces. For example, the metal oxide layer 121, the oxide semiconductor layer 122, and the gold The nitrogen concentration obtained by SIMS at the metal oxide layer 123 and at the respective interfaces is 1×10 15 atoms / cm 3 5x10 or more 19 atoms / cm 3 Below, preferably 1×10 15 atoms / cm 3 5x10 or more 18 atoms / cm 3 The following is more preferred: 1×10 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 Further details are as follows: Preferably 1 x 10 15 atoms / cm 3 5x10 or more 17 atoms / cm 3 Below This allows the transistor 10 to have a voltage that makes the threshold voltage positive. It can have temperamental properties.

[0132] However, this does not apply when excess zinc is contained in the oxide semiconductor layer 122. Excess zinc may cause oxygen vacancies in the oxide semiconductor layer 122. When zinc is contained, the oxide semiconductor layer 122 contains 0.001 to 3 atomic % of nitrogen. By having the element, oxygen deficiency caused by excess zinc may be inactivated. Therefore, the nitrogen eliminates variations in transistor characteristics and improves reliability. It can be done.

[0133] <About carrier density> Reducing impurities in the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 By this, the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 Therefore, the carrier density can be reduced. 122 and the metal oxide layer 123 have a carrier density of 1×10 15 pieces / cm 3 Below is good Preferably 1 x 10 13 pieces / cm 3 Less than 8 × 10, more preferably 11 pieces / cm 3 less than, More preferably 1 × 10 11 pieces / cm 3 less than 1 x 10 10 pieces / cm 3 Not yet is 1×10 -9 pieces / cm 3 That's all.

[0134] The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are formed by adding impurities. By using an oxide semiconductor layer with a low concentration and a low density of defect states, even better electrical characteristics can be achieved. Here, a transistor having a low impurity concentration and a defect level can be manufactured. Low density (low oxygen deficiency) is called high purity intrinsic or substantially high purity intrinsic. An oxide semiconductor layer that is pure intrinsic or substantially highly pure intrinsic has a small carrier generation source. Therefore, the carrier density can be reduced in some cases. The transistor in which the channel region is formed tends to have electrical characteristics in which the threshold voltage is positive. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor layer has a high density of defect states. The trap level density may also be low due to the low concentration. A transistor using a highly purified intrinsic oxide semiconductor layer has an extremely small off-state current. When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, The off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 After A Therefore, a channel region is formed in the oxide semiconductor layer. The transistors that are produced by this method may have little fluctuation in electrical characteristics and may become highly reliable. be.

[0135] In addition, a transistor using the above-described highly purified oxide semiconductor layer for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is 0.1 V, 5 V or about 10V, the off-state current normalized by the transistor channel width It is possible to reduce the current density to several yA / μm to several zA / μm.

[0136] The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may be, for example, a non-single layer. The non-single crystal structure may be, for example, a CAAC-OS, a polycrystalline structure, or a microcrystalline structure, which will be described later. It includes crystalline structure and amorphous structure. In non-single crystalline structure, the amorphous structure has the most defect level. The density of defect states is high in CAAC-OS, and the density of defect states is lowest in CAAC-OS.

[0137] The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are, for example, finely divided. The metal oxide layer 121, the oxide semiconductor layer 122, and the metal The oxide layer 123 contains, for example, microcrystals with a size of 1 nm or more and less than 10 nm in the film. Alternatively, the oxide film and the oxide semiconductor film having a microcrystalline structure may have an amorphous phase having a thickness of 1 nm or more. It has a mixed phase structure with crystalline parts less than 0 nm.

[0138] The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are, for example, amorphous. The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 may have an amorphous structure. The metal oxide layer 123 has, for example, a disordered atomic arrangement and does not have a crystalline component. The amorphous oxide film and oxide semiconductor film have, for example, a completely amorphous structure and are not crystalline. It has no department.

[0139] The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are formed by CA It was a mixed film having regions of two or more structures: AC-OS, microcrystalline structure, and amorphous structure. The mixed film may be, for example, a film having an amorphous structure, a microcrystalline structure, and a CAAC Alternatively, a mixed film may have a single layer structure having an amorphous structure. The structure has a stacked structure of a region with a crystal structure, a region with a microcrystalline structure, and a region with a CAAC-OS structure.

[0140] The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are, for example, For example, it may have a single crystal structure.

[0141] The oxide film is less likely to have oxygen vacancies than the oxide semiconductor layer 122. By providing the insulating film 121 above and below the insulating film 121, oxygen vacancies in the oxide semiconductor layer 122 can be reduced. In addition, the oxide semiconductor layer 122 can be formed by adding one of the metal elements constituting the oxide semiconductor layer 122. Since the metal oxide layer 121 and the metal oxide layer 123 are in contact with each other, the metal oxide layer 12 the interface between the oxide semiconductor layer 122 and the metal oxide layer 123; For example, the interface state density at the surface of the metal oxide layer 121 is extremely low. 3. After adding oxygen to the gate insulating layer 150, the insulating layer 110, and the insulating layer 180, heat treatment is performed. By this, the oxygen is transferred to the oxide semiconductor via the metal oxide layer 121 and the metal oxide layer 123. Oxygen moves to the dielectric layer 122, but at this time, oxygen is not easily captured by the interface state, and the efficiency is improved. The oxygen contained in the metal oxide layer 121 or the metal oxide layer 123 is efficiently removed from the oxide semiconductor layer 1 As a result, oxygen vacancies in the oxide semiconductor layer 122 can be removed. In addition, the metal oxide layer 121 or the metal oxide layer 123 can be formed by Since oxygen is added to the metal oxide layer 121 and the metal oxide layer 123, oxygen deficiency in the metal oxide layer 121 and the metal oxide layer 123 is reduced. That is, it is possible to reduce the localized state density of at least the oxide semiconductor layer 122. It is possible.

[0142] In addition, the oxide semiconductor layer 122 may be formed of an insulating film having a different constituent element (for example, a silicon oxide film). When the semiconductor comes into contact with the gate insulating layer, an interface state is formed, and the interface state forms a channel. In such a case, a second transistor with a different threshold voltage appears, However, the apparent threshold voltage of the oxide semiconductor The metal oxide layer 121 and the metal oxide layer 122 each contain one or more metal elements. 3 is in contact with the oxide semiconductor layer 122, the metal oxide layer 121 and the oxide semiconductor layer 122 and the interface between the metal oxide layer 123 and the oxide semiconductor layer 122. It becomes.

[0143] The metal oxide layer 121 and the metal oxide layer 123 are the insulating layer 110 and the gate insulating layer 112, respectively. The constituent elements of the layer 150 are mixed into the oxide semiconductor layer 122, and an impurity level is formed. It also functions as a barrier film to prevent this.

[0144] For example, the insulating layer 110 or the gate insulating layer 150 may be an insulating film containing silicon. In this case, the silicon in the gate insulating layer 150 or the insulating layer 110 and the gate insulating layer 150 The carbon that can be mixed in the metal oxide layer 121 or the metal oxide layer 123 flows from the interface into the metal oxide layer 121 or the metal oxide layer 123. The impurities such as silicon and carbon may be mixed into the oxide semiconductor layer 122 to a depth of several nanometers. When it enters the electrons, it forms an impurity level, which acts as a donor and generates electrons, making the material n-type. Sometimes I do.

[0145] However, if the thickness of the metal oxide layer 121 and the metal oxide layer 123 is thicker than several nm, In this case, impurities such as silicon and carbon do not reach the oxide semiconductor layer 122. The influence of impurity levels is reduced.

[0146] Therefore, by providing the metal oxide layer 121 and the metal oxide layer 123, The variation in electrical characteristics such as threshold voltage can be reduced.

[0147] In addition, the gate insulating layer 150 and the oxide semiconductor layer 122 come into contact with each other, and a channel is formed at the interface. If the interface is too thick, interface scattering occurs at the interface, reducing the field-effect mobility of the transistor. However, the metal oxide layer 12 containing one or more metal elements constituting the oxide semiconductor layer 122 1. The metal oxide layer 123 is provided in contact with the oxide semiconductor layer 122. At the interfaces between the layer 122 and the metal oxide layer 121 and the metal oxide layer 123, scattering of carriers occurs. This makes it difficult for the electrons to be broken down, and the field effect mobility of the transistor can be increased.

[0148] In this embodiment, the amount of oxygen vacancies in the oxide semiconductor layer 122 and the oxide semiconductor layer The amount of oxygen vacancies in the metal oxide layer 121 and the metal oxide layer 123 in contact with the metal oxide layer 122 can be reduced. This makes it possible to reduce the density of localized states in the oxide semiconductor layer 122. The transistor 10 described in this embodiment has the following characteristics: it has little fluctuation in threshold voltage and is highly reliable. Furthermore, the transistor 10 described in this embodiment has excellent electrical characteristics. It has.

[0149] Note that an insulating film containing silicon is often used as a gate insulating layer of a transistor. For the above reasons, the region serving as a channel of the oxide semiconductor layer is It can be said that a structure that does not come into contact with the gate insulating layer, such as a gate electrode, is preferable. When a channel is formed at the interface between the insulating layer and the oxide semiconductor layer, carriers are scattered at the interface. This can cause a decrease in the field-effect mobility of the transistor. It is preferable that the region of the oxide semiconductor layer that serves as a channel be separated from the gate insulating layer. .

[0150] Therefore, the laminated structure of the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 With this structure, a channel can be formed in the oxide semiconductor layer 122, and a high field effect A transistor having high mobility and stable electrical characteristics can be formed.

[0151] The oxide semiconductor layer does not necessarily have to be a three-layer structure, but may be a single layer, two layers, four layers, or even five layers. In the case of a single layer, the oxide semiconductor layer 12 shown in this embodiment may have a structure of more than one layer. A layer equivalent to 2 can be used.

[0152] <Band diagram> Here, band diagrams of the transistor of one embodiment of the present invention will be described with reference to FIGS. 2A and 2B. The band diagram shown in FIG. 2(B) is a diagram showing the insulating layer 110, the metal an oxide layer 121, an oxide semiconductor layer 122, a metal oxide layer 123, and a gate insulating layer 15; 0, the energy level at the bottom of the conduction band (Ec) and the energy level at the top of the valence band (Ev).

[0153] As shown in FIG. 2B, a metal oxide layer 121, an oxide semiconductor layer 122, and a metal oxide layer 1 In the metal oxide layer 23, the energy level of the conduction band minimum changes continuously. The oxide semiconductor layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 are made of the same elements. This can be understood from the fact that oxygen easily diffuses between the metal oxide layers 121 and 122. The oxide semiconductor layer 122 and the metal oxide layer 123 are stacked layers of films with different compositions, but the physical properties are the same. It can also be said to be essentially continuous.

[0154] The oxide semiconductor film, which is stacked with the same main component, is not simply stacked but is joined continuously. In this case, the energy level of the conduction band edge changes continuously between layers. The U-Shape Well structure is formed. There are no impurities at the interface that can form defect levels such as trap centers or recombination centers. If impurities are present between the layers of the laminated multilayer film, The continuity of the energy band is lost, and carriers are trapped or disappear by recombination at the interface. It will be destroyed.

[0155] The metal oxide layer 121 and the metal oxide layer 123 have the same Ec. 2(B), but they may be different.

[0156] As shown in FIG. 2B, the oxide semiconductor layer 122 serves as a well, and the oxide semiconductor layer 122 is It can be seen that a channel is formed in the oxide semiconductor layer 122. The conduction band bottom energy changes continuously from the bottom of the layer 122. The channel can also be called a buried channel.

[0157] The metal oxide layer 121 and the metal oxide layer 123 are connected to an insulating film such as a silicon oxide film. In the vicinity of the interface, trap levels due to impurities or defects may be formed. The presence of the oxide semiconductor layer 122 can separate the trap states. However, the Ec of the metal oxide layer 121 or the metal oxide layer 123 and the oxide semiconductor When the energy difference between the Ec of the oxide semiconductor layer 122 and the Ec of the oxide semiconductor layer 122 is small, electrons in the oxide semiconductor layer 122 The electrons that have a negative charge can reach the trap level beyond the energy difference. When the electrons are trapped in the level, a negative fixed charge is generated at the interface of the insulating film, and the threshold of the transistor is reached. Furthermore, in long-term storage tests of transistors, Therefore, there is a concern that the traps may not be fixed and may cause fluctuations in characteristics.

[0158] Therefore, to reduce the variation in the threshold voltage of the transistor, the metal oxide layer 121, and an energy difference is provided between Ec of the metal oxide layer 123 and the oxide semiconductor layer 122. The respective energy differences are preferably 0.1 eV or more, and 0. More preferably, it is 2 eV or more.

[0159] The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 each have a crystalline portion. It is preferable that the crystals are included. In particular, the use of c-axis oriented crystals makes the transistor stable. It is possible to impart excellent electrical properties.

[0160] In the band diagram shown in FIG. 2B, the metal oxide layer 123 is not provided, and the oxide An In-Ga oxide (for example, an In-Ga oxide having an atomic ratio of I Alternatively, gallium oxide or the like may be used. Alternatively, the metal oxide layer 123 may be connected to the gate electrode 124 while the metal oxide layer 123 is in the state where the metal oxide layer 123 is provided. An In-Ga oxide may be provided between the insulating layers 150, or gallium oxide may be provided. It is okay to do so.

[0161] The oxide semiconductor layer 122 is more electron-philic than the metal oxide layer 121 and the metal oxide layer 123. For example, the oxide semiconductor layer 122 may be a metal oxide layer 12 1 and the metal oxide layer 123, and has an electron affinity of 0.07 eV or more and 1.3 eV or less. Preferably, 0.1 eV or more and 0.7 eV or less, and more preferably 0.2 eV or more and 0.4 eV or less. Larger oxides can be used.

[0162] The transistor described in this embodiment includes at least one metal element included in the oxide semiconductor layer 122. The metal oxide layer 121 includes a metal oxide layer 123. The interface between the metal oxide layer 121 and the oxide semiconductor layer 122, and the interface between the metal oxide layer 123 and the oxide semiconductor layer Therefore, the interface state is hardly formed at the interface between the metal oxide layer 121 and the metal oxide layer 122. By providing the material layer 123, the variation in electrical characteristics such as the threshold voltage of the transistor can be reduced. and fluctuations can be reduced.

[0163] Gate insulating layer 150 The gate insulating layer 150 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al ), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge ), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd) , hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlO x ), magnesium oxide (MgO x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon oxynitride (SiN x O y ) , silicon nitride (SiN x ), gallium oxide (GaOx ), germanium oxide (GeO x ), yttrium oxide (YO x ), zirconium oxide (ZrO x ), lanthanum oxide (La O x ), neodymium oxide (NdO x ), hafnium oxide (HfO x ) and tantalum oxide ( TaO x The gate insulating layer 150 may be a stack of the above materials. The gate insulating layer 150 may be formed of lanthanum (La), nitrogen, zirconium, or the like. It may contain impurities such as Zr.

[0164] Next, an example of the stacked structure of the gate insulating layer 150 will be described. The gate insulating layer 150 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and preferably includes silicon oxide or silicon oxynitride.

[0165] Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the thickness of the gate insulating layer 150 can be increased compared to when silicon oxide is used. Therefore, the leakage current due to the tunnel current can be reduced. Furthermore, hafnium oxide, which has a crystalline structure, can be used to realize an amorphous transistor. It has a higher dielectric constant than hafnium oxide, which has a porous structure. To make a small transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these.

[0166] By the way, the surface on which hafnium oxide having a crystalline structure is formed has interface states due to defects. The interface states may function as trap centers. When hafnium oxide is placed close to the channel region of a transistor, the interface states This may cause deterioration of the electrical characteristics of the transistor. To achieve this, another film is placed between the channel region of the transistor and the hafnium oxide. It may be preferable to separate the membranes from each other by using a The film having the buffer function may be a film included in the gate insulating layer 150, or may be an oxide semiconductor. The film may be a film included in the conductive film. That is, the film having a buffer function may be silicon oxide. A silicon oxynitride layer, an oxide semiconductor layer, or the like can be used. The film to be formed may include, for example, a semiconductor having a larger energy gap than the semiconductor that will be the channel region. Alternatively, the film having a buffer function may be formed by, for example, forming a channel region and A semiconductor or insulator having a smaller electron affinity than the semiconductor is used. The film has, for example, a layer having a larger ionization energy than the semiconductor that becomes the channel region. A semiconductor or insulator is used.

[0167] On the other hand, the interface states (trap By trapping charge in the charge center, the threshold voltage of the transistor can be controlled. In order to make the charge exist stably, for example, the channel region and hafnium oxide If an insulator with a larger energy gap than hafnium oxide is placed between the hafnium and the Alternatively, if a semiconductor or insulator with a smaller electron affinity than hafnium oxide is placed, Alternatively, a film with a buffer function may be made of hafnium oxide with a larger ionization energy than hafnium oxide. By using such an insulator, the interface state This makes it difficult for the trapped charge to be released, and the charge can be retained for a long period of time. can.

[0168] Examples of such insulators include silicon oxide and silicon oxynitride. In order to trap charges in the interface state in the gate insulating layer 150, the gate potential is Electrons can be moved toward the polar layer 160. , 125°C or higher and 450°C or lower, typically 150°C or higher and 300°C or lower), The potential of the electrode layer 160 is set higher than the potential of the source electrode layer 130 and the drain electrode layer 140. It is sufficient to maintain the temperature for at least one second, typically at least one minute.

[0169] In this way, a transistor in which a desired number of electrons are trapped in the interface states of the gate insulating layer 150 or the like is formed. The threshold voltage of the gate electrode layer 160 is shifted to the positive side. By adjusting the time for capturing electrons, the amount of electrons captured (the amount of change in threshold voltage) can be controlled. If charges can be trapped, they can be trapped in the gate insulating layer 150. A laminated film having a similar structure may be used for other insulating layers.

[0170] For example, if a conductive layer is provided under the transistor 10, the insulating layer 110 may be a gate insulating layer 1 50 may have the same structure and function.

[0171] Gate electrode layer 160 The gate electrode layer 160 may include, for example, aluminum (Al), titanium (Ti), chromium (C r), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium Zirconium (Zr), Molybdenum (Mo), Ruthenium (Ru), Silver (Ag), Tantalum (T The substrate may have materials such as tungsten (W), silicon (Si), or silicon dioxide (C). The gate electrode layer 160 may be a laminated layer. Alternatively, they may be used in combination, or in combination with a material containing nitrogen, such as a nitride of the above materials. They may also be used in combination.

[0172] Insulating layer 180 The insulating layer 180 is made of, for example, magnesium oxide (MgO x ), silicon oxide (SiO x ) , silicon oxynitride (SiO x N y ), silicon oxynitride (SiN x O y ), silicon nitride SiN x ), gallium oxide (GaO x ), germanium oxide (GeO x ), oxide Thorium (YO x ), zirconium oxide (ZrO x ), lanthanum oxide (LaO x ), oxidation Neodymium (NdO x ), hafnium oxide (HfO x ) and tantalum oxide (TaO x ), Aluminum oxide (AlO x ) can be used as an insulating film. Layer 180 may be a stack of the above materials. The insulating layer may have a higher than stoichiometric composition. The oxygen released from the insulating layer 180 passes through the gate insulating layer 150. The oxide semiconductor layer 122 can be diffused into the channel formation region through the oxide semiconductor layer 122. Oxygen vacancies formed in the channel formation region can be filled with oxygen. The electrical characteristics of the transistor can be obtained.

[0173] Conductive layer 190 The conductive layer 190 can be formed using a material similar to that of the gate electrode layer 160 .

[0174] Conductive Layer 195 The conductive layer 195 can be formed using a material similar to that of the gate electrode layer 160 .

[0175] <Transistor manufacturing method> Next, a method for manufacturing the semiconductor device according to this embodiment will be described with reference to FIGS. Note that the parts that overlap with those explained in the above transistor configuration will be omitted. The A1-A2 direction shown in FIGS. 5 to 13 corresponds to the channel shown in FIGS. 1(A) and 1(B). 5 to 13 is the same as the direction of the arrow A3-A4 in FIG. This direction may be referred to as the channel width direction shown in FIG. 1(A) and FIG. 1(C).

[0176] In this embodiment, each layer constituting a transistor (an insulating layer, an oxide semiconductor layer, a conductive layer etc.) are the sputtering method, chemical vapor deposition (CVD), deposition method, vacuum evaporation method, pulsed laser deposition (PLD) method Alternatively, the film can be formed by a coating method or a laser deposition method. It can be formed by printing. Film formation methods include sputtering and plasma CVD. A typical example of the thermal CVD method is metal organic chemical vapor deposition (MOCVD). The metal organic chemical vapor deposition (MOCVD) method or the atomic layer deposition (ALD) method may be used. Also, in the sputtering method, the embedding property can be improved by combining the long throw method and the collimator method. Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage. Also, in the thermal CVD method, the source gas and the oxidant are simultaneously fed into the chamber, and the chamber is under atmospheric pressure or reduced pressure, and reacted near or on the substrate to be deposited on the substrate to form a film. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc.

[0177] <Thermal CVD method> Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage. Also, in the thermal CVD method, the source gas and the oxidant are simultaneously fed into the chamber, and the chamber is under atmospheric pressure or reduced pressure, and reacted near or on the substrate to be deposited on the substrate to form a film.

[0178] Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc.

[0179] Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described above. For example, when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc.

[0180] <ALD method> Conventional CVD deposition equipment requires a precursor gas for the reaction during deposition. One or more of the above are simultaneously supplied to the chamber. Precursors for the reaction are introduced into the chamber in sequence, and the gas introduction sequence is repeated. For example, by switching each switching valve (also called high-speed valve), Two or more precursors are supplied to the chamber in sequence by switching between them, and multiple precursors are mixed. To avoid this, an inert gas (such as argon or nitrogen) is added after the first precursor. In addition, instead of introducing an inert gas, a vacuum pump is used. Thus, after the first precursor is evacuated, the second precursor can be introduced.

[0181] Figures 3(A), (B), (C), and (D) show the film formation process by the ALD method. O1 is adsorbed onto the surface of the substrate (see FIG. 3(A)), and a first monolayer is formed (see FIG. 3(B)). In this case, metal atoms contained in the precursor bond with hydroxyl groups present on the substrate surface. The metal atom is bonded to an alkyl group such as a methyl group or an ethyl group. The first precursor 601 is evacuated and then reacted with the second precursor 602 introduced. In response (see FIG. 3(C)), a second monolayer is deposited on the first monolayer to form a thin film. (See Figure 3(D)). For example, if an oxidizing agent is included as the second precursor, a metal atom or an alkyl group bonded to a metal atom present in the first precursor; and an oxidizing agent A chemical reaction occurs between the oxide film and the silicon dioxide.

[0182] The ALD method is a film formation method based on surface chemical reactions, in which precursors are adsorbed onto the surface to be filmed, A self-limiting mechanism acts, and the resulting layer is formed. For example, trimethylaluminum Such precursors react with the hydroxyl groups (OH groups) present on the surface of the film to be formed. Since only surface reactions occur due to the precursor coming into contact with the surface to be coated, the thermal energy Metal atoms in the precursor can be adsorbed onto the surface to be film-formed through the precursor. Casa has a high vapor pressure, is thermally stable before film formation, and does not self-decompose. It has the characteristics of rapid chemical adsorption. In addition, the precursor is introduced as a gas, so the exchange If the precursors introduced into each other have enough time to diffuse, high aspect ratios can be achieved. Even in areas with irregularities, a film can be formed with good coverage.

[0183] In addition, in the ALD method, the gas introduction order is controlled and repeated multiple times until the desired thickness is achieved. By repeating this process, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the nozzle is turned on. By increasing the pressure, the film formation speed can be increased and the impurity concentration in the film can be reduced. can be done.

[0184] In addition, the ALD method includes ALD using heat (thermal ALD method), ALD using plasma ( In thermal ALD, thermal energy is used to induce the reaction of precursors. The plasma ALD method involves reacting precursors in a radical state. do.

[0185] The ALD method can deposit extremely thin films with high precision. Surface coating is possible even on uneven surfaces. High rate and high film density.

[0186] <Plasma ALD method> Also, by forming a film by the plasma ALD method, compared with the ALD method using heat (thermal ALD method) it is possible to form a film at a lower temperature. The plasma ALD method can, for example, form a film without reducing the film formation rate even at 100 °C or lower. Also, in the plasma ALD method, N2 can be radicalized by plasma, so it is possible to form not only oxides but also nitrides.

[0187] Also, in the plasma ALD method, the oxidizing power of the oxidant can be enhanced. As a result, when forming a film by the ALD method, the precursors remaining in the film or the organic components desorbed from the precursors can be reduced, and carbon, chlorine, hydrogen, etc. in the film can be reduced, and a film with a low impurity concentration can be obtained.

[0188] Also, when performing the plasma ALD method, when generating radical species, plasma can be generated in a state separated from the substrate, such as ICP (Indu ctively Coupled Plasma), and the plasma damage to the substrate or the film on which the protective film is to be formed can be suppressed.

[0189] As described above, by using the plasma ALD method, compared with other film formation methods, the process temperature can be lowered, the surface coverage rate can be increased, and the film can be formed. This can suppress the intrusion of water and hydrogen from the outside. Therefore, the reliability of transistor characteristics can be improved.

[0190] <Explanation of the ALD apparatus> [[ID=]]Fig. 4(A) shows an example of a film forming apparatus using the ALD method. The film forming apparatus using the ALD method is , a film-forming chamber (chamber 1701), raw material supply units 1711a and 1711b, and a flow rate controller high-speed valves 1712a and 1712b, raw material inlets 1713a and 1713b, and raw material The chamber 1701 has a fuel outlet 1714 and an exhaust device 1715. The raw material inlets 1713a and 1713b are connected to the raw material supply units 1711a and 1711b via supply pipes and valves. 11b, and the raw material discharge port 1714 is connected to a discharge pipe, a valve, and a pressure regulator. It is connected to the exhaust device 1715 via

[0191] Inside the chamber, there is a substrate holder 1716 equipped with a heater, and the substrate to be formed is placed on the substrate holder. A substrate 1700 is placed on which the film is to be deposited.

[0192] In the raw material supply units 1711a and 1711b, solid raw materials and liquid raw materials are supplied by vaporizers and heating means. Alternatively, the raw material supply units 1711a and 1711b may supply a gas The raw material gas may be supplied.

[0193] Although an example in which two raw material supply units 1711a and 1711b are provided is shown, this is not particularly limited. In addition, the high-speed valves 1712a and 1712b can be precisely controlled by the time. It is possible to control the supply of either the raw material gas or the inert gas. The high-speed valves 1712a and 1712b are flow rate controllers for the source gases and also for the inert gas. It can also be called a flow rate controller.

[0194] In the film forming apparatus shown in FIG. 4(A), a substrate 1700 is carried onto a substrate holder 1716. After the bar 1701 is sealed, the substrate 1700 is heated by the heater of the substrate holder 1716. The temperature is set to a desired temperature (for example, 100°C or higher or 150°C or higher), and the supply and exhaust of the raw material gas are controlled. The exhaust by the exhaust device 1715, the supply of the inert gas, and the exhaust by the exhaust device 1715 are repeated. By repeating this process, a thin film is formed on the surface of the substrate.

[0195] In the film forming apparatus shown in FIG. 4(A), raw materials (volatile materials) are prepared in raw material supply units 1711a and 1711b. By appropriately selecting the appropriate activating agent (e.g., volatile organometallic compounds), hafnium, aluminum, tungsten Oxides (including composite oxides) containing one or more elements selected from the group consisting of aluminum, zirconium, etc. Specifically, an insulating layer containing hafnium oxide can be formed. an insulating layer comprising aluminum oxide; an insulating layer comprising hafnium silicate; an insulating layer containing palladium or an insulating layer containing aluminum silicate; In addition, the raw materials (volatilized materials) prepared in the raw material supply units 1711a and 1711b can be By appropriately selecting the appropriate metal layer (e.g., ionic organic metal compound), a metal layer such as a tungsten layer or a titanium layer can be formed. It is also possible to deposit thin films such as metal layers and nitride layers such as titanium nitride layers.

[0196] For example, when a hafnium oxide layer is formed using a film forming apparatus that uses the ALD method, a solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is vaporized hafnium amide (such as TDMAH) and acid In this case, two kinds of gases are used: The first source gas supplied from the source supply unit 1711b is TDMAH, and the second source gas supplied from the source supply unit 1711c is TDMAH. The raw material gas becomes ozone. The chemical formula of tetrakisdimethylamidohafnium is Hf [N(CH3)2]4. Other materials include tetrakis(ethylmethylamine). Nitrogen has the function of eliminating charge trapping levels. Therefore, when the source gas contains nitrogen, a hafnium oxide film with a low charge trap level density can be formed. It is possible.

[0197] For example, when forming an aluminum oxide layer using a film forming apparatus that uses the ALD method, A raw material gas containing a catalyst and a liquid containing an aluminum precursor compound (such as TMA) is vaporized, and an oxidizing agent is added. In this case, two kinds of gases are used, one of which is a gas containing HCl and the other is H2O. The first source gas is TMA, and the second source gas supplied from the source supply unit 1711b is H 2O. The chemical formula for trimethylaluminum is Al(CH3)3. Other liquid materials include tris(dimethylamido)aluminum and triisobutylaluminum. Aluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione) Examples include:

[0198] For example, when forming a silicon oxide film using a film forming device that uses the ALD method, Chlorodisilane is adsorbed onto the surface to be coated, removing the chlorine contained in the adsorbed material, and the oxidizing gas (O 2. Nitrous oxide (NO) radicals are supplied to react with the adsorbed material.

[0199] For example, when forming a tungsten film using a film forming device that uses the ALD method, WF6 The initial tungsten film was formed by sequentially introducing BH gas and BH gas. The tungsten film is formed by repeatedly introducing B2H6 gas and H2 gas in sequence. SiH4 gas may be used instead of gas.

[0200] For example, an oxide semiconductor film, such as In-Ga-Zn- When forming an O film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced repeatedly to form a Ga After that, Zn(CH3)2 gas and O3 gas were introduced repeatedly to form an O layer. The order of these layers is not limited to this example. Mixed compound layers such as In-Ga-O, In-Zn-O, and Ga-Zn-O layers are formed. It is also possible to use H2 obtained by bubbling an inert gas such as Ar instead of O3 gas. Although O gas may be used, it is preferable to use O gas that does not contain H. Instead of In(C2H5)3 gas, Ga(CH3) Instead of the Zn(CH3)2 gas, Ga(C2H5)3 gas may be used. may also be used.

[0201] <<Multi-chamber manufacturing equipment>> Also, a multi-chamber manufacturing apparatus having at least one film forming apparatus shown in FIG. An example is shown in Figure 4(B).

[0202] The manufacturing equipment shown in Figure 4(B) can continuously form laminated films without exposing them to the atmosphere. We aim to prevent impurities from being mixed in and improve throughput.

[0203] The manufacturing apparatus shown in FIG. 4(B) includes a load chamber 1702, a transfer chamber 1720, a pre-treatment chamber 1703, The system has at least a chamber 1701, which is a film-forming chamber, and an unloading chamber 1706. The chambers of the manufacturing equipment (including the load chamber, processing chamber, transfer chamber, deposition chamber, unload chamber, etc.) In order to prevent moisture from adhering, the container is filled with an inert gas (such as nitrogen gas) with a controlled dew point. It is preferable to keep the pressure reduced, and it is desirable to maintain the pressure reduced.

[0204] In addition, chambers 1704 and 1705 are the same ALD method as chamber 1701. Alternatively, a film forming apparatus using a plasma CVD method may be used. Alternatively, a film forming apparatus using a sputtering method may be used, or a film forming apparatus using an MOCVD method may be used. It may also be a device.

[0205] For example, the chamber 1704 is a film forming device that uses a plasma CVD method. The following is an example of a film deposition system using the MOCVD method as the 1705. show.

[0206] In FIG. 4B, the top view of the transfer chamber 1720 shows an example of a hexagonal shape, but it may be changed depending on the number of layers of the laminated film. If necessary, a manufacturing device having a polygonal shape or more and connected to more chambers may be used. In addition, although the top surface shape of the substrate is shown as a rectangle in FIG. 4(B), it is not particularly limited. Although Figure 4(B) shows an example of a single-substrate type, batch-type film formation in which films are formed on multiple substrates is also possible. It may also be a device.

[0207] <Formation of Insulating Layer 110> First, an insulating layer 110 is formed on a substrate 100. The insulating layer 110 is formed by a plasma CVD method, a thermal For example, oxidation is performed by a CVD method (MOCVD method, ALD method), a sputtering method, etc. Aluminum, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, acid Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, Metal oxide films such as hafnium oxide and tantalum oxide, silicon nitride, silicon oxide nitride Nitride insulating films such as aluminum nitride, aluminum nitride oxide, or mixtures of these The material may be a laminate of the above materials. The upper layer of the stack that is in contact with the first metal oxide film that will later become the metal oxide layer 121 is an oxide semiconductor layer. It is preferable to form it from a material containing excess oxygen that can be a source of oxygen to 122 .

[0208] In forming the insulating layer 110, the insulating layer 110 does not contain hydrogen or the hydrogen content is 1% or less. By using this material, generation of oxygen vacancies in the oxide semiconductor layer can be suppressed, and This can stabilize the operation of the transistor.

[0209] For example, the insulating layer 110 is formed by plasma CVD using silicon oxynitride having a thickness of 100 nm. A membrane can be used.

[0210] Next, a first heat treatment may be performed to remove water, hydrogen, and the like contained in the insulating layer 110. As a result, it is possible to reduce the concentration of water, hydrogen, etc. contained in the insulating layer 110, The heat treatment reduces the amount of water, hydrogen, etc. that diffuses into the first metal oxide film that will be formed later. It is possible.

[0211] <Formation of First Metal Oxide Film, Oxide Semiconductor Film to Become Oxide Semiconductor Layer 122> Next, a first metal oxide film, which will later become the metal oxide layer 121, and an oxide film, which will later become the metal oxide layer 122, are formed on the insulating layer 110. The first metal oxide film, the oxide semiconductor film, which will become the oxide semiconductor layer 122 is formed. The oxide semiconductor film that becomes the dielectric layer 122 can be formed by a sputtering method, an MOCVD method, a PLD method, or the like. It is more preferable to form the layer by sputtering. There are three types of sputtering methods: RF sputtering, DC sputtering, and AC sputtering. In the sputtering method, the facing target method can be used. (Counter electrode method, Vapor phase sputtering method, VDSP (Vapor Depositio By using the plasma sputtering method, Can reduce damage.

[0212] For example, an oxide semiconductor film to be the oxide semiconductor layer 122 is formed by a sputtering method. In this case, each chamber in the sputtering apparatus contains impurities that may become impurities for the oxide semiconductor film. In order to remove as much water as possible, an adsorption type vacuum pump such as a cryopump is used. High vacuum (5×10 -7 Pa~1×10 -4 Pa) and film formation It is preferable that the substrate to be treated can be heated to 100°C or higher, preferably 400°C or higher. The turbomolecular pump and cold trap are combined to extract carbon dioxide from the exhaust system into the chamber. It is preferable to prevent gas containing components, moisture, etc. from flowing backward. An exhaust system combining a pump and a cryopump may also be used.

[0213] In order to obtain a high-purity intrinsic oxide semiconductor film, not only is the chamber evacuated to a high vacuum, It is also desirable to use a highly purified sputtering gas. The dew point of the nitrogen gas and argon gas is -40°C or less, preferably -80°C or less, more preferably By using gas that has been highly purified to -100°C or lower, moisture and other substances are absorbed into the oxide semiconductor film. It is possible to prevent intrusion as much as possible.

[0214] The sputtering gas is a rare gas (typically argon), oxygen, or a mixture of rare gas and oxygen. In the case of a mixture of rare gas and oxygen, the ratio of the oxygen gas to the rare gas is It is preferable to increase the ratio.

[0215] Note that when an oxide semiconductor film to be the oxide semiconductor layer 122 is formed, for example, a sputtering method is used. When the heating method is used, the substrate temperature is set to 150°C or higher and 750°C or lower, preferably 150°C or higher and 450°C or lower. The oxide semiconductor film is formed at a temperature of 50° C. or lower, more preferably 200° C. or higher and 420° C. or lower. By this, a CAAC-OS film can be formed.

[0216] The first metal oxide film has a lower electron affinity than the oxide semiconductor film that will become the oxide semiconductor layer 122. The material can be selected to be small.

[0217] In addition, in the first metal oxide film, the oxide semiconductor film to be the oxide semiconductor layer 122, for example, For example, when forming a film by sputtering, a multi-chamber sputtering device is used. As a result, the first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122 are exposed to the air. In this case, the first metal oxide film and the oxide semiconductor film can be formed successively without any need for a The oxide semiconductor film that will become the layer 122 is prevented from being impurities from entering the interface therewith. As a result, the electrical characteristics of the transistor can be improved. This can stabilize the characteristics in performance, especially reliability tests.

[0218] Furthermore, when damage occurs in the insulating layer 110, the metal oxide layer 121 The oxide semiconductor layer 122, which is the main conductive path, can be kept away from the damaged area. This can stabilize the electrical characteristics of transistors, especially in reliability tests. can.

[0219] For example, the first metal oxide film is formed by sputtering using In: An insulating film with a thickness of 20 nm is used, using Ga:Zn=1:3:4 (atomic ratio). In addition, an oxide semiconductor film can be formed by sputtering. :Ga:Zn=1:1:1 (atomic ratio) was used to form an oxide semiconductor film with a thickness of 15 nm. It can be used.

[0220] After the first metal oxide film and the oxide semiconductor film to be the oxide semiconductor layer 122 are formed, By performing the heat treatment, the first metal oxide film and the oxide semiconductor layer 122 are formed. The amount of oxygen vacancy in the conductive film can be reduced.

[0221] The temperature of the second heat treatment is 250°C or higher and lower than the substrate strain point, preferably 300°C or higher and 650°C or lower. °C or less, and more preferably 350°C or more and 550°C or less.

[0222] The second heat treatment is carried out using a rare gas such as helium, neon, argon, xenon, or krypton, or or in an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, Atmosphere or dry air (dew point is -80°C or less, preferably -100°C or less, preferably - Heating may be carried out in an air atmosphere at a temperature of 120°C or less, or under reduced pressure. In addition to the dry air, it is preferable that the inert gas and oxygen do not contain hydrogen, water, etc. Typically, the dew point is -80°C or less, preferably -100°C or less. The treatment time ranges from 3 minutes to 24 hours.

[0223] In the heat treatment, instead of an electric furnace, heat conduction from a heating element such as a resistance heating element or Alternatively, a device that heats the object to be treated by thermal radiation may be used. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. For the gas, a noble gas such as argon or an inert gas such as nitrogen is used.

[0224] Note that the second heat treatment is performed after forming the metal oxide layer 121 and the oxide semiconductor layer 122, which will be described later. This may be done after etching.

[0225] For example, after heat treatment at 450°C for 1 hour in a nitrogen atmosphere, The heat treatment can be carried out at 450°C for 1 hour.

[0226] Through the above steps, the first metal oxide film and the oxide semiconductor film that will become the oxide semiconductor layer 122 are obtained. It is possible to reduce oxygen vacancies and impurities such as hydrogen and water. The first metal oxide film having a reduced concentration is formed as an oxide semiconductor film to be the oxide semiconductor layer 122. It is possible.

[0227] In addition, high-density plasma irradiation using oxygen as a material can produce the same effect as heat treatment. The irradiation time is from 1 minute to 3 hours, preferably from 3 minutes to 2 hours, and more preferably The duration shall be between 5 minutes and 1 hour.

[0228] <Formation of the first conductive film> Next, a first conductive film used as a hard mask is formed over the oxide semiconductor layer 122. The conductive film 1 is formed by sputtering, chemical vapor deposition (CVD) (metal organic chemical vapor deposition ( MOCVD, metal chemical vapor deposition, atomic layer deposition (ALD) or plasma chemistry Chemical vapor deposition (PECVD), evaporation, pulsed laser deposition (PLD), etc. It can be formed by

[0229] The material of the first conductive film is copper (Cu), tungsten (W), molybdenum (Mo), gold (A u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt ( Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S r) or alloys, or compounds with these as the main components. A single layer or a stack of conductive films is preferred.

[0230] For example, a tungsten film having a thickness of 20 to 100 nm is formed on the first conductive layer by sputtering. It can be formed as a film.

[0231] In this embodiment, the first conductive film is formed as a hard mask, but this is not limiting. Alternatively, an insulating film may be formed instead.

[0232] <Formation of Metal Oxide Layer 121 and Oxide Semiconductor Layer 122> Next, a resist mask is formed by a lithography process. The first conductive film is selectively etched to form the conductive layer 130b. After removing the resist on the mask, the oxide semiconductor film that will become the oxide semiconductor layer 122 and the first metal oxide film are The oxide semiconductor layer 122 and the metal oxide layer 121 are selectively etched to form islands. (See FIG. 5.) The etching method used is dry etching. The oxide semiconductor layer can be etched using the conductive layer 130b as a hard mask. By etching, the etching of the oxide semiconductor layer after etching is improved compared to the resist mask. It can reduce giraffeness.

[0233] <Formation of Metal Oxide Film 123a> Next, a metal oxide layer 123 is formed on the oxide semiconductor layer 122 and the insulating layer 110. The metal oxide film 123a is formed by depositing an oxide semiconductor film, a first metal oxide film, and a second metal oxide film. The metal oxide film 123a can be formed by the same method as that for forming an oxide semiconductor film. The material can be selected to have a smaller electron affinity than

[0234] In addition, the metal oxide film 123a is formed by a long-throw sputtering method. Therefore, the embedding property of the metal oxide film 123a in the grooves 174 can be improved.

[0235] For example, the metal oxide film 123a is formed by sputtering a metal oxide film of In:Ga:Zn=1 A 5-nm-thick oxide semiconductor film was formed using a target with an atomic ratio of 3:2. It is possible.

[0236] <Deposition of the first insulating film> Next, a first insulating film, which will later become the insulating layer 175, is formed on the metal oxide film 123a. This insulating film can be formed in the same manner as the insulating layer 110 .

[0237] The first insulating film is formed by plasma CVD, thermal CVD (MOCVD, ALD), or For example, aluminum oxide, magnesium oxide, silicon oxide, etc. are deposited by sputtering. , silicon oxynitride, silicon oxyfluoride, gallium oxide, germanium oxide, iodide Thorium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and oxide Metal oxide films such as tantalum, silicon nitride, silicon nitride oxide, aluminum nitride, The insulating film is formed using a nitride insulating film such as aluminum oxide or a mixture of these materials. Alternatively, the material may be a laminate of the above materials.

[0238] <Planarization of the first insulating film> Next, the first insulating film is planarized to form an insulating layer 175b (see FIG. 6). Chemical Mechanical Polishing (CMP) method is used for the chemical treatment. This can be done by dry etching, reflow, or the like. When planarizing the first insulating film, a film having a different composition from the first insulating film is introduced onto the first insulating film. This makes it possible to make the thickness of the insulating layer 175b uniform within the substrate surface after the CMP process.

[0239] <Groove formation> Next, a resist mask is formed on the planarized insulating layer 175b by a lithography process. In addition, after applying an organic film on the insulating layer, or after applying it on a resist mask, The lithography process may be performed from the organic film. The organic film can have a structure such as a fluorine-containing compound, a fluorine-containing compound, an ethyl ether, an ethyl lactate, etc. In addition to the anti-reflection effect, it also has other effects such as improving adhesion between the resist mask and the film and improving resolution. The organic film can also be used in other processes.

[0240] When forming a transistor with an extremely short channel length, electron beam exposure, immersion exposure, Fine line processing using light and EUV (Extreme Ultra-Violet) exposure A resist mask is processed using a method suitable for the above, and etching is performed using the resist mask. When a resist mask is formed by electron beam exposure, the resist If a positive resist is used as the photomask, the exposed area can be minimized. This method can improve the throughput by extending the channel length by 10 It is now possible to form transistors with thicknesses of 0 nm or less, 30 nm or less, and even 20 nm or less. Alternatively, microfabrication may be performed by exposure technology using X-rays or the like.

[0241] The resist mask is used to remove the insulating layer 175b until the metal oxide film 123a is exposed. The insulating layer 175 is then subjected to a groove processing process by dry etching. , a groove 174 is formed.

[0242] The groove 174 is preferably shaped perpendicular to the substrate surface.

[0243] The method for processing the groove 174 is not limited to the above method. Alternatively, a hard mask may be used, or a half-tone mask may be used in the lithography process. The shape of the resist mask may be controlled by using a nanoimprint method or the like. The shape of the mask may be controlled by the masking. This method can also be applied to other processes.

[0244] <Formation of second insulating film 150a> Next, a second insulating layer 175 is formed on the metal oxide film 123a and the insulating layer 175 to become the gate insulating layer 150. The second insulating film 150a is formed. For example, aluminum oxide (A lO x ), magnesium oxide (MgO x ), silicon oxide (SiO x ), silicon oxynitride SiO x N y ), silicon oxynitride (SiN x O y ), silicon nitride (SiN x ), Gallium oxide (GaO x ), germanium oxide (GeO x ), yttrium oxide (YO x ), zirconium oxide (ZrO x ), lanthanum oxide (LaO x ), neodymium oxide (NdO x ), hafnium oxide (HfO x ) and tantalum oxide (TaO x ) etc. can be used. The second insulating film 150a may be a laminate of the above materials. 150a is a method for forming a thin film by a sputtering method, a CVD method (plasma CVD method, MOCVD method, ALD method) The second insulating film 150a can be formed by using a method such as a silicon dioxide film (SiO 2 ) or an MBE method. The insulating layer 110 can be formed by a method similar to that for the insulating layer 110, as appropriate.

[0245] For example, the second insulating film 150a is formed by depositing silicon oxynitride to a thickness of 10 n by plasma CVD. m can be formed.

[0246] <Formation of Conductive Film 160a> Next, a conductive film 160a that will become the gate electrode layer 160 is formed on the second insulating film 150a. (See FIG. 7.) The conductive film 160a is made of, for example, aluminum (Al), titanium (Ti ), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag) , tantalum (Ta), tungsten (W), or alloy materials with these as the main components. The conductive film 160a can be formed by a sputtering method or a CVD method (plasma CVD method, It can be formed by MOCVD, ALD, MBE, vapor deposition, plating, etc. Furthermore, a conductive film containing nitrogen may be used as the conductive film 160a. A laminate of a film and a nitrogen-containing conductive film may also be used.

[0247] For example, titanium nitride is formed to a thickness of 10 nm by the ALD method as the conductive film 160a. A laminated structure in which 150 nm of tungsten is formed by metal CVD can be used. .

[0248] <Flattening process> Next, a planarization process is performed using a CMP method, dry etching method, etc. The planarization process may be terminated when the second insulating film 150a is exposed. However, the process may be terminated when the insulating layer 175 is exposed. A gate insulating layer 150 may be formed (see FIG. 8).

[0249] <Etch-back treatment of insulating layer 175> Next, the insulating layer 175 is etched back by dry etching to form a metal oxide film Furthermore, the metal oxide layer 123a is exposed in the portion not overlapping with the gate electrode layer 160. The film 123a is etched to form the metal oxide layer 123 (see FIG. 9).

[0250] The method for forming the structure shown in FIG. 9 is not limited to the above.

[0251] For example, as shown in FIG. 10, the metal oxide layer 123b and the gate insulating layer 150b are formed in the groove portion 174. Alternatively, a structure having a gate electrode layer 160 may be used. Alternatively, as shown in FIG. The insulating film 150a may be formed on the metal oxide film 123a.

[0252] <Ion addition treatment> Next, ions 167 are added to the oxide semiconductor layer 122 (see FIG. 12). The materials to be added are hydrogen (H), helium (He), neon (Ne), argon (Ar), and Lipton (Kr), Xenon (Xe), Boron (B), Phosphorus (P), Tungsten (W) The method of adding the metal is ion doping. These include ion implantation, plasma immersion ion implantation, and high density plasma treatment. In miniaturization, ion implantation is used to add impurities other than the specified ions. In addition, ion doping and plasma immersion ion doping are also preferred. The ion implantation method is advantageous when treating a large area.

[0253] In the ion doping process, the ion acceleration voltage is adjusted according to the ion species and implantation depth. For example, it is desirable to set the voltage between 1kV and 100kV, or between 3kV and 60kV. The ion dose is 1×10 12 ions / cm 2 More than 1×10 1 7 ions / cm 2 Less than 1 × 10 14 ions / cm 2 5x10 or more 16 i ons / cm 2 It is desirable to do the following:

[0254] By the ion addition treatment, oxygen vacancies are formed in the oxide semiconductor layer 122, and the low-resistance region 125 (see FIG. 13). Ions are also diffused into the region overlapping with the electrode layer, and the low resistance region 125 overlaps with the gate electrode layer. It may also be formed in minutes.

[0255] In addition, by performing a heat treatment after the ion addition treatment, the film damage that occurred during the ion addition treatment can be reduced. Can repair damage.

[0256] Next, a third insulating film is formed, which will later become the insulating layer 180. The third insulating film is formed by After the third insulating film is formed, it is desirable to flatten it. I wish.

[0257] Next, the third insulating film is etched by dry etching to form an opening.

[0258] Next, a third conductive film that will become the conductive layer 190 is formed in the opening, and then a planarization process is performed. Layer 190 is formed.

[0259] Next, a fourth conductive film that will become the conductive layer 195 is formed on the conductive layer 190. By using a photolithography method, a nanoimprinting method, etc., a conductive layer Form 195.

[0260] The transistor 10 can be formed by using the above manufacturing method. By using this method, it is possible to achieve channel lengths of 100 nm or less, 30 nm or less, and even 20 nm or less. This makes it possible to stably manufacture extremely small transistors such as those shown below.

[0261] The transistor 10 has a region where the gate insulating layer 150 contacts the side surface of the gate electrode layer. This may be done (see FIG. 14).

[0262] <Modification 1 of Transistor 10: Transistor 11> Regarding the transistor 11, which has a different shape from the transistor 10 shown in FIG. 1, we will use FIG. 15 to explain.

[0263] 15(A), 15(B), and 15(C) are a top view and a cross-sectional view of the transistor 11. FIG. 15(A) is a top view of the transistor 11, and FIG. 15(B) is a top view of the transistor 11. 15(B) is a cross-sectional view taken along the dashed line B1-B2, and FIG. 15(C) is a cross-sectional view taken along the dashed line B3-B4.

[0264] The transistor 11 has an insulating layer 170 and an insulating layer 172, which is different from the transistor 10. is different from.

[0265] Insulating layer 170 The insulating layer 170 contains oxygen, nitrogen, fluorine, aluminum (Al), magnesium (Mg), , silicon (Si), gallium (Ga), germanium (Ge), yttrium (Y), Zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium (Hf), The material may include tantalum (Ta), titanium (Ti), etc. Aluminum oxide (AlO x ), magnesium oxide (MgO x ), silicon oxide (SiO x ), silicon oxynitride ( SiO x N y ), silicon oxynitride (SiN x O y ), silicon nitride (SiN x ), oxidation Gallium (GaO x ), germanium oxide (GeO x ), yttrium oxide (YO x ), Zirconium oxide (ZrO x ), lanthanum oxide (LaO x ), neodymium oxide (NdO x ) , hafnium oxide (HfO x ) and tantalum oxide (TaO x ) can.

[0266] The insulating layer 170 is made of aluminum oxide (AlO x ) film. The aluminum film is a barrier that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the film. Therefore, the aluminum oxide film can be used in the manufacturing process of a transistor. During and after the manufacturing process, hydrogen, moisture, etc., which can cause fluctuations in the electrical characteristics of transistors, Preventing impurities from being mixed into the metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 , a metal oxide layer 121 of oxygen, which is the main component material, an oxide semiconductor layer 122, and a metal oxide layer 1 23 and the insulating layer 110. It is suitable for use as a

[0267] The insulating layer 170 is preferably a film having an oxygen supplying ability. During film formation, a mixed layer is formed at the interface with other oxide layers, and the mixed layer or other oxide layers are not oxidized. The oxygen is then diffused into the oxide semiconductor layer by subsequent heat treatment, and the oxide semiconductor layer is then Oxygen vacancies in the conductor layer can be compensated for, and transistor characteristics (e.g., The threshold voltage, reliability, etc. can be improved.

[0268] The insulating layer 170 may be a single layer or a multilayer. Alternatively, the insulating layer may have another insulating layer underneath, such as magnesium oxide, silicon oxide, or oxynitride. Silicon oxide, silicon nitride, silicon nitride, gallium oxide, germanium oxide, oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulating film containing one or more kinds of tantalum oxide can be used. The insulating layer has a stoichiometric composition. The oxygen released from the insulating layer is preferably more than the gate insulating layer. The oxide semiconductor layer 122 is formed in a channel formation region through the insulating layer 110 or the insulating layer 150. Since oxygen can be diffused, oxygen is filled in the oxygen vacancies formed in the channel formation region. Therefore, stable electrical characteristics of the transistor can be obtained.

[0269] Insulating layer 172 The insulating layer 172 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), Tritium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), Huff The metals may include niobium (Hf), tantalum (Ta), titanium (Ti), etc. , aluminum oxide (AlO x ), magnesium oxide (MgO x ), silicon oxide (Si O x ), silicon oxynitride (SiO x N y ), silicon oxynitride (SiN x O y ), nitriding Silicon (SiN x ), gallium oxide (GaO x ), germanium oxide (GeO x ),acid Yttrium chloride (YO x ), zirconium oxide (ZrO x ), lanthanum oxide (LaO x ) , neodymium oxide (NdO x ), hafnium oxide (HfO x ) and tantalum oxide (TaO x The insulating layer 172 can be formed of a laminate of the above materials. may be.

[0270] The insulating layer 172 preferably includes an aluminum oxide film. It has a blocking effect that prevents impurities such as hydrogen and moisture, as well as oxygen, from passing through the membrane. Therefore, the aluminum oxide film can be used during the manufacturing process of the transistor. After manufacturing, metal impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors, Prevention of contamination of the oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123, and main component materials The metal oxide layer 121, the oxide semiconductor layer 122, and the metal oxide layer 123 emit oxygen, which is the and is suitable for use as a protective film having the effect of preventing oxygen from being released from the insulating layer 110. is doing.

[0271] The insulating layer 172 can also function as a protective film. This makes it possible to protect the gate insulating layer 150 from plasma damage. This makes it possible to prevent electron traps from being formed near the channel.

[0272] <Method for manufacturing transistor 11> A method for manufacturing the transistor 11 will be described with reference to FIGS. For the same parts as in the manufacturing method of 10, the explanation therefor is incorporated by reference.

[0273] <Formation of insulating layer 172> An insulating layer 172 is formed on the insulating layer 110, the oxide semiconductor layer 122, and the gate electrode layer 160. Note that the insulating layer 172 is formed to prevent the oxide semiconductor layer 122 and the gate insulating layer 172 from being damaged (see FIG. 16). Since the gate insulating layer 150 may be damaged by plasma, MOCVD and ALD methods are not suitable. It is preferable to use a film formed by the method described above.

[0274] The thickness of the insulating layer 172 is 1 nm or more and 30 nm or less, preferably 3 nm or more and 10 nm or less. It is preferable that:

[0275] In addition, even if ion addition treatment is performed on the oxide semiconductor layer 122 after the insulating layer 172 is formed, This allows the formation of a low resistance region while reducing the oxide formed during the ion addition process. Damage to the semiconductor layer 122 can be reduced (see FIG. 17).

[0276] After the insulating layer 172 is formed, it is subjected to lithography, nanoimprinting, dry etching, or the like. The insulating film may be provided by processing using a coating method or the like, or may be simply formed as a film.

[0277] <Formation of insulating layer 170> Next, the insulating layer 170 is formed on the insulating layer 172. The insulating layer 170 may be a single layer or The insulating layer 170 may be formed using the same material and method as the insulating layer 110. It is possible.

[0278] The insulating layer 170 is an aluminum oxide film formed by sputtering. When forming an aluminum oxide film by sputtering, it is preferable to use It is preferable that the gas contains oxygen gas. In addition, the oxygen gas is contained in an amount of 1% by volume or more and 100% by volume or more. % by volume or less, preferably 4% by volume or more and 100% by volume or less, and more preferably 10% by volume or more It is desirable that the insulating layer contains 100% by volume or less of oxygen. It is possible to supply excess oxygen to the insulating layer between the insulating layer and the adjacent insulating layer. Oxygen can be added to the layer.

[0279] For example, the insulating layer 170 is formed by sputtering using aluminum oxide as a target. The gas used is oxygen gas, which contains 50% by volume, and the film is formed to a thickness of less than 20 nm. It can be up to 40 nm.

[0280] Next, it is preferable to perform a heat treatment. The heat treatment is typically performed at a temperature of 150° C. or higher. Less than the strain point, preferably 250°C or more and 500°C or less, more preferably 300°C or more and 450°C or less By this heat treatment, the insulating layer (for example, the insulating layer 110) can be doped with The oxygen 173 diffuses and moves to the oxide semiconductor layer 122. This allows oxygen to be supplied to compensate for the oxygen vacancies present in the silicon dioxide (see FIG. 18).

[0281] In this embodiment mode, heat treatment can be performed in an oxygen atmosphere at 400° C. for 1 hour.

[0282] The heat treatment may be carried out in other steps as needed. This makes it possible to repair defects present in the film and reduce the interface state density. Cut.

[0283] <Oxygen addition> Note that the treatment for adding oxygen is not limited to the treatment via the insulating layer 170. The doping treatment may be performed on the insulating layer 110, the insulating layer 175, or the first metal oxide film, The addition may be performed on the metal oxide film 123a or on other insulating layers. The oxygen may be any one of oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. The above methods are used. The oxygen doping method and the ion implantation method are also available. , plasma immersion ion implantation, etc.

[0284] When ion implantation is used as a method for adding oxygen, oxygen atomic ions can be used. Alternatively, oxygen molecular ions may be used. When oxygen molecular ions are used, the amount of oxygen added to the film increases. The oxygen molecular ions are released from the surface of the film to which the oxygen is added. The oxygen molecules are separated into oxygen atoms and added as oxygen atom ions. Since energy is used, when oxygen molecular ions are added to the membrane to which the oxygen is added, The energy per oxygen atom ion in This is lower than when oxygen is added to the film, reducing damage to the film to which it is added. can.

[0285] In addition, by using oxygen molecular ions, oxygen atoms are implanted into the film to which the oxygen is added. Since the energy of each ion is reduced, the oxygen atomic ions are implanted at a shallower position. Therefore, in the subsequent heat treatment, oxygen atoms are easily moved, and the metal oxide layer 121, More oxygen can be supplied to the oxide semiconductor layer 122 and the metal oxide layer 123. .

[0286] In addition, when oxygen molecular ions are implanted, the oxygen is more easily absorbed than when oxygen atomic ions are implanted. The energy per atomic ion is low, so it is possible to implant oxygen molecular ions. This allows for a higher acceleration voltage and therefore a higher throughput. In addition, by using oxygen molecular ions for implantation, compared to when oxygen atomic ions are used, It is possible to halve the dose, which results in increased throughput. .

[0287] When oxygen is added to the film to which oxygen is added, oxygen atomic ions are added to the film to which oxygen is added. The film to which the oxygen is added is prepared under the conditions under which the peak of the oxygen concentration profile is located. As a result, compared to the case where oxygen atomic ions are implanted, The acceleration voltage during implantation can be lowered, and damage to the film to which the oxygen is added can be reduced. That is, the amount of defects in the film to which oxygen is added can be reduced, and the Furthermore, the insulating layer 110 and the gold layer 111 can be formed by the same method. The amount of oxygen atoms added at the interface of the metal oxide layer 121 is 1×10 21 atoms / cm 3 Not yet Full, or 1 x 10 20 atoms / cm 3Less than or equal to 1 x 10 19 atoms / cm 3 By adding oxygen to the film to be doped with oxygen so that the oxygen content is less than The amount of oxygen added can be reduced, and as a result, damage to the film to which the oxygen is added can be reduced. Therefore, the change in the electrical characteristics of the transistor can be suppressed.

[0288] Also, a plasma method is used in which a film to which oxygen is added is exposed to plasma generated in an atmosphere containing oxygen. By plasma immersion ion implantation (PIA), oxygen is added to the film to which the oxygen is added. The oxygen-containing atmosphere may be oxygen, ozone, nitrous oxide, nitrogen dioxide, or the like. The atmosphere contains a chemical gas. By exposing the film to which oxygen is to be added to the plasma, oxygen is added to the film to which oxygen is to be added. It is possible to increase the amount of added gas, which is preferable. An example of an apparatus for performing such plasma treatment is shown below. As an example, there is an ashing device.

[0289] For example, the acceleration voltage is 60 kV and the dose is 2 × 10 16 / cm 2 of oxygen molecular ions The insulating layer 110 can be doped by ion implantation.

[0290] The above process can be applied to transistor 10 as well as other transistors.

[0291] As a result, the density of localized states in the oxide semiconductor film is reduced, and a transistor having excellent electrical characteristics is obtained. It is also possible to produce a transistor that can withstand changes in electrical characteristics due to aging or stress testing. Therefore, highly reliable transistors with fewer defects can be manufactured.

[0292] <Modification 2 of Transistor 10: Transistor 12> Regarding the transistor 12, which has a different shape from the transistor 10 shown in FIG. 1, we will use FIG. 19 to explain.

[0293] 19(A), 19(B), and 19(C) are a top view and a cross-sectional view of the transistor 12. 19(A) is a top view of the transistor 12, and FIG. 19(B) is a top view of the transistor 12. 19(C) is a cross-sectional view taken along the dashed line C1-C2, and FIG. 19(C) is a cross-sectional view taken along the dashed line C3-C4.

[0294] The transistor 12 has a metal oxide layer 123, an oxide semiconductor layer 122, and a metal oxide layer 121. and the conductive layer 165. The transistor 12 is different from the transistor 10 in that the metal oxide film 123a is not etched. It can be used as the metal oxide layer 123 .

[0295] Conductive layer 165 The conductive layer 165 may be made of, for example, aluminum (Al), titanium (Ti), chromium (Cr), Cobalt (Co), Nickel (Ni), Copper (Cu), Yttrium (Y), Zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (Ta), The conductive layer 1 may be made of a material such as tungsten (W) or silicon. 65 can be a laminate. When it is a laminate, it is possible to use a nitride such as a nitride of the above materials. It may be used in combination with materials containing

[0296] The conductive layer 165 can have a function similar to that of the gate electrode layer 160. The same potential as that of the gate electrode layer 160 may be applied to the gate electrode layer 162, or a different potential may be applied to the gate electrode layer 162. It may also be configured as follows.

[0297] In the transistor 12 provided with the conductive layer 165, the insulating layer 110 is a gate insulating layer. 150 may have the same structure and function.

[0298] The above structure can suppress damage to the oxide semiconductor layer during ion addition treatment. (See FIGS. 20 and 21.) In addition, the side edges of the oxide semiconductor layer 122 can be protected. As a result, the electrical characteristics of the transistor can be stabilized.

[0299] <Modification 3 of Transistor 10: Transistor 13> Regarding the transistor 13, which has a different shape from the transistor 10 shown in FIG. 1, we will use FIG. 22 to explain.

[0300] 22(A), 22(B), and 22(C) are a top view and a cross-sectional view of the transistor 13. 22(A) is a top view of the transistor 13, and FIG. 22(B) is a top view of the transistor 13. 22(B) is a cross-sectional view taken along the dashed line D1-D2 of FIG. 22(B), and FIG. 22(C) is a cross-sectional view taken along the dashed line D3-D4 of FIG.

[0301] The transistor 13 is similar to the transistor 12 in that the metal oxide layer 123 is formed on the oxide semiconductor layer 1 22, a region in contact with the side end portions of the metal oxide layer 121 in the channel length direction and the channel width direction; In addition to the above, the gate insulating layer 151 and the gate insulating layer 152 are provided. It is different from Transistor 10.

[0302] <Gate insulating layer 151, gate insulating layer 152> The gate insulating layer 151 and the gate insulating layer 152 have the same material as the gate insulating layer 150. It is possible.

[0303] The gate insulating layer 151 and the gate insulating layer 152 are preferably made of different materials. I wish.

[0304] <Method for manufacturing transistor 13> A method for manufacturing the transistor 13 will be described with reference to FIGS. For the same parts as in the manufacturing method of 10, the explanation therefor is incorporated by reference.

[0305] <Formation of Gate Insulating Layer 151> After the metal oxide layer 123 is formed, the gate insulating layer 151 is formed. Sputtering method, CVD method (plasma CVD method, MOCVD method, ALD method, etc.), MBE The method can be used to form the film.

[0306] For example, aluminum oxide is formed to a thickness of 5 nm by the ALD method as the gate insulating layer 151. This can be done.

[0307] <Formation of insulating film 152a> Next, after the groove portion 174 is formed, the insulating film 152a and the conductive film 152b are formed on the gate insulating layer 151 and the insulating layer 175. A film 160a is formed (see FIG. 23).

[0308] The insulating film 152a is formed using the same material and method as the second insulating film 150a of the transistor 10. For example, the insulating film 152a can be formed by an oxide film formed by a plasma CVD method. The recon can be formed to a thickness of 5 nm.

[0309] Next, the insulating film 152a and the conductive film 160a are planarized to form a gate electrode. The pole layer 160 and the insulating layer 152b are formed (see FIG. 24).

[0310] Next, the insulating layer 175 is etched until the gate insulating layer 151 is exposed. 152b is etched except for the portion overlapping with the gate electrode layer 160. A gate insulating layer 152 may be formed.

[0311] Next, an addition process of ions 167 is performed (see FIG. 25). The ion addition process is performed by adding ions 167 to the gate insulating layer 151, the oxide semiconductor layer 122 is subjected to the metal oxide layer 123, and a low resistance region 125 (see FIG. 26).

[0312] By using the above method, for example, the metal oxide layer 123 in the manufacture of a fine transistor can be formed. It is possible to reduce film loss and damage that occurs during processing. The shape of even minute transistors can be stabilized. The electrical characteristics and reliability of the device can be improved.

[0313] <Modification 4 of Transistor 10: Transistor 14> Regarding the transistor 14, which has a different shape from the transistor 10 shown in FIG. 1, we will use FIG. 27 to explain.

[0314] 27(A), 27(B), and 27(C) are a top view and a cross-sectional view of the transistor 14. 27(A) is a top view of the transistor 14, and FIG. 27(B) is a top view of the transistor 14. 27(B) is a cross-sectional view taken along the dashed line E1-E2, and FIG. 27(C) is a cross-sectional view taken along the dashed line E3-E4.

[0315] The transistor 14 has the same shape as the transistor 12, and the metal oxide layer 123 is The gate insulating layer 150 has a region in contact with the side surface of the gate electrode layer 160, and the gate insulating layer The transistor 10 is provided with an insulating layer 176 having a region in contact with the side of the transistor 150. is different from.

[0316] The angle (gradient) between the bottom surface of the substrate and the tangent of the side surface of the gate electrode layer is 30 degrees or more and 90 degrees or less. It is desirable that the angle be less than 60 degrees and preferably between 60 degrees and 85 degrees.

[0317] By adopting the above structure, it becomes possible to control the size of the low resistance region 125. This can improve the on-state current and stabilize the transistor characteristics. Cut.

[0318] Insulating layer 176 The insulating layer 176 can be made of the same material as the insulating layer 175 .

[0319] <Method for manufacturing transistor 14> A method for manufacturing the transistor 14 will be described with reference to FIGS. The same explanation as in the method for producing the star is used for the same parts.

[0320] The second insulating film 150a and the conductive film 160 are formed in the groove 174 provided on the metal oxide film 123a. Form a (see Figure 28).

[0321] 28 shows the same manufacturing process as in FIG. 7, but in providing the groove 174, the bottom surface of the substrate and The angle (gradient) of the tangent of the side surface of the insulating layer 175 is 30 degrees or more and less than 90 degrees, preferably 6 It is desirable to set the angle between 0 and 85 degrees.

[0322] The above gradient can be obtained in the same manner on the conductive film 160a facing the insulating layer 175. can be done.

[0323] Next, the second insulating film 150a and the conductive film 160a are subjected to a planarization process, A gate electrode layer 160 and a gate insulating layer 150 are formed (see FIG. 29).

[0324] Next, the gate electrode layer 160 is used as a mask to dry the insulating layer 175 and the gate insulating layer 150. The metal oxide film 123a is etched by etching until it is exposed. The metal oxide layer 123 and the insulating layer 176 are formed (see FIG. 30). By using the above process, the sidewalls can be formed in a self-aligned manner. This allows the process to be simplified.

[0325] Next, a low resistance region is formed by adding ions 167 (see FIG. 31). (See Figure 32).

[0326] By providing the insulating layer 176, ions are prevented from flowing laterally when a heat treatment is performed, for example. The size of the low-resistance region can be controlled even if the ion-doped region contains the ion. Therefore, it is possible to achieve a channel length of 100 nm or less, 60 nm or less, 30 nm or less, Even at nanometers or even 20 nm, transistors can operate stably.

[0327] Note that the transistor 14 may have a structure in which an insulating layer 170 is provided (see FIG. 33). Alternatively, the metal oxide layer 123 may be processed (see FIG. 34). The second insulating film 150a, which will become the insulating layer 150, may be provided before the groove is formed (see FIG. 35).

[0328] Furthermore, when the angle (gradient) between the bottom surface of the substrate and the tangent line of the side surface of the gate electrode layer 160 is large, There may be areas that do not have the insulating layer 176 (see FIG. 36).

[0329] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0330] (Embodiment 2) <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0331] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned oxide semiconductor (CAAC-OS) crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l amorphous oxide semiconductors and amorphous oxide semiconductors. do.

[0332] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0333] Amorphous structures are generally isotropic and have no heterogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and there is short-range order but no long-range order. It is said that...

[0334] That is, the stable oxide semiconductor is completely amorphous. ) and cannot be called an oxide semiconductor. On the other hand, a-li oxide semiconductors cannot be called completely amorphous oxide semiconductors. The ke OS is not isotropic but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. .

[0335] <caac-os> First, let me explain about CAAC-OS.

[0336] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0337] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the analysis of InGaZnO4, which is classified into the space group R-3m, Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in FIG. 37(A), a peak appears at a diffraction angle (2θ) of approximately 31°. The crystal structure is attributed to the (009) plane of the InGaZnO4 crystal. The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the surface, or in a direction approximately perpendicular to the surface. In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the nucleus are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not exhibit such a peak.

[0338] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction parallel to the surface to be formed. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I The lattice constant is fixed at 2θ around 56°. The analysis (φ scan) is performed by rotating the sample around the normal vector of the sample surface (φ axis). Even if the peak is increased, no clear peak appears, as shown in Figure 37(B). When φ is scanned with 2θ fixed at around 56° for nO4, the results are as shown in Figure 37(C). As shown in Fig. 1, six peaks are observed that are attributed to the crystal plane equivalent to the (110) plane. From the structural analysis using RD, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0339] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the surface on which the CAAC-OS was formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (control pattern) as shown in Figure 37(D) is generated. This diffraction pattern may contain In. This includes spots due to the (009) plane of the GaZnO4 crystal. Even in such cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed. On the other hand, for the same sample, the direction of the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly is shown in Figure 37(E). As shown in Figure 37(E), a ring-shaped diffraction pattern is observed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed the presence of pellets in CAAC-OS. It can be seen that the a-axis and b-axis of the dots do not have any orientation. The ring is due to the (010) and (100) planes of the InGaZnO4 crystal. It is thought that the second ring in Figure 37(E) is due to the (110) plane, etc. It is possible.

[0340] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image) reveals multiple pellets. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. It may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0341] Figure 38(A) shows a high-resolution T image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image shown here is a spherical aberration correction (SAC) image. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that

[0342] From Figure 38(A), it is possible to confirm the pellet, which is the region where metal atoms are arranged in layers. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). Also, CAAC-OS can be used with CANC (C-Axis Aligned Nano The pellets can also be called oxide semiconductors with CAAC -OS surface or upper surface unevenness is reflected, and CAAC-OS surface or upper surface unevenness is reflected. is parallel to the surface.

[0343] 38(B) and 38(C) show the CAAC images observed from a direction approximately perpendicular to the sample surface. Figures 38(D) and 38(E) show Cs-corrected high-resolution TEM images of the -OS surface. These are the images obtained by image processing of Figure 38(B) and Figure 38(C), respectively. First, the fast Fourier transform (FFT) of FIG. Then, the FFT image is obtained by Fourier Transform (FFT). In the FFT image, the origin is used as the reference point, and the -1 to 5.0 nm -1 Remaining range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT). Inverse Fast Fourier Transform (FFT) processing The image thus obtained is called an FFT filtered image. The filtered image is an image in which the periodic components are extracted from a Cs-corrected high-resolution TEM image. The sequence is shown.

[0344] In Figure 38(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the broken line is the connection between the pellets. The broken line indicates a hexagonal shape, which indicates that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0345] In FIG. 38(E), a dotted line separates an area with a uniform lattice arrangement from an area with a different uniform lattice arrangement. The lattice orientation is indicated by a dotted line, and the direction of the lattice arrangement is indicated by a dashed line. If you connect the grid points around the dotted line, you will get a distorted hexagon. In other words, the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not close-packed in the ab-plane direction. The substitution of metal elements causes changes in the bond distance between atoms, which can lead to distortion. This is thought to be because it can be tolerated.

[0346] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor with an anchored crystal. do.

[0347] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects ( It can also be said to be an oxide semiconductor with few oxygen vacancies.

[0348] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0349] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0350] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8 × 10 11 pieces / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1 × 10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be a high-purity intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0351] <nc-os> Next, we will explain nc-OS.

[0352] We will explain the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of nc-OS do not have any orientation.

[0353] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region shown in FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nano) when an electron beam with a probe diameter of 1 nm is incident on the same sample. The electron diffraction pattern (B) is shown in Figure 39(B). Therefore, nc-OS has a probe diameter of 50 nm. Although the order is not confirmed by irradiating an electron beam, the order is confirmed by irradiating an electron beam with a probe diameter of 1 nm. By projecting the images, order is confirmed.

[0354] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in Figure 39(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals are oriented in various directions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0355] Figure 39(D) shows the Cs-corrected high-resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. There are two areas where crystals can be seen, as shown in Fig. 1, and areas where no clear crystals can be seen. The crystal part contained in the nc-OS has a size of 1 nm to 10 nm. In particular, the size is often between 1 nm and 3 nm. An oxide semiconductor having a size of more than 0 nm and not more than 100 nm is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, the crystalline part of nc-OS may be referred to as pellets below.

[0356] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. Therefore, no regularity in the crystal orientation is observed between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0357] Since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0358] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0359] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0360] Figure 40 shows a high-resolution cross-sectional TEM image of the a-like OS. This is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. ) is 4.3 × 10 8 e - / nm 2 electrons (e - ) High a-like OS after irradiation 40(A) and 40(B) show that the a-like OS It can be seen that bright striped regions extending in the vertical direction are observed from the start of electron irradiation. It can be seen that the bright areas change shape after electron irradiation. It is estimated to be in the degree range.

[0361] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0362] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0363] First, high-resolution cross-sectional TEM images of each sample are acquired. Each of these has a crystalline portion.

[0364] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that it has a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is estimated to be 0.29 nm from crystal structure analysis. Below, the area where the lattice spacing is between 0.28 nm and 0.30 nm is InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0365] Figure 41 shows an example of investigating the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. The crystal part of the OS grows in size according to the cumulative amount of electron irradiation used to obtain the TEM image. From Figure 41, it can be seen that in the early stages of TEM observation, the size of the particles was about 1.2 nm. The crystal part (also called the initial nucleus) that was - ) cumulative exposure is 4.2 × 10 8 e - / nm 2 On the other hand, in the case of nc, the size of the crystals grows to about 1.9 nm. The cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of The size of the crystalline parts of nc-OS and CAAC-OS was It can be seen that the thicknesses are approximately 1.3 nm and 1.8 nm, respectively. A Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The acceleration voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0366] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. That is, compared with nc-OS and CAAC-OS, It is clear that this is an unstable structure.

[0367] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78% of that of the oxide semiconductor.

[0368] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of the a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . Also , for example, in an oxide semiconductor satisfying In:Ga:Zn = 1:1:1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0369] In addition, when there is no single crystal of the same composition, the density corresponding to the single crystal in the desired composition can be estimated by combining single crystals with different compositions at an arbitrary ratio. The density corresponding to the single crystal of the desired composition may be estimated using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible. As described above, the oxide semiconductor has various structures and each has various characteristics. In addition, the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, CAAC-OS.

[0370] As described above, the oxide semiconductor has various structures and each has various characteristics. In addition, the oxide semiconductor may be, for example, a laminated film having two or more of an amorphous oxide semiconductor, a-like OS, nc-OS, CAAC-OS.

[0371] <Configuration of CAC> Hereinafter, the configuration of the CAC (Cloud Aligned Complementary)-OS that can be used in one aspect of the present invention will be described.

[0372] The CAC is, for example, a configuration of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following, in the oxide semiconductor, one or more metal elements are unevenly distributed . The region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 The mixed state of particles with sizes of less than 1 nm or close to that size is called a mosaic or patch state. cormorant.

[0373] For example, CAC-IGZ in In-Ga-Zn oxide (hereinafter also referred to as IGZO) O is indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0.) , or indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z 2 is a real number greater than 0) and gallium oxide (GaO X3 (X3 is 0 ), or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0.) This results in a mosaic pattern, and the mosaic InO X1 , or In X2 Zn Y2 O Z2 However, the structure is such that the particles are uniformly distributed in the film (hereinafter also referred to as a cloud-like structure).

[0374] In other words, CAC-IGZO is GaO X3 The region where In is the main component and X2 Zn Y2 O Z 2, or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the ratio of an In atom to the element M in the first region is The atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region. , the concentration of In is higher than that of the first region.

[0375] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0376] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and, in the ab plane, It is a non-oriented, connected crystal structure.

[0377] On the other hand, CAC is related to the material composition. CAC is a material containing In, Ga, Zn, and O. In terms of material composition, there are areas where nanoparticles with Ga as the main component are observed, and areas where In is observed. The nanoparticle-like regions, which are mainly composed of , and the regions observed are randomly dispersed in a mosaic pattern. Therefore, the crystal structure is a secondary element in CAC.

[0378] Note that CAC does not include a laminated structure of two or more films with different compositions. However, this does not include a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component.

[0379] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0380] <Analysis of CAC-IGZO> Subsequently, using various measurement methods, the results of measuring the oxide semiconductor formed on the substrate are described below.

[0381] ≪Sample composition and fabrication method≫ Hereinafter, nine samples according to one aspect of the present invention will be described. Each sample is fabricated under different conditions of the substrate temperature and oxygen gas flow ratio when forming the oxide semiconductor. In addition, the sample has a structure including a substrate and an oxide semiconductor on the substrate.

[0382] The fabrication method of each sample will be described.

[0383] First, a glass substrate is used as the substrate. Subsequently, using a sputtering apparatus, indium-gallium-zinc oxide with a thickness of 100 nm is formed as an oxide semiconductor on the glass substrate. The film formation conditions are such that the pressure in the chamber is 0.6 Pa, and an oxide target ( In:Ga:Zn = 4:2:4.1 [atomic ratio]) is used for the target. Also, 2500 W of AC power is supplied to the oxide target installed in the sputtering apparatus. In:Ga:Zn = 4:2:4.1 [atomic ratio]) is used for the target. Also, 2500 W of AC power is supplied to the oxide target installed in the sputtering apparatus. In:Ga:Zn = 4:2:4.1 [atomic ratio]) is used for the target. Also, 2500 W of AC power is supplied to the oxide target installed in the sputtering apparatus.

[0384] Note that as the conditions for forming the oxide, the substrate temperature is intentionally not heated (hereinafter also referred to as R.T.), 130 °C, or 170 °C. Also, the flow ratio of oxygen gas to the mixed gas of Ar and oxygen (hereinafter also referred to as the oxygen gas flow ratio) is set to 10%, 30%, or 100% to fabricate nine samples. 100% to fabricate nine samples.

[0385] ≪Analysis by X-ray diffraction≫ In this section, X-ray diffraction (XRD: X-ray diffractio The results of the measurements will be explained below. The XRD equipment used was a Bruker D 8 ADVANCE was used. The conditions were θ / 2 In θ scan, the scanning range is 15° to 50°, and the step width is 0.02 deg. g., and the scanning speed was 3.0 deg. / min.

[0386] Figure 68 shows the results of measuring the XRD spectrum using the out-of-plane method. In Figure 68, the upper row shows the measurement results for a sample where the substrate temperature during film formation was 170°C. As a result, the middle row shows the measurement results for a sample with a substrate temperature of 130°C during film formation, and the bottom row shows the measurement results for a sample with a substrate temperature of 130°C during film formation. The left column shows the measurement results for samples with a substrate temperature of RT. The center column shows the measurement results for the sample with a flow rate ratio of 10%. The center column shows the measurement results for the sample with a flow rate ratio of 3%. The right column shows the measurement results for the sample with a 0% oxygen gas flow rate, and the right column shows the measurement results for the sample with a 100% oxygen gas flow rate. The measurement results are shown below.

[0387] The XRD spectrum shown in Figure 68 shows that the increase in the substrate temperature during film formation or the decrease in the amount of oxygen during film formation Increasing the gas flow rate ratio increases the peak intensity around 2θ=31°. The peak at 2θ=31° indicates that the c-axis is oriented in the direction approximately perpendicular to the surface on which the film is formed or the upper surface. Crystalline IGZO compound (CAAC(c-axis aligned crystallization) It is also called ine)-IGZO. ) is known to be derived from the fact that

[0388] In addition, the XRD spectrum shown in Figure 68 shows that the substrate temperature during film formation was low or the oxygen gas flow The smaller the ratio of the amount of SiO2, the less clear the peak. Alternatively, the sample with a small oxygen gas flow rate may have ab-plane and c-axis orientations in the measurement area. It turns out that it cannot be seen.

[0389] <Analysis by electron microscope> In this section, the samples were prepared at a substrate temperature of RT during film formation and an oxygen gas flow rate of 10%. ,HAADF(High-Angle Annular Dark Field)-ST EM(Scanning Transmission Electron Micros) The results of the observation and analysis using HAADF-S are described below (hereafter referred to as HAADF-S). Images obtained by TEM are also called TEM images.

[0390] Planar images obtained by HAADF-STEM (hereinafter also referred to as planar TEM images), and The results of image analysis of the cross-sectional images (hereinafter also referred to as cross-sectional TEM images) will be described below. The TEM images were observed using a spherical aberration correction function. The atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. was used for the photographs. The electron beam was irradiated at an acceleration voltage of 200 kV with a beam diameter of approximately 0.1 nmφ.

[0391] Figure 69(A) shows the results of a sample prepared at a substrate temperature of RT during film formation and an oxygen gas flow rate of 10%. Figure 69(B) shows the substrate temperature RT and oxygen gas concentration during film formation. This is a cross-sectional TEM image of a sample prepared at a flow rate ratio of 10%.

[0392] <Electron diffraction pattern analysis> In this section, the sample was prepared at a substrate temperature of RT and an oxygen gas flow rate of 10% during film formation. By irradiating an electron beam with a probe diameter of 1 nm (also called a nano-beam electron beam), The results of the X-ray diffraction pattern obtained will be explained below.

[0393] As shown in Figure 69(A), the film was formed at a substrate temperature of RT and an oxygen gas flow rate of 10%. In the planar TEM image of the sample, black spots a1, a2, a3, a4, and The electron beam diffraction pattern shown in a5 is observed. While irradiating the light, move the light at a constant speed from the 0-second position to the 35-second position. The results for black point a1 are shown in Figure 69(C), the results for black point a2 are shown in Figure 69(D), and the results for black point a3 are shown in Figure 69( The results for black point a4 are shown in Figure 69(F), and the results for black point a5 are shown in Figure 69(G).

[0394] From Figure 69(C), Figure 69(D), Figure 69(E), Figure 69(F), and Figure 69(G), A bright area can be observed in a circular (ring-like) pattern. Several spots can be observed.

[0395] In addition, as shown in FIG. 69(B), when the substrate temperature during film formation is RT and the oxygen gas flow rate ratio is 10%, In the cross-sectional TEM image of the prepared sample, black spots b1, b2, b3, b4, and Observe the electron diffraction patterns indicated by black spots b1 and b5. The results of black point b2 are shown in Figure 69(I), the results of black point b3 are shown in Figure 69(J), and the results of black point b4 are shown in Figure 69( The results for black point b5 are shown in Figure 69(L).

[0396] From Figure 69(H), Figure 69(I), Figure 69(J), Figure 69(K), and Figure 69(L), A ring-shaped area of ​​high brightness can be observed. Also, multiple spots can be observed in the ring-shaped area. can.

[0397] Here, for example, for a CAAC-OS having InGaZnO4 crystals, When an electron beam with a probe diameter of 300 nm is incident on the InGaZnO4 crystal, ) planes. It is clear that the film has a c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface. On the other hand, an electron beam with a probe diameter of 300 nm is incident perpendicularly to the sample surface. When the diffraction pattern is measured, a ring-shaped diffraction pattern is observed. It can be seen that the axes have no orientation.

[0398] In addition, oxide semiconductors having microcrystals (nano crystalline oxide semiconductor. Hereafter referred to as nc-OS.) For example, when electron diffraction is performed using an electron beam of 50 nm or more, a halo pattern is observed. In addition, a small probe diameter electron beam (e.g. When nanobeam electron diffraction is performed using a material with a thickness of less than 50 nm, bright spots are observed. In addition, when nanobeam electron diffraction is performed on nc-OS, a circular (ring-shaped) structure is observed. ) A bright area may be observed. In addition, multiple bright spots may be observed in a ring-shaped area. This may be the case.

[0399] The electron diffraction pattern of the sample prepared at the substrate temperature RT during film formation and with an oxygen gas flow rate of 10% The turn has a ring-shaped area of ​​high brightness and multiple bright spots in the ring area. The sample fabricated at a substrate temperature of RT and an oxygen gas flow rate of 10% during film formation was analyzed by electron beam diffraction. The pattern becomes nc-OS and has no orientation in the planar direction or cross-sectional direction. .

[0400] From the above, an oxide semiconductor formed at a low substrate temperature or a low oxygen gas flow rate ratio has the following properties: It is clearly different from both an oxide semiconductor film with an amorphous structure and an oxide semiconductor film with a single crystal structure. It can be assumed that it has the properties.

[0401] ≪Elemental analysis≫ In this article, we will discuss energy dispersive X-ray spectroscopy (EDX). EDX mapping was obtained and evaluated using X-ray spectroscopy. By this, the film was produced at a substrate temperature of RT and an oxygen gas flow rate of 10% during film formation. The results of the elemental analysis of the sample are explained below. The EDX measurement was carried out using an elemental analyzer and The energy dispersive X-ray analyzer JED-2300T manufactured by JEOL Ltd. is used. A Si drift detector is used to detect the X-rays emitted from the sample.

[0402] In EDX measurement, each point in the analysis area of ​​the sample is irradiated with an electron beam, and the resulting The energy and frequency of characteristic X-rays of the material are measured, and an EDX spectrum corresponding to each point is obtained. In this embodiment, the peaks in the EDX spectrum at each point are determined as electron transitions to the L shell of the In atom. , electron transition to the K shell of Ga atom, electron transition to the K shell of Zn atom, and electron transition to the K shell of O atom The ratio of each atom at each point is calculated. By performing EDX analysis on a region, it is possible to obtain EDX mapping that shows the distribution of the ratio of each atom. This can be done.

[0403] Figure 70 shows the results of the sample fabricated at a substrate temperature of RT and an oxygen gas flow rate of 10% during film formation. Figure 70(A) shows EDX mapping of Ga atoms ( The ratio of Ga atoms to all atoms is in the range of 1.18 to 18.64 [atomic%]. ) Figure 70(B) shows the EDX mapping of In atoms (the ratio of In atoms to all atoms). The ratio is in the range of 9.28 to 33.74 [atomic%]. C) EDX mapping of Zn atoms (ratio of Zn atoms to total atoms is 6.69 to 2.0). 4.99 [atomic%] range.) Also, Figure 70(A) and Figure 70(B) ), and Figure 70(C) shows the results when the substrate temperature during film formation was RT and the oxygen gas flow rate ratio was 10%. The cross section of the prepared sample shows the same area. The more elements measured in the range, the brighter it becomes, and the less elements measured, the darker it becomes. The ratio of elements is shown by light and dark. The magnification of the EDX mapping shown in Figure 70 is 7.2 million. It's double.

[0404] In the EDX mapping shown in Figure 70(A), Figure 70(B), and Figure 70(C), the images show The relative distribution of light and dark is observed. The substrate temperature during film formation is RT, and the oxygen gas flow rate is 10%. In the sample prepared in step 1, it can be seen that each atom exists with its own distribution. , the area surrounded by the solid line and the area surrounded by the dashed line shown in Figure 70(A), Figure 70(B), and Figure 70(C) Pay attention to the range.

[0405] In Figure 70(A), the area enclosed by the solid line contains many relatively dark areas, and the area enclosed by the dashed line contains many relatively dark areas. , and contains many relatively bright areas. Also, in Figure 70(B), the area enclosed by the solid line is relatively The area surrounded by the dashed line contains many bright areas, while the area surrounded by the dashed line contains many relatively dark areas.

[0406] In other words, the area surrounded by the solid line is the area where the In atoms are relatively abundant, and the area surrounded by the dashed line is the area where the In atoms are relatively abundant. In Figure 70(C), in the area surrounded by the solid line, The right side is a relatively bright area, and the left side is a relatively dark area. The range is In X2 Zn Y2 O Z2 , or InO X1 This is the area where the main components are:

[0407] The area surrounded by the solid line is the area where the number of Ga atoms is relatively small, and the area surrounded by the dashed line is the area where the number of Ga atoms is relatively small. In Figure 70(C), the area surrounded by the dashed line is the upper left area. The area at the bottom right is a relatively bright area, and the area at the bottom right is a relatively dark area. The area enclosed by the line is GaO X3 , or Ga X4 Zn Y4 O Z4 In the area where the main components are be.

[0408] Also, from Figures 70(A), 70(B), and 70(C), the distribution of In atoms is The atoms are relatively uniformly distributed, and X1 The region where is the main component is In X2 Zn Y2 O Z2 It appears that they are connected to each other through the area where In this way, X2 Zn Y2 O Z2 , or InO X1 The area where is the main component is It is formed in a loud, spreading shape.

[0409] Thus, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 In-Ga-Zn oxide with a structure in which the regions in which The material can be called CAC-IGZO.

[0410] The crystal structure of CAC is an nc structure. The nc structure of CAC is In the X-ray diffraction pattern, bright spots originating from IGZO including single crystal, polycrystalline, and CAAC structures In addition to the spot, there are several bright spots. In addition to the bright spots, the crystal structure is defined as a ring-shaped area of ​​high brightness. do.

[0411] Also, from Figures 70(A), 70(B), and 70(C), GaO X3 is the main component Areas where X2 Zn Y2 O Z2 , or InO X1 The size of the region where is the principal component is The observed size is 0.5 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less. In EDX mapping, the diameter of the area where each metal element is the main component is 1 nm or more. The thickness should be 2 nm or less.

[0412] From the above, CAC-IGZO has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. CAC-IGZO has a structure different from that of IGZO compounds. X3 The region where In is the main component. X2 Zn Y2 O Z2 , or InO X1 is the main component The structure is such that the regions with each element as the main component are separated into phases, forming a mosaic. Therefore, when CAC-IGZO is used in a semiconductor device, GaO X3 Due to factors such as Properties and In X2 Zn Y2 O Z2 , or InO X1 The properties resulting from this act in a complementary manner. This results in a high on-state current (I on ), and high field-effect mobility (μ) It is possible.

[0413] In addition, semiconductor devices using CAC-IGZO are highly reliable. O is ideal for a variety of semiconductor devices, including displays.

[0414] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0415] (Embodiment 3) In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention is shown in a drawing. Please refer to the following for explanation.

[0416] <Cross-sectional structure> FIG. 42A is a cross-sectional view of a semiconductor device of one embodiment of the present invention. In FIG. The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. The semiconductor device shown in FIG. 2 has a transistor 2200 using a first semiconductor material in the lower part, In FIG. 42(A), a transistor 2100 using a second semiconductor material is provided in the semiconductor layer. As the transistor 2100 using the second semiconductor material, the transistor exemplified in the above embodiment may be used. The left side of the dashed line is the channel of the transistor. The right side is a cross section in the longitudinal direction, and the left side is a cross section in the channel width direction.

[0417] The first and second semiconductor materials preferably have different band gaps. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). (including), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide the second semiconductor (e.g., gallium gallium, indium phosphide, gallium nitride, organic semiconductors, etc.); The body material can be an oxide semiconductor. On the other hand, transistors using oxide semiconductors can easily operate at high speed. By applying the transistor exemplified in the previous embodiment, the S value (sub The threshold value can be reduced, making it possible to create a miniaturized transistor. In addition, high-speed operation is possible due to the fast switching speed, and leakage current is low due to the low off-current. The flow is small.

[0418] The transistor 2200 may be an n-channel transistor or a p-channel transistor. Either of these transistors may be used, and an appropriate transistor may be used depending on the circuit. The transistor of one embodiment of the present invention using a nitride semiconductor is used, and other materials and structures are not limited to these. However, the specific configuration of the semiconductor device does not need to be limited to that shown here.

[0419] In the structure shown in FIG. 42A, an insulator 2201 and an insulator The transistor 2100 is connected via the transistor 2207. A plurality of wirings 2202 are provided between the transistor 2100 and the A plurality of plugs 2203 embedded in the substrate allow wiring provided on the upper and lower layers to be The electrodes are electrically connected to the insulator 2204 covering the transistor 2100. , and a wiring 2205 is provided on the insulator 2204 .

[0420] In this way, stacking two types of transistors reduces the area occupied by the circuit, Multiple circuits can be arranged at higher density.

[0421] Here, when a silicon-based semiconductor material is used for the transistor 2200 provided in the lower layer, The hydrogen in the insulator provided near the semiconductor film of the transistor 2200 is converted into silicon dung. This has the effect of terminating the ring bond and improving the reliability of the transistor 2200. When an oxide semiconductor is used for the transistor 2100 provided in the upper layer, the transistor 21 Hydrogen in the insulator provided near the semiconductor film of 00 generates carriers in the oxide semiconductor. This may be one of the factors that cause the reliability of the transistor 2100 to decrease. Therefore, the upper layer of the transistor 2200 made of silicon-based semiconductor material is oxidized. When the transistor 2100 using a compound semiconductor is stacked, hydrogen diffusion between them It is particularly effective to provide an insulator 2207 that has the function of preventing the insulator 220 7 improves the reliability of the transistor 2200 by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, and thus the transistor 2100 At the same time, reliability can be improved.

[0422] The insulator 2207 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0423] In addition, a transistor 2100 including an oxide semiconductor film is formed so as to cover the transistor 2100. It is preferable to form a blocking film on the surface of the substrate 2100, which has the function of preventing hydrogen diffusion. The blocking film can be made of the same material as the insulator 2207, and in particular, It is preferable to use aluminum oxide. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. It has a high blocking effect, preventing both pure substances and oxygen from passing through the membrane. Therefore, an aluminum oxide film is used as the blocking film covering the transistor 2100. This prevents oxygen from being released from the oxide semiconductor film included in the transistor 2100. In addition, water and hydrogen can be prevented from entering the oxide semiconductor film. The locking film may be used by laminating the insulator 2204 or by placing the insulator 2204 under the insulator 2204. It may also be provided in.

[0424] The transistor 2200 is not limited to a planar transistor, but may be any of various types. For example, FIN type, TRI-GATE type, The transistor may be a ligate type transistor. An example of a cross section of such a transistor is shown below. As shown in FIG. 42(D), an insulator 2212 is provided on a semiconductor substrate 2211. The conductive substrate 2211 has a protrusion (also called a fin) with a thin tip. The protrusions may not have a thin tip, for example, The protrusions may be rectangular parallelepiped or may have thick tips. On the convex portion, a gate insulator 2214 is provided, and on top of that, a gate electrode 2213 is provided. In the semiconductor substrate 2211, source regions and drain regions 2215 are formed. Here, an example in which the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

[0425] <Circuit configuration example> In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device of one aspect of the present invention will be described.

[0426] <CMOS inverter circuit> The circuit diagram shown in FIG. 42(B) shows the configuration of a so-called CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.

[0427] <CMOS analog switch> Also, the circuit diagram shown in FIG. 42(C) shows a configuration in which the sources and drains of the transistor 2100 and the transistor 2200 are connected. By adopting such a configuration, it can function as a so-called CMOS analog switch.

[0428] <Example of a memory device> An example of a semiconductor device (memory device) that can maintain stored content even when power is not supplied and has no limit on the number of write operations by using a transistor which is one aspect of the present invention is shown in FIG. 43.

[0429] The semiconductor device shown in FIG. 43A includes a transistor 3200 using a first semiconductor material and a second semiconductor material. The semiconductor device includes a transistor 3300 and a capacitor 3400 made of two semiconductor materials. Note that the transistor 3300 is the transistor described in the previous embodiment. It is possible.

[0430] 43(B) shows a cross-sectional view of the semiconductor device shown in FIG. In the figure, a configuration in which a back gate is provided in the transistor 3300 is shown. It may be configured not to provide.

[0431] The transistor 3300 is a transistor in which a channel is formed in a semiconductor including an oxide semiconductor. The transistor 3300 has a small off-state current. It is possible to retain memory contents for a long period of time, i.e., no refresh operation is required. It is possible to provide a semiconductor memory device that does not require refresh operations or that requires extremely low frequency of refresh operations. This allows for a sufficient reduction in power consumption.

[0432] In FIG. 43A, a first wiring 3001 is electrically connected to a source electrode of a transistor 3200. The second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. The third wiring 3003 is connected to the source electrode or drain of the transistor 3300. The fourth wiring 3004 is electrically connected to one of the drain electrodes of the transistor 3300. The gate electrode of the transistor 3200 is electrically connected to the transistor 3200. The other of the source electrode and the drain electrode of the transistor 3300 and the capacitor 3400 The fifth wiring 3005 is electrically connected to the first terminal of the capacitor 3400. are electrically connected.

[0433] In the semiconductor device shown in FIG. 43A, the potential of the gate electrode of the transistor 3200 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows: do.

[0434] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is turned on by applying a potential to the transistor 3300. As a result, the potential of the third wiring 3003 is applied to the gate electrode of the transistor 3200 and and the capacitance element 3400. That is, the gate electrode of the transistor 3200 is A predetermined charge is applied (write). Here, the charge that gives two different potential levels is (hereinafter referred to as Low level charge and High level charge) After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off. By turning off the transistor 3300, the gate of the transistor 3200 The charge applied to the port electrode is retained (retention).

[0435] Since the off-state current of the transistor 3300 is extremely small, the gate voltage of the transistor 3200 The charge on the pole is maintained for a long period of time.

[0436] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (read potential) is applied to the fifth wiring 3005, the transistor The second wiring 3002 is at a different potential depending on the amount of charge held in the gate electrode of the capacitor 3200. In general, if the transistor 3200 is an n-channel type, then the transistor 3200 The apparent threshold voltage V when a high level charge is applied to the gate electrode of th_H is seen when a low level charge is applied to the gate electrode of transistor 3200. Threshold V th_L Here, the apparent threshold voltage is The potential of the fifth wiring 3005 required to turn on the transistor 3200 is Therefore, the potential of the fifth wiring 3005 is set to V th_H and V th_L Between By setting the potential V0, the charge given to the gate electrode of the transistor 3200 is determined. For example, if a high level charge is applied during writing, The potential of the wiring 3005 of 5 is V0 (>V th_H ), then transistor 3200 is "ON" When a low level charge is applied, the voltage of the fifth wiring 3005 is The digit is V0( <V th_L ), transistor 3200 remains in the "off state." Therefore, the stored data can be read by determining the potential of the second wiring 3002. It can be put out.

[0437] When memory cells are arranged in an array, only the information in the desired memory cell can be read. For example, in a memory cell that does not read information, the gate state The potential at which transistor 3200 is in the "off state" regardless of the voltage, i.e., V t h_H By applying a smaller potential to the fifth wiring 3005, only the information of the desired memory cell is stored. Alternatively, in a memory cell from which information is not read, The potential at which transistor 3200 is in the "on state" regardless of the state of the gate, i.e., Chi, V th_L By applying a larger potential to the fifth wiring 3005, the desired memory cell It is sufficient to have a configuration in which only the information can be read out.

[0438] The semiconductor device shown in FIG. 43(C) is different from the semiconductor device shown in FIG. 43(A) in that it does not include the transistor 3200. In this case, the same operations as above are performed to write and store information. It is possible.

[0439] Next, the reading of information will be described. When the transistor 3300 is turned on, The third wiring 3003 in the free state and the capacitor element 3400 are electrically connected to each other. Charge is redistributed between the capacitors 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is determined by the potential of the first terminal of the capacitor 3400 ( Alternatively, it takes on different values ​​depending on the charge stored in the capacitor element 3400.

[0440] For example, the potential of the first terminal of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the potential of the third terminal of the capacitor 3400 is V. The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× Therefore, the state of the memory cell is If the potential of the first terminal of the transistor 3400 is in two states, V1 and V0 (V1>V0), The potential of the third wiring 3003 when the potential V1 is held (=(CB×VB0+C×V1) / (CB+C)) is the potential (=(C It can be seen that this is higher than B×VB0+C×V0) / (CB+C)).

[0441] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0442] In this case, the first semiconductor material is applied to a drive circuit for driving the memory cell. A transistor is used, and a transistor in which a second semiconductor material is applied as the transistor 3300 is used. The transistor may be stacked on the driver circuit.

[0443] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is This allows the frequency of operations to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is desirable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0444] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating layer does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the on / off state of the transistor determines the amount of information Since writing is performed, high speed operation can be easily achieved.

[0445] By using the semiconductor device described in this embodiment, low power consumption and high capacity (for example It is possible to create memory devices with a capacity of 1 terabit or more.

[0446] In this specification, the terms "active elements" and "passive elements" are used interchangeably. For all terminals of elements such as capacitors and resistors, the connection destination must be specified. However, a person skilled in the art may be able to compose an aspect of the invention. Even if the destination is not specified, one aspect of the invention can be said to be clear. When the content is described in this specification, etc., one aspect of the invention that does not specify the connection destination is In particular, if the terminal is connected to multiple If several cases are possible, there is no need to limit the connection destination of the terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitance elements, resistance elements) By specifying the connection destinations for only some of the terminals of a device (such as a semiconductor device), This may constitute an aspect of the invention.

[0447] In this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art. It may be possible for a person skilled in the art to identify an invention. A person skilled in the art may be able to identify an invention by at least specifying the function. In other words, if the function is specified, it can be said that one aspect of the invention is clear. In some cases, it may be possible to determine that one aspect of the invention is described in this specification or the like. Thus, for a certain circuit, even without specifying the function, if the connection destination is specified, it is disclosed as one aspect of the invention and can constitute one aspect of the invention. Or for a certain circuit, even without specifying the connection destination, if the function is specified, it is disclosed as one aspect of the invention and can constitute one aspect of the invention. Note that in this specification or the like, in a certain embodiment, in the figure or text described, it is possible to extract a part thereof to constitute one aspect of the invention. Therefore, when a figure or text describing a certain part is described, the content obtained by extracting a part of the figure or text is also disclosed as one aspect of the invention and can be considered to constitute one aspect of the invention. Thus, for example, in a drawing or text in which one or more active elements (such as transistors, diodes, etc.), wirings, passive elements (such as capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductors, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc. are described, it is possible to extract a part thereof to constitute one aspect of the invention.

[0448] For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute one aspect of the invention. As yet another example, from N ( In addition, in a certain embodiment, in the figure or text described, it is possible to extract a part thereof to constitute one aspect of the invention. Therefore, when a figure or text describing a certain part is described, the content obtained by extracting a part of the figure or text is also disclosed as one aspect of the invention and can be considered to constitute one aspect of the invention. Thus, for example, in a drawing or text in which one or more active elements (such as transistors, diodes, etc.), wirings, passive elements (such as capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductors, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc. are described, it is possible to extract a part thereof to constitute one aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute one aspect of the invention. As yet another example, from N ( In some cases, it may be possible to determine that one aspect of the invention is described in this specification or the like. Thus, for a certain circuit, even without specifying the function, if the connection destination is specified, it is disclosed as one aspect of the invention and can constitute one aspect of the invention. Or for a certain circuit, even without specifying the connection destination, if the function is specified, it is disclosed as one aspect of the invention and can constitute one aspect of the invention. Note that in this specification or the like, in a certain embodiment, in the figure or text described, it is possible to extract a part thereof to constitute one aspect of the invention. Therefore, when a figure or text describing a certain part is described, the content obtained by extracting a part of the figure or text is also disclosed as one aspect of the invention and can be considered to constitute one aspect of the invention. Thus, for example, in a drawing or text in which one or more active elements (such as transistors, diodes, etc.), wirings, passive elements (such as capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductors, organic materials, inorganic materials, components, devices, operation methods, manufacturing methods, etc. are described, it is possible to extract a part thereof to constitute one aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute one aspect of the invention. As yet another example, from N ( For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute one aspect of the invention. As yet another example, from N ( For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute one aspect of the invention. As yet another example, from N ( For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute one aspect of the invention. As yet another example, from N ( For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute one aspect of the invention. As yet another example, from N ( For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute one aspect of the invention. As yet another example, from N ( For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) to constitute one aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute one aspect of the invention. As yet another example, from N ( From a flowchart consisting of M elements (M is an integer, M <N) It is possible to extract the elements and configure one aspect of the invention.

[0449] <Imaging device> An imaging device according to one aspect of the present invention will be described below.

[0450] FIG. 44A is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral circuit The pixel section 210 has p rows and q columns. (p and q are integers of 2 or more) are arranged in a matrix. The peripheral circuits 260, 270, 280, and 290 are each The pixel 211 is connected to the plurality of pixels 211 and has a function of supplying signals for driving the plurality of pixels 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 can be considered a part of the peripheral circuit.

[0451] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel portion 210 is formed. In addition, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuitry. The peripheral circuits include the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be omitted.

[0452] As shown in FIG. 44B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the images captured.

[0453] <Pixel configuration example 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and each sub-pixel The pixel 212 is combined with a filter (color filter) that transmits light of a specific wavelength band. By doing so, it is possible to obtain information for realizing a color image display.

[0454] FIG. 45(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in 45(A) is provided with a color filter that transmits light in the red (R) wavelength band. The subpixel 212 (hereinafter also referred to as "subpixel 212R") receives light in the green (G) wavelength band. A sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") is provided with a color filter that transmits light. A sub-pixel 212 is provided with a color filter that transmits light in the wavelength bands of blue (B) and blue (C). (hereinafter also referred to as "sub-pixel 212B"). It can be made to function.

[0455] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, in the nth line (n is an integer between 1 and p), The wiring 248 and the wiring 249 connected to the pixel 211 of and wiring 249[n]. For example, in the m-th column (m is an integer between 1 and q), The wiring 253 connected to the pixel 211 is referred to as wiring 253[m]. ), the wiring 253 connected to the sub-pixel 212R of the pixel 211 in the m-th column is connected to the wiring 2 53[m]R, the wiring 253 connected to the sub-pixel 212G is the wiring 253[m]G, and the sub-pixel The wiring 253 connected to the subpixel 212B is described as wiring 253[m]B. , and are electrically connected to the peripheral circuits via the wiring.

[0456] In addition, the imaging device 200 detects color filters of adjacent pixels 211 that transmit light in the same wavelength band. The sub-pixels 212 provided with the filters are electrically connected to each other via switches. In Figure 45(B), there are n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). The sub-pixel 212 of the pixel 211 and the pixel 211 adjacent to the pixel 211 in the n+1th row and the mth column are 45B shows an example of connection of sub-pixels 212 included in the arranged pixel 211. In FIG. The sub-pixel 212R arranged in the row and column m and the sub-pixel 212R arranged in the row and column n+1 are switched. The sub-pixels 212G and 212H are connected via a switch 201. The sub-pixels 212G and 212H are arranged in n rows and m columns. The sub-pixel 212G arranged in the +1 row and the m column is connected via the switch 202. , the sub-pixel 212B arranged in the nth row and the mth column, and the sub-pixel 212B arranged in the n+1th row and the mth column They are connected via a switch 203 .

[0457] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light, respectively. A single pixel 211 may have sub-pixels for detecting light of three different wavelength bands. By providing 212, a full color image can be obtained.

[0458] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are installed. In addition to the sub-pixel 212, a sub-pixel having a color filter that transmits yellow (Y) light is provided. Pixel 211 may be used with pixel 212. Alternatively, cyan (C), yellow (Y), In addition to the sub-pixel 212 provided with a color filter that transmits light of blue (Y) and magenta (M), The pixel 21 has a sub-pixel 212 provided with a color filter that transmits blue (B) light. One pixel 211 may have sub-pixels 2 that detect light in four different wavelength bands. By providing the lens 12, the color reproducibility of the acquired image can be further improved.

[0459] Also, for example, in FIG. 45(A), the sub-pixel 212 detects light in the red wavelength band, a subpixel 212 for detecting light in a wavelength band, and a subpixel 212 for detecting light in a blue wavelength band; The pixel ratio (or light receiving area ratio) does not have to be 1:1:1. For example, A Bayer array with a light receiving area ratio of red:green:blue=1:2:1 may also be used. The pixel number ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0460] The number of sub-pixels 212 provided in the pixel 211 may be one, but it is preferable that there are two or more. By providing two or more sub-pixels 212 that detect light in the same wavelength band, redundancy is increased, and the image This can improve the reliability of the imaging device 200.

[0461] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

[0462] In addition, an ND (Neutral Density) filter (neutral density filter) is used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows for a wider dynamic range of the device.

[0463] In addition to the above-mentioned filter, a lens may be provided in the pixel 211. An example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described using a cross-sectional view. By providing the lens 255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 46(A), a lens 255 and a filter 25 formed in the pixel 211 4 (filter 254R, filter 254G and filter 254B), and pixel circuit 2 30 or the like, light 256 can be made incident on the photoelectric conversion element 220.

[0464] However, as shown in the area surrounded by the dashed line, part of the light 256 indicated by the arrow is reflected by the wiring 257. Therefore, as shown in Figure 46(B), A lens 255 and a filter 254 are arranged on the conversion element 220 side, and the photoelectric conversion element 220 It is preferable that the light 256 is received efficiently from the photoelectric conversion element 220 side. By making the light incident on the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity is provided. can be done.

[0465] The photoelectric conversion element 220 shown in FIG. 46 is formed with a pn-type junction or a pin-type junction. A photoelectric conversion element may also be used.

[0466] The photoelectric conversion element 220 is made of a material that has the function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating charges may be a ceramic. Lead, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy etc.

[0467] For example, if selenium is used for the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, including X-rays and gamma rays 20 can be achieved.

[0468] Here, one pixel 211 included in the imaging device 200 has, in addition to the sub-pixel 212 shown in FIG. 2. The pixel 212 may have a first filter.

[0469] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of configuring a pixel using the above will be described.

[0470] 47(A) and 47(B) are cross-sectional views of elements that constitute the imaging device.

[0471] The imaging device shown in FIG. 47(A) is a silicon-based transistor provided on a silicon substrate 300. a transistor 351 using an oxide semiconductor and stacked over the transistor 351; The transistor 353 and the anode 361 and the cathode 362 are provided on the silicon substrate 300. 362. Each transistor and photodiode 360 is electrically connected to various plugs 370 and wires 371, 372, and 373. The anode 361 of the photodiode 360 ​​is connected to the low resistance region 363. 370 and electrically connected thereto.

[0472] The imaging device also includes a transistor 351 and a photodiode 352 provided on the silicon substrate 300. A layer 310 having an electrode 360 ​​and a layer 371 provided in contact with the layer 310. 20, a layer 330 provided in contact with the layer 320 and having a transistor 353, and The layer 340 is provided in contact with the wiring 372 and the wiring 373 .

[0473] In the example of the cross-sectional view of FIG. 47(A), the transistor 3 is formed on the silicon substrate 300. The light receiving surface of the photodiode 360 ​​is located on the opposite side to the surface on which the photodiode 51 is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. The light-receiving surface of the gate 360 ​​may be the same as the surface on which the transistor 351 is formed.

[0474] Note that when a pixel is formed using a transistor including an oxide semiconductor, the layer 310 Alternatively, the layer 310 may be omitted. Alternatively, a pixel may be formed using only a transistor including an oxide semiconductor.

[0475] In the cross-sectional view of FIG. 47(A), the photodiode 360 ​​provided in the layer 310 and the layer The transistor 330 can be formed so as to overlap with the transistor 330. In other words, the resolution of the imaging device can be increased.

[0476] In addition, in FIG. 47(B), the imaging device has a photodiode 365 on the layer 340 side. In FIG. 47(B), for example, the layer 310 may have a structure in which: The layer 320 includes a transistor 351 using silicon, the layer 320 includes a wiring 371, and the layer 330 includes a The layer 340 includes a transistor 353 using an oxide semiconductor and an insulating layer 380. The power supply 361 has a diode 365, and is connected to a wiring 373 and a wiring 374 via a plug 370. are emotionally connected.

[0477] By using the element configuration shown in FIG. 47(B), the aperture ratio can be improved.

[0478] The photodiode 365 is made of an amorphous silicon film or a microcrystalline silicon film. The photodiode 365 may be an n-type semiconductor. 368, an i-type semiconductor 367, and a p-type semiconductor 366 are stacked in this order. It is preferable to use amorphous silicon for the i-type semiconductor 367. The conductor 366 and the n-type semiconductor 368 contain dopants that impart their respective conductivity types. Amorphous silicon or microcrystalline silicon, which contains amorphous silicon, can be used. The photodiode 365 used as the electric conversion layer has high sensitivity in the visible light wavelength range, and Visible light is easily detected.

[0479] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0480] (Fourth embodiment) In this embodiment, the transistor including the oxide semiconductor layer described in the above embodiment ( An example of a circuit configuration to which an OS transistor can be applied will be described with reference to FIGS. do.

[0481] Figure 48(A) shows an inverter that can be applied to memory, FPGA, CPU, etc. The inverter 2800 inverts the logic of the signal applied to the input terminal IN. The inverter 2800 has a plurality of OS transistors. . signal S BG is a signal that can switch the electrical characteristics of the OS transistor.

[0482] FIG. 48B is a circuit diagram of an example of the inverter 2800. The inverter 2800 is , OS transistor 2810, and OS transistor 2820. 800 can be manufactured as an n-channel type, and can be configured as a so-called unipolar circuit. Since the inverter can be fabricated with a unipolar circuit configuration, it is suitable for CMOS (Complementary Metal Oxide Semiconductor) ary Metal Oxide Semiconductor) circuit with inverter (C It can be fabricated at a lower cost than fabricating a conventional MOS inverter.

[0483] The inverter 2800 having an OS transistor is a C inverter made of Si transistors. It can also be placed on a MOS circuit. The inverter 2800 is important for the CMOS circuit configuration. Since the inverters can be placed side by side, the increase in circuit area due to the addition of 2800 inverters can be suppressed. can.

[0484] The OS transistor 2810 and the OS transistor 2820 function as front gates. The first gate functions as a gate electrode, the second gate functions as a back gate, and one of the source and drain electrodes. a first terminal that functions as one of the source and drain, and a second terminal that functions as the other of the source and drain. do.

[0485] The first gate of OS transistor 2810 is connected to the second terminal. The second gate of 810 receives the signal S BG connected to the wiring that transmits the OS transistor 281 The first terminal of OS transistor 2810 is connected to a wiring that supplies voltage VDD. The second terminal is connected to the output terminal OUT.

[0486] A first gate of the OS transistor 2820 is connected to the input terminal IN. The second gate of the OS transistor 2820 is connected to the input terminal IN. The first terminal of the OS transistor 2820 is connected to the output terminal OUT. Connected to the wire that supplies VSS.

[0487] FIG. 48C is a timing chart for explaining the operation of the inverter 2800. In the timing chart of Figure 48(C), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are Signal waveform, signal S BG and the change in the threshold voltage of the OS transistor 2810. This shows the following.

[0488] signal S BG is applied to the second gate of the OS transistor 2810, The threshold voltage of 2810 can be controlled.

[0489] signal S BG is the voltage V for shifting the threshold voltage negatively BG_A , threshold voltage Voltage V BG_B The second gate has a voltage V BG_A To give Thus, the OS transistor 2810 has a threshold voltage V TH_A can be negatively shifted to Also, the second gate is connected to a voltage V BG_B By providing Threshold voltage V TH_B can be shifted positively to

[0490] To visualize the above explanation, FIG. 49(A) shows one of the electrical characteristics of a transistor. 1 shows a graph of the Vg-Id curve.

[0491] The electrical characteristics of the OS transistor 2810 described above are determined by setting the voltage of the second gate to a voltage V BG_A of By increasing the value, the curve is shifted to the curve shown by the dashed line 2840 in FIG. 49(A). The electrical characteristics of the OS transistor 2810 can be determined by the voltage of the second gate. Voltage V BG_B By making it smaller, the solid line 2841 in Figure 49(A) can be As shown in FIG. 49(A), the OS transistor 28 10 is signal S BG voltage V BG_A Or voltage V BG_B Switching like this This allows the threshold voltage to be shifted in a positive or negative direction.

[0492] The threshold voltage is V TH_B By shifting the voltage to the positive side, the OS transistor 2810 This state can be visualized in Figure 49(B). As shown in FIG. 49B, the current I B Extreme Therefore, when the signal applied to the input terminal IN is high level, When the transistor 2820 is in the ON state (ON), it makes the voltage at the output terminal OUT drop sharply. It can be done.

[0493] As shown in FIG. 49B, the current flowing through the OS transistor 2810 is difficult. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 2831 can be made to change sharply. It is possible to reduce the through current flowing between the wiring that supplies SS, resulting in low power consumption. The following operations can be performed.

[0494] Also, the threshold voltage is V TH_A By shifting the voltage to the negative side, the OS transistor 2810 can be made to be in a state where current can easily flow. As shown in Figure 49(C), the current I A At least Flow I B Therefore, the signal applied to the input terminal IN is low level. When the OS transistor 2820 is in the OFF state, the voltage at the output terminal OUT is The rise can be made steeper.

[0495] As shown in FIG. 49C, the OS transistor 2810 is in a state where a current easily flows. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 2832 can be made to change sharply.

[0496] In addition, signal S BG The control of the threshold voltage of OS transistor 2810 by It is preferable to perform this before the state of the controller 2820 is switched, that is, before time T1 or T2. For example, as shown in FIG. 48(C), when the signal applied to the input terminal IN is at a high level, Before the time T1 at which the transistor switches to the threshold voltage V TH_A to threshold voltage V TH_B OS to It is preferable to switch the threshold voltage of the transistor 2810. In this way, before time T2 when the signal applied to the input terminal IN is switched to low level, Threshold voltage V TH_B to threshold voltage V TH_A The threshold voltage of the OS transistor 2810 is then changed. It is preferable to change it.

[0497] In the timing chart of FIG. 48(C), the signal S BG However, other configurations may be used. For example, a configuration for controlling the threshold voltage may be used. The voltage for this purpose is maintained at the second gate of the OS transistor 2810, which is in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. ) shown.

[0498] In FIG. 50A, in addition to the circuit configuration shown in FIG. 48B, an OS transistor 2850 The first terminal of OS transistor 2850 is connected to the second gate of OS transistor 2810. The second terminal of OS transistor 2850 is connected to the voltage V BG_B (be or voltage V BG_A ) is connected to the wiring that provides the first gate of the OS transistor 2850. The signal S F The second gate of OS transistor 2850 is connected to a wiring that provides Voltage V BG_B (or voltage V BG_A ) is connected to the wire that gives

[0499] The operation of the circuit configuration in Figure 50(A) will be explained using the timing chart in Figure 50(B). Reveal.

[0500] The voltage for controlling the threshold voltage of the OS transistor 2810 is determined by the signal applied to the input terminal IN. Before time T3 when the signal is switched to a high level, the second gate of the OS transistor 2810 The signal S F is set to a high level to turn on the OS transistor 2850. In this state, node N BG Voltage V for controlling the threshold voltage BG_B Give.

[0501] Node N BG is the voltage V BG_B After this, the OS transistor 2850 is turned off. The OS transistor 2850 has an extremely small off-state current and can be kept in an off state. So, once node N BG The voltage V BG_B Therefore, , the second gate of the OS transistor 2850 is supplied with a voltage V BG_B The number of actions to give Therefore, the voltage V BG_B Therefore, the power consumption required for rewriting the data can be reduced.

[0502] In the circuit configurations of FIGS. 48B and 50A, the first 2. We have shown a configuration in which the voltage applied to the gate is controlled externally, but For example, the voltage for controlling the threshold voltage may be set as a signal to be applied to the input terminal IN. Alternatively, the second gate of the OS transistor 2810 may be provided with a second gate electrode of the OS transistor 2810. An example of a circuit configuration that can realize this configuration is shown in FIG.

[0503] In Figure 51(A), the input terminal IN and the OS transformer are connected in the circuit configuration shown in Figure 48(B). A CMOS inverter 2860 is provided between the first gate of the transistor 2810 and the second gate of the transistor 2810. The input terminal of the inverter 2860 is connected to the input terminal IN. The 0 output terminal is connected to the second gate of OS transistor 2810.

[0504] The operation of the circuit configuration of Figure 51(A) will be explained using the timing chart of Figure 51(B). In the timing chart of FIG. 51(B), the signal waveform of the input terminal IN and the signal waveform of the output terminal O The signal waveform of UT, the output waveform IN_B of the CMOS inverter 2860, and the OS transistor 28 shows the change in threshold voltage of the transistor 2810.

[0505] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is 49(A) can be used as a signal to control the threshold voltage of the resistor 2810. As described in (a) to (c), the threshold voltage of the OS transistor 2810 can be controlled. For example, at time T4 in FIG. 51(B), the signal applied to the input terminal IN is at a high level. At this time, the OS transistor 2820 is turned on. Therefore, the OS transistor 2810 is in a state where it is difficult for current to flow. This allows the voltage at the output terminal OUT to drop sharply.

[0506] Also, at time T5 in FIG. 51(B), the signal applied to the input terminal IN is low level. At this time, the OS transistor 2820 is turned off. Therefore, the OS transistor 2810 can be made to be in a state where current can easily flow. This allows the voltage at the output terminal OUT to rise sharply.

[0507] As described above, in the configuration of this embodiment, in the inverter having the OS transistor, The back gate voltage is switched according to the logic of the signal at the input terminal IN. By configuring the OS transistor in this manner, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the output terminal OU in accordance with the signal given to the input terminal IN, This makes it possible to make the voltage change of T steeper. Also, it is possible to reduce the through current between the wiring that supplies the power supply voltage. Therefore, it is possible to reduce power consumption.

[0508] (Embodiment 5) <RFタグ> In this embodiment, an RF device including a transistor or a memory device described in the previous embodiment is used. The tag will be explained with reference to FIG.

[0509] The RF tag in this embodiment has a memory circuit inside, and stores necessary information in the memory circuit. It transmits and receives information to and from the outside using non-contact means, such as wireless communication. Due to these characteristics, RF tags are used as individual devices to identify items by reading their individual information. It can be used for biometric authentication systems. High reliability is required.

[0510] The structure of an RF tag will be described with reference to Fig. 52. Fig. 52 is a block diagram showing an example of the structure of an RF tag. FIG.

[0511] As shown in FIG. 52, an RF tag 800 includes a communicator 801 (also known as an interrogator, reader / writer, etc.). 8, which receives a radio signal 803 transmitted from an antenna 802 connected to the The RF tag 800 also includes a rectifier circuit 805, a constant voltage circuit 806, and a demodulator circuit 808. 07, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. In addition, the reverse current of the transistor showing the rectification action included in the demodulation circuit 807 is sufficiently suppressed. A material capable of achieving this, for example, an oxide semiconductor, may be used. This suppresses the degradation of rectification caused by reverse current and prevents the output of the demodulation circuit from saturating. In other words, the output of the demodulation circuit can be made closer to linearity with respect to the input of the demodulation circuit. The data transmission format is a pair of coils arranged facing each other and communicating through mutual induction. electromagnetic coupling, electromagnetic induction, which communicates by induced electromagnetic fields; and radio wave communication. The RF tag 800 shown in this embodiment can be used with any of these methods. It can also be used for

[0512] Next, the configuration of each circuit will be explained. The rectifier circuit 802 is used to transmit and receive a radio signal 803 to and from the antenna 802. 05 rectifies an input AC signal generated by receiving a radio signal through an antenna 804. For example, half-wave double voltage rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. The rectifier circuit 805 is a circuit for generating an input potential by rectifying the input side or A limiter circuit may be provided on the output side. When the internally generated voltage is large, it is necessary to prevent power above a certain level from being input to the subsequent circuit. This is a circuit for controlling the

[0513] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. The constant voltage circuit 806 may have a reset signal generating circuit inside. The reset signal generation circuit uses the rising edge of the stable power supply voltage to reset the logic circuit 80. This is a circuit for generating the reset signal for 9.

[0514] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. The modulation circuit 808 is a circuit for modulating the data output from the antenna 804. This is a circuit for performing modulation based on the received signal.

[0515] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. It is a circuit that holds input information, and includes a row decoder, column decoder, memory area, etc. The ROM 811 stores a unique number (ID) and outputs it according to the processing. This is a circuit for

[0516] The above-mentioned circuits can be selected or removed as needed.

[0517] Here, the semiconductor device described in the above embodiment can be used for the memory circuit 810. The memory circuit of one embodiment of the present invention can retain data even when power is cut off. Furthermore, the memory circuit of one embodiment of the present invention can be suitably used for an RF tag. The power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, It is also possible not to cause a difference in the maximum communication distance during reading and writing of the tag. Furthermore it is possible to suppress malfunction or incorrect writing due to insufficient power during data writing .

[0518] Also, the memory circuit according to one aspect of the present invention can be used as a non-volatile memory and thus can be applied to the ROM811. In that case, it is preferable for the producer to separately prepare a command for writing data into the ROM811 and prevent the user from freely rewriting it . By writing the unique number before shipment by the producer and then shipping the product , it becomes possible to assign unique numbers not to all the manufactured RF tags but only to the good products to be shipped , and customer management corresponding to the shipped products becomes easy without the unique numbers of the shipped products being discontinuous .

[0519] Note that this embodiment can be appropriately combined with other embodiments and examples shown in this specification .

[0520] (Embodiment 6) In this embodiment, a CPU including the memory device described in the previous embodiment will be described

[0521] FIG. 53 is a block diagram showing a configuration example of a CPU using at least a part of the transistors described in the previous embodiment .

[0522] <Circuit diagram of CPU> The CPU shown in FIG. 53 has an ALU1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, and an instruction tion decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1 198, rewritable ROM 1199, and ROM interface 1189 The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. 199 and the ROM interface 1189 may be provided on separate chips. The CPU shown in Figure 53 is merely an example of a simplified configuration. There are various configurations depending on the application. For example, the CPU or arithmetic circuit shown in Figure 53 A configuration including the above is considered as one core, and multiple cores are included, and each core operates in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is For example, it can be 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0523] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0524] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes register 1196 depending on the CPU state.

[0525] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal based on the reference clock signal. The internal clock generator supplies an internal clock signal to the various circuits.

[0526] In the CPU shown in FIG. 53, a memory cell is provided in the register 1196. The transistor described in Embodiment 1 can be used as the memory cell 1196. .

[0527] In the CPU shown in FIG. 53, the register controller 1197 receives the data from the ALU 1191. According to the instruction, the holding operation is selected in register 1196. In the memory cell of 96, data is held by a flip-flop or a capacitance Select whether to hold data by the element. When selected, the power supply voltage is applied to the memory cells in the register 1196. If data retention in the capacitor is selected, rewriting data to the capacitor This allows the supply of power supply voltage to the memory cells in the register 1196 to be stopped. .

[0528] <Memory circuit> FIG. 54 is an example of a circuit diagram of a storage element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized when the power is cut off, and a circuit 1202 in which stored data is volatilized when the power is cut off. A non-volatile circuit 1202, a switch 1203, a switch 1204, and a logic element The circuit includes a transistor 1206, a capacitor 1207, and a circuit 1220 having a selection function. 1202 includes a capacitor element 1208, a transistor 1209, a transistor 1210, The memory element 1200 may include a diode, a resistor, an inductor, etc., as needed. It may further include other elements such as a capacitor.

[0529] Here, the memory device described in the above embodiment can be used for the circuit 1202. When the supply of power supply voltage to the memory element 1200 is stopped, the transistor 120 The gate of the transistor 9 is supplied with a ground potential (0V) or a potential that turns off the transistor 1209. For example, the first gate of the transistor 1209 is connected to the load such as a resistor. The circuit is configured to be grounded.

[0530] The switch 1203 uses a transistor 1213 of one conductivity type (for example, n-channel type). The switch 1204 is configured as a transistor of a conductivity type opposite to the one conductivity type (for example, a p-channel type). An example using a transistor 1214 is shown. Here, the first terminal of the switch 1203 The input corresponds to one of the source and drain of the transistor 1213, and the second input of the switch 1203. The terminal of corresponds to the other of the source and drain of the transistor 1213, and the switch 1203 A control signal RD input to the gate of the transistor 1213 switches the first terminal and the second terminal Conduction or non-conduction between the terminals (i.e., the on or off state of transistor 1213) The first terminal of the switch 1204 is connected to the source and drain of the transistor 1214. The second terminal of the switch 1204 corresponds to one of the inputs, and the second terminal of the switch 1204 corresponds to the source of the transistor 1214. The other drain of the switch 1204 is connected to the gate of the transistor 1214. The control signal RD determines whether conduction or non-conduction (i.e., traction) occurs between the first and second terminals. The on or off state of transistor 1214 is selected.

[0531] One of the source and drain of the transistor 1209 is connected to the first terminal of the capacitor 1208 and and the gate of the transistor 1210. Here, the connection part is referred to as a node M. 2. One of the source and drain of the transistor 1210 is supplied with a low power supply potential. The other end is electrically connected to a wiring (for example, a GND line) that can be connected to the first terminal of the switch 1203. 1 (one of the source and drain of the transistor 1213). The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) is The first terminal of the switch 1204 (one of the source and drain of the transistor 1214) is electrically connected to the The second terminal of the switch 1204 (the source and drain of the transistor 1214) is connected to The other terminal of the switch is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the transistor 1203 (the other of the source and drain of the transistor 1213) and the a first terminal of the transistor 1204 (either the source or drain of the transistor 1214) and a logic element The input terminal of the capacitor 1206 and the first terminal of the capacitor 1207 are electrically connected. The connection point is referred to as a node M1. A constant potential is input to the second terminal of the capacitor 1207. For example, a low power supply potential (GND, etc.) or a high power supply potential ( VDD or the like) can be input to the second terminal of the capacitor 1207. It is electrically connected to a wiring (for example, a GND line) that can supply a power supply potential. The second terminal of the resistor 1208 can be configured to receive a constant potential. It can be configured so that a low power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) is input. The second terminal of the capacitor 1208 is connected to a wiring (for example, It is electrically connected to the ground line (e.g., GND line).

[0532] The capacitors 1207 and 1208 are used to reduce the parasitic capacitance of transistors and wirings. It is possible to omit it by actively using it.

[0533] A control signal WE is input to the first gate (first gate electrode) of the transistor 1209. The switches 1203 and 1204 are connected to a control signal RD, which is different from the control signal WE. A conductive state or a non-conductive state between the first terminal and the second terminal is selected by When the first terminal and the second terminal of one switch are in a conductive state, the first terminal and the second terminal of the other switch are in a conductive state. There is no conduction between terminals 2.

[0534] In the transistor 1209 in FIG. 54, the second gate electrode (second gate electrode: back The first gate receives a control signal WE, and the second gate receives a control signal WE. The control signal WE2 can be input to the output. The control signal WE2 is a signal with a constant potential. The constant potential may be, for example, the ground potential GND or the solenoid voltage of the transistor 1209. At this time, the control signal WE2 is set to a potential smaller than the source potential of the transistor. This is the potential signal for controlling the threshold voltage of 1209, and is the voltage when the gate voltage VG is 0V. The control signal WE2 is a potential signal having the same potential as the control signal WE. The transistor 1209 may be a transistor without a second gate. A star can also be used.

[0535] The other of the source and drain of the transistor 1209 is connected to a data line held in the circuit 1201. In FIG. 54, the signal output from the circuit 1201 is The example shown is input to the other of the source and drain of the switch 1203. The signal output from the second terminal (the other of the source and drain of the transistor 1213) is The logic value is inverted by the logic element 1206 to become an inverted signal, and is output via the circuit 1220. and input to the circuit 1201.

[0536] In FIG. 54, the second terminal of the switch 1203 (the source and drain of the transistor 1213) The signal output from the other of the two trains is routed through logic element 1206 and circuit 1220. The example shown is an input to the circuit 1201, but is not limited to this. The signal output from the other of the source and drain of the transistor 1213 is inverted. For example, the following may be included in the circuit 1201: When there is a node that holds a signal whose logical value is the inverse of the signal input from the input terminal The second terminal of the switch 1203 (the other of the source and drain of the transistor 1213) A signal output from the node can be input to the node.

[0537] In addition, in FIG. 54, among the transistors used in the memory element 1200, The transistors other than the transistor 1209 are formed by a layer or a substrate 119 made of a semiconductor other than an oxide semiconductor. For example, a transistor with a channel formed in a silicon layer or The transistor may have a channel formed in a silicon substrate. All transistors used in 1200 are transistors whose channels are formed of oxide semiconductors. Alternatively, the memory element 1200 may include other elements in addition to the transistor 1209. The other transistors may include a transistor in which the channel is formed of an oxide semiconductor. The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It may also be a transistor.

[0538] For example, a flip-flop circuit can be used for the circuit 1201 in FIG. The logic element 1206 may be, for example, an inverter or a clocked inverter. It is possible.

[0539] In the semiconductor device according to one embodiment of the present invention, while a power supply voltage is not supplied to the memory element 1200, The data stored in the circuit 1201 is transferred to the capacitor 120 provided in the circuit 1202. It can be held by 8.

[0540] In addition, a transistor in which a channel is formed in an oxide semiconductor has an extremely small off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is The off-state current is significantly lower than that of transistors whose channels are formed in silicon. By using this transistor as the transistor 1209, the memory element 120 The signal held in the capacitor 1208 is maintained for a long period of time even when power supply voltage is not supplied to the capacitor 1208. In this way, the storage element 1200 maintains its stored contents (data) even when the supply of power supply voltage is stopped. ) can be held.

[0541] Furthermore, by providing the switches 1203 and 1204, the precharge operation Since the memory element is characterized by performing the above operation, after the power supply voltage is restarted, the circuit 1201 This reduces the time required to restore the original data.

[0542] In the circuit 1202, the signal held by the capacitor 1208 is Therefore, the supply of the power supply voltage to the memory element 1200 is resumed. After that, the signal held by the capacitor element 1208 is transferred to the state ( The state can be converted to an ON state or an OFF state and read out from the circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates slightly, the original signal can be accurately read out.

[0543] Such a storage element 1200 may be used as a register or cache memory of a processor. By using it in a storage device, it is possible to prevent the loss of data in the storage device due to a power supply interruption. In addition, after the supply of power voltage is resumed, the state before the power supply was stopped can be restored in a short time. Therefore, the entire processor, or one or more components of the processor, can stop power supply for a short time in multiple logic circuits, reducing power consumption. It can be suppressed.

[0544] In this embodiment, the storage element 1200 is used as a CPU. 200 is equipped with a DSP (Digital Signal Processor), custom L LSIs such as SI and PLD (Programmable Logic Devices), R It can also be applied to F (Radio Frequency) tags.

[0545] This embodiment mode may be appropriately combined with other embodiment modes and examples shown in this specification. It is possible.

[0546] (Embodiment 7) In this embodiment, a structural example of a display device using a transistor according to one embodiment of the present invention will be described. explain.

[0547] <Display device circuit configuration example> FIG. 55A is a top view of a display device of one embodiment of the present invention, and FIG. 55B is a top view of a display device of one embodiment of the present invention. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display device of one embodiment will be described. 55C is a circuit diagram showing a pixel of a display device according to one embodiment of the present invention. 1 is a circuit diagram illustrating a pixel circuit that can be used when an organic EL element is applied. .

[0548] The transistor disposed in the pixel portion can be formed according to Embodiment 1. Since the transistor can be easily made into an n-channel type, the n-channel A part of the driver circuit can be configured with transistors of the same substrate as the transistors in the pixel section. In this way, the transistor described in the above embodiment is formed in the pixel portion or the driver circuit. By using this, a highly reliable display device can be provided.

[0549] An example of a top view of an active matrix display device is shown in Figure 55(A). On the display panel 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit 70 3, a signal line driver circuit 704. A plurality of signal lines are connected to the pixel portion 701 via the signal line driver circuit 704, and a plurality of scanning lines are connected to the first scanning line driving circuit 702 and the second scanning line driving circuit 703. The scanning lines are arranged in a direction extending from the scanning line driving circuit 703. In each of the display devices, pixels each having a display element are arranged in a matrix. The substrate 700 is a connection part such as an FPC (Flexible Printed Circuit). It is connected to a timing control circuit (also called a controller or control IC) via

[0550] In FIG. 55A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal line The driver circuit 704 is formed on the same substrate 700 as the pixel portion 701. This reduces the number of components, such as the drive circuit, that are required on the board 7, thereby reducing costs. If a driver circuit is provided outside the 00, the wiring must be extended, and the number of connections between the wiring increases. When a driver circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. This can improve reliability or yield. Any one of the circuit 702, the second scanning line driver circuit 703, and the signal line driver circuit 704 is mounted on the substrate 70. 0 or may be provided outside the substrate 700.

[0551] <Liquid crystal display device> An example of the circuit configuration of a pixel is shown in Figure 55(B). 1 shows a pixel circuit that can be applied to a pixel of a display device.

[0552] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels in a multi-domain design to The signals applied to the electrode layers can be controlled independently.

[0553] The scan line 712 of the transistor 716 and the scan line 713 of the transistor 717 have different On the other hand, the signal line 714 is separated so that a gate signal can be applied. The transistor 716 and the transistor 717 share the same The transistor described in Embodiment 1 can be used as appropriate for the transistor 717. This makes it possible to provide a highly reliable liquid crystal display device.

[0554] The transistor 716 is electrically connected to a first pixel electrode layer. The second pixel electrode layer is electrically connected to the first pixel electrode layer 17. The first pixel electrode layer and the second pixel electrode layer are separated from each other. For example, the first pixel electrode layer may be V-shaped.

[0555] The gate electrode of the transistor 716 is connected to the scanning line 712, and the gate electrode of the transistor 717 is connected to the scanning line 712. The gate electrode is connected to the scanning line 713. Different gate signals are applied to the scanning lines 712 and 713. By giving a signal to the transistor 716 and the transistor 717, the operation timing is made different. The orientation of the molecules can be controlled.

[0556] Also, the capacitor wiring 710, the gate insulating layer functioning as a dielectric, and the first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0557] In the multi-domain design, one pixel has a first liquid crystal element 718 and a second liquid crystal element 719. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. can be.

[0558] It should be noted that the pixel circuit shown in FIG. 55(B) is not limited to this. For example, The pixel circuit is newly equipped with switches, resistors, capacitors, transistors, sensors, or logic elements. Circuits etc. may be added.

[0559] 56(A) and 56(B) are an example of a top view and a cross-sectional view of a liquid crystal display device. In FIG. 56(A), the display device 20, the display area 21, the peripheral circuit 22, and the FPC ( A typical configuration having a flexible printed circuit board (FPC) 42 is shown. The display uses a reflective liquid crystal display.

[0560] In Figure 56(B), the dashed lines A-A', B-B', C-C', and DD in Figure 56(A) are shown. A-A' shows the peripheral circuit area, B-B' shows the display area, and C The area between -C' indicates the connection with the FPC.

[0561] The display device 20 using the liquid crystal element includes a transistor 50 and a transistor 52 (in the embodiment). In addition to the transistor 10 shown in Embodiment 1, a conductive layer 165, a conductive layer 197, an insulating layer 420, a liquid crystal layer crystal layer 490, liquid crystal element 80, capacitive element 60, capacitive element 62, insulating layer 430, spacer 44 0, colored layer 460, adhesive layer 470, conductive layer 480, light shielding layer 418, substrate 400, adhesive layer 4 73, adhesive layer 474, adhesive layer 475, adhesive layer 476, polarizing plate 103, polarizing plate 403, protection It has a substrate 105 , a protective substrate 402 , and an anisotropic conductive layer 510 .

[0562] <Organic EL display device> Another example of the circuit configuration of a pixel is shown in Figure 55(C). 1 shows the pixel structure of the device.

[0563] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are released from one of the pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. The recombination of electrons and holes causes the light-emitting organic compound to form an excited state, which This mechanism is what causes this type of luminescence. The element is called a current-excited light-emitting element.

[0564] FIG. 55(C) is a diagram showing an example of an applicable pixel circuit. This example shows how two transistors are used in one pixel. Adjustable driving can be applied.

[0565] Regarding the configuration of applicable pixel circuits and pixel operation when digital time gray scale driving is applied, and explain.

[0566] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light-emitting element The switching transistor 721 has a gate electrode 724 and a capacitor element 723. The source electrode layer is connected to the scanning line 726, and the first electrode (the source electrode layer and the drain electrode layer) The second electrode (the other of the source electrode layer and the drain electrode layer) is co...

Claims

[Claim 1] forming a first insulating layer on a substrate; forming a stack of a first metal oxide layer and a first oxide semiconductor layer on the first insulating layer; a first mask is used to etch the stack of the first metal oxide layer and the first oxide semiconductor layer into an island shape to form a second metal oxide layer and a second oxide semiconductor layer; forming a third metal oxide layer on the second oxide semiconductor layer and the first insulating layer; forming a second insulating layer on the third metal oxide layer; performing a planarization process on the second insulating layer to form a third insulating layer; forming a fourth insulating layer having a groove portion that reaches the third metal oxide layer by etching a portion of the third insulating layer using a second mask; forming a fifth insulating layer on the fourth insulating layer and the third metal oxide layer; forming a first conductive layer on the fifth insulating layer; performing a planarization process on the first conductive layer and the fifth insulating layer until the fourth insulating layer is exposed, thereby forming a gate electrode layer and a sixth insulating layer; forming a gate insulating layer by etching the fourth insulating layer and the sixth insulating layer using the gate electrode layer as a mask; a source region and a drain region are formed by adding ions to the second oxide semiconductor layer using the gate electrode layer as a mask.

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