Method for driving semiconductor device

Abstract

To provide a method for driving a semiconductor device that enables reduction of switching loss.SOLUTION: There is provided a method for driving a semiconductor device according to an embodiment, the semiconductor device that includes a first trench, a first gate electrode provided in the first trench, a second trench, a second gate electrode provided in the second trench, a third trench, a third gate electrode provided in the third trench, a first electrode pad electrically connected to the first gate electrode, a second electrode pad electrically connected to the second gate electrode, and a third electrode pad electrically connected to the third gate electrode. The second gate electrode and the third gate electrode are controlled with turn-off voltages having different magnitudes.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a method for driving a semiconductor device. [Background technology]

[0002] An example of a power semiconductor device is an insulated gate bipolar transistor (IGBT). An IGBT has, for example, a p-type collector region, an n-type drift region, and a p-type base region provided on a collector electrode. A gate electrode is provided in a trench that penetrates the p-type base region and reaches the n-type drift region, with a gate insulating film sandwiched between them. Furthermore, an n-type emitter region connected to an emitter electrode is provided in a region adjacent to the trench on the surface of the p-type base region.

[0003] In IGBTs, it is expected to reduce switching losses. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-161786 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a method for driving a semiconductor device that enables a reduction in switching loss. [Means for solving the problem]

[0006] A method for driving a semiconductor device according to an embodiment includes: a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface; a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface; a first trench provided on the side of the first surface in the conductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first gate electrode provided in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench, a second gate electrode provided in the second trench, second gate insulating films provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; at least one third trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode provided in the at least one third trench; a third gate insulating film provided between the electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region; a first electrode provided on the first surface side of the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side of the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate electrode;a second electrode pad electrically connected to the second gate electrode, and a third electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate electrode, the semiconductor layer including a first transistor having the first gate electrode, a second transistor having the second gate electrode, and a third transistor having the third gate electrode, wherein a threshold voltage of the third transistor is lower than a threshold voltage of the first transistor, and a threshold voltage of the third transistor is lower than a threshold voltage of the second transistor, wherein the second gate electrode and the third gate electrode are controlled by turn-off voltages of different magnitudes; [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic diagram of a semiconductor circuit according to a first embodiment. [Figure 2] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is a schematic top view of a part of the semiconductor device according to the first embodiment. [Figure 4] FIG. 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 5] FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Figure 6] FIG. 2 is an explanatory diagram of a method for driving the semiconductor device according to the first embodiment. [Figure 7] FIG. 4 is an enlarged schematic cross-sectional view of a part of a semiconductor device according to a modified example of the first embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a second embodiment. [Figure 9] FIG. 6 is an enlarged schematic cross-sectional view of a portion of a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a third embodiment. [Figure 11] FIG. 10 is an enlarged schematic cross-sectional view of a portion of a semiconductor device according to a third embodiment. [Figure 12]FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 10 is an enlarged schematic cross-sectional view of a part of a semiconductor device according to a fourth embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a fifth embodiment. [Figure 15] FIG. 10 is a schematic top view of a part of a semiconductor device according to a fifth embodiment. [Figure 16] FIG. 10 is a schematic cross-sectional view of a part of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0009] In this specification, n + shape, n shape, n - When there is a notation with form, n + shape, n shape, n - This means that the n-type impurity concentration decreases in the order of the p + shape, p shape, p - If there is a form notation, p + shape, p shape, p - This means that the p-type impurity concentration decreases in the order of n + shape, n shape, n - The two types are sometimes simply referred to as n-type. + shape, p shape, p - The shape is sometimes collectively referred to simply as p-shape.

[0010] In this specification, the n-type impurity concentration does not refer to the actual n-type impurity concentration, but refers to the effective n-type impurity concentration after compensation. Similarly, the p-type impurity concentration does not refer to the actual p-type impurity concentration, but refers to the effective p-type impurity concentration after compensation. For example, if the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the concentration obtained by subtracting the p-type impurity concentration from the actual n-type impurity concentration is taken as the n-type impurity concentration. The same applies to the p-type impurity concentration.

[0011] In this specification, the distribution and absolute value of the impurity concentration in a semiconductor region can be measured using, for example, secondary ion mass spectrometry (SIMS). The relative magnitude relationship between the impurity concentrations in two semiconductor regions can be determined using, for example, scanning capacitance microscopy (SCM). The distribution and absolute value of the impurity concentration can be measured using, for example, spreading resistance analysis (SRA). SCM and SRA can determine the relative magnitude relationship and absolute value of the carrier concentration in a semiconductor region. By assuming the activation rate of the impurities, the relative magnitude relationship between the impurity concentrations in two semiconductor regions, the distribution of the impurity concentrations, and the absolute value of the impurity concentrations can be determined from the measurement results of SCM and SRA.

[0012] In this specification, a transistor portion in a semiconductor device that is driven using a first gate electrode may be referred to as a "first transistor having a first gate electrode." Similarly, a transistor portion that is driven using a second gate electrode may be referred to as a "second transistor having a second gate electrode," and a transistor portion that is driven using a third gate electrode may be referred to as a "third transistor having a third gate electrode."

[0013] (First embodiment) The semiconductor device of the first embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of a first conductivity type provided in the semiconductor layer, a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface, a third semiconductor region of the first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface, a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface, and a fourth semiconductor region of the second conductivity type provided on the side of the first surface in the semiconductor layer. a first trench in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first gate electrode provided in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a second gate electrode provided in the second trench; a second gate insulating film provided between the electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; at least one third trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode provided in the at least one third trench; and a third gate electrode provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region. a third gate insulating film provided therebetween; a first electrode provided on the first surface side of the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side of the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate electrode; and a third electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate electrode.The third semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with at least one third trench, and the thickness of the third portion in the direction from the first surface toward the second surface is thinner than the thickness of the first portion, and the thickness of the third portion in the direction from the first surface toward the second surface is thinner than the thickness of the second portion.

[0014] The semiconductor circuit of the first embodiment includes a control circuit that drives the semiconductor device.

[0015] The semiconductor device of the first embodiment is an IGBT 100. The IGBT 100 is a trench-gate IGBT having a gate electrode in a trench formed in a semiconductor layer. Hereinafter, an example will be described in which the first conductivity type is p-type and the second conductivity type is n-type.

[0016] The control circuit of the first embodiment is a gate driver circuit 150. The semiconductor circuit of the first embodiment is composed of a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor module in which the IGBT 100 and the gate driver circuit 150 are mounted.

[0017] FIG. 1 is a schematic diagram of a semiconductor circuit according to the first embodiment.

[0018] 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment, taken along the line AA' in FIG.

[0019] Fig. 3 is a schematic top view of a part of the semiconductor device of the first embodiment, Fig. 3 is a top view on the first face F1, Fig. 2 is a cross section taken along line AA' in Fig. 3.

[0020] 4 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment, taken along the line BB' in FIG.

[0021] The semiconductor circuit of the first embodiment includes an IGBT 100 and a gate driver circuit 150. The IGBT 100 includes a transistor region 101. The transistor region 101 includes a plurality of transistors that operate at different timings.

[0022] The IGBT 100 is an example of a semiconductor device, and the gate driver circuit 150 is an example of a control circuit.

[0023] The IGBT 100 of the first embodiment includes a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a first gate insulating film 41, a second gate insulating film 42, a third gate insulating film 43, a first gate electrode 51, a second gate electrode 52, a third gate electrode 53, an interlayer insulating layer 61, a first gate electrode pad 104 (first electrode pad), a second gate electrode pad 105 (second electrode pad), and a third gate electrode pad 106 (third electrode pad).

[0024] Within the semiconductor layer 10, a first gate trench 21 (first trench), a second gate trench 22 (second trench), a third gate trench 23 (third trench), a collector region 26 (first semiconductor region), a drift region 27 (second semiconductor region), a base region 28 (third semiconductor region), an emitter region 29 (fourth semiconductor region), a contact region 30, and a barrier region 31 (fifth semiconductor region) are provided.

[0025] The base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c. The barrier region 31 includes a fourth portion 31a, a fifth portion 31b, and a sixth portion 31c.

[0026] The semiconductor layer 10 has a first face F1 and a second face F2 facing the first face F1. The semiconductor layer 10 is, for example, single crystal silicon. The thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0027] In this specification, a direction parallel to the first surface F1 is referred to as a "first direction." A direction parallel to the first surface F1 and perpendicular to the first direction is referred to as a "second direction." A direction from the first surface F1 toward the second surface F2 is referred to as a "third direction."

[0028] In addition, in this specification, the "depth" is defined as the distance from the first surface F1 toward the second surface F2.

[0029] The emitter electrode 12 is provided on the first face F1 side of the semiconductor layer 10. At least a portion of the emitter electrode 12 contacts the first face F1 of the semiconductor layer 10. The emitter electrode 12 is made of, for example, a metal.

[0030] The emitter electrode 12 is in contact with the emitter region 29. The emitter electrode 12 is electrically connected to the emitter region 29.

[0031] The emitter electrode 12 is in contact with the contact region 30. The emitter electrode 12 is electrically connected to the contact region 30. The emitter electrode 12 is electrically connected to the base region 28 via the contact region 30.

[0032] The collector electrode 14 is provided on the second face F2 side of the semiconductor layer 10. At least a portion of the collector electrode 14 contacts the second face F2 of the semiconductor layer 10. The collector electrode 14 is made of, for example, a metal.

[0033] The collector electrode 14 is in contact with the collector region 26. The collector electrode 14 is electrically connected to the collector region 26.

[0034] The collector region 26 is p + The collector region 26 is a semiconductor region having a shape similar to that of the first face F1. The collector region 26 is in contact with the second face F2. The collector region 26 is electrically connected to the collector electrode 14. The collector region 26 is in contact with the collector electrode 14. The collector region 26 serves as a source of holes when the IGBT 100 is in the on state.

[0035] The drift region 27 is -The drift region 27 is provided between the collector region 26 and the first face F1.

[0036] The drift region 27 serves as a path for an on-current when the IGBT 100 is in an on-state. The drift region 27 is depleted when the IGBT 100 is in an off-state, and has the function of maintaining the breakdown voltage of the IGBT 100.

[0037] The base region 28 is a p-type semiconductor region. The base region 28 is provided between the drift region 27 and the first face F1. The drift region 27 is sandwiched between the base region 28 and the collector region 26.

[0038] The depth of the base region 28 is, for example, 5 μm or less. When the IGBT 100 is in the on state, an n-type inversion layer is formed in the region of the base region 28 facing the first gate electrode 51, the region of the base region 28 facing the second gate electrode 52, and the region of the base region 28 facing the third gate electrode 53. The base region 28 functions as a channel region of the transistor.

[0039] The barrier region 31 is an n-type semiconductor region. The barrier region 31 is provided between the drift region 27 and the base region 28. The n-type impurity concentration of the barrier region 31 is higher than the n-type impurity concentration of the drift region 27.

[0040] The barrier region 31 has a function of increasing the amount of carrier accumulation in the drift region 27 when the IGBT 100 is in the on state. By providing the barrier region 31, the on-resistance of the IGBT 100 is reduced, and the steady-state loss of the IGBT 100 is reduced.

[0041] The emitter region 29 is n + The emitter region 29 is provided between the base region 28 and the first face F1.

[0042] The emitter region 29 is in contact with the first gate insulating film 41, the second gate insulating film 42, and the third gate insulating film 43.

[0043] The n-type impurity concentration of the emitter region 29 is higher than the n-type impurity concentration of the drift region 27 .

[0044] The emitter region 29 is in contact with the emitter electrode 12. The emitter region 29 is electrically connected to the emitter electrode 12. The emitter region 29 serves as a supply source of electrons when the IGBT 100 is in the on state.

[0045] The contact region 30 is p + The contact region 30 is a semiconductor region having a shape similar to that of the base region 28. The contact region 30 is provided between the base region 28 and the first face F1. The contact region 30 is in contact with the emitter electrode 12. The contact region 30 is electrically connected to the emitter electrode 12.

[0046] The p-type impurity concentration of the contact region 30 is higher than the p-type impurity concentration of the base region 28 .

[0047] The first gate trench 21 is provided on the first face F1 side of the semiconductor layer 10. The first gate trench 21 is a groove provided in the semiconductor layer 10. The first gate trench 21 is a part of the semiconductor layer 10.

[0048] 3, the first gate trench 21 extends in a first direction parallel to the first face F1 on the first face F1. The first gate trench 21 has a stripe shape. A plurality of the first gate trenches 21 are repeatedly arranged in a second direction perpendicular to the first direction.

[0049] The first gate trench 21 contacts the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The first gate trench 21 penetrates the base region 28 and reaches the drift region 27. The depth of the first gate trench 21 is, for example, 8 μm or less.

[0050] The first gate electrode 51 is provided in the first gate trench 21. The first gate electrode 51 is, for example, a semiconductor or a metal. The first gate electrode 51 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The first gate electrode 51 is electrically connected to the first gate electrode pad 104.

[0051] The first gate insulating film 41 is provided between the first gate electrode 51 and the semiconductor layer 10. The first gate insulating film 41 is provided between the first gate electrode 51 and the drift region 27, between the first gate electrode 51 and the base region 28, between the first gate electrode 51 and the emitter region 29, and between the first gate electrode 51 and the barrier region 31. The first gate insulating film 41 is in contact with the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The first gate insulating film 41 is made of, for example, silicon oxide.

[0052] The second gate trench 22 is provided on the first face F1 side of the semiconductor layer 10. The second gate trench 22 is a groove provided in the semiconductor layer 10. The second gate trench 22 is a part of the semiconductor layer 10.

[0053] 3, the second gate trenches 22 extend in a first direction parallel to the first face F1 on the first face F1. The second gate trenches 22 have a stripe shape. The second gate trenches 22 are repeatedly arranged in a second direction perpendicular to the first direction.

[0054] The second gate trench 22 contacts the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The second gate trench 22 penetrates the base region 28 and reaches the drift region 27. The depth of the second gate trench 22 is, for example, 8 μm or less.

[0055] The second gate electrode 52 is provided in the second gate trench 22. The second gate electrode 52 is, for example, a semiconductor or a metal. The second gate electrode 52 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The second gate electrode 52 is electrically connected to the second gate electrode pad 105.

[0056] The second gate insulating film 42 is provided between the second gate electrode 52 and the semiconductor layer 10. The second gate insulating film 42 is provided between the second gate electrode 52 and the drift region 27, between the second gate electrode 52 and the base region 28, between the second gate electrode 52 and the emitter region 29, and between the second gate electrode 52 and the barrier region 31. The second gate insulating film 42 is in contact with the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The second gate insulating film 42 is made of, for example, silicon oxide.

[0057] The third gate trench 23 is provided on the first face F1 side of the semiconductor layer 10. The third gate trench 23 is a groove provided in the semiconductor layer 10. The third gate trench 23 is a part of the semiconductor layer 10.

[0058] 3, the third gate trench 23 extends in a first direction parallel to the first face F1 on the first face F1. The third gate trench 23 has a stripe shape. A plurality of the third gate trenches 23 are repeatedly arranged in a second direction perpendicular to the first direction.

[0059] The third gate trench 23 contacts the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The third gate trench 23 penetrates the base region 28 and reaches the drift region 27. The depth of the third gate trench 23 is, for example, 8 μm or less.

[0060] The third gate electrode 53 is provided in the third gate trench 23. The third gate electrode 53 is, for example, a semiconductor or a metal. The third gate electrode 53 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The third gate electrode 53 is electrically connected to the third gate electrode pad 106.

[0061] The third gate insulating film 43 is provided between the third gate electrode 53 and the semiconductor layer 10. The third gate insulating film 43 is provided between the third gate electrode 53 and the drift region 27, between the third gate electrode 53 and the base region 28, between the third gate electrode 53 and the emitter region 29, and between the third gate electrode 53 and the barrier region 31. The third gate insulating film 43 is in contact with the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The third gate insulating film 43 is made of, for example, silicon oxide.

[0062] The interlayer insulating layer 61 is provided between the first gate electrode 51 and the emitter electrode 12. The interlayer insulating layer 61 electrically separates the first gate electrode 51 from the emitter electrode 12. The interlayer insulating layer 61 is provided between the second gate electrode 52 and the emitter electrode 12.

[0063] The interlayer insulating layer 61 electrically isolates the second gate electrode 52 from the emitter electrode 12. The interlayer insulating layer 61 is provided between the third gate electrode 53 and the emitter electrode 12. The interlayer insulating layer 61 electrically isolates the third gate electrode 53 from the emitter electrode 12. The interlayer insulating layer 61 is made of, for example, silicon oxide.

[0064] The first gate electrode pad 104 is provided on the first face F1 side of the semiconductor layer 10. The first gate electrode pad 104 is electrically connected to the first gate electrode 51. The first gate electrode pad 104 and the first gate electrode 51 are connected by, for example, a metal wiring (not shown).

[0065] To the first gate electrode pad 104, a first gate voltage (Vg1) is applied. To the first gate electrode pad 104, for example, a first turn-on voltage (Von1) and a first turn-off voltage (Voff1) are applied.

[0066] The second gate electrode pad 105 is provided on the first face F1 side of the semiconductor layer 10. The second gate electrode pad 105 is electrically connected to the second gate electrode 52. The second gate electrode pad 105 and the second gate electrode 52 are connected by, for example, a metal wiring (not shown).

[0067] A second gate voltage (Vg2) is applied to the second gate electrode pad 105. To the second gate electrode pad 105, for example, a second turn-on voltage (Von2) and a second turn-off voltage (Voff2) are applied.

[0068] The third gate electrode pad 106 is provided on the first face F1 side of the semiconductor layer 10. The third gate electrode pad 106 is electrically connected to the third gate electrode 53. The third gate electrode pad 106 and the third gate electrode 53 are connected by, for example, a metal wiring (not shown).

[0069] A third gate voltage (Vg3) is applied to the third gate electrode pad 106. To the third gate electrode pad 106, for example, a third turn-on voltage (Von3) and a third turn-off voltage (Voff3) are applied.

[0070] The gate driver circuit 150 is provided, for example, on the same circuit board as the RC-IGBT 100 or on a different circuit board. The gate driver circuit 150 has a function of driving the IGBT 100.

[0071] The gate driver circuit 150 has a function of applying a desired first gate voltage (Vg1), a desired second gate voltage (Vg2), and a desired third gate voltage (Vg3) to the first gate electrode pad 104, the second gate electrode pad 105, and the third gate electrode pad 106 at a desired timing.

[0072] The gate driver circuit 150 applies a first turn-on voltage (Von1) to the first gate electrode pad 104, a second turn-on voltage (Von2) to the second gate electrode pad 105, and a third turn-on voltage (Von3) to the third gate electrode pad 106. After applying a turn-on voltage (Von3), a third turn-off voltage (Voff3) is applied to the third gate electrode pad 106, after applying the third turn-off voltage (Voff3) to the third gate electrode pad 106, a second turn-off voltage (Voff2) is applied to the second gate electrode pad 105, after applying the second turn-off voltage (Voff2) to the second gate electrode pad 105, a first turn-off voltage (Voff1) is applied to the first gate electrode pad 104.

[0073] 5 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the first embodiment, and is an enlarged view of a part of FIG.

[0074] As shown in FIG. 5, the base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c.

[0075] The first portion 28a is a portion of the base region 28 that contacts the first gate trench 21. The first portion 28a contacts the first gate insulating film 41. The first portion 28a faces the first gate electrode 51.

[0076] The first portion 28a functions as a channel region of a first transistor having a first gate electrode 51, a first gate insulating film 41, and the first portion 28a. The first transistor is driven by a first gate voltage (Vg1) applied to the first gate electrode 51.

[0077] The second portion 28b is a portion of the base region 28 that contacts the second gate trench 22. The second portion 28b contacts the second gate insulating film 42. The second portion 28b faces the second gate electrode 52.

[0078] The second portion 28b functions as a channel region of a second transistor having a second gate electrode 52, a second gate insulating film 42, and the second portion 28b. The second transistor is driven by a second gate voltage (Vg2) applied to the second gate electrode 52.

[0079] The third portion 28c is a portion of the base region 28 that contacts the third gate trench 23. The third portion 28c contacts the third gate insulating film 43. The third portion 28c faces the third gate electrode 53.

[0080] The third portion 28c functions as a channel region of a third transistor having a third gate electrode 53, a third gate insulating film 43, and the third portion 28c. The third transistor is a transistor driven by a third gate voltage (Vg3) applied to the third gate electrode 53.

[0081] The thickness in the third direction of third portion 28c (t3 in FIG. 5) is thinner than the thickness in the third direction of first portion 28a (t1 in FIG. 5). The thickness in the third direction of third portion 28c (t3) is, for example, 20% to 70% of the thickness in the third direction of first portion 28a (t1).

[0082] The thickness in the third direction of third portion 28c (t3 in FIG. 5) is thinner than the thickness in the third direction of second portion 28b (t2 in FIG. 5). The thickness in the third direction of third portion 28c (t3) is, for example, 20% to 70% of the thickness in the third direction of second portion 28b (t2).

[0083] As shown in FIG. 5, the barrier region 31 includes a fourth portion 31a, a fifth portion 31b, and a sixth portion 31c.

[0084] The fourth portion 31a is a portion of the barrier region 31 that contacts the first gate trench 21. The fourth portion 31a contacts the first gate insulating film 41. The fourth portion 31a faces the first gate electrode 51. The fourth portion 31a is provided between the drift region 27 and the first portion 28a.

[0085] The fifth portion 31b is a portion of the barrier region 31 that contacts the second gate trench 22. The fifth portion 31b contacts the second gate insulating film 42. The fifth portion 31b faces the second gate electrode 52. The fifth portion 31b is provided between the drift region 27 and the second portion 28b.

[0086] The sixth portion 31c is a portion of the barrier region 31 that contacts the third gate trench 23. The sixth portion 31c contacts the third gate insulating film 43. The sixth portion 31c faces the third gate electrode 53. The sixth portion 31c is provided between the drift region 27 and the third portion 28c.

[0087] The thickness in the third direction of the sixth portion 31c (t6 in FIG. 5) is thicker than the thickness in the third direction of the fourth portion 31a (t4 in FIG. 5). The thickness in the third direction of the sixth portion 31c (t6) is, for example, 150% or more of the thickness in the third direction of the fourth portion 31a (t4).

[0088] The thickness of the sixth portion 31c in the third direction (t6 in FIG. 5) is greater than the thickness of the fifth portion 31b in the third direction (t5 in FIG. 5). The thickness t6 of the sixth portion 31c in the third direction is, for example, 150% or more of the thickness t5 of the fifth portion 31b in the third direction.

[0089] Next, an example of a method for driving the IGBT 100 will be described.

[0090] 6 is an explanatory diagram of a method for driving the semiconductor device of the first embodiment. Fig. 6 is a timing chart of a first gate voltage (Vg1) applied to the first gate electrode pad 104, a second gate voltage (Vg2) applied to the second gate electrode pad 105, and a third gate voltage (Vg3) applied to the third gate electrode pad 106.

[0091] When the IGBT 100 is in an off state, for example, an emitter voltage is applied to the emitter electrode 12. The emitter voltage is, for example, 0 V. A collector voltage is applied to the collector electrode 14. The collector voltage is, for example, 200 V or more and 6500 V or less.

[0092] When the IGBT 100 is in the off state, a first turn-off voltage (Voff1) is applied to the first gate electrode pad 104. The first gate voltage (Vg1) becomes the first turn-off voltage (Voff1). Therefore, the first turn-off voltage (Voff1) is also applied to the first gate electrode 51.

[0093] The first turn-off voltage (Voff1) is a voltage below the threshold voltage at which the first transistor having the first gate electrode 51 does not turn on, and is, for example, 0 V or a negative voltage.

[0094] In the off state, no n-type inversion layer is formed in the base region 28 that faces the first gate electrode 51 and is in contact with the first gate insulating film 41.

[0095] When the IGBT 100 is in the off state, a second turn-off voltage (Voff2) is applied to the second gate electrode pad 105. The second gate voltage (Vg2) becomes the second turn-off voltage (Voff2). Therefore, the second turn-off voltage (Voff2) is also applied to the second gate electrode 52.

[0096] The second turn-off voltage (Voff2) is a voltage below the threshold voltage at which the second transistor having the second gate electrode 52 does not turn on, and is, for example, 0 V or a negative voltage.

[0097] In the off state, no n-type inversion layer is formed in the base region 28 that faces the second gate electrode 52 and is in contact with the second gate insulating film 42.

[0098] When the IGBT 100 is in the off state, a third turn-off voltage (Voff3) is applied to the third gate electrode pad 106. The third gate voltage (Vg3) becomes the third turn-off voltage (Voff3). Therefore, the third turn-off voltage (Voff3) is also applied to the third gate electrode 53.

[0099] The third turn-off voltage (Voff3) is a voltage below the threshold voltage at which the third transistor having the third gate electrode 53 does not turn on, and is, for example, 0V.

[0100] In the off state, no n-type inversion layer is formed in the base region 28 that faces the third gate electrode 53 and is in contact with the third gate insulating film 43.

[0101] At time T1, a first turn-on voltage (Von1) is applied to the first gate electrode pad 104. The first gate voltage (Vg1) becomes the first turn-on voltage (Von1). The first turn-on voltage (Von1) is also applied to the first gate electrode 51.

[0102] The first turn-on voltage (Von1) is a positive voltage that exceeds the threshold voltage of the first transistor having the first gate electrode 51. The first turn-on voltage (Von1) is, for example, 15 V. When the first turn-on voltage (Von1) is applied to the first gate electrode 51, the first transistor having the first gate electrode 51 is turned on.

[0103] In the on-state, an n-type inversion layer is formed in the base region 28 that faces the first gate electrode 51 and is in contact with the first gate insulating film 41.

[0104] At time T1, a second turn-on voltage (Von2) is applied to the second gate electrode pad 105. The second gate voltage (Vg2) becomes the second turn-on voltage (Von2). The second turn-on voltage (Von2) is also applied to the second gate electrode 52.

[0105] The second turn-on voltage (Von2) is a positive voltage that exceeds the threshold voltage of the second transistor having the second gate electrode 52. The second turn-on voltage (Von2) is, for example, 15 V. Application of the second turn-on voltage (Von2) to the second gate electrode 52 turns the second transistor having the second gate electrode 52 into an on state.

[0106] In the on-state, an n-type inversion layer is formed in the base region 28 that faces the second gate electrode 52 and is in contact with the second gate insulating film 42.

[0107] At time T1, a third turn-on voltage (Von3) is applied to the third gate electrode pad 106. The third gate voltage (Vg3) becomes the third turn-on voltage (Von3). The third turn-on voltage (Von3) is also applied to the third gate electrode 53.

[0108] The third turn-on voltage (Von3) is a positive voltage that exceeds the threshold voltage of the third transistor having the third gate electrode 53. The third turn-on voltage (Von3) is, for example, 15 V. When the third turn-on voltage (Von3) is applied to the third gate electrode 53, the third transistor having the third gate electrode 53 is turned on.

[0109] In the on-state, an n-type inversion layer is formed in the base region 28 that faces the third gate electrode 53 and is in contact with the third gate insulating film 43 .

[0110] After time T1, the IGBT 100 is turned on.

[0111] At time T2, a third turn-off voltage (Voff3) is applied to the third gate electrode pad 106. The third gate voltage (Vg3) becomes the third turn-off voltage (Voff3). The third turn-off voltage (Voff3) is also applied to the third gate electrode 53.

[0112] By applying a third turn-off voltage (Voff3) to the third gate electrode 53, the third transistor having the third gate electrode 53 is turned off.

[0113] At time T3, the second turn-off voltage (Voff2) is applied to the second gate electrode pad 105. The second gate voltage (Vg2) becomes the second turn-off voltage (Voff2). The second turn-off voltage (Voff2) is also applied to the second gate electrode 52.

[0114] Application of a second turn-off voltage (Voff2) to the second gate electrode 52 turns the second transistor having the second gate electrode 52 into an off state.

[0115] For example, when the second turn-off voltage (Voff2) is a negative voltage, a p-type inversion layer is formed in the drift region 27 in contact with the second gate insulating film 42. The second turn-off voltage (Voff2) is, for example, −15V or more and less than 0V.

[0116] At time T4, the first turn-off voltage (Voff1) is applied to the first gate electrode pad 104. The first gate voltage (Vg1) becomes the first turn-off voltage (Voff1). The first turn-off voltage (Voff1) is also applied to the first gate electrode 51.

[0117] By applying a first turn-off voltage (Voff1) to the first gate electrode 51, the first transistor having the first gate electrode 51 is turned off.

[0118] After time T4, the first transistor having the first gate electrode 51, the second transistor having the second gate electrode 52, and the third transistor having the third gate electrode 53 are all turned off.

[0119] Next, the operation and effects of the semiconductor device and semiconductor circuit of the first embodiment will be described.

[0120] The IGBT 100 of the first embodiment includes a transistor region 101 including a first transistor having a first gate electrode 51, a second transistor having a second gate electrode 52, and a third transistor having a third gate electrode 53. Each transistor can be driven independently. This configuration reduces turn-on loss and turn-off loss of the IGBT 100.

[0121] At time T1, the first transistor having the first gate electrode 51, the second transistor having the second gate electrode 52, and the third transistor having the third gate electrode 53 are all turned on. When the first transistor having the first gate electrode 51, the second transistor having the second gate electrode 52, and the third transistor having the third gate electrode 53 are all turned on, electrons are injected from the emitter region 29 into the drift region 27 in the transistor region 101. Correspondingly, holes are injected from the collector region 26 into the drift region 27.

[0122] For example, compared to a case where the third transistor having the third gate electrode 53 is not provided, the amount of electrons injected from the emitter region 29 to the drift region 27 increases. Therefore, the turn-on time of the IGBT 100 can be shortened. Therefore, the turn-on loss of the IGBT 100 is reduced.

[0123] At time T2, the third transistor having the third gate electrode 53 is turned off. At time T2, the third transistor having the third gate electrode 53 stops injecting electrons into the drift region 27. After time T2, the third transistor having the third gate electrode 53 functions as a dummy gate.

[0124] By stopping the injection of electrons into the drift region 27 by the third transistor having the third gate electrode 53, the carrier density on the emitter region 29 side of the drift region 27 decreases. This reduces the saturation current of the IGBT 100. This improves, for example, the short-circuit resistance of the IGBT 100.

[0125] At time T3, the second transistor having the second gate electrode 52 is turned off. Then, at time T4, the first transistor having the first gate electrode 51 is turned off. At time T4, the IGBT 100 is turned off.

[0126] At time T3, the second transistor having the second gate electrode 52 is turned off, thereby reducing the carrier density in the drift region 27. Therefore, the amount of carriers to be discharged after the first transistor having the first gate electrode 51 is turned off is reduced.

[0127] This reduces the turn-off time of the IGBT 100, thereby reducing the turn-off loss of the IGBT 100.

[0128] In particular, when the second turn-off voltage (Voff2) applied to the second gate electrode 52 is a negative voltage, a p-type inversion layer is formed in the drift region 27 in contact with the second gate insulating film 42. Therefore, the discharge of holes from the drift region 27 to the emitter electrode 12 is promoted until time T4, and the amount of carriers to be discharged after the first transistor having the first gate electrode 51 is turned off is further reduced. This further reduces the turn-off loss of the IGBT 100.

[0129] In the IGBT 100 of the first embodiment, the thickness in the third direction of the third portion 28c of the base region 28 (t3 in FIG. 5) is thinner than the thickness in the third direction of the first portion 28a (t1 in FIG. 5). Therefore, the channel length of the third transistor having the third gate electrode 53 is shorter than the channel length of the first transistor having the first gate electrode 51. Therefore, the threshold voltage of the third transistor having the third gate electrode 53 is lower than the threshold voltage of the first transistor having the first gate electrode 51 due to the short channel effect.

[0130] Furthermore, in the IGBT 100 of the first embodiment, the thickness in the third direction of the third portion 28c of the base region 28 (t3 in FIG. 5) is thinner than the thickness in the third direction of the second portion 28b (t2 in FIG. 5). Therefore, the channel length of the third transistor having the third gate electrode 53 is shorter than the channel length of the second transistor having the second gate electrode 52. Therefore, the threshold voltage of the second transistor having the second gate electrode 52 is lower than the threshold voltage of the second transistor having the second gate electrode 52 due to the short channel effect.

[0131] The threshold voltage of the third transistor having the third gate electrode 53 is lower than the threshold voltage of the first transistor having the first gate electrode 51 and the threshold voltage of the second transistor having the second gate electrode 52. Therefore, for example, when a turn-on voltage is applied to the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53 simultaneously at time T1, the third transistor having the third gate electrode 53 starts to turn on quickly. This quickly increases the amount of electrons injected into the drift region 27. This further shortens the turn-on time of the IGBT 100. This further reduces the turn-on loss of the IGBT 100.

[0132] From the viewpoint of lowering the threshold voltage of the third transistor having the third gate electrode 53, the thickness t3 in the third direction of the third portion 28c is preferably 70% or less, and more preferably 50% or less, of the thickness t1 in the third direction of the first portion 28a. From the viewpoint of lowering the threshold voltage of the third transistor having the third gate electrode 53, the thickness t3 in the third direction of the third portion 28c is preferably 70% or less, and more preferably 50% or less, of the thickness t2 in the third direction of the second portion 28b.

[0133] (Variation) Fig. 7 is an enlarged schematic cross-sectional view of a part of a semiconductor device according to a modification of the first embodiment, and corresponds to Fig. 5 of the first embodiment.

[0134] The semiconductor device of the modified example of the first embodiment is an IGBT 101. The modified IGBT 101 differs from the IGBT 100 of the first embodiment in that the n-type impurity concentration of the sixth portion 31c of the barrier region 31 is higher than the n-type impurity concentration of the fourth portion 31a, and the n-type impurity concentration of the sixth portion 31c is higher than the n-type impurity concentration of the fifth portion 31b.

[0135] The n-type impurity concentration of the sixth portion 31c is, for example, 120% to 200% of the n-type impurity concentration of the fourth portion 31a. The n-type impurity concentration of the fifth portion 31b is, for example, 120% to 200% of the n-type impurity concentration of the fourth portion 31a.

[0136] Because the n-type impurity concentration of the sixth portion 31c is higher than the n-type impurity concentration of the fourth portion 31a, the threshold voltage of the third transistor having the third gate electrode 53 becomes lower, due to the short channel effect, than the threshold voltage of the first transistor having the first gate electrode 51. Furthermore, because the n-type impurity concentration of the sixth portion 31c is higher than the n-type impurity concentration of the fifth portion 31b, the threshold voltage of the third transistor having the third gate electrode 53 becomes lower, due to the short channel effect, than the threshold voltage of the second transistor having the second gate electrode 52.

[0137] The third transistor having the third gate electrode 53 starts to turn on more quickly. Therefore, the amount of electrons injected into the drift region 27 increases more quickly. Therefore, the turn-on time of the IGBT 101 can be further shortened. Therefore, the turn-on loss of the IGBT 101 is further reduced.

[0138] As described above, according to the first embodiment and the modified example, a semiconductor device and a semiconductor circuit that can reduce switching loss can be realized.

[0139] (Second embodiment) The semiconductor device and semiconductor circuit of the second embodiment differ from the semiconductor device and semiconductor circuit of the first embodiment in that at least one third trench includes a pair of adjacent third trenches, and the third portion is located between the pair of third trenches. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0140] The semiconductor device of the second embodiment is an IGBT 200. The IGBT 200 is a trench-gate IGBT having a gate electrode in a trench formed in a semiconductor layer. The following description will be given taking as an example a case where the first conductivity type is p-type and the second conductivity type is n-type.

[0141] The control circuit of the second embodiment is a gate driver circuit 150. The semiconductor circuit of the second embodiment is composed of a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor module in which an IGBT 200 and a gate driver circuit 150 are mounted.

[0142] Fig. 8 is a schematic cross-sectional view of a part of the semiconductor device of the second embodiment, which corresponds to Fig. 2 of the first embodiment.

[0143] The IGBT 200 of the second embodiment includes a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a first gate insulating film 41, a second gate insulating film 42, a third gate insulating film 43, a first gate electrode 51, a second gate electrode 52, a third gate electrode 53, an interlayer insulating layer 61, a first gate electrode pad 104 (first electrode pad), a second gate electrode pad 105 (second electrode pad), and a third gate electrode pad 106 (third electrode pad).

[0144] Within the semiconductor layer 10, a first gate trench 21 (first trench), a second gate trench 22 (second trench), a third gate trench 23 (third trench), a collector region 26 (first semiconductor region), a drift region 27 (second semiconductor region), a base region 28 (third semiconductor region), an emitter region 29 (fourth semiconductor region), a contact region 30, and a barrier region 31 (fifth semiconductor region) are provided.

[0145] The base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c. The barrier region 31 includes a fourth portion 31a, a fifth portion 31b, and a sixth portion 31c.

[0146] The IGBT 200 of the second embodiment includes a pair of third gate trenches 23 adjacent to each other in the second direction. The first gate trench 21 and the second gate trench 22 are not present between the pair of adjacent third gate trenches 23.

[0147] Fig. 9 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the second embodiment. Fig. 9 is an enlarged view of a part of Fig. 8. Fig. 9 is a view corresponding to Fig. 5 of the first embodiment.

[0148] As shown in FIG. 9, the base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c.

[0149] The first portion 28a is a portion of the base region 28 that contacts the first gate trench 21. The first portion 28a contacts the first gate insulating film 41. The first portion 28a faces the first gate electrode 51.

[0150] The first portion 28a functions as a channel region of a first transistor having a first gate electrode 51, a first gate insulating film 41, and the first portion 28a. The first transistor is driven by a first gate voltage (Vg1) applied to the first gate electrode 51.

[0151] The second portion 28b is a portion of the base region 28 that contacts the second gate trench 22. The second portion 28b contacts the second gate insulating film 42. The second portion 28b faces the second gate electrode 52.

[0152] The second portion 28b functions as a channel region of a second transistor having a second gate electrode 52, a second gate insulating film 42, and the second portion 28b. The second transistor is driven by a second gate voltage (Vg2) applied to the second gate electrode 52.

[0153] The third portion 28c is a portion of the base region 28 that contacts the third gate trench 23. The third portion 28c contacts the third gate insulating film 43. The third portion 28c faces the third gate electrode 53.

[0154] The third portion 28c is provided between a pair of third gate trenches 23 adjacent to each other in the second direction.

[0155] The third portion 28c functions as a channel region of a third transistor having a third gate electrode 53, a third gate insulating film 43, and the third portion 28c. The third transistor is a transistor driven by a third gate voltage (Vg3) applied to the third gate electrode 53.

[0156] The thickness in the third direction of third portion 28c (t3 in FIG. 9) is thinner than the thickness in the third direction of first portion 28a (t1 in FIG. 9). The thickness in the third direction of third portion 28c (t3) is, for example, 20% to 70% of the thickness in the third direction of first portion 28a (t1).

[0157] Furthermore, the thickness in the third direction of third portion 28c (t3 in FIG. 9) is thinner than the thickness in the third direction of second portion 28b (t2 in FIG. 9). The thickness in the third direction of third portion 28c, t3, is, for example, 20% to 70% of the thickness in the third direction, t2, of second portion 28b.

[0158] As shown in FIG. 9, the barrier region 31 includes a fourth portion 31a, a fifth portion 31b, and a sixth portion 31c.

[0159] The fourth portion 31a is a portion of the barrier region 31 that contacts the first gate trench 21. The fourth portion 31a contacts the first gate insulating film 41. The fourth portion 31a faces the first gate electrode 51. The fourth portion 31a is provided between the drift region 27 and the first portion 28a.

[0160] The fifth portion 31b is a portion of the barrier region 31 that contacts the second gate trench 22. The fifth portion 31b contacts the second gate insulating film 42. The fifth portion 31b faces the second gate electrode 52. The fifth portion 31b is provided between the drift region 27 and the second portion 28b.

[0161] The sixth portion 31c is a portion of the barrier region 31 that contacts the third gate trench 23. The sixth portion 31c contacts the third gate insulating film 43. The sixth portion 31c faces the third gate electrode 53. The sixth portion 31c is provided between the drift region 27 and the third portion 28c.

[0162] The thickness in the third direction of the sixth portion 31c (t6 in FIG. 9) is thicker than the thickness in the third direction of the fourth portion 31a (t4 in FIG. 9). The thickness in the third direction of the sixth portion 31c (t6) is, for example, 150% or more of the thickness in the third direction of the fourth portion 31a (t6).

[0163] The thickness of the sixth portion 31c in the third direction (t6 in FIG. 9) is greater than the thickness of the fifth portion 31b in the third direction (t5 in FIG. 9). The thickness t6 of the sixth portion 31c in the third direction is, for example, 150% or more of the thickness t5 of the fifth portion 31b in the third direction.

[0164] The IGBT 200 of the second embodiment reduces switching loss due to the same action as the IGBT 100 of the first embodiment.

[0165] Furthermore, compared to the IGBT 100 of the first embodiment, the IGBT 200 of the second embodiment has a higher density of the third gate trenches 23 in the first surface F1 than the density of the first gate trenches 21 and the density of the second gate trenches 22. Therefore, the amount of electrons injected when the IGBT 200 is turned on is even greater than that of the IGBT 100. This further reduces turn-on loss.

[0166] As described above, according to the second embodiment, it is possible to realize a semiconductor device and a semiconductor circuit that enable a reduction in switching loss.

[0167] (Third embodiment) The semiconductor device of the third embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of a first conductivity type provided in the semiconductor layer, a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface, a third semiconductor region of the first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface, a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface, and a second semiconductor region of the second conductivity type provided on the side of the first surface in the semiconductor layer. a first trench in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first gate electrode provided in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a second gate electrode provided in the second trench; a second gate insulating film provided between the electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; at least one third trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode provided in the at least one third trench; and a third gate electrode provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region. a third gate insulating film provided therebetween; a first electrode provided on the first surface side of the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side of the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate electrode; and a third electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate electrode.The third semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with at least one third trench, and the first conductivity type impurity concentration of the third portion is lower than the first conductivity type impurity concentration of the first portion, and the first conductivity type impurity concentration of the third portion is lower than the first conductivity type impurity concentration of the second portion.

[0168] The semiconductor circuit of the third embodiment includes a control circuit that drives the semiconductor device.

[0169] The semiconductor device and semiconductor circuit of the third embodiment differ from the semiconductor device and semiconductor circuit of the first embodiment in that the first conductivity type impurity concentration in the third portion is lower than the first conductivity type impurity concentration in the first portion, and the first conductivity type impurity concentration in the third portion is lower than the first conductivity type impurity concentration in the second portion. Hereinafter, description of content that overlaps with the first embodiment may be omitted.

[0170] The semiconductor device of the third embodiment is an IGBT 300. The IGBT 300 is a trench-gate IGBT having a gate electrode in a trench formed in a semiconductor layer. Hereinafter, an example will be described in which the first conductivity type is p-type and the second conductivity type is n-type.

[0171] The control circuit of the third embodiment is a gate driver circuit 150. The semiconductor circuit of the third embodiment is composed of a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor module in which an IGBT 300 and the gate driver circuit 150 are mounted.

[0172] Fig. 10 is a schematic cross-sectional view of a part of the semiconductor device of the third embodiment, which corresponds to Fig. 2 of the first embodiment.

[0173] The IGBT 300 of the third embodiment includes a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a first gate insulating film 41, a second gate insulating film 42, a third gate insulating film 43, a first gate electrode 51, a second gate electrode 52, a third gate electrode 53, an interlayer insulating layer 61, a first gate electrode pad 104 (first electrode pad), a second gate electrode pad 105 (second electrode pad), and a third gate electrode pad 106 (third electrode pad).

[0174] Within the semiconductor layer 10, a first gate trench 21 (first trench), a second gate trench 22 (second trench), a third gate trench 23 (third trench), a collector region 26 (first semiconductor region), a drift region 27 (second semiconductor region), a base region 28 (third semiconductor region), an emitter region 29 (fourth semiconductor region), a contact region 30, and a barrier region 31 (fifth semiconductor region) are provided.

[0175] The base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c.

[0176] Fig. 11 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the third embodiment. Fig. 11 is an enlarged view of a part of Fig. 10. Fig. 11 is a view corresponding to Fig. 5 of the first embodiment.

[0177] As shown in FIG. 11, the base region 28 includes a first portion 28a, a second portion 28b, and a third portion 28c.

[0178] The first portion 28a is a portion of the base region 28 that contacts the first gate trench 21. The first portion 28a contacts the first gate insulating film 41. The first portion 28a faces the first gate electrode 51.

[0179] The first portion 28a functions as a channel region of a first transistor having a first gate electrode 51, a first gate insulating film 41, and the first portion 28a. The first transistor is driven by a first gate voltage (Vg1) applied to the first gate electrode 51.

[0180] The second portion 28b is a portion of the base region 28 that contacts the second gate trench 22. The second portion 28b contacts the second gate insulating film 42. The second portion 28b faces the second gate electrode 52.

[0181] The second portion 28b functions as a channel region of a second transistor having a second gate electrode 52, a second gate insulating film 42, and the second portion 28b. The second transistor is driven by a second gate voltage (Vg2) applied to the second gate electrode 52.

[0182] The third portion 28c is a portion of the base region 28 that contacts the third gate trench 23. The third portion 28c contacts the third gate insulating film 43. The third portion 28c faces the third gate electrode 53.

[0183] The third portion 28c functions as a channel region of a third transistor having a third gate electrode 53, a third gate insulating film 43, and the third portion 28c. The third transistor is a transistor driven by a third gate voltage (Vg3) applied to the third gate electrode 53.

[0184] The p-type impurity concentration of the third portion 28c is lower than the p-type impurity concentration of the first portion 28a, and is, for example, 50% to 80% of the p-type impurity concentration of the first portion 28a.

[0185] The p-type impurity concentration of the third portion 28c is lower than the p-type impurity concentration of the second portion 28b, and is, for example, 50% to 80% of the p-type impurity concentration of the second portion 28b.

[0186] In the IGBT 300 of the third embodiment, the p-type impurity concentration of the third portion 28c is lower than the p-type impurity concentration of the first portion 28a, and therefore the threshold voltage of the third transistor having the third gate electrode 53 is lower than the threshold voltage of the first transistor having the first gate electrode 51.

[0187] In the IGBT 300 of the third embodiment, the p-type impurity concentration of the third portion 28 c is lower than the p-type impurity concentration of the second portion 28 b. Therefore, the threshold voltage of the third transistor having the third gate electrode 53 is lower than the threshold voltage of the second transistor having the second gate electrode 52.

[0188] The threshold voltage of the third transistor having the third gate electrode 53 is lower than the threshold voltage of the first transistor having the first gate electrode 51 and the threshold voltage of the second transistor having the second gate electrode 52. Therefore, for example, when a turn-on voltage is applied to the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53 simultaneously at time T1 in FIG. 6, the third transistor having the third gate electrode 53 starts to turn on quickly. This quickly increases the amount of electrons injected into the drift region 27. This shortens the turn-on time of the IGBT 300. This reduces the turn-on loss of the IGBT 300.

[0189] The p-type impurity concentration of the third portion 28c is preferably 80% or less of the p-type impurity concentration of the second portion 28b from the viewpoint of lowering the threshold voltage of the third transistor having the third gate electrode 53. The p-type impurity concentration of the third portion 28c is preferably 80% or less of the p-type impurity concentration of the second portion 28b from the viewpoint of lowering the threshold voltage of the third transistor having the third gate electrode 53.

[0190] As described above, according to the third embodiment, it is possible to realize a semiconductor device and a semiconductor circuit that enable a reduction in switching loss.

[0191] (Fourth embodiment) A semiconductor device according to a fourth embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of a first conductivity type provided in the semiconductor layer, a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface, a third semiconductor region of the first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface, a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface, and a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the second semiconductor region and the third surface. a fifth semiconductor region of a second conductivity type provided between the semiconductor regions and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second semiconductor region; a first trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a first gate electrode provided in the first trench; and third gate electrodes provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, between the first gate electrode and the fourth semiconductor region, and between the first gate electrode and the fifth semiconductor region. a first gate insulating film; a second trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a second gate electrode provided in the second trench; a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, between the second gate electrode and the fourth semiconductor region, and between the second gate electrode and the fifth semiconductor region; at least one third trench in contact with the conductor region and the fifth semiconductor region; a third gate electrode provided in the at least one third trench; third gate insulating films provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, between the third gate electrode and the fourth semiconductor region, and between the third gate electrode and the fifth semiconductor region; a first electrode provided on the first surface side of the semiconductor layer and in contact with the fourth semiconductor region; and a second electrode provided on the second surface side of the semiconductor layer and in contact with the first semiconductor region.The fifth semiconductor region includes a first electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate electrode, a second electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate electrode, and a third electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate electrode. The fifth semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with at least one third trench, and the second conductivity type impurity concentration of the third portion is higher than the second conductivity type impurity concentration of the first portion, and the second conductivity type impurity concentration of the third portion is higher than the second conductivity type impurity concentration of the second portion.

[0192] The semiconductor circuit of the fourth embodiment includes a control circuit that drives the semiconductor device.

[0193] The semiconductor device and semiconductor circuit of the fourth embodiment differ from the semiconductor device and semiconductor circuit of the first embodiment in that the fifth semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with at least one third trench, and the second conductivity type impurity concentration of the third portion is higher than the second conductivity type impurity concentration of the first portion, and the second conductivity type impurity concentration of the third portion is higher than the second conductivity type impurity concentration of the second portion. Hereinafter, description of content that overlaps with the first embodiment may be omitted.

[0194] The semiconductor device of the fourth embodiment is an IGBT 400. The IGBT 400 is a trench-gate IGBT having a gate electrode in a trench formed in a semiconductor layer. Hereinafter, an example will be described in which the first conductivity type is p-type and the second conductivity type is n-type.

[0195] The control circuit of the fourth embodiment is a gate driver circuit 150. The semiconductor circuit of the fourth embodiment is composed of a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor module in which an IGBT 400 and a gate driver circuit 150 are mounted.

[0196] Fig. 12 is a schematic cross-sectional view of a part of a semiconductor device according to the fourth embodiment, which corresponds to Fig. 2 of the first embodiment.

[0197] The IGBT 400 of the fourth embodiment includes a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a first gate insulating film 41, a second gate insulating film 42, a third gate insulating film 43, a first gate electrode 51, a second gate electrode 52, a third gate electrode 53, an interlayer insulating layer 61, a first gate electrode pad 104 (first electrode pad), a second gate electrode pad 105 (second electrode pad), and a third gate electrode pad 106 (third electrode pad).

[0198] Within the semiconductor layer 10, a first gate trench 21 (first trench), a second gate trench 22 (second trench), a third gate trench 23 (third trench), a collector region 26 (first semiconductor region), a drift region 27 (second semiconductor region), a base region 28 (third semiconductor region), an emitter region 29 (fourth semiconductor region), a contact region 30, and a barrier region 31 (fifth semiconductor region) are provided.

[0199] The barrier region 31 includes a first low-concentration portion 31x (first portion), a second low-concentration portion 31y (second portion), and a high-concentration portion 31z (third portion).

[0200] 13 is an enlarged schematic cross-sectional view of a part of the semiconductor device of the fourth embodiment.

[0201] As shown in FIG. 13, the barrier region 31 includes a first low concentration portion 31x, a second low concentration portion 31y, and a high concentration portion 31z.

[0202] The first low concentration portion 31x is a portion of the barrier region 31 that contacts the first gate trench 21. The first low concentration portion 31x contacts the first gate insulating film 41. The first low concentration portion 31x faces the first gate electrode 51.

[0203] The second low concentration portion 31y is a portion of the barrier region 31 that contacts the second gate trench 22. The second low concentration portion 31y contacts the second gate insulating film 42. The second low concentration portion 31y faces the second gate electrode 52.

[0204] The heavily doped portion 31z is a portion of the barrier region 31 that contacts the third gate trench 23. The heavily doped portion 31z contacts the third gate insulating film 43. The heavily doped portion 31z faces the third gate electrode 53.

[0205] The n-type impurity concentration of the high concentration portion 31z is higher than the n-type impurity concentration of the first low concentration portion 31x, and is, for example, 120% to 200% of the n-type impurity concentration of the first low concentration portion 31x.

[0206] The n-type impurity concentration of the high concentration portion 31z is higher than the n-type impurity concentration of the second low concentration portion 31y and is, for example, 120% to 200% of the n-type impurity concentration of the second low concentration portion 31y.

[0207] Because the n-type impurity concentration of the high-concentration portion 31z is higher than the n-type impurity concentration of the first low-concentration portion 31x, the threshold voltage of the third transistor having the third gate electrode 53 becomes lower, due to the short channel effect, than the threshold voltage of the first transistor having the first gate electrode 51. Furthermore, because the n-type impurity concentration of the high-concentration portion 31z is higher than the n-type impurity concentration of the second low-concentration portion 31y, the threshold voltage of the third transistor having the third gate electrode 53 becomes lower, due to the short channel effect, than the threshold voltage of the second transistor having the second gate electrode 52.

[0208] Therefore, when the IGBT 400 is turned on, the third transistor having the third gate electrode 53 starts to turn on quickly. This quickly increases the amount of electrons injected into the drift region 27. This shortens the turn-on time of the IGBT 400. This reduces the turn-on loss of the IGBT 400.

[0209] As described above, according to the fourth embodiment, it is possible to realize a semiconductor device and a semiconductor circuit that enable a reduction in switching loss.

[0210] (Fifth embodiment) A semiconductor device according to a fifth embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, a first semiconductor region of a first conductivity type provided in the semiconductor layer, a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface, a third semiconductor region of the first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface, a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface, and a second semiconductor region of the second conductivity type provided on the side of the first surface in the semiconductor layer. a first trench in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first gate electrode provided in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a second gate electrode provided in the second trench; a second gate insulating film provided between the electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; at least one third trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode provided in the at least one third trench; and a third gate electrode provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region. a third gate insulating film provided therebetween; a first electrode provided on the first surface side of the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side of the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate electrode; and a third electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate electrode.The semiconductor device includes a first transistor having a first gate electrode, a second transistor having a second gate electrode, and a third transistor having a third gate electrode, and the threshold voltage of the third transistor is lower than the threshold voltage of the first transistor, and the threshold voltage of the third transistor is lower than the threshold voltage of the second transistor.

[0211] The semiconductor circuit of the fifth embodiment includes a control circuit that drives the semiconductor device.

[0212] The semiconductor device of the fifth embodiment is an IGBT 500. The IGBT 500 is a trench-gate IGBT having a gate electrode in a trench formed in a semiconductor layer. Hereinafter, an example will be described in which the first conductivity type is p-type and the second conductivity type is n-type.

[0213] The control circuit of the fifth embodiment is similar to the gate driver circuit 150 of the first embodiment. The semiconductor circuit of the fifth embodiment is composed of a semiconductor device and a control circuit that controls the semiconductor device. The semiconductor circuit is, for example, a semiconductor module in which an IGBT 500 and a gate driver circuit 150 are mounted.

[0214] FIG. 14 is a schematic cross-sectional view of a part of the semiconductor device of the fifth embodiment.

[0215] Fig. 15 is a schematic top view of a part of the semiconductor device of the fifth embodiment, Fig. 15 is a top view on the first face F1, Fig. 14 is a cross section taken along CC' in Fig. 15.

[0216] 16 is a schematic cross-sectional view of a part of the semiconductor device of the fifth embodiment, taken along the line DD' in FIG.

[0217] The IGBT 500 of the fifth embodiment includes a semiconductor layer 10, an emitter electrode 12 (first electrode), a collector electrode 14 (second electrode), a first gate insulating film 41, a second gate insulating film 42, a third gate insulating film 43, a first gate electrode 51, a second gate electrode 52, a third gate electrode 53, an interlayer insulating layer 61, a first gate electrode pad 104 (first electrode pad), a second gate electrode pad 105 (second electrode pad), and a third gate electrode pad 106 (third electrode pad).

[0218] Within the semiconductor layer 10, a first gate trench 21 (first trench), a second gate trench 22 (second trench), a third gate trench 23 (third trench), a collector region 26 (first semiconductor region), a drift region 27 (second semiconductor region), a base region 28 (third semiconductor region), an emitter region 29 (fourth semiconductor region), a contact region 30, and a barrier region 31 (fifth semiconductor region) are provided.

[0219] The semiconductor layer 10 has a first face F1 and a second face F2 facing the first face F1. The semiconductor layer 10 is, for example, single crystal silicon. The thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0220] A direction parallel to the first surface F1 is referred to as the first direction. A direction parallel to the first surface F1 and perpendicular to the first direction is referred to as the second direction. A direction from the first surface F1 toward the second surface F2 is referred to as the third direction.

[0221] Moreover, the "depth" is defined as the distance from the first surface F1 toward the second surface F2.

[0222] The emitter electrode 12 is provided on the first face F1 side of the semiconductor layer 10. At least a portion of the emitter electrode 12 contacts the first face F1 of the semiconductor layer 10. The emitter electrode 12 is made of, for example, a metal.

[0223] The emitter electrode 12 is in contact with the emitter region 29. The emitter electrode 12 is electrically connected to the emitter region 29.

[0224] The emitter electrode 12 is in contact with the contact region 30. The emitter electrode 12 is electrically connected to the contact region 30. The emitter electrode 12 is electrically connected to the base region 28 via the contact region 30.

[0225] The collector electrode 14 is provided on the second face F2 side of the semiconductor layer 10. At least a portion of the collector electrode 14 contacts the second face F2 of the semiconductor layer 10. The collector electrode 14 is made of, for example, a metal.

[0226] The collector electrode 14 is in contact with the collector region 26. The collector electrode 14 is electrically connected to the collector region 26.

[0227] The collector region 26 is p + The collector region 26 is a semiconductor region having a shape similar to that of the first face F1. The collector region 26 is in contact with the second face F2. The collector region 26 is electrically connected to the collector electrode 14. The collector region 26 is in contact with the collector electrode 14. The collector region 26 serves as a source of holes when the IGBT 500 is in the on state.

[0228] The drift region 27 is - The drift region 27 is provided between the collector region 26 and the first face F1.

[0229] The drift region 27 serves as a path for an on-current when the IGBT 500 is in an on-state. The drift region 27 is depleted when the IGBT 500 is in an off-state, and has the function of maintaining the breakdown voltage of the IGBT 500.

[0230] The base region 28 is a p-type semiconductor region. The base region 28 is provided between the drift region 27 and the first face F1. The drift region 27 is sandwiched between the base region 28 and the collector region 26.

[0231] The depth of the base region 28 is, for example, 5 μm or less. When the IGBT 500 is in the on state, an n-type inversion layer is formed in the region of the base region 28 facing the first gate electrode 51, the region of the base region 28 facing the second gate electrode 52, and the region of the base region 28 facing the third gate electrode 53. The base region 28 functions as a channel region of the transistor.

[0232] The barrier region 31 is an n-type semiconductor region. The barrier region 31 is provided between the drift region 27 and the base region 28. The n-type impurity concentration of the barrier region 31 is higher than the n-type impurity concentration of the drift region 27.

[0233] The barrier region 31 has a function of increasing the amount of carrier accumulation in the drift region 27 when the IGBT 500 is in the on state. By providing the barrier region 31, the on-resistance of the IGBT 500 is reduced, and the steady-state loss of the IGBT 500 is reduced.

[0234] The emitter region 29 is n + The emitter region 29 is provided between the base region 28 and the first face F1.

[0235] The emitter region 29 is in contact with the first gate insulating film 41, the second gate insulating film 42, and the third gate insulating film 43.

[0236] The n-type impurity concentration of the emitter region 29 is higher than the n-type impurity concentration of the drift region 27 .

[0237] The emitter region 29 is in contact with the emitter electrode 12. The emitter region 29 is electrically connected to the emitter electrode 12. The emitter region 29 serves as a supply source of electrons when the IGBT 500 is in the on state.

[0238] The contact region 30 is p +The contact region 30 is a semiconductor region having a shape similar to that of the base region 28. The contact region 30 is provided between the base region 28 and the first face F1. The contact region 30 is in contact with the emitter electrode 12. The contact region 30 is electrically connected to the emitter electrode 12.

[0239] The p-type impurity concentration of the contact region 30 is higher than the p-type impurity concentration of the base region 28 .

[0240] The first gate trench 21 is provided on the first face F1 side of the semiconductor layer 10. The first gate trench 21 is a groove provided in the semiconductor layer 10. The first gate trench 21 is a part of the semiconductor layer 10.

[0241] 15, the first gate trench 21 extends in a first direction parallel to the first face F1 on the first face F1. The first gate trench 21 has a stripe shape. A plurality of the first gate trenches 21 are repeatedly arranged in a second direction perpendicular to the first direction.

[0242] The first gate trench 21 contacts the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The first gate trench 21 penetrates the base region 28 and reaches the drift region 27. The depth of the first gate trench 21 is, for example, 8 μm or less.

[0243] The first gate electrode 51 is provided in the first gate trench 21. The first gate electrode 51 is, for example, a semiconductor or a metal. The first gate electrode 51 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The first gate electrode 51 is electrically connected to the first gate electrode pad 104.

[0244] The first gate insulating film 41 is provided between the first gate electrode 51 and the semiconductor layer 10. The first gate insulating film 41 is provided between the first gate electrode 51 and the drift region 27, between the first gate electrode 51 and the base region 28, between the first gate electrode 51 and the emitter region 29, and between the first gate electrode 51 and the barrier region 31. The first gate insulating film 41 is in contact with the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The first gate insulating film 41 is made of, for example, silicon oxide.

[0245] The second gate trench 22 is provided on the first face F1 side of the semiconductor layer 10. The second gate trench 22 is a groove provided in the semiconductor layer 10. The second gate trench 22 is a part of the semiconductor layer 10.

[0246] 15, the second gate trenches 22 extend in a first direction parallel to the first face F1 on the first face F1. The second gate trenches 22 have a stripe shape. The second gate trenches 22 are repeatedly arranged in a second direction perpendicular to the first direction.

[0247] The second gate trench 22 contacts the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The second gate trench 22 penetrates the base region 28 and reaches the drift region 27. The depth of the second gate trench 22 is, for example, 8 μm or less.

[0248] The second gate electrode 52 is provided in the second gate trench 22. The second gate electrode 52 is, for example, a semiconductor or a metal. The second gate electrode 52 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The second gate electrode 52 is electrically connected to the second gate electrode pad 105.

[0249] The second gate insulating film 42 is provided between the second gate electrode 52 and the semiconductor layer 10. The second gate insulating film 42 is provided between the second gate electrode 52 and the drift region 27, between the second gate electrode 52 and the base region 28, between the second gate electrode 52 and the emitter region 29, and between the second gate electrode 52 and the barrier region 31. The second gate insulating film 42 is in contact with the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The second gate insulating film 42 is made of, for example, silicon oxide.

[0250] The third gate trench 23 is provided on the first face F1 side of the semiconductor layer 10. The third gate trench 23 is a groove provided in the semiconductor layer 10. The third gate trench 23 is a part of the semiconductor layer 10.

[0251] 15, the third gate trench 23 extends in a first direction parallel to the first face F1 on the first face F1. The third gate trench 23 has a stripe shape. A plurality of the third gate trenches 23 are repeatedly arranged in a second direction perpendicular to the first direction.

[0252] The third gate trench 23 contacts the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The third gate trench 23 penetrates the base region 28 and reaches the drift region 27. The depth of the third gate trench 23 is, for example, 8 μm or less.

[0253] The third gate electrode 53 is provided in the third gate trench 23. The third gate electrode 53 is, for example, a semiconductor or a metal. The third gate electrode 53 is, for example, amorphous silicon or polycrystalline silicon containing n-type impurities or p-type impurities. The third gate electrode 53 is electrically connected to the third gate electrode pad 106.

[0254] The third gate insulating film 43 is provided between the third gate electrode 53 and the semiconductor layer 10. The third gate insulating film 43 is provided between the third gate electrode 53 and the drift region 27, between the third gate electrode 53 and the base region 28, between the third gate electrode 53 and the emitter region 29, and between the third gate electrode 53 and the barrier region 31. The third gate insulating film 43 is in contact with the drift region 27, the base region 28, the emitter region 29, and the barrier region 31. The third gate insulating film 43 is made of, for example, silicon oxide.

[0255] The interlayer insulating layer 61 is provided between the first gate electrode 51 and the emitter electrode 12. The interlayer insulating layer 61 electrically separates the first gate electrode 51 from the emitter electrode 12. The interlayer insulating layer 61 is provided between the second gate electrode 52 and the emitter electrode 12.

[0256] The interlayer insulating layer 61 electrically isolates the second gate electrode 52 from the emitter electrode 12. The interlayer insulating layer 61 is provided between the third gate electrode 53 and the emitter electrode 12. The interlayer insulating layer 61 electrically isolates the third gate electrode 53 from the emitter electrode 12. The interlayer insulating layer 61 is made of, for example, silicon oxide.

[0257] The first gate electrode pad 104 is provided on the first face F1 side of the semiconductor layer 10. The first gate electrode pad 104 is electrically connected to the first gate electrode 51. The first gate electrode pad 104 and the first gate electrode 51 are connected by, for example, a metal wiring (not shown).

[0258] To the first gate electrode pad 104, a first gate voltage (Vg1) is applied. To the first gate electrode pad 104, for example, a first turn-on voltage (Von1) and a first turn-off voltage (Voff1) are applied.

[0259] The second gate electrode pad 105 is provided on the first face F1 side of the semiconductor layer 10. The second gate electrode pad 105 is electrically connected to the second gate electrode 52. The second gate electrode pad 105 and the second gate electrode 52 are connected by, for example, a metal wiring (not shown).

[0260] A second gate voltage (Vg2) is applied to the second gate electrode pad 105. To the second gate electrode pad 105, for example, a second turn-on voltage (Von2) and a second turn-off voltage (Voff2) are applied.

[0261] The third gate electrode pad 106 is provided on the first face F1 side of the semiconductor layer 10. The third gate electrode pad 106 is electrically connected to the third gate electrode 53. The third gate electrode pad 106 and the third gate electrode 53 are connected by, for example, a metal wiring (not shown).

[0262] A third gate voltage (Vg3) is applied to the third gate electrode pad 106. To the third gate electrode pad 106, for example, a third turn-on voltage (Von3) and a third turn-off voltage (Voff3) are applied.

[0263] The IGBT 500 of the fifth embodiment includes a first transistor having a first gate electrode 51 , a second transistor having a second gate electrode 52 , and a third transistor having a third gate electrode 53 .

[0264] The first transistor having the first gate electrode 51 is a transistor that is driven using the first gate electrode 51. The first transistor is composed of the first gate electrode 51, a first gate insulating film 41, a base region 28 facing the first gate electrode 51, an emitter region 29, and a barrier region 31. The base region 28 facing the first gate electrode 51 becomes the channel region of the first transistor. The emitter region 29 and the barrier region 31 The portion of this layer that contacts the first gate insulating film 41 becomes the source / drain region of the first transistor.

[0265] The second transistor having the second gate electrode 52 is a transistor that is driven using the second gate electrode 52. The second transistor is composed of the second gate electrode 52, the second gate insulating film 42, the base region 28 facing the second gate electrode 52, the emitter region 29, and the barrier region 31. The base region 28 facing the second gate electrode 52 becomes the channel region of the second transistor. The emitter region 29 and the barrier region 31 The portion in contact with the second gate insulating film 42 becomes the source / drain region of the second transistor.

[0266] The third transistor having the third gate electrode 53 is a transistor that is driven using the third gate electrode 53. The third transistor includes the third gate electrode 53, a third gate insulating film 43, a base region 28 facing the third gate electrode 53, an emitter region 29, and a barrier region 31. The base region 28 facing the third gate electrode 53 becomes the channel region of the third transistor. The emitter region 29 and the barrier region 31 The portion of this layer that contacts the third gate insulating film 43 becomes the source / drain region of the third transistor.

[0267] In the IGBT 500 of the fifth embodiment, the threshold voltage of the third transistor is lower than the threshold voltage of the first transistor, and the threshold voltage of the third transistor is lower than the threshold voltage of the second transistor.

[0268] For example, the thickness of the third gate insulating film 43 of the third transistor is thinner than the first gate insulating film 41 of the first transistor. Also, the thickness of the third gate insulating film 43 of the third transistor is thinner than the second gate insulating film 42 of the second transistor. The thinner third gate insulating film 43 of the third transistor reduces the threshold voltage of the third transistor.

[0269] Furthermore, for example, the dielectric constant of the third gate insulating film 43 of the third transistor is higher than the dielectric constant of the first gate insulating film 41 of the first transistor. Also, the dielectric constant of the third gate insulating film 43 of the third transistor is higher than the dielectric constant of the second gate insulating film 42 of the second transistor. The high dielectric constant of the third gate insulating film 43 of the third transistor reduces the threshold voltage of the third transistor.

[0270] Furthermore, for example, the work function of the third gate electrode 53 of the third transistor is different from the work function of the first gate electrode 51 of the first transistor. Also, the work function of the third gate electrode 53 of the third transistor is different from the work function of the second gate electrode 52 of the second transistor. The difference in work function of the third gate electrode 53 of the third transistor reduces the threshold voltage of the third transistor.

[0271] Furthermore, for example, the p-type impurity concentration of the base region 28 facing the third gate electrode 53 of the third transistor is lower than the p-type impurity concentration of the base region 28 facing the first gate electrode 51 of the first transistor. Also, the p-type impurity concentration of the base region 28 facing the third gate electrode 53 of the third transistor is lower than the p-type impurity concentration of the base region 28 facing the second gate electrode 52 of the second transistor. The lower p-type impurity concentration of the base region 28 facing the third gate electrode 53 of the third transistor reduces the threshold voltage of the third transistor.

[0272] Next, the operation and effects of the semiconductor device and semiconductor circuit of the fifth embodiment will be described.

[0273] The IGBT 500 of the fifth embodiment operates in the same driving method as the IGBT 100 of the first embodiment.

[0274] Similar to the IGBT 100 of the first embodiment, the IGBT 500 of the fifth embodiment includes a first transistor having a first gate electrode 51, a second transistor having a second gate electrode 52, and a third transistor having a third gate electrode 53 in a transistor region 101. Each transistor can be driven independently. This configuration reduces the turn-on loss and turn-off loss of the IGBT 500.

[0275] In the IGBT 500 of the fifth embodiment, the threshold voltage of the third transistor is lower than the threshold voltage of the first transistor, and the threshold voltage of the third transistor is lower than the threshold voltage of the second transistor.

[0276] The threshold voltage of the third transistor of the IGBT 500 of the fifth embodiment is lower than the threshold voltage of the first transistor and the threshold voltage of the second transistor. Therefore, for example, when a turn-on voltage is applied to the first gate electrode 51, the second gate electrode 52, and the third gate electrode 53 simultaneously at time T1 in FIG. 6, the third transistor having the third gate electrode 53 starts to turn on quickly. Therefore, the amount of electrons injected into the drift region 27 increases quickly. This further shortens the turn-on time of the IGBT 500. This further reduces the turn-on loss of the IGBT 500.

[0277] As described above, according to the fifth embodiment, it is possible to realize a semiconductor device and a semiconductor circuit that enable a reduction in switching loss.

[0278] In the first to fifth embodiments, the semiconductor layer is made of single crystal silicon, but the semiconductor layer is not limited to single crystal silicon. For example, the semiconductor layer may be made of other single crystal semiconductors such as single crystal silicon carbide.

[0279] In the first to fifth embodiments, the semiconductor device has been described as having a first gate trench, a second gate trench, and a third gate trench, but it is also possible to further provide a dummy trench in which the potential of the conductive layer in the trench is a fixed potential or a floating potential.

[0280] In the first to fifth embodiments, the trenches are arranged in a stripe shape in parallel to one another. However, the present invention can also be applied to trenches in a mesh shape in which trenches intersect, or to trenches in a dot shape.

[0281] In the first to fifth embodiments, the first conductivity type is p-type and the second conductivity type is n-type, but it is also possible for the first conductivity type to be n-type and the second conductivity type to be p-type.

[0282] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0283] 10 Semiconductor layer 12 Emitter electrode (first electrode) 14 Collector electrode (second electrode) 21 First gate trench (first trench) 22 Second gate trench (second trench) 23 Third gate trench (third trench) 26 Collector region (first semiconductor region) 27 Drift region (second semiconductor region) 28 base region (third semiconductor region) 28a First Part 28b Second Part 28c Third Part 29 Emitter region (fourth semiconductor region) 31 Barrier region (fifth semiconductor region) 31a Fourth Section 31b Fifth Section 31c Sixth Section 31x First low concentration part (first part) 31y Second low concentration part (second part) 31z High density part (third part) 41 First gate insulating film 42 Second gate insulating film 43 Third gate insulating film 51 first gate electrode 52 second gate electrode 53 Third gate electrode 100 IGBT (semiconductor device) 104 First gate electrode pad (first electrode pad) 105 Second gate electrode pad (second electrode pad) 106 Third gate electrode pad (third electrode pad) 150 Gate driver circuit (control circuit) 200 IGBT (semiconductor device) 300 IGBT (semiconductor device) 400 IGBT (semiconductor device) 500 IGBT (semiconductor device) F1 First Side F2 Second side

Claims

1. a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface; a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface; a first trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a first gate electrode disposed in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, and between the first gate electrode and the fourth semiconductor region; a second trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a second gate electrode disposed in the second trench; a second gate insulating film provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, and between the second gate electrode and the fourth semiconductor region; at least one third trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, and the fourth semiconductor region; a third gate electrode disposed in the at least one third trench; a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, and between the third gate electrode and the fourth semiconductor region; a first electrode provided on the first surface side of the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side of the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate electrode; a third electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate electrode; Equipped with a first transistor having the first gate electrode, a second transistor having the second gate electrode, and a third transistor having the third gate electrode; a threshold voltage of the third transistor is lower than a threshold voltage of the first transistor; A method for driving a semiconductor device, wherein a threshold voltage of the third transistor is lower than a threshold voltage of the second transistor, The second gate electrode and the third gate electrode are controlled by turn-off voltages of different magnitudes.

2. the third semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with the at least one third trench; a thickness of the third portion in a direction from the first surface toward the second surface is smaller than a thickness of the first portion in the direction; 2. The method for driving a semiconductor device according to claim 1, wherein a thickness of said third portion in a direction from said first surface toward said second surface is thinner than a thickness of said second portion in said direction.

3. the third semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with the at least one third trench; a first conductivity type impurity concentration of the third portion is lower than a first conductivity type impurity concentration of the first portion; 2. The method for driving a semiconductor device according to claim 1, wherein the concentration of the first conductivity type impurity in said third portion is lower than the concentration of the first conductivity type impurity in said second portion.

4. a semiconductor layer having a first surface and a second surface opposite to the first surface; a first semiconductor region of a first conductivity type provided in the semiconductor layer; a second semiconductor region of a second conductivity type provided in the semiconductor layer and between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided in the semiconductor layer and between the second semiconductor region and the first surface; a fourth semiconductor region of the second conductivity type provided in the semiconductor layer and between the third semiconductor region and the first surface; a fifth semiconductor region of a second conductivity type provided in the semiconductor layer, between the second semiconductor region and the third semiconductor region, the fifth semiconductor region having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second semiconductor region; a first trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a first gate electrode disposed in the first trench; a first gate insulating film provided between the first gate electrode and the second semiconductor region, between the first gate electrode and the third semiconductor region, between the first gate electrode and the fourth semiconductor region, and between the first gate electrode and the fifth semiconductor region; a second trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a second gate electrode disposed in the second trench; second gate insulating films provided between the second gate electrode and the second semiconductor region, between the second gate electrode and the third semiconductor region, between the second gate electrode and the fourth semiconductor region, and between the second gate electrode and the fifth semiconductor region; at least one third trench provided on the first surface side in the semiconductor layer and in contact with the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region; a third gate electrode disposed in the at least one third trench; a third gate insulating film provided between the third gate electrode and the second semiconductor region, between the third gate electrode and the third semiconductor region, between the third gate electrode and the fourth semiconductor region, and between the third gate electrode and the fifth semiconductor region; a first electrode provided on the first surface side of the semiconductor layer and in contact with the fourth semiconductor region; a second electrode provided on the second surface side of the semiconductor layer and in contact with the first semiconductor region; a first electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the first gate electrode; a second electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the second gate electrode; a third electrode pad provided on the first surface side of the semiconductor layer and electrically connected to the third gate electrode; Equipped with the fifth semiconductor region includes a first portion in contact with the first trench, a second portion in contact with the second trench, and a third portion in contact with the at least one third trench; a second conductivity type impurity concentration in the third portion is higher than a second conductivity type impurity concentration in the first portion, and the second conductivity type impurity concentration in the third portion is higher than a second conductivity type impurity concentration in the second portion, The second gate electrode and the third gate electrode are controlled by turn-off voltages of different magnitudes.

5. applying a first turn-on voltage to the first electrode pad; applying a second turn-on voltage to the second electrode pad; applying a third turn-on voltage to the third electrode pad; applying the first turn-on voltage to the first electrode pad, applying the second turn-on voltage to the second electrode pad, applying the third turn-on voltage to the third electrode pad, and then applying a third turn-off voltage to the third electrode pad; applying the third turn-off voltage to the third electrode pad, and then applying a second turn-off voltage to the second electrode pad; 5. The method for driving a semiconductor device according to claim 1, further comprising the step of applying the second turn-off voltage to the second electrode pad and then applying the first turn-off voltage to the first electrode pad.

6. 6. The method of driving a semiconductor device according to claim 5, wherein the second turn-off voltage is a negative voltage.

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