Semiconductor device

Abstract

To provide a semiconductor device that installs a heteroepitaxial layer that is a contact layer on a first surface of a semiconductor layer to allow a conductive layer to form electrical connection with a source region via the contact layer, and thereby reduces source contact resistance.SOLUTION: A semiconductor device includes a semiconductor layer, a trench gate structure including a gate dielectric layer 151 and a gate conductor 152, and a conductive layer 170. The semiconductor layer has a first surface 10 and a second surface 20 facing each other, and includes a source region 130, a body region 110, and a drift region 101. At least part of the trench gate structure is located on a trench of the first surface of the semiconductor layer. The source region extends toward a direction from the first surface to the second surface. The contact layer 190 is a heteroepitaxial layer of the semiconductor layer and covers the first surface of the semiconductor layer. The conductive layer is adjacent to the contact layer and electrically connected to the source region via the contact layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly to semiconductor devices having trench gate structures. [Background technology]

[0002] Silicon carbide (SiC) semiconductor devices have advantages such as fast switching speed and high power density, and their vertical transistor structure is more advantageous than planar transistor structures in balancing barrier voltage and conduction resistance within the same area. Currently, SiC power devices have high source contact resistance, which reduces the reliability of semiconductor devices due to the self-heating effect of the contact resistance. Summary of the Invention [Problem to be solved by the invention]

[0003] In view of the above problems, an object of the present disclosure is to provide a semiconductor device in which the source contact resistance is reduced by providing a contact layer. [Means for solving the problem]

[0004] 1. A semiconductor device according to an embodiment of the present disclosure, comprising: a semiconductor layer; a trench gate structure; a contact layer; and a conductive layer, wherein the semiconductor layer has opposing first and second surfaces, and at least a portion of the trench gate structure is located in a trench in the first surface of the semiconductor layer; The semiconductor layer is a source region extending from the first surface toward the second surface; a drift region and a body region, at least a portion of the drift region being located between the body region and the second surface of the semiconductor layer; a first portion of the body region is located between the source region and the drift region along a direction from the first surface toward the second surface, and both the first portion of the body region and the source region are adjacent to a first sidewall of the trench; the contact layer is a heteroepitaxial layer of the semiconductor layer, located on a first surface of the semiconductor layer and adjacent to the source region; the conductive layer is adjacent to the contact layer and is electrically connected to the source region via the contact layer; The source region and the drift region are of a first conductivity type, and the body region is of a second conductivity type, and the first conductivity type and the second conductivity type are opposite.

[0005] Optionally, the semiconductor layer includes a SiC semiconductor layer, and the contact layer includes one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer.

[0006] Optionally, the thickness of the contact layer comprises a thickness of one or more atomic layers.

[0007] Optionally, the contact layer is crystalline.

[0008] Optionally, the first portion, the second portion, and the third portion of the body region are adjacent to each other in order along a width direction of the trench gate structure; the first and second portions of the body region are located between two of the trench gate structures, the first portion is adjacent to a first sidewall of the trench gate structure, the second portion is adjacent to a second sidewall of the trench gate structure, and the first sidewall and the second sidewall face each other; the third portion and the second portion are adjacent to the same trench gate structure, and the third portion is located between a bottom surface of the trench gate structure and the second surface, and the third portion and the first portion are separated by the drift region; The second portion is adjacent to the second sidewall, or the second portion and the second sidewall are separated by the drift region.

[0009] Optionally, the third portion of the body region extends from a bottom surface of the trench gate structure toward the second surface, or A bottom surface of at least a portion of the trench gate structure and a third portion of the body region are separated by the drift region along a direction from the first surface toward the second surface.

[0010] Optionally, the second portion of the body region includes a first sub-region and a second sub-region that are connected; Along a width direction of the trench gate structure, the first sub-region is adjacent to a first portion of the body region, and the second sub-region is adjacent to a third portion of the body region; a distance from an edge of the first portion of the body region in a direction toward the second surface to the first surface is a first distance, a distance from an edge of the first sub-region in a direction toward the second surface to the first surface is a second distance, and a distance from an edge of the second sub-region in a direction toward the second surface to the first surface is a third distance; The third distance is greater than the second distance, and the second distance is greater than the first distance.

[0011] Optionally, a distance from a bottom surface of the trench gate structure to the first surface is a fourth distance, and the second distance is equal to or greater than the fourth distance.

[0012] Optionally, a distance that the drift region separates a third portion of the body region and a bottom surface of the trench gate structure along a direction from the second surface toward the first surface is a fifth distance; The sum of the fourth distance and the fifth distance is equal to the second distance.

[0013] Alternatively, an edge of the second portion of the body region in a direction toward the second surface and an edge of the third portion in a direction toward the second surface are connected; or An edge of the third portion in a direction toward the second surface is closer to the second surface than an edge of the second portion in a direction toward the second surface.

[0014] Optionally, the semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, whereby the source region, the first portion of the body region, and the channel drain region are adjacent to each other in order along a direction from the first surface to the second surface and are all adjacent to a first sidewall of the trench gate structure; the channel drain region is further adjacent to the drift region and the second portion of the body region, respectively, and the channel drain region and the third portion of the body region are separated by the drift region; The channel drain region is of a first conductivity type.

[0015] Optionally, the doping concentration of the channel drain region is greater than the doping concentration of the drift region.

[0016] Optionally, a distance from an edge of the channel drain region in a direction toward the second surface to the first surface is equal to or less than a distance from a bottom surface of the trench gate structure to the first surface; or The distance from the edge of the channel drain region toward the second surface to the first surface is greater than the distance from a bottom surface of the trench gate structure to the first surface, and the channel drain region is adjacent to a portion of the bottom surface of the trench gate structure.

[0017] Optionally, the semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, whereby the source region, the first portion of the body region, and the channel drain region are adjacent to each other in order along a direction from the first surface to the second surface and are all adjacent to a first sidewall of the trench gate structure; the channel drain region is further adjacent to the drift region and the second portion of the body region, respectively, and the channel drain region and the third portion of the body region are separated by the drift region; the channel drain region is of a first conductivity type; a distance from an edge of the channel drain region in a direction toward the second surface to the first surface is a sixth distance; The sixth distance is greater than the second distance, and the third distance is greater than the sixth distance, whereby the channel drain region and the second sub-region are separated by the drift region along a width direction of the trench gate structure.

[0018] Optionally, the semiconductor layer further includes a body contact region, the body contact region extending from the first surface toward the second surface, the body contact region adjacent to the body region, the body contact region is adjacent to the source region or separated by the body region; The body contact region is of a second conductivity type.

[0019] Optionally, along the extension direction of the trench gate structure, a part of the body contact region is adjacent to the second sidewall, and there is a gap between another part of the body contact region and the second sidewall, and the part of the body contact region adjacent to the second sidewall and the part having the gap are alternately arranged along the extension direction of the trench gate structure, Alternatively, the body contact region and the second sidewall are both separated by the body region.

[0020] Optionally, the trench gate structure includes the gate dielectric layer and a gate conductor; the gate dielectric layer covers an inner surface of the trench and a portion of the first surface adjacent to the trench, the trench extending from the first surface toward the second surface; a portion of the gate conductor is located in the trench and another portion extends outside the trench and covers the gate dielectric layer; The gate dielectric layer is located between the gate conductor and the semiconductor layer to separate the gate conductor and the semiconductor layer.

[0021] Optionally, the semiconductor device is a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

[0022] Optionally, between two of the trench gate structures, the source region extends from a first sidewall of one of the trench gate structures toward a second sidewall of the other of the trench gate structures and is adjacent to a second portion of the body region. [Effects of the Invention]

[0023] One of the above technical solutions has the following beneficial effects.

[0024] By providing a heteroepitaxial layer as a contact layer on the first surface of the semiconductor layer, the conductive layer forms an electrical connection with the source region through the contact layer, thereby reducing the source contact resistance and improving the reliability of the semiconductor device.

[0025] In some embodiments, a portion of the body region is located below the bottom surface of the trench gate structure, and the drift region separates the bottom surface of the trench gate structure from the portion of the body region, thereby adjusting the electric field distribution near the bottom and corners of the trench and mitigating damage problems caused by excessive electric field concentration at the trench bottom and corners of the gate dielectric layer.

[0026] In some embodiments, the channel drain region, the first portion of the body region, and the source region are vertically arranged adjacent to the first sidewall of the same trench gate structure, and the position of the channel drain region is used to control the length of the channel, thereby improving the uniformity of the channel length, the uniformity of the overlapping portion of the channel with the drain region, and the concentration uniformity of the drain region, thereby improving the overall performance of the device.

[0027] In some embodiments, the distance from the first sidewall of the trench gate structure to the body region gradually increases along the direction from the first surface to the second surface, so that in an on-state of the device, the current path through the source region and the channel to the second surface gradually becomes wider, thereby reducing the conduction resistance and further improving the performance of the device.

[0028] In some embodiments, the gate dielectric layer extends from the interior of the trench to the first surface of the semiconductor layer, thereby protecting a portion of the trench gate structure adjacent to the first surface of the semiconductor layer.

[0029] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and are not intended to limit the present disclosure. [Brief explanation of the drawings]

[0030] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. Obviously, the drawings in the following description are not the limitation of the present disclosure, but are only related to some embodiments of the present disclosure.

[0031] [Figure 1] 1 shows a schematic perspective structural view of a semiconductor device according to a first embodiment of the present disclosure; [Figure 2] 2 shows a schematic cross-sectional view taken along line AA in FIG. 1. [Figure 3] FIG. 2 shows a structural schematic diagram of a semiconductor device according to a second embodiment of the present disclosure. [Figure 4] FIG. 10 shows a structural schematic diagram of a semiconductor device according to a third embodiment of the present disclosure. [Figure 5] FIG. 10 shows a structural schematic diagram of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 6] FIG. 10 shows a structural schematic diagram of a semiconductor device according to a fifth embodiment of the present disclosure. [Figure 7] FIG. 10 shows a structural schematic diagram of a semiconductor device according to a sixth embodiment of the present disclosure. [Figure 8] FIG. 10 shows a structural schematic diagram of a semiconductor device according to a seventh embodiment of the present disclosure. [Figure 9] FIG. 13 shows a structural schematic diagram of a semiconductor device according to an eighth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0032] The present disclosure will now be described in more detail with reference to the drawings. In each drawing, the same elements are represented by the same reference numerals. For clarity, parts of the drawings are not drawn to scale. Also, some known parts may not be shown. For simplicity, a semiconductor structure obtained through several steps may be depicted in one drawing.

[0033] In describing the structure of a device, when a layer or region is referred to as being "on" or "above" another layer or region, it should be understood that it may be directly on top of the other layer or region, or that other layers or regions may be included between the other layer or region. Also, if the device is inverted, the layer or region would be "below" or "below" the other layer or region.

[0034] To describe a layer or region that is directly on top of another layer or region, this specification uses expressions such as "directly on top of" or "on top of and adjacent to."

[0035] Power devices generally include an active device region, an edge termination region, and a crack-stop or blocking region. The active device region includes an active device array. This disclosure relates to active device structures. The dimensions of the active devices may vary depending on product needs, and bulk regions may exist between the active devices within the active device region.

[0036] In the following, many specific details of the present disclosure, such as device structures, materials, dimensions, processing processes, techniques, etc., are set forth to provide a clearer understanding of the present disclosure, but as will be understood by those skilled in the art, the present disclosure may not necessarily be practiced according to these specific details.

[0037] Fig. 1 shows a schematic perspective view of a semiconductor device according to a first embodiment of the present disclosure, and Fig. 2 shows a schematic cross-sectional view taken along line AA in Fig. 1. In Fig. 1, some of the structures on the semiconductor layer are omitted in order to more clearly show the positional relationship between the respective structures.

[0038] As shown in FIGS. 1 and 2 , a semiconductor device according to a first embodiment of the present disclosure includes a semiconductor layer 100, a contact layer 190, a plurality of trench gate structures 150, an interlayer dielectric layer 160, and a conductive layer 170. The semiconductor layer 100 has opposing first and second surfaces 10 and 20, and a plurality of trenches 102 extending from the first surface 10 toward the second surface 20 into the semiconductor layer 100. The plurality of trench gate structures 150 are located in the corresponding trenches 102. The semiconductor layer 100 is, for example, a SiC substrate or a stacked structure including a SiC substrate and an epitaxial layer. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art can provide the semiconductor layer 100 with other materials and with other numbers of layers as needed.

[0039] The semiconductor layer 100 includes a drift region 101, a body region 110, a source region 130, a body contact region 140, and a drain contact region 180. The source region 130 and the drift region 101 are of a first conductivity type, and the body region 110 and the body contact region 140 are of a second conductivity type, with the doping concentration of the body contact region 140 being greater than the doping concentration of the body region 110. The first conductivity type and the second conductivity type are opposite. The first conductivity type is one of P-type and N-type, and the second conductivity type is the other of P-type and N-type.

[0040] The semiconductor device of this embodiment may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), and the conductivity type of the drain contact region 180 may be set to a first conductivity type or a second conductivity type accordingly. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may set other conductivity types of the regions in the semiconductor layer 100 as needed, thereby making the semiconductor device a MOSFET or an IGBT.

[0041] The trench gate structure 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 coats the inner surface of the trench 102, and the gate conductor 152 is located in the trench 102. The gate dielectric layer 151 is located between the semiconductor layer 100 and the gate conductor 152 to separate the semiconductor layer 100 and the gate conductor 152. The trench gate structure 150 has a first sidewall 150a, a second sidewall 150b, and a bottom surface 150c, where the first sidewall 150a and the second sidewall 150b are opposite each other. The trench gate structures 150 extend along the Y-axis direction and are spaced apart along the X-axis direction (which can be considered as the width direction of the trench gate structure 150). Optionally, the X-axis direction, the Y-axis direction, and the Z-axis direction (which is along the direction from the second surface 20 toward the first surface 10) are perpendicular to each other. Alternatively, the X-axis direction is the <11-20> direction or the <1-100> direction, and the plane of the first side wall 102a and the plane of the second side wall 102b are the (11-20) plane or the (1-100) plane.

[0042] The body region 110 includes a first portion 111, a second portion 112, and a third portion 113, which are connected in order along the X-axis direction. The first portion 111 is adjacent to a first sidewall 150a of the trench gate structure 150, the second portion 112 is adjacent to a second sidewall 150b of the trench gate structure 150, and the third portion 113 is located between a bottom surface 150c of the trench gate structure 150 and the second surface 20, and is adjacent to the bottom surface 150c of the trench gate structure 150. An edge of the second portion 112 facing the second surface 20 and an edge of the third portion 113 facing the second surface 20 are substantially flush with each other. Optionally, the first portion 111, the second portion 112, and the third portion 113 have different doping concentrations.

[0043] The source region 130 extends from the first surface 10 toward the second surface 20 of the semiconductor layer 100. The source region 130 and the drift region 101 are separated along the Z-axis direction by a first portion 111 of the body region 110. Between two trench gate structures 150, the source region 130 and the first portion 111 are adjacent to a first sidewall 150a of the same trench gate structure 150.

[0044] Optionally, between the two trench gate structures 150, the source region 130 extends from the first sidewall 150 a of one trench gate structure 150 toward the second sidewall 150 b of the other trench gate structure 150, thereby adjacent to the second portion 112 of the body region 110. When the junction depth of the source region 130 is deep, increasing the width of the source region 130 helps reduce the contact diffusion resistance of the source region 130.

[0045] The body contact region 140 extends in a direction from the first surface 10 toward the second surface 20 of the semiconductor layer 100 and is adjacent to the body region 110. Between two adjacent trench gate structures 150 along the X-axis direction, one end of the body contact region 140 is adjacent to the source region 130 and the other end is close to the second sidewall 150b of the trench gate structure 150 but is not connected to the second sidewall 150b, and the body contact region 140 and the second sidewall 150b are separated by the body region 110. Optionally, the body contact region 140 and the source region 130 are separated by the body region 110.

[0046] Optionally, along the Y-axis direction, a portion of the body contact region 140 is adjacent to the second sidewall 150b, and another portion of the body contact region 140 and the second sidewall 150b are separated by the body region 110 with a gap, and along the Y-axis direction, the portions of the body contact region 140 adjacent to the second sidewall 150b and the portions with the gap are arranged alternately.

[0047] The gate-to-source capacitance is composed of three parts: the capacitance from the gate conductor 152 to the body region 110, the capacitance from the gate conductor 152 to the body contact region 140, and the capacitance from the gate conductor 152 to the source region 130. The source region 130 is electrically connected to the body region 110. Because the body contact region 140 has a higher doping concentration than the body region 110 and therefore a higher capacitance per unit area, the total gate-to-source capacitance can be adjusted by adjusting the area of ​​the second sidewall 150b that directly contacts the body contact region 140. Different applications and system requirements may require different ratios of gate charge or gate-to-drain capacitance / (gate-to-drain capacitance + gate-to-source capacitance). For example, during the turn-off of a hard-switched transistor, the drain voltage may suddenly increase, causing gate self-turn-on behavior due to capacitive coupling. If there is a limited margin for gate self-turn-on, increasing the gate-to-source capacitance can improve the margin.

[0048] The contact layer 190 is located on the first surface 10 of the semiconductor layer 100 and is adjacent to the source region 130 and the body contact region 140, respectively. A portion of the body region 110 is exposed at the first surface 10, and the contact layer 190 is adjacent to this portion of the body region 110 exposed at the first surface 10. The contact layer 190 is a heteroepitaxial layer in the crystal form of the semiconductor layer 100. Optionally, the contact layer 190 includes one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer. The heteroepitaxial layer may be made of other semiconductor crystalline materials or crystalline materials with low in-situ impurity doping. The thickness of the contact layer 190 is at the atomic layer level. For example, the thickness of the buffer layer 190 is one atomic layer thick or two to three atomic layers thick so as not to impart a significant barrier to carrier flow.

[0049] The conductive layer 170 is located on the first surface 100 of the semiconductor layer 100 and adjacent to the contact layer 190. The conductive layer 170 is electrically connected to the body region 110, the source region 130, and the body contact region 140, respectively, through the contact layer 190. The interlayer dielectric layer 160 is located between the semiconductor layer 100 and the conductive layer 170, and the interlayer dielectric layer 160 and the gate structure 150 are correspondingly disposed to separate the conductive layer 170 from the trench gate structure 150.

[0050] In this embodiment, the conductive layer 170 is a source metal layer, and the conductive layer 170 and the interlayer dielectric layer 160 may have a multi-layer structure made of different materials. As an example of a multi-layer source metal layer, the source metal layer includes a tungsten (W) layer directly covering the contact layer 190 and an aluminum copper (AlCu) layer directly covering the tungsten layer. This embodiment may optionally further include a portion not shown, such as connecting the gate conductor 152 and the gate metal layer by opening a gate contact region directly above the gate conductor 152, where the gate contact region is located directly on the gate conductor 152 and the gate conductor 152 is separated from the source metal layer by the interlayer dielectric layer 160.

[0051] In this embodiment, a heteroepitaxial layer, which is a contact layer 190, is disposed on the first surface 10 of the semiconductor layer 100, and the conductive layer 170 forms an electrical connection with the source region 130 through the contact layer 190, thereby reducing the source contact resistance and improving the reliability of the semiconductor device.

[0052] At least a portion of the drift region 101 is located between the body region 110 and the second surface 20, and is adjacent to the second portion 112, the third portion 113 of the body region 110, the bottom surface 102c of the trench gate structure 150, and the drain contact region 180, respectively, and the drain contact region 180 extends from the second surface 20 of the semiconductor layer 100 toward the first surface 10.

[0053] Furthermore, the semiconductor device of this embodiment further includes a drain metal layer (not shown) located on the second surface 20 of the semiconductor layer 100 and connected to the drain contact region 180 .

[0054] In this embodiment, by providing a plurality of recesses 11 on the first surface 10 of the semiconductor layer 100, the conductive layer 170 extends to the recesses 11 adjacent to the first surface 10 of the conductive layer 170, thereby increasing the contact area between the conductive layer 170 and the source region 130 per unit area, reducing the source contact resistance, and improving the reliability of the semiconductor device.

[0055] FIG. 3 shows a structural schematic diagram of a semiconductor device according to a second embodiment of the present disclosure.

[0056] As shown in FIG. 3 , the second embodiment of the semiconductor device of the present disclosure is similar to the first embodiment of the semiconductor device of the present disclosure and will not be further described here. Please refer to the descriptions of FIGS. 1 and 2 for the differences. In this embodiment, along the Z-axis direction, at least a portion of the bottom surface 150 c of the trench gate structure 150 and the third portion 113 of the body region 110 are separated by the drift region 101. Optionally, the third portion 113 is adjacent to the bottom surface 150 c near a corner of the second sidewall 150 b and the bottom surface 150 c. Optionally, the third portion 113 and the bottom surface 150 c are completely separated by the drift region 101. Optionally, the second portion 112 of the body region 110 and the second sidewall 150 b of the trench gate structure 150 are separated by the drift region 101.

[0057] In this embodiment, the drift region 101 separates the bottom surface 150c of the trench gate structure 150 from the third portion 113 of the body region 110, thereby adjusting the electric field distribution near the bottom and corners of the trench 102 and mitigating the damage problem caused by excessive electric field concentration at the bottom and corners of the trench 102 in the gate dielectric layer 151.

[0058] FIG. 4 shows a structural schematic diagram of a semiconductor device according to a third embodiment of the present disclosure.

[0059] As shown in Figure 4, the semiconductor device of the third embodiment of the present disclosure is similar to the first embodiment, and therefore will not be further described here, but please refer to the descriptions of Figures 1 and 2. The differences are as follows: the semiconductor layer 100 of this embodiment further includes a channel drain region 120, which is of a first conductivity type and has a doping concentration greater than that of the drift region 101.

[0060] The channel drain region 120 is located between the first portion 111 of the body region 110 and the drift region 101, such that the source region 130, the first portion 111 of the body region 110, and the channel drain region 120 are adjacent to each other in this order along a direction from the first surface 10 to the second surface 20. Between the two trench gate structures 150, the first portion 111, the channel drain region 120, and the source region 130 are adjacent to a first sidewall 150a of the same trench gate structure 150. The channel drain region 120 is close to a bottom surface 150c of the trench gate structure 150 and adjacent to the second portion 112. The channel drain region 120 and the third portion 113 of the body region 110 are separated by the drift region 101. Optionally, the distance from the edge of the channel drain region 120 in the direction toward the second surface 20 to the first surface 10 is equal to or less than the distance from the bottom surface 150c of the trench gate structure 150 to the first surface 10. Optionally, the distance from the edge of the channel drain region 120 in the direction toward the second surface 20 to the first surface 10 is greater than the distance from the bottom surface 150c of the trench gate structure 150 to the first surface 10, and the channel drain region 120 is adjacent to a portion of the bottom surface 150c of the trench gate structure 150.

[0061] In this embodiment, when the semiconductor device is in an on-state, the conductivity type of the first portion 111 of the body region 110 adjacent to the first sidewall 102a of the trench 102 is inverted, thereby forming a channel. By providing the channel drain region 120 at the bottom surface 150c adjacent to the trench gate structure 150, the length of the channel can be precisely controlled, thereby improving the uniformity of the lengths of the channels in the semiconductor device. Furthermore, providing the channel drain region 120 further improves the uniformity of the portion of the channel overlapping with the drain region and the concentration uniformity of the drain region, thereby improving the overall performance of the device.

[0062] In some specific embodiments, the channel drain region 120 and the source region 130 are formed in the same process step to provide more precise control over the channel length and to further increase the uniformity of the channel length.

[0063] FIG. 5 shows a structural schematic diagram of a semiconductor device according to a fourth embodiment of the present disclosure.

[0064] As shown in FIG. 5 , the semiconductor device of the fourth embodiment of the present disclosure is similar to the third embodiment of the present disclosure and will not be further described here; refer to the description of FIG. 4 . The differences are as follows: In this embodiment, along the Z-axis direction, at least a portion of the bottom surface 150 c of the trench gate structure 150 and the third portion 113 of the body region 110 are separated by the drift region 101. Optionally, the third portion 113 is adjacent to the bottom surface 150 c near a corner of the second sidewall 150 b and the bottom surface 150 c. Optionally, the third portion 113 and the bottom surface 150 c are completely separated by the drift region 101. Optionally, the second portion 112 of the body region 110 and the second sidewall 150 b of the trench gate structure 150 are separated by the drift region 101.

[0065] In this embodiment, the drift region 101 separates the bottom surface 150c of the trench gate structure 150 from the third portion 113, thereby adjusting the electric field distribution near the bottom and corners of the trench 102 and mitigating the damage problem caused by excessive electric field concentration at the bottom and corners of the trench 102 in the gate dielectric layer 151.

[0066] FIG. 6 shows a structural schematic diagram of a semiconductor device according to a fifth embodiment of the present disclosure.

[0067] As shown in FIG. 6, the fifth embodiment of the semiconductor device of the present disclosure is similar to the second embodiment of the semiconductor device of the present disclosure and will not be further described here; refer to the description of FIG. 3. The differences are as follows: In this embodiment, the second portion 112 of the body region 110 includes a first sub-region 112a and a second sub-region 112b that are connected. Along the X-axis direction, the first sub-region 112a is adjacent to the first portion 111 of the body region 110, and the second sub-region 112b is adjacent to the third portion 113 of the body region 110.

[0068] The distance from the edge of the first portion 111 in the direction toward the second surface 20 to the first surface 10 is a first distance d1, the distance from the edge of the first sub-region 112a in the direction toward the second surface 20 to the first surface 10 is a second distance d2, and the distance from the edge of the second sub-region 112b in the direction toward the second surface 20 to the first surface 10 is a third distance d3, where the third distance d3 is greater than the second distance d2 and the second distance d2 is greater than the first distance d1.

[0069] In this embodiment, by adjusting the distance d2 from the bottom edge of the first sub-region 112a to the first surface, the edge of the body region 110 adjacent to the first sidewall 150a becomes stepped, and the distance from the first sidewall 150a to the second portion 112 of the body region 110 gradually increases along the direction from the first surface 10 to the second surface 20. In this way, when the device is on, the current path through the source region 130 and the channel to the second surface 20 gradually widens, thereby reducing the conduction resistance and further improving the performance of the device.

[0070] Optionally, the distance from the bottom surface 150c of the trench gate structure 150 to the first surface 10 is a fourth distance d4, and the second distance d2 is greater than or equal to the fourth distance d4, thereby reducing the effect of the high electric field experienced by the bottom of the trench 102.

[0071] Optionally, the distance along the Z-axis direction by which the third portion 111 of the body region 110 and the bottom surface 150c of the trench gate structure 150 are separated by the drift region 101 is a fifth distance d5, and the sum of the fourth distance d4 and the fifth distance d5 is equal to the second distance d2, so that the bottom surface 112-1 of the second sub-region 112b and the separation surface 113-1 of the third portion 113 of the body region 110 are substantially flush with each other. This allows the depth of the second sub-region 112b to be controlled to an appropriate degree, and prevents the second distance d2 from being too large and limiting the effectiveness of charge compensation in reducing on-resistance.

[0072] FIG. 7 shows a structural schematic diagram of a semiconductor device according to a sixth embodiment of the present disclosure.

[0073] 7, the sixth embodiment of the semiconductor device of the present disclosure is similar to the third embodiment, and therefore will not be further described here. Please refer to the description of FIG. 4 for the differences. In this embodiment, the second portion 112 of the body region 110 includes a first sub-region 112a and a second sub-region 112b that are connected. Along the X-axis direction, the first sub-region 112a is adjacent to the first portion 111 of the body region 110, and the second sub-region 112b is adjacent to the third portion 113 of the body region 110.

[0074] The distance from the edge of the first portion 111 in the direction toward the second surface 20 to the first surface 10 is a first distance d1, the distance from the edge of the first sub-region 112a in the direction toward the second surface 20 to the first surface 10 is a second distance d2, and the distance from the edge of the second sub-region 112b in the direction toward the second surface 20 to the first surface 10 is a third distance d3, where the third distance d3 is greater than the second distance d2 and the second distance d2 is greater than the first distance d1.

[0075] In this embodiment, by adjusting the distance d2 from the bottom edge of the first sub-region 112a to the first surface, the edge of the body region 110 adjacent to the first sidewall 150a becomes stepped, and the distance from the first sidewall 150a to the second portion 112 of the body region 110 gradually increases along the direction from the first surface 10 to the second surface 20. In this way, when the device is on, the current path through the source region 130 and the channel to the second surface 20 gradually widens, thereby reducing the conduction resistance and further improving the performance of the device.

[0076] Optionally, the distance from the edge of the channel drain region 120 toward the second surface 20 to the first surface 10 is a sixth distance d6, the sixth distance d6 being greater than the second distance d2, and the third distance d3 being greater than the sixth distance d6, whereby a portion of the channel drain region 120 and the second sub-region 112b are separated by the drift region 101 along the X-axis direction.

[0077] FIG. 8 shows a structural schematic diagram of a semiconductor device according to a seventh embodiment of the present disclosure.

[0078] As shown in FIG. 8 , the seventh embodiment of the present disclosure is similar to the sixth embodiment of the semiconductor device, and therefore will not be further described here. Please refer to the description of FIG. 7 for the differences. In this embodiment, along the Z-axis direction, at least a portion of the bottom surface 150 c of the trench gate structure 150 and the third portion 113 of the body region 110 are separated by the drift region 101. Optionally, the third portion 113 is adjacent to the bottom surface 150 c near a corner of the second sidewall 150 b and the bottom surface 150 c. Optionally, the third portion 113 and the bottom surface 150 c are completely separated by the drift region 101. Optionally, the second portion 112 of the body region 110 and the second sidewall 150 b of the trench gate structure 150 are separated by the drift region 101.

[0079] In this embodiment, the drift region 101 separates the bottom surface 150c of the trench gate structure 150 from the third portion 113, thereby adjusting the electric field distribution near the bottom and corners of the trench 102 and mitigating the damage problem caused by excessive electric field concentration at the bottom and corners of the trench 102 in the gate dielectric layer 151.

[0080] FIG. 9 shows a structural schematic diagram of a semiconductor device according to an eighth embodiment of the present disclosure.

[0081] As shown in Figure 9, the semiconductor device of the eighth embodiment of the present disclosure is similar to the first embodiment, and therefore will not be further described here, and reference may be made to the descriptions of Figures 1 and 2. The differences are as follows: in this embodiment, a portion of the trench gate structure 150 is located within the trench 102, and another portion is located above the first surface 10. Specifically, the gate dielectric layer 151 covers the inner surface of the trench 102 and a portion of the first surface 10 adjacent to the trench 102, and a portion of the gate conductor 152 is located in the trench 102, and another portion extends outside the trench 102 and covers the gate dielectric layer 151 located on the first surface 10.

[0082] The trench gate structure 150 of this embodiment extends from inside the trench 102 to the first surface 10, protecting the portion of the first surface 10 adjacent to the trench 102 and reducing damage to the portion of the first surface 10 adjacent to the trench 102 during manufacturing.

[0083] Optionally, in the semiconductor device of the eighth embodiment of the present disclosure, as in the second, fourth, fifth, and seventh embodiments of the present disclosure, at least a portion of the bottom surface 150c of the trench gate structure 150 and the third portion 113 may be separated by a drift region 101 along the Z-axis direction.

[0084] Optionally, in the semiconductor device of the eighth embodiment of the present disclosure, a channel drain region 120 may be provided as in the third, fourth, sixth and seventh embodiments of the present disclosure.

[0085] Optionally, in the semiconductor device of the eighth embodiment of the present disclosure, the first sub-region 112a and the second sub-region 112b may be provided as in the fifth, sixth, and seventh embodiments of the present disclosure.

[0086] The above describes the embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is limited by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. 1. A semiconductor device comprising: a semiconductor layer; a trench gate structure; a contact layer; and a conductive layer, the semiconductor layer having opposing first and second surfaces, and at least a portion of the trench gate structure located in a trench in the first surface of the semiconductor layer; The semiconductor layer is a source region extending from the first surface toward the second surface; a drift region and a body region, at least a portion of the drift region being located between the body region and the second surface of the semiconductor layer; a first portion of the body region is located between the source region and the drift region along a direction from the first surface toward the second surface, and both the first portion of the body region and the source region are adjacent to a first sidewall of the trench; the contact layer is a heteroepitaxial layer of the semiconductor layer, located on a first surface of the semiconductor layer and adjacent to the source region; the conductive layer is adjacent to the contact layer and is electrically connected to the source region via the contact layer; A semiconductor device, wherein the source region and the drift region are of a first conductivity type, and the body region is of a second conductivity type, and the first conductivity type and the second conductivity type are opposite.

2. The semiconductor device of claim 1 , wherein the semiconductor layer comprises a SiC semiconductor layer, and the contact layer comprises one or more of a Si layer, a SiGe layer, a GaN layer, and a GaAs layer.

3. The semiconductor device of claim 1 , wherein the thickness of the contact layer comprises a thickness of one or more atomic layers.

4. The semiconductor device of claim 1 , wherein the contact layer is a crystalline structure.

5. the first portion, the second portion, and the third portion of the body region are adjacent to each other in order along a width direction of the trench gate structure; the first and second portions of the body region are located between two of the trench gate structures, the first portion is adjacent to a first sidewall of the trench gate structure, the second portion is adjacent to a second sidewall of the trench gate structure, and the first sidewall and the second sidewall face each other; the third portion and the second portion are adjacent to the same trench gate structure, and the third portion is located between a bottom surface of the trench gate structure and the second surface, and the third portion and the first portion are separated by the drift region; The semiconductor device of claim 1 , wherein the second portion is adjacent to the second sidewall, or the second portion and the second sidewall are separated by the drift region.

6. a third portion of the body region extending from a bottom surface of the trench gate structure toward the second surface; or 6. The semiconductor device of claim 5, wherein a bottom surface of at least a portion of the trench gate structure and a third portion of the body region are separated by the drift region along a direction from the first surface toward the second surface.

7. the second portion of the body region includes a first sub-region and a second sub-region that are connected; Along a width direction of the trench gate structure, the first sub-region is adjacent to a first portion of the body region, and the second sub-region is adjacent to a third portion of the body region; a distance from an edge of the first portion of the body region in a direction toward the second surface to the first surface is a first distance, a distance from an edge of the first sub-region in a direction toward the second surface to the first surface is a second distance, and a distance from an edge of the second sub-region in a direction toward the second surface to the first surface is a third distance; The semiconductor device of claim 6 , wherein the third distance is greater than the second distance, and the second distance is greater than the first distance.

8. 8. The semiconductor device of claim 7, wherein a distance from a bottom surface of the trench gate structure to the first surface is a fourth distance, and the second distance is greater than or equal to the fourth distance.

9. a distance from a bottom surface of the trench gate structure to the first surface along a direction from the second surface to the first surface is a fourth distance, and a distance by which the third portion of the body region and the bottom surface of the trench gate structure are separated by the drift region is a fifth distance; The semiconductor device of claim 7 , wherein the sum of the fourth distance and the fifth distance is equal to the second distance.

10. an edge of the second portion of the body region facing the second surface and an edge of the third portion of the body region facing the second surface are connected; or The semiconductor device of any one of claims 5 to 9, wherein an edge of the third portion toward the second surface is closer to the second surface than an edge of the second portion toward the second surface.

11. the semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, whereby the source region, the first portion of the body region, and the channel drain region are adjacent to each other in order along a direction from the first surface to the second surface and are all adjacent to a first sidewall of the trench gate structure; the channel drain region is further adjacent to the drift region and the second portion of the body region, respectively, and the channel drain region and the third portion of the body region are separated by the drift region; The semiconductor device of any one of claims 1 to 9, wherein the channel drain region is of a first conductivity type.

12. The semiconductor device of claim 11 , wherein the channel drain region has a doping concentration greater than a doping concentration of the drift region.

13. a distance from an edge of the channel drain region in a direction toward the second surface to the first surface is equal to or less than a distance from a bottom surface of the trench gate structure to the first surface; or 12. The semiconductor device of claim 11, wherein a distance from an edge of the channel drain region toward the second surface to the first surface is greater than a distance from a bottom surface of the trench gate structure to the first surface, and the channel drain region is adjacent to a portion of the bottom surface of the trench gate structure.

14. the semiconductor layer further includes a channel drain region located between the first portion of the body region and the drift region, whereby the source region, the first portion of the body region, and the channel drain region are adjacent to each other in order along a direction from the first surface to the second surface and are all adjacent to a first sidewall of the trench gate structure; the channel drain region is further adjacent to the drift region and the second portion of the body region, respectively, and the channel drain region and the third portion of the body region are separated by the drift region; the channel drain region is of a first conductivity type; a distance from an edge of the channel drain region in a direction toward the second surface to the first surface is a sixth distance; 8. The semiconductor device of claim 7, wherein the sixth distance is greater than the second distance and the third distance is greater than the sixth distance, whereby the channel drain region and the second sub-region are separated by the drift region along a width direction of the trench gate structure.

15. the semiconductor layer further includes a body contact region, the body contact region extending from the first surface toward the second surface, the body contact region adjacent to the body region; the body contact region is adjacent to the source region or separated by the body region; The semiconductor device of any one of claims 1 to 9, wherein the body contact region is of a second conductivity type.

16. a portion of the body contact region is adjacent to a second sidewall of the trench gate structure along an extension direction of the trench gate structure, and a gap is formed between another portion of the body contact region and the second sidewall, and the portion of the body contact region adjacent to the second sidewall and the portion having the gap are alternately arranged along the extension direction of the trench gate structure; Alternatively, the body contact region and the second sidewall are both separated by the body region.

17. the trench gate structure includes the gate dielectric layer and a gate conductor; the gate dielectric layer covers an inner surface of the trench and a portion of the first surface adjacent to the trench, the trench extending from the first surface toward the second surface; a portion of the gate conductor is located in the trench and another portion extends outside the trench and covers the gate dielectric layer; The semiconductor device of any one of claims 1 to 9, wherein the gate dielectric layer is located between the gate conductor and the semiconductor layer so as to separate the gate conductor and the semiconductor layer.

18. The semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is a metal-oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

19. 10. The semiconductor device of claim 5, wherein the source region extends between two of the trench gate structures from a first sidewall of one of the trench gate structures toward a second sidewall of the other of the trench gate structures and is adjacent to a second portion of the body region.

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