Hybrid image sensor having both segmented and square light detection pixels

Abstract

To provide various configurations of hybrid pixel arrays.SOLUTION: A hybrid pixel array includes a combination of a square photodiode (PD) pixel structure and a split PD pixel structure. The square PD pixel structure includes one photodiode per pixel unit, while the split PD pixel structure includes two photodiodes per pixel unit. In a specific example, the hybrid pixel array uses a square PD pixel structure for green light pixels and a split PD pixel structure for blue light pixels and red light pixels. The combination of the square PD pixel structure and the split PD pixel structure provides autofocus capabilities with higher signal strength. Various techniques for row addressing and readout from the hybrid pixel array are also disclosed.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates generally to image sensors, and more particularly to pixel designs for capturing light on image sensors having hybrid pixel light detection capabilities.

[0002] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Patent Application No. 63 / 649,856, filed May 20, 2024, entitled "Hybrid Image Sensor with Both Split Photodetection and Square Photodetection Pixels," the disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0003] Image capture devices such as cameras are widely used in various electronic devices, such as mobile devices (e.g., smartphones, tablets, laptops, etc.), robotic equipment, or security surveillance devices, among others. An image capture device may include an image sensor having a plurality of light-gathering pixels. The pixels may include photodiodes. The image capture device can capture light from the environment and pass the light to the image sensor. When exposed to light, the photodiodes of the pixels can accumulate photoelectrons. A digital image can be generated from an array of pixels by reading analog signals (e.g., voltage signals) from the pixels, converting the analog signals to digital signals, and then processing the digital signals with an image signal processor to generate the digital image. There are various types of pixel structures that can be implemented in a pixel array. A pixel array typically includes pixel structures that are all the same across the array to simplify processing and programming (e.g., addressing and reading) of the pixel array. While having the same pixel structure across the pixel array can simplify processing and programming, performance trade-offs can be made between using different types of pixel structures within the pixel array. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 2 is a top view of an exemplary pixel array having a square PD pixel structure, according to some embodiments.

[0005] [Figure 2] 1 is an illustrative schematic diagram of a portion of a pixel array according to some embodiments.

[0006] [Figure 3] FIG. 2 is a top view of an exemplary pixel array having a split PD pixel structure, according to some embodiments.

[0007] [Figure 4] 1 is an illustrative schematic diagram of a portion of a pixel array according to some embodiments.

[0008] [Figure 5] FIG. 1 is a top view of a contemplated hybrid pixel array, according to some embodiments.

[0009] [Figure 6] 1 is an illustrative schematic diagram of a portion of a pixel array according to some embodiments.

[0010] [Figure 7] FIG. 1 is a top view of another contemplated hybrid pixel array, according to some embodiments.

[0011] [Figure 8] 1 is an illustrative schematic diagram of a portion of a pixel array according to some embodiments.

[0012] [Figure 9] 1 is a circuit layout for addressing and readout of a pixel array, according to some embodiments.

[0013] [Figure 10]4 illustrates a timing diagram of the operation of transistors in a pixel array according to some embodiments.

[0014] [Figure 11] FIG. 10 is a top view of yet another contemplated hybrid pixel array, according to some embodiments.

[0015] [Figure 12] 1 is an exemplary process flow for forming a hybrid pixel array structure according to some embodiments.

[0016] [Figure 13] 1 is a schematic diagram of an exemplary image sensor, according to some embodiments.

[0017] [Figure 14] 1 is a flowchart illustrating an exemplary method for processing image signals of an image sensor to generate a digital image, according to some embodiments.

[0018] [Figure 15] 1 shows a schematic diagram of an exemplary device that may include an image capture device (e.g., a camera) having an image sensor, according to some embodiments.

[0019] [Figure 16] 1 shows a schematic block diagram of an exemplary computing device that may include or host an embodiment of an image capture device (e.g., a camera) having an image sensor, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0020] This specification includes references to "one embodiment" or "an embodiment." Appearances of the phrases "in one embodiment" or "in an embodiment" do not necessarily refer to the same embodiment. The particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0021] "Comprising." This term is open-ended. When used in the following claims, it does not exclude additional structures or steps. Consider a claim that recites "an apparatus comprising one or more processor units...." Such a claim does not exclude the apparatus from including additional components (e.g., a network interface unit, graphics circuitry, etc.).

[0022] "Configured to." Various units, circuits, or other components may be described or claimed as being "configured to" perform a task or tasks. In this context, "configured to" is used to connote structure by indicating that the unit / circuit / component includes structure (e.g., a circuit) that, when operational, performs those task(s). In this manner, a unit / circuit / component can be said to be configured to perform a task even when the specified unit / circuit / component is not currently operational (e.g., not turned on). A unit / circuit / component used with the phrase "configured to" includes hardware, e.g., circuits, memory that stores executable program instructions to perform an operation, etc. It is expressly intended that a statement that a unit / circuit / component is "configured to" perform one or more tasks does not invoke 35 U.S.C. § 112(f) with respect to that unit / circuit / component. Additionally, "configured to" can include general-purpose structure (e.g., general-purpose circuitry) that is manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor running software) to operate in a manner capable of performing the task(s) in question. "Configured to" may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to produce a device (e.g., an integrated circuit) that is adapted to perform or execute one or more tasks.

[0023] As used herein, "first," "second," etc., are used as labels for the nouns they precede and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, a buffer circuit may be described herein as performing write operations on "first" and "second" values. The terms "first" and "second" do not necessarily imply that the first value must be written before the second value.

[0024] "Based on." As used herein, this term is used to describe one or more factors that influence a decision. This term does not exclude additional factors that may influence the decision. That is, the decision may be based solely on those factors, or may be based at least in part on those factors. Consider the phrase "determining A based on B." In this case, B is a factor that influences the decision on A, but such phrase does not exclude that the decision on A is also based on C. In other cases, A may be determined solely on B.

[0025] In this specification, terms such as "first," "second," etc. may be used to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact, without departing from the intended scope. Although the first contact and the second contact are both contacts, they are not the same contact.

[0026] The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Also, as used herein, the term "and / or" should be understood to refer to and encompass any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0027] As used herein, the term "if" can be interpreted to mean "when" or "upon," or "in response to determining," or "in response to detecting," depending on the context. Similarly, the phrase "when it is determined" or "when [a stated condition or event] is detected" can be interpreted to mean "determined to" or "in response to determining" [a stated condition or event], or "upon detecting" [a stated condition or event], or "in response to detecting" [a stated condition or event], depending on the context.

[0028] Various embodiments described herein relate to image sensors having a combination of different types of pixel structures. In particular embodiments, the image sensor includes a pixel array having a combination of square photodiode (PD) pixel structures and split photodiode (PD) pixel structures. A square PD pixel structure is a pixel structure having one photodiode per pixel structure unit. A split PD pixel structure is a pixel structure having two photodiodes per pixel structure unit. A split PD pixel structure typically has rectangular photodiodes that each occupy half the area of ​​the pixel structure unit. An image sensor having both square PD pixel structures and split PD pixel structures can utilize the advantages of both types of pixel structures while reducing the trade-offs associated with having only one type of pixel structure on the image sensor.

[0029] FIG. 1 is a top view of an exemplary pixel array having square PD pixel structures, according to some embodiments. In the illustrated embodiment, pixel array 100 includes square PD pixel structures 110A-P. For square PD pixel structures 110, each square PD pixel structure 110 includes one photodiode (not shown) inside its square perimeter. Thus, pixel array 100 includes one photodiode per square unit (defined by the perimeter shape of pixel structure 110). In addition, each square PD pixel structure 110A-P includes a corresponding lens 120A-P within pixel array 100. Lens 120 may be, for example, a microlens or other lens structure for focusing light onto the photodiode within square PD pixel structure 110.

[0030] In some embodiments, pixel array 100 is a color filter array having a combination of red (R), green (G), and blue (B) pixel structures (e.g., the color filter array is an RGB filter array). The red pixel structures include photodiodes that accumulate photoelectrons when exposed to red light (e.g., light in the red light spectrum wavelength). The green pixel structures include photodiodes that accumulate photoelectrons when exposed to green light (e.g., light in the green light spectrum wavelength). The blue pixel structures include photodiodes that accumulate photoelectrons when exposed to blue light (e.g., light in the blue light spectrum wavelength).

[0031] In various embodiments, because the human eye has a more tuned (e.g., enhanced) sensitivity to green light spectrum wavelengths, pixel array 100 may include more green pixel structures to accommodate the behavior of the human eye in collecting light to generate an image. Additionally, in some lighting conditions (such as outdoors or bright indoor areas), green light spectrum wavelengths may have stronger intensity compared to red or blue light spectrum wavelengths. Therefore, having more green pixel structures may improve the quality of images generated by an image sensor including pixel array 100.

[0032] In the embodiment shown in FIG. 1 , pixel structures 110A-D and 110M-P are green pixel structures, pixel structures 110E-H are blue pixel structures, and pixel structures 110I-L are red pixel structures. Thus, pixel array 100 includes eight green pixel structures, four blue pixel structures, and four red pixel structures. However, it should be understood that any number or combination of different color pixel structures may be implemented in pixel array 100. Additionally, because pixel array 100 includes square PD pixel structures 110A-P, the pixel array does not have phase detection auto-focus (PDAF) capability. PDAF capability may be implemented for pixel array 100 by adding an optical shield (described herein) or a multi-pixel on-chip lens (OCL) to one or more pixel structures 110 in the pixel array.

[0033] FIG. 2 is an exemplary schematic diagram of a portion of pixel array 100, according to some embodiments. In the illustrated embodiment, schematic diagram 200 is provided for portion 130 of pixel array 100 (shown in dashed lines in FIG. 1). As shown in FIG. 1, portion 130 includes pixel structures 110A-D and pixel structures 110I-L. As shown in FIG. 2, schematic diagram 200 includes photodiodes (PDs) 210A-D and 210I-L, respectively, corresponding to pixel structures 110A-D and pixel structures 110I-L of FIG. 1. Each PD 210A-D and PD 210I-L has its own corresponding transfer gate (TG) 220A-D and TG 220I-L, respectively.

[0034] The TGs 220A-D are coupled to each other at a floating diffusion (FD) region 225A, while the TGs 220I-L are coupled to each other at a floating diffusion (FD) region 225B. The FD region 225A is coupled to a reset gate (RST) 230A, a source follower (SF) transistor 240A, and a row selector (RS) transistor 250A. The FD region 225B is coupled to a reset gate (RST) 230B, a source follower (SF) transistor 240B, and a row selector (RS) transistor 250B. An output 260 is coupled to the outputs of RS 250A and RS 250B. Correspondingly, the output 260 can be a single output connected to both sets of pixel structures corresponding to the set of photodiodes (PDs) 210A-D and the set of PDs 210I-L. In a particular embodiment, the photodiodes (PDs) 210 and floating diffusion (FD) regions 225 are formed in the substrate of the pixel array, while the gates / transistors are formed above the substrate (e.g., the transfer gates (TGs) 220, reset gates (RSTs) 230, source follower (SF) transistors 240, and row selector (RS) transistors 250 are formed above the substrate).

[0035] FIG. 3 is a top view of an exemplary pixel array having a split-PD pixel structure, according to some embodiments. In the illustrated embodiment, pixel array 300 includes split-PD pixel structures 310A-P. For split-PD pixel structures 310, each split-PD pixel structure 310 has two photodiodes (PDs) 315A / 315B inside its square perimeter. Thus, pixel array 300 has two photodiodes per square unit (defined by the peripheral shape of pixel structure 310). Note that for simplicity of illustration, only PDs 315A / 315B are identified in FIG. 3 for split-PD pixel structure 310A. In various embodiments, PDs 315A and 315B are rectangular photodiodes that occupy half the area of ​​the square unit of pixel structure 310. For example, as shown in FIG. 3, PDs 315A and 315B are separated by a vertical line that passes through the center of split-PD pixel structure 310A. Correspondingly, vertical lines passing through the remaining split PD pixel structures 310B-P may delineate the corresponding photodiodes within each pixel structure.

[0036] Similar to the square PD pixel structure of FIG. 1, each split PD pixel structure 310A-P includes a corresponding lens 320A-P in pixel array 300. Lens 320 may be, for example, a microlens or other lens structure for focusing light onto both photodiodes 315A / 315B in split PD pixel structure 310. Similar to pixel array 100, pixel array 300 may be a color filter array having a combination of red (R), green (G), and blue (B) pixel structures (e.g., the color filter array is an RGB filter array). In the embodiment shown in FIG. 3, pixel structures 310A-D and 310M-P are green pixel structures, pixel structures 310E-H are blue pixel structures, and pixel structures 310I-L are red pixel structures. Thus, pixel array 300 includes eight green pixel structures, four blue pixel structures, and four red pixel structures. However, it should be understood that pixel array 300 may be implemented with any number or combination of different color pixel structures.

[0037] Due to the implementation of split photodiodes (e.g., PD315A and PD315B) in each split PD pixel structure 310A-P, pixel array 300 supports PDAF. PDAF is inherently supported in pixel array 300 because the dual photodiodes in each pixel structure 310 enable detection of the signal difference between the left photodiode (e.g., PD315A) and the right photodiode (e.g., PD315B). The signal difference can be a function of the angle of the incident light. Correspondingly, the phase and corresponding focus can be determined based on the signal difference between the left and right photodiodes.

[0038] FIG. 4 is an exemplary schematic diagram of a portion of pixel array 300, according to some embodiments. In the illustrated embodiment, schematic diagram 400 is provided for portion 330 of pixel array 300 (shown in FIG. 3 by dashed lines). As shown in FIG. 3, portion 330 includes pixel structures 310A-D and pixel structures 310I-L. As shown in FIG. 4, schematic diagram 400 includes photodiodes (PD) 410A-D and photodiodes (PD) 410I-L, which correspond to pixel structures 310A-D and pixel structures 310I-L, respectively, from FIG. 3. Note that in FIG. 4, each photodiode (PD) 410 includes a pair of photodiodes. For example, photodiode (PD) 410 includes a left (L) photodiode and a right (R) photodiode, indicated by the symbols "L" and "R" in FIG. 4. Correspondingly, the left and right photodiode pairs in PDs 410A-D and PDs 210I-L have their own corresponding left and right pairs of transfer gates (TG) 420A-D and TGs 420I-L, respectively.

[0039] The left and right pairs of transfer gates (TG) 420A-D are coupled to each other at a floating diffusion (FD) region 425A, while the left and right pairs of transfer gates (TG) 420I-L are coupled to each other at a floating diffusion (FD) region 425B. The FD region 425A is coupled to a reset gate (RST) 430A, a source follower (SF) transistor 440A, and a row selector (RS) transistor 450A. The FD region 425B is coupled to a reset gate (RST) 430B, a source follower (SF) transistor 440B, and a row selector (RS) transistor 450B. An output 460 is coupled to the outputs of RS 450A and RS 450B. Correspondingly, the output 460 may be a single output connected to both sets of pixel structures corresponding to the sets of pairs of photodiodes (PD) 410A-D and PDs 410I-L.

[0040] As described above, autofocus capability can be added to a pixel array 100 implementing a square PD pixel structure 110 by adding an optical shield (or multi-pixel OCL) to some of the pixel structures. The added optical shield is limited to a small portion (e.g., approximately 10%) of the overall area of ​​the pixel array 100 to maintain normal light-sensing functionality within the pixel array. Correspondingly, a pixel array 300 implementing a split PD pixel structure 310 may provide better autofocus performance (e.g., using PDAF) than a pixel array 100 with an optical shield. The pixel array 300 may have better autofocus performance because 100% (or nearly 100%) of the pixel structure is used for autofocus detection, while only a small portion (e.g., 10%) of the pixel array 100 is usable for autofocus detection.

[0041] However, pixel array 100 may have a larger photodiode detection area and simpler readout circuitry than pixel array 300 due to the use of square PD pixel structure 110. The larger photodiode detection area and simpler readout circuitry of square PD pixel structure 110 may provide better signal-to-noise, better dynamic range, and response uniformity than would be obtained if split PD pixel structure 310 were implemented. Because current devices implement pixel arrays with either square PD pixel structures or split PD pixel structures, image sensor designers often must make a decision as to which pixel array to use in a particular device based on the trade-offs of using one type of pixel structure or the other.

[0042] To address these current challenges in implementing pixel arrays within image sensors, this disclosure contemplates pixel array embodiments that implement both square and split PD pixel structures, along with corresponding operation of such pixel arrays. Having a combination of square and split PD pixel structures (e.g., a hybrid structure) can address the performance tradeoffs of having only one type of pixel structure. For example, a hybrid pixel array structure having both square and split PD pixel structures can perform autofocus with better performance than a pixel array structure with only square PD pixels, while also having a higher signal-to-noise ratio, better dynamic range, and response uniformity than a pixel array structure with only split PD pixels. The hybrid pixel array structures described herein can have various arrangements of the square and split PD pixel structures. The arrangements can further include variations in color options for the different PD pixel structures. Timing schemes for readout of signals from the hybrid pixel array structure are also described herein.

[0043] 5 is a top view of a contemplated hybrid pixel array according to some embodiments. In particular embodiments, pixel array 500 includes photodiodes and other components formed in a substrate, such as a silicon substrate. In various embodiments, pixel array 500 is part of an image sensor on an image capture device. The image sensor can be part of devices including, but not limited to, a camera, a mobile device (e.g., a smartphone, a tablet, a laptop, etc.), a robotic device, or a security surveillance device.

[0044] In the illustrated embodiment, pixel array 500 includes two sets of square PD pixel structures, namely, square PD pixel structures 510A-D and square PD pixel structures 510M-P, along with two sets of split PD pixel structures, namely, split PD pixel structures 520E-H and split PD pixel structures 520I-L. Square PD pixel structure 510 includes one photodiode (PD) 515 inside the square perimeter of the pixel structure, while split PD pixel structure 520 includes two photodiodes, PD 525A and PD 525B, inside the square perimeter of the pixel structure. Thus, pixel array 500 includes both pixel structures with one photodiode per square unit and pixel structures with two photodiodes per square unit. Note that for simplicity of illustration, only PD 515 is identified in square PD pixel structure 510A in FIG. 5 . Similarly, only PD 525A and PD 525B are identified in split PD pixel structure 520E in FIG. 5 . In various embodiments, PD 515 is a square photodiode that occupies the entire area of ​​the square unit of pixel structure 510, and PD 525A and PD 525B are rectangular photodiodes that occupy half of the area of ​​the square unit of pixel structure 520. As shown in Figure 5, PD 525A and PD 525B are separated by a vertical line that passes through the center of split PD pixel structure 520E. Correspondingly, vertical lines that pass through the remaining split PD pixel structures 520F-L may delineate corresponding photodiodes within each split PD pixel structure.

[0045] In various embodiments, both the square PD pixel structures 510A-D and 510M-P and the split PD pixel structures 520E-L have corresponding lenses 530A-P in the pixel array 500. The lenses 530 may be, for example, microlenses or other lens structures for focusing light onto the photodiode(s) in the pixel structures. In particular embodiments, the pixel array 500 is a color filter array having a combination of red (R), green (G), and blue (B) pixel structures (e.g., the color filter array is an RGB filter array). In some embodiments, the square PD pixel structure 510 is a green pixel structure, while the split PD pixel structure 520 is used for blue or red pixel structures. Other embodiments may be contemplated in which the square PD pixel structure 510 and / or the split PD pixel structure 520 are pixel structures of colors other than those described herein. For example, embodiments using monochrome pixel structures, clear pixel structures, or yellow pixel structures (e.g., in a red / yellow / blue image sensor) may be contemplated. Additionally, the locations and patterns of the square PD pixel structures 510 and split PD pixel structures 520 within the pixel array may be varied from those shown by way of example in FIG. 5 (and FIG. 7, described below). The patterns of the square PD pixel structures 510 and split PD pixel structures 520 may be regular or irregular.

[0046] In the embodiment shown in FIG. 5 , pixel array 500 is a quadra color filter array (CFA). In a quadra CFA, pixel array 500 includes a total of eight square PD pixel structures 510A-D and 510M-P, which are green pixel structures, four split PD pixel structures 520E-H, which are blue pixel structures, and four split PD pixel structures 520I-L, which are red pixel structures. As mentioned above, pixel array 500 may have more green pixels to increase the signal response to green light relative to blue or red light. This pattern of pixel array 500 may be repeated across multiple pixel arrays to form larger pixel arrays for implementation as a quadra CFA in an image sensor. Embodiments are contemplated in which the number of square PD pixel structures and the number of split PD pixel structures are unequal across the pixel array. For example, in a quadra CFA, the repeating pattern may include 12 split PD pixel structures and four square PD pixel structures. In such an embodiment, some of the split PD pixel structures can be green pixel structures to allow for higher green light sensitivity.

[0047] FIG. 6 is an exemplary schematic diagram of a portion of pixel array 500, according to some embodiments. In the illustrated embodiment, schematic diagram 600 is provided for portion 540 of pixel array 500 (shown by the dashed line in FIG. 5 ). As shown in FIG. 5 , portion 540 includes square PD pixel structures 510A-D and split PD pixel structures 520I-L. As shown in FIG. 6 , schematic diagram 600 includes photodiodes (PD) 610A-D and photodiodes (PD) 610I-L, which correspond to square PD pixel structures 510A-D and split PD pixel structures 520I-L, respectively, from FIG. 5 . Note that in FIG. 6 , photodiodes (PD) 610A-D include single photodiodes, while photodiodes 610I-L include pairs of photodiodes, indicated in FIG. 6 by the symbols “L” and “R” as left (L) and right (R) photodiodes. The photodiodes 610A-D have their corresponding target gates (TG) 620A-D, while the photodiodes 610I-L have corresponding left and right pairs of transfer gates (TG) 620I-L.

[0048] Transfer gates (TG) 620A-D are coupled to each other at a floating diffusion (FD) region 625A, while left and right pairs of transfer gates (TG) 620I-L are coupled to each other at a floating diffusion (FD) region 625B. FD region 625A is coupled to a reset gate (RST) 630A, a source follower (SF) transistor 640A, and a row selector (RS) transistor 650A. Output 660 is coupled to the output of RS 650A to provide outputs from the square PD pixel structures corresponding to the photodiodes (PD) 610A-D. FD region 625B is coupled to a reset gate (RST) 630B, a source follower (SF) transistor 640B, and a row selector (RS) transistor 650B. Output 670 is coupled to the output of RS 650B to provide outputs from the split PD pixel structures corresponding to the left / right pairs of photodiodes (PD) 610I-L. Correspondingly, outputs 660 and 670 may be separate outputs of two different types of pixel structures implemented in pixel array 500, namely, a square PD pixel structure and a split PD pixel structure. As described herein, having separate outputs from different types of pixel structures may allow the pixel structures to be separately addressed and read out therefrom. Separating signal outputs between different types of pixel structures may allow separate signal processing (e.g., analog-to-digital conversion) to be performed on the readout signals. Separating addressing of different types of pixel structures may allow separate row addressing units and timing signals to be provided to the different types of pixel structures. In some contemplated embodiments, addressing and readout may be handled via a single output.

[0049] 7 is a top view of another contemplated hybrid pixel array, according to some embodiments. In a particular embodiment, pixel array 700 includes photodiodes and other components formed in a substrate, such as a silicon substrate. In various embodiments, pixel array 700 is part of an image sensor on an image capture device. The image sensor may be part of a device including, but not limited to, a camera, a mobile device (e.g., a smartphone, a tablet, a laptop, etc.), a robotic device, or a security surveillance device.

[0050] In the illustrated embodiment, pixel array 700 includes an alternating pattern of square PD pixel structures 710 and split PD pixel structures 720. The basic alternating pattern is a set of four pixels (e.g., pixel units A-D) including two square PD pixel structures at opposite corners (e.g., square PD pixel structures 710A / D) and two split PD pixel structures at opposite corners (e.g., split PD pixel structures 720B / C). This basic pattern can be repeated throughout pixel array 700 to form an alternating pattern including square PD pixel structures 720A / D / E / H / I / L / M / P and split PD pixel structures 710B / C / F / G / J / K / N / O, as shown in FIG. Similar to pixel array 500, square PD pixel structure 710 includes one photodiode (PD) 715 inside the pixel structure's square perimeter, while split PD pixel structure 720 includes two photodiodes, PD 725A and PD 725B, inside the pixel structure's square perimeter. Thus, pixel array 700 alternates between pixel structures with one photodiode per square unit and pixel structures with two photodiodes per square unit. Note that for ease of illustration, only PD 715 is identified in square PD pixel structure 710A and only PD 725A and PD 725B are identified in split PD pixel structure 720F in FIG. 7 . In various embodiments, both square PD pixel structures 710A / D / E / H / I / L / M / P and split PD pixel structures 720B / C / F / G / J / K / N / O have corresponding lenses 730A-P within pixel array 700.

[0051] In particular embodiments, pixel array 700 is a color filter array having a combination of red (R), green (G), and blue (B) pixel structures (e.g., the color filter array is an RGB filter array). In some embodiments, square PD pixel structure 710 is the green pixel structure, while split PD pixel structure 720 is used for either the blue or red pixel structure. In the embodiment shown in FIG. 7, pixel array 700 is a Bayer color filter array (CFA). In the case of a Bayer CFA, pixel array 700 includes a total of eight square PD pixel structures 710A / D / E / H / I / L / M / P that are green pixel structures, four split PD pixel structures 720B / F / J / N that are blue pixel structures, and four split PD pixel structures 720C / G / K / O that are red pixel structures. The basic alternating pattern of a Bayer CFA is a set of four pixels including two green pixel structures (e.g., square PD pixel structures 710A / D) at opposite corners and a blue pixel structure and a red pixel structure (e.g., split PD pixel structure 720B is a blue pixel and split PD pixel structure 720C is a red pixel) at opposite corners. Similar to pixel array 500, pixel array 700 may have more green pixels to increase the signal response to green light relative to blue or red light. The alternating pattern of pixel array 700 may be repeated across multiple pixel arrays to form larger pixel arrays for implementation as a Bayer CFA in an image sensor.

[0052] FIG. 8 is an exemplary schematic diagram of a portion of a pixel array 700, according to some embodiments. In the illustrated embodiment, schematic diagram 800 is provided for portion 740 (shown by dashed lines in FIG. 7) of pixel array 700. Portion 740 includes a square PD pixel structure 710A and a split PD pixel structure 720C, as shown in FIG. 5. As shown in FIG. 8, schematic diagram 800 includes a photodiode (PD) 810 and a photodiode (PD) 810C corresponding to square PD pixel structure 710A and split PD pixel structure 720C, respectively, from FIG. 7. Photodiode (PD) 810A includes a single photodiode, while photodiode 810C includes a pair of photodiodes, indicated in FIG. 8 by the symbols "L" and "R" as a left (L) photodiode and a right (R) photodiode. Photodiode 810A has its corresponding target gate (TG) 820A, while photodiode 810C has its corresponding left and right pair of transfer gates (TG) 820C.

[0053] A transfer gate (TG) 820A is coupled to a floating diffusion (FD) region 825A, while a left and right pair of transfer gates (TG) 820C are coupled together and to a floating diffusion (FD) region 825B. The FD region 825A is coupled to a reset gate (RST) 830A, a source follower (SF) transistor 840A, and a row selector (RS) transistor 850A. An output 860 is coupled to the output of RS 850A to provide an output from the square PD pixel structure corresponding to the photodiode (PD) 810A. The FD region 825B is coupled to a reset gate (RST) 830B, a source follower (SF) transistor 840B, and a row selector (RS) transistor 850B. An output 870 is coupled to the output of RS 850B to provide an output from the split PD pixel structure corresponding to the left and right pair of photodiodes (PD) 810C. Correspondingly, outputs 860 and 870 may be separate outputs of two different types of pixel structures implemented in pixel array 700: a square PD pixel structure and a split PD pixel structure.

[0054] 9 is a circuit layout for addressing and readout of a pixel array, according to some embodiments. Circuit layout 900 is an example of one contemplated embodiment of addressing and readout of a large pixel array formed by a repeating pattern of pixel array 500 shown in FIG. 5. Thus, in a particular embodiment, circuit layout 900 is a contemplated circuit layout for a quadra CFA that implements a combination of a square PD pixel structure and a split PD pixel structure. While circuit layout 900 shows one example of a circuit layout for addressing and readout of a quadra CFA, it should be understood that additional embodiments for addressing and readout may be contemplated within the scope of the present disclosure.

[0055] In the illustrated embodiment, the circuit layout 900 includes a quadra CFA 910. The CFA 910 includes a pattern of square PD pixel structures 510 and split PD pixel structures 520. The pattern of the square PD pixel structures 510 and split PD pixel structures 520 may be based on the pattern of pixel structures in the pixel array 500 (shown in FIG. 5 ), for example. For ease of illustration, not all square PD pixel structures 510 and split PD pixel structures 520 are labeled in FIG. 9 . Nevertheless, as previously shown and described throughout this disclosure, the square PD pixel structures 510 are represented in FIG. 9 by circles within squares, while the split PD pixel structures 520 are represented by circles within squares with a vertical line dividing the square and circle in half (representing the split photodiodes within the pixel structure). In a particular embodiment, the CFA 910 further includes a pattern of green, red, and blue pixel structures of the pixel array 500 (shown in FIG. 5 ).

[0056] In various embodiments, the circuit layout 900 includes a plurality of square PD pixel structure row addressing circuits 920 and a plurality of split PD pixel structure row addressing circuits 930 coupled to the CFA 910. In the embodiment shown in Figure 9, there are four square PD pixel structure row addressing circuits 920A-D and four split PD pixel structure row addressing circuits 930A-D. The square PD pixel structure row addressing circuits 920A-D are coupled to the square PD pixel structure 510 by circuit lines 925A-D (solid lines), and the split PD pixel structure row addressing circuits 930A-D are coupled to the split PD pixel structure 520 by circuit lines 935A-D (dashed lines). As shown in Figure 9, the circuit lines 925A-D and circuit lines 935A-D may zigzag back and forth between the offset square PD pixel structure 510 and the offset split PD pixel structure 520, respectively. By zigzagging the circuit lines 925A-D and 935A-D between the offset pixel structures, the control signal timing (e.g., row addressing) can be made the same for all pixel structures along the same row. For example, all square PD pixel structures 510 coupled to the square PD row addressing circuit 920A by the zigzag circuit line 925A have the same timing based on receiving the same control signals. Similarly, all split PD pixel structures coupled to the split PD row addressing circuit 930A by the zigzag circuit line 935A have the same timing based on receiving the same control signals.

[0057] In addition to the different row addressing circuits, the circuit layout 900 includes two analog-to-digital conversion (ADC) circuits 940A and 940B. The ADC circuit 940A is coupled to the output 660 from the square PD pixel structure 510 (note that the output 660 is also shown in the schematic diagram of FIG. 6 ). The ADC circuit 940B is coupled to the output 670 from the split PD pixel structure 520 (note that the output 670 is also shown in the schematic diagram of FIG. 6 ). Separate readout paths may be necessary because the timing of the readout from the square PD pixel structure 510 is slightly different from the timing of the readout from the split PD pixel structure 520 (e.g., the square PD pixel structure 510 has a readout from a single photodiode, while the split PD pixel structure 520 has a readout from a pair of photodiodes). Therefore, having separate ADC circuits for the different types of pixel structures allows the readout signals to be read out in parallel. For example, the readout signal from output 660 of square PD pixel structure 510 may be read out by ADC circuit 940A in parallel with the readout signal from output 670 of split PD pixel structure 520 being read out by ADC circuit 940B. This parallel readout scheme may be more efficient in obtaining a readout from the hybrid pixel array structures described herein. Some embodiments may be contemplated in which a single ADC circuit performs readout from both square PD pixel structure 510 and split PD pixel structure 520. Such a single ADC circuit may perform the readout serially due to the different nature of the photodiodes read out by the ADC circuit (e.g., readout from a single photodiode versus a pair of photodiodes in each pixel structure).

[0058] FIG. 10 shows a timing diagram of the operation of transistors in a pixel array according to some embodiments. In the illustrated embodiment, two sets of timing are implemented: square PD pixel timing 1000 and split PD pixel timing 1005. Square PD pixel timing 1000 is implemented for a set of four square PD pixel structures represented by curves for four transfer gate (TG) transistors TG620A, TG620B, TG620C, and TG620D. As shown in FIG. 6, these four transfer gate (TG) transistors are coupled to reset gate (RST) transistor 630A and row selector (RS) transistor 650A, which also have corresponding curves in the timing diagram. The output of the square PD pixel structures is provided to ADC 940A (shown in FIG. 9), which also has corresponding curves in the timing diagram.

[0059] Split-PD pixel timing 1005 is implemented for a set of four split-PD pixel structures represented by the curves TG620I-L, TG620I-R, TG620J-L, TG620J-R, TG620K-L, TG620K-R, TG620L-L, and TG620L-R, with eight transfer gate (TG) transistors (four left and four right TG transistors). As shown in FIG. 6, these eight transfer gate (TG) transistors are coupled to reset gate (RST) transistor 630B and row selector (RS) transistor 650B, which also have corresponding curves in the timing diagram. The output of the split-PD pixel structure is provided to ADC 940B (shown in FIG. 9), which also has corresponding curves in the timing diagram.

[0060] During operation of the pixel array, a pixel (e.g., pixel structure) can undergo four operational periods: shuttering 1010, integrating 1020, readout 1030, and idle 1040. Shuttering 1010 is a period of operation during which all photoelectrons are drained from the photodiode (e.g., the photodiode is reset). Integration 1020 is a period of operation during which photoelectrons are accumulated in the photodiode (e.g., by exposing the photodiode to light to generate photoelectrons and blocking the photoelectrons from being transferred from the photodiode). Readout 1030 is a period of operation during which a signal is read out from the pixel structure. During readout 1030, photoelectrons are transferred from the photodiode to a floating diffusion (FD) region via a transfer gate (TG). Idle 1040 is a period of operation during which the pixel array is idle after readout 1030 and before the resetting of the photodiode in shuttering 1010. Note that the shuttering 1010, integration 1020, readout 1030, and idle 1040 periods are substantially the same for both the square PD pixel timing 1000 and the split PD pixel timing 1005.

[0061] As shown in the timing diagram of FIG. 10, shuttering 1010 involves pulsing the transfer gates (TG) (TG620A-L) while the reset transistors (RST630A and RST630B) are turned on, allowing photoelectrons to pass through them, and the row select transistors (RS650A and RS650B) are turned off. This shuttering can be performed for both square and split PD pixel structures. Any photoelectrons emitted during the TG transistor pulse are transferred to the drain (e.g., Vdd) through the reset transistor. The TG transistor pulse can be set long enough to drain all photoelectrons from the photodiode.

[0062] After resetting the photodiode in shuttering 1010, the operation of the pixel can switch to integration 1020. During integration, the photodiode is exposed to light to generate photoelectrons in the photodiode. This operation stores the photoelectrons in the photodiode and generates a signal for later readout from the pixel structure. Therefore, during integration 1020, the TG transistor is kept off, preventing photoelectrons from being transferred through the TG transistor. The reset transistor can be left on to allow any photoelectrons passing through the TG transistor to pass to the drain.

[0063] After the accumulation of photoelectrons in integration 1020, operation of the pixel array transitions to readout 1030. In readout 1030, the reset transistors (RST 630A and RST 630B) are turned off and the TG transistors (TG 620A-L) are pulsed for various short periods to transfer the photoelectrons from the photodiodes to the FD regions. The FD regions accumulate charge from the photoelectrons, which is then read out from the pixel array to the ADC circuits (ADC 940A and ADC 940B) as an analog signal. To allow the analog signal to be read out, the row select transistors (RS 650A and RS 650B) are turned on, which allows the analog signal to transfer from the FD regions to outputs 660 and 670 at the drains of the row select transistors (as shown in FIG. 6).

[0064] As shown in the illustrated embodiment, the readout for the square PD pixel timing 1000 and split PD pixel timing 1005 may differ due to the different structures of the square PD pixel structure and the split PD pixel structure. For example, because the square PD pixel structure has only a single photodiode and corresponding transfer gate (TG 620A-D), each individual transfer gate may be pulsed once, and the ADC may be sampled twice (shown as a black triangle along ADC 940A): once before the pulse and once after the pulse. The first sample before the TG pulse represents a baseline level, while the second sample after the TG pulse represents a signal level based on the accumulation of photoelectrons in the photodiode associated with the TG. The level of the photodiode signal is then determined based on subtracting the baseline level from the signal level read out from each transfer gate (TG) transistor. Note that the reset transistor (RST 630A) is pulsed between samplings of different transfer gate (TG) transistors to reset the baseline level between TG pulses.

[0065] Because the split-PD pixel structure has two photodiodes (a left-right pair) and corresponding transfer gates (TG620I-L (and L / R)), the left and right pairs of transfer gate (TG) transistors can be pulsed separately between reset transistor (RST630B) pulses. Thus, for each pair of left and right photodiodes in a single split-PD pixel structure, the ADC (ADC940B) samples the signal three times (shown as filled triangles along ADC940B): once before the first TG pulse of one photodiode (either left or right), once after the first TG pulse, and once after the second TG pulse of the other photodiode. The first sample before the first TG pulse represents a baseline level, while the second sample after the first TG pulse represents a signal level based on the accumulation of photoelectrons in the first photodiode associated with the TG pulse, and the third sample after the second TG pulse represents a signal level based on the accumulation of photoelectrons in the second photodiode associated with the second TG pulse. The level of the signal of the first photodiode is determined based on subtracting the baseline level from the second sample signal level read after the first TG pulse, while the level of the signal of the second photodiode is determined based on subtracting the baseline level and the second sample signal level from the third sample signal level read after the second TG pulse.

[0066] As an example of the photodiode pairs associated with TG620I-L and TG620I-R, the readout 1030 begins with the first readout sample 1042 of the ADC 940B before the first TG pulse 1032. Then, a second readout sample 1044 is taken after the first TG pulse 1032 and before the second TG pulse 1034. Then, a third readout sample 1046 is taken after the second TG pulse 1034. The reset transistor (RST630B) is then pulsed to reset the signal level to the baseline before readout of the photodiode pairs associated with TG620J-L ​​and TG620J-R.

[0067] To maintain overall synchronous timing for readout 1030 between the square PD pixel timing 1000 and the split PD pixel timing 1005, the pulsing of the reset transistors (RST630A and RST630B) may be synchronized. Correspondingly, the split PD pixel timing 1005 provides timing for the readout of both photodiodes in the split PD pixel structure that is synchronized with timing for the readout of a single photodiode in the square PD pixel structure. Maintaining this overall synchronous timing allows a single overall timing circuit to be implemented in the timing diagram. For example, a single timing control circuit may apply the shuttering 1010, integration 1020, readout 1030, and idle 1040 timing for both types of pixel structures. Utilizing a single timing control circuit, as described herein, may reduce the circuit complexity involved in implementing a hybrid pixel array structure.

[0068] FIG. 11 is a top view of yet another contemplated hybrid pixel array according to some embodiments. In the illustrated embodiment, pixel array 1100 includes a pattern of square PD pixel structures 510 and split PD pixel structures 520. The pattern of square PD pixel structures 510 and split PD pixel structures 520 may be based on the pattern of pixel structures in pixel array 500 (shown in FIG. 5) or pixel array 700 (shown in FIG. 7), for example. For ease of illustration, not all square PD pixel structures 510 and split PD pixel structures 520 are labeled in FIG. 11 . Nevertheless, as previously shown and described throughout this disclosure, square PD pixel structures 510 are represented in FIG. 11 by circles within squares, while split PD pixel structures 520 are represented by circles within squares with a vertical line dividing the square and circle in half (representing the split photodiodes within the pixel structures). In certain embodiments, pixel array 1100 further includes any pattern of green, red, and blue pixel structures contemplated by this disclosure.

[0069] In a particular embodiment, the pixel array 1100 includes an optical shield element 1110 disposed over one or more square PD pixel structures 510. The optical shield element 1110 may include, for example, an optical shield formed on the back surface of the pixel structure (such as in a back-illumination process) or a multi-pixel on-chip lens (OCL). The material of the optical shield element 1110 may include, but is not limited to, tungsten or other light-absorbing metals. As shown in FIG. 11 , the optical shield element 1110 may be disposed over half of the area of ​​the square PD pixel structure 510. For example, the optical shield element 1110 may be disposed on either the left or right half of the square PD pixel structure 510.

[0070] The addition of the optical shield element 1110 to the square PD pixel structure 510 may enable different operating modes and / or additional options for autofocus (e.g., PDAF) for an image sensor having the pixel array 1100. For example, the optical shield element 1110 may enable a mode of autofocus operation that utilizes less power by allowing the split PD pixel structure to be turned off during certain autofocus modes. As another example, the optical shield element 1110 may provide the capability for subsampling of the optical signal. Subsampling may enable deeper interpretation of the photoelectron accumulation results to generate an image.

[0071] FIG. 12 is an exemplary process flow for forming a hybrid pixel array structure according to some embodiments. The illustrated process flow shows various possible steps for forming a hybrid pixel array structure on a single substrate. In the illustrated embodiment, the process flow begins with a substrate 1200 in (a). The substrate 1200 may be, for example, a silicon substrate, although other substrates are contemplated. In (b), deep trench isolation (DTI) or another isolation trench formation method may be performed to form trenches 1210 in the substrate 1200. In some embodiments, the trenches 1210 are filled with an isolation material. In particular embodiments, the trenches 1210 are formed with a single mask. The trenches 1210 may be formed to define implantation areas / regions for the photodiodes of the square PD pixel structure 1220 and the split PD pixel structure 1230. As shown in FIG. 12 , the density of the trenches 1210 is different for the square PD pixel structure 1220 and the split PD pixel structure 1230. A pixel array with DTI trenches 1210 may provide improved optical and electrical isolation between pixels.

[0072] After forming trench 1210, the process flow continues at (c) with implanting the photodiodes for the pixel structures. Implanting the photodiodes may include forming photodiode (PD) 1222 for square PD pixel structure 1220, and left photodiode (LPD) 1232 and right photodiode (RPD) 1234 for split PD pixel structure 1230. In some embodiments, a single mask may be used to form photodiode (PD) 1222, along with left photodiode (LPD) 1232 and right photodiode (RPD) 1234. In other embodiments, two (or more) photodiodes may be used. For example, a first mask may be used to form photodiode (PD) 1222, and a second mask may be used to form left photodiode (LPD) 1232 and right photodiode (RPD) 1234. Two or more masks may be used, for example, if no additional implants are shared between different photodiodes. In some embodiments, doping of epitaxial silicon may be performed instead of implantation to form the photodiode.

[0073] After the formation of the implants in (c), shallow implants 1240 can be formed in (d). The shallow implants 1240 can include implants of a different material than the material implanted in (c) at a shallow depth below the surface of the substrate 1200. As with the deep implants, a single mask or a combination of two or more masks can be used to form the shallow implants 1240, depending on whether there are implant differences between the square PD pixel structure and the split PD pixel structure. After the formation of the shallow implants 1240, a gate 1250 can be formed on the surface of the substrate 1200 in (e). The gate 1250 may be formed in a single mask process unless different types of gates are required for different photodiodes. The gate 1250 can include, for example, various transfer gates (TG), reset transistors (RST), or row selector (RS) transistors described herein.

[0074] In (f), transistor implant 1260 is formed in shallow implant 1240. As with the other implants, a single mask or a combination of two or more masks can be used to form transistor implant 1260, depending on whether there are implant differences between the square PD pixel structure and the split PD pixel structure. In (g), metallization 1270 is formed on the surface of substrate 1200. Metallization 1270 includes various routing and connections to gate 1250 for operation of the pixel structure. For example, metallization may include routing to ADC circuitry or row addressing circuitry.

[0075] After the metallization in (g), backside thinning can be performed in (h) to remove excess portions of the substrate 1200 from the backside of the pixel array. In some embodiments, after backside thinning, patterning of various backside metals can be performed. The backside metal patterning can include, for example, patterning of optical shields or patterning of other optical metals. The backside metal patterning can be similar for both square and split PD pixel structures, or can differ between different types of pixel structures.

[0076] FIG. 13 is a schematic diagram of an exemplary image sensor, according to some embodiments. As shown in FIG. 13 , the image sensor 1300 may include a plurality of light-gathering pixels 1302 (e.g., a square PD pixel structure or a split PD pixel structure described herein) organized as a pixel array 1320. In some embodiments, the image sensor 1300 may include one or more amplifiers 1304, one or more ADC (analog-to-digital conversion) circuits and memory 1308, and one or more image signal processing circuits 1322. In various embodiments, the image signal processing circuits include data interface circuits. In some embodiments, the image signals of the pixels 1302 of the pixel array 1320 may be read out row by row or column by column (or even pixel by pixel). For illustrative purposes, in this example, the image sensor 1300 may also include a row logic circuit 1324 for providing control signals to perform a row-by-row readout of the pixels 1302. Using row-by-row readout, pixels 1302 on the same row may be read out simultaneously or nearly simultaneously, while pixels 1302 on the same column but different rows may be read out sequentially row-by-row.

[0077] In some embodiments, the readout of image signals of pixels 1302 may be implemented using one or more readout circuits, as described herein. For example, at least some of the pixels 1302 may include one or more photodiodes and pixel readout circuits. The photodiodes can generate and store photoelectrons when exposed to light. During readout, under control signals from row logic circuit 1324, the row select transistor and source follower transistor may be turned on, releasing an analog signal output through output 1326. Output 1326 may be coupled to a floating diffusion region, which may output an analog output signal having a reset value or a signal value depending on the states of a transfer gate and a reset gate.

[0078] FIG. 14 is a flowchart illustrating an exemplary method for processing image signals of an image sensor to generate a digital image, according to some embodiments. In FIG. 14 , in some embodiments, photoelectrons are accumulated in a photodiode of at least one pixel on an image sensor in response to exposing the at least one pixel to light, as indicated by block 1402. During readout, these photoelectrons are transferred out of the photodiode and can generate an analog signal output (e.g., an analog voltage output) in the FD region of the pixel that can be further accessed at the pixel's output. In FIG. 14 , in some embodiments, in block 1404, the pixel provides an analog signal output having a reset value. In block 1406, the pixel provides an analog signal output having a signal value. Then, in block 1408, the reset value and the signal value are converted to a final digital signal value. In various embodiments, the final digital signal value is generated by a combination of an ADC, an SRAM, a digital processing circuit, and a data interface circuit. In block 1410, a digital image is generated from the final digital signal value. For example, digital processing circuitry and / or data interface circuitry can generate a digital image from the final digital signal values.

[0079] 15 shows a schematic diagram of an example device 1500 that may include an image capture device (e.g., a camera) having an image sensor, according to some embodiments. In some embodiments, device 1500 may be a mobile device and / or a multifunction device. In various embodiments, device 1500 may be any of a variety of types of device, including, but not limited to, a personal computer system, a desktop computer, a laptop, a notebook, a tablet, a slate, a pad, or a netbook computer, a mainframe computer system, a handheld computer, a workstation, a network computer, a camera, a set-top box, a mobile device, an augmented reality (AR) and / or virtual reality (VR) headset, a consumer device, a video game console, a handheld video game device, an application server, a storage device, a television, a video recording device, a peripheral device such as a switch, modem, router, or generally any type of computing or electronic device.

[0080] In some embodiments, device 1500 may include a display system 1502 (e.g., including a display and / or a touch-sensitive surface) and / or one or more cameras 1504. In some non-limiting embodiments, display system 1502 and / or one or more front-facing cameras 1504a may be provided on the front side of device 1500, for example, as shown in FIG. 15 . Additionally or alternatively, one or more rear-facing cameras 1504b may be provided on the rear side of device 1500. In some embodiments with multiple cameras 1504, some or all of the cameras may be the same or similar to one another. Additionally or alternatively, some or all of the cameras may be different from one another. In various embodiments, the position(s) and / or placement(s) of camera(s) 1504 may differ from that shown in FIG. 15 . In various embodiments, camera 1504 includes lens(es) 1505. An image sensor (eg, image sensor 1300) may receive light that passes through lens(es) 1505 and reaches the image sensor.

[0081] Among other things, device 1500 may include memory 1506 (e.g., comprising an operating system 1508 and / or application(s) / program instructions 1510), one or more processors and / or controllers 1512 (e.g., comprising CPU(s), memory controller(s), display controller(s), and / or camera controller(s), etc.), and / or one or more sensors 1516 (e.g., orientation sensor(s), proximity sensor(s), and / or position sensor(s), etc.). In some embodiments, device 1500 can communicate with one or more other devices and / or services, such as computing device(s) 1518, cloud service(s) 1520, etc., via one or more networks 1522. For example, device 1500 may include a network interface that allows device 1500 to send and receive data to and from network(s) 1522. Additionally or alternatively, device 1500 may be capable of communicating with other devices via wireless communication using any of a variety of communication standards, protocols, and / or technologies.

[0082] 16 shows a schematic block diagram of an exemplary computing device, referred to as computing device 1600, that may include or host an embodiment of an image capture device (e.g., a camera) having an image sensor, according to some embodiments. Additionally, computer system 1600 may implement methods for controlling the operation of the camera and / or for performing image processing of images captured using the camera. In some embodiments, a device (described herein with reference to FIG. 16) may additionally or instead include some or all of the functional components of computer system 1600 described herein.

[0083] Computer system 1600 may be configured to perform any or all of the above-described embodiments. In different embodiments, computer system 1600 may be any of a variety of types of devices, including, but not limited to, a personal computer system, a desktop computer, a laptop, a notebook, a tablet, a slate, a pad, or a netbook computer, a mainframe computer system, a handheld computer, a workstation, a network computer, a camera, a set-top box, a mobile device, an augmented reality (AR) and / or virtual reality (VR) headset, a consumer device, a video game console, a handheld video game device, an application server, a storage device, a television, a video recording device, a peripheral device such as a switch, modem, router, or generally any type of computing or electronic device.

[0084] In the illustrated embodiment, computer system 1600 includes one or more processors 1602 coupled to system memory 1604 via an input / output (I / O) interface 1606. Computer system 1600 further includes one or more cameras 1608 coupled to I / O interface 1606. Computer system 1600 further includes a network interface 1610 coupled to I / O interface 1606, and one or more input / output devices 1612, such as a cursor control device 1614, a keyboard 1616, and a display(s) 1618. While in some cases, an embodiment may be implemented using a single instance of computer system 1600, it is contemplated that in other embodiments, multiple such systems, or multiple nodes comprising computer system 1600, may be configured to host different portions or instances of an embodiment. For example, in one embodiment, some elements may be implemented via one or more nodes of computer system 1600 that are different from the nodes implementing other elements.

[0085] In various embodiments, computer system 1600 may be a uniprocessor system including one processor 1602, or a multiprocessor system including multiple processors 1602 (e.g., two, four, eight, or another suitable number). Processor 1602 may be any suitable processor capable of executing instructions. For example, in various embodiments, processor 1602 may be a general-purpose or embedded processor implementing any of various ISAs, such as the x86, PowerPC, SPARC, or MIPS ISA, or any other suitable instruction set architectures (ISAs). Also, in some embodiments, one or more of processors 1602 may include additional types of processors, such as graphics processing units (GPUs), application specific integrated circuits (ASICs), etc. In a multiprocessor system, each of processors 1602 may generally, but not necessarily, implement the same ISA. In some embodiments, computer system 1600 may be implemented as a system on a chip (SoC). For example, in some embodiments, the processor 1602, memory 1604, I / O interface 1606 (e.g., fabric), etc. may be implemented in a single SoC with multiple components integrated on a single chip. For example, the SoC may include multiple CPU cores, a multi-core GPU, a multi-core neural engine, a cache, one or more memories, etc. integrated on a single chip. In some embodiments, the SoC embodiment may implement a reduced instruction set computing (RISC) architecture, or any other suitable architecture.

[0086] The system memory 1604 may be configured to store program instructions 1620 accessible by the processor 1602. In various embodiments, the system memory 1604 may be implemented using any suitable memory technology, such as static random access memory (SRAM), synchronous dynamic RAM (SDRAM), non-volatile / flash-type memory, or any other type of memory. Additionally, existing camera control data 1622 in the memory 1604 may include any of the information or data structures for implementing the techniques described above. In some embodiments, the program instructions 1620 and / or data 1622 may be received, sent, or stored on different types of computer-accessible media, or on similar media separate from the system memory 1604 or the computer system 1600. In various embodiments, some or all of the functionality described herein may be performed via such a computer system 1600.

[0087] In one embodiment, I / O interface 1606 may be configured to coordinate I / O traffic between processor 1602, system memory 1604, and any peripheral devices within the device, including other peripheral interfaces such as network interface 1610 or input / output devices 1612. In some embodiments, I / O interface 1606 may perform any necessary protocol, timing, or other data conversions to convert data signals from one component (e.g., system memory 1604) into a format suitable for use by another component (e.g., processor 1602). In some embodiments, I / O interface 1606 may include support for devices connected via various types of peripheral buses, such as, for example, variants of the Peripheral Component Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard. In some embodiments, the functionality of I / O interface 1606 may be split between two or more separate components, such as, for example, a northbridge and a southbridge. Also, in some embodiments, some or all of the functionality of I / O interface 1606 , such as an interface to system memory 1604 , may be incorporated directly into processor 1602 .

[0088] Network interface 1610 may be configured to allow data to be exchanged between computer system 1600 and other devices (e.g., carrier or agent devices) connected to network 1624, or between nodes of computer system 1600. In various embodiments, network 1624 may include one or more networks, including, but not limited to, local area networks (LANs) (e.g., Ethernet or enterprise networks), wide area networks (WANs) (e.g., the Internet), wireless data networks, some other electronic data networks, or some combination thereof. In various embodiments, network interface 1610 may support communication over any suitable type of wired or wireless general-purpose data network, such as an Ethernet network, over a telecommunications / telephone network, such as an analog voice network or a digital fiber communications network, over a storage area network such as a Fibre Channel SAN, or over any other suitable type of network and / or protocol.

[0089] Input / output devices 1612, in some embodiments, may include one or more display terminals, keyboards, keypads, touchpads, scanning devices, voice or optical recognition devices, or any other devices suitable for inputting or accessing data by one or more computer systems 1600. Multiple input / output devices 1612 may be present within computer system 1600 or may be distributed on various nodes of computer system 1600. In some embodiments, similar input / output devices may be separate from computer system 1600 and may interact with one or more nodes of computer system 1600 through wired or wireless connections, such as via network interface 1610.

[0090] Those skilled in the art will appreciate that computer system 1600 is merely exemplary and is not intended to limit the scope of the embodiments. In particular, computer systems and devices may include any combination of hardware or software capable of performing the specified functions, including computers, network devices, Internet appliances, PDAs, wireless telephones, pagers, etc. Computer system 1600 may also be connected to other devices not shown, or alternatively, may operate as a stand-alone system. Additionally, functionality provided by the illustrated components may, in some embodiments, be combined into fewer components or distributed among additional components. Similarly, in some embodiments, the functionality of some of the illustrated components may not be provided, and / or other additional functionality may be available.

[0091] Those skilled in the art will also appreciate that while various items are illustrated as being stored in memory or on a storage device during use, these items, or portions thereof, may be transferred between memory and other storage devices for purposes of memory management and data integrity. Alternatively, in other embodiments, some or all of the software components may execute in memory on another device and communicate with the illustrated computer system via computer-to-computer communications. Some or all of the system components or data structures may also be stored (e.g., as instructions or structured data) on a computer-accessible medium or portable article to be read by an appropriate drive, various examples of which are described above. In some embodiments, instructions stored on a computer-accessible medium separate from computer system 1600 may be transmitted to computer system 1600 via signals, such as electrical, electromagnetic, or digital signals, conveyed over a transmission medium or communications medium, such as a network and / or a wireless link. Various embodiments may further include receiving, sending, or storing instructions and / or data on a computer-accessible medium, as implemented in accordance with the preceding description. Generally speaking, a computer-accessible medium may include a non-transitory computer-readable storage medium or memory medium, such as, for example, a magnetic or optical medium such as a disk or DVD / CD-ROM, a volatile or non-volatile medium such as RAM (e.g., SDRAM, DDR, RDRAM, SRAM, etc.), a ROM, etc. In some embodiments, a computer-accessible medium may include a signal, such as an electrical signal, an electromagnetic signal, or a digital signal, conveyed over a transmission medium or a communication medium such as a network and / or a wireless link.

[0092] The methods described herein may, in different embodiments, be implemented in the form of software, hardware, or a combination thereof. In addition, the order of method blocks may be changed, and various elements may be added, rearranged, combined, omitted, modified, etc. Various modifications and variations may be made, as would be apparent to one of ordinary skill in the art having the benefit of this disclosure. The various embodiments described herein are illustrative and not limiting. Many variations, modifications, additions, and improvements are possible. Correspondingly, multiple examples may be provided for components described herein as a single example. Boundaries between various components, operations, and data stores are somewhat arbitrary, and particular operations are illustrated in the context of specific illustrative configurations. Other allocations of functionality are contemplated and may be included within the scope of the following claims. Finally, structures and functionality presented as separate components in illustrative configurations may be implemented as combined structures or components. These and other variations, modifications, additions, and improvements may be included within the scope of the embodiments, as defined by the following claims.

Claims

1. 1. A pixel array device, comprising: A silicon substrate; an array of pixel structures disposed within the substrate, the array configured to generate a signal based on photoelectrons accumulated by the pixels upon exposure to light, the pixel structures being square pixel structures having photodiodes formed within the substrate, the square pixel structures comprising: a set of first pixel structures of a first type, the first type pixel structures including one photodiode formed in the substrate per square pixel structure; an array of pixel structures including: a set of second pixel structures of a second type, the second type pixel structures including two photodiodes formed in the substrate per square pixel structure; and a first signal output circuit coupled to the first set of pixel structures, the first signal output circuit configured to receive a readout signal from the one photodiode in the first set of pixel structures; a second signal output circuit coupled to the second set of pixel structures, the second signal output circuit configured to receive readout signals from the two photodiodes in the second set of pixel structures. Pixel array device.

2. The pixel array device of claim 1 , wherein the first type of pixel structure is a square photodiode pixel structure.

3. The pixel array device of claim 1 , wherein the second type of pixel structure is a split photodiode pixel structure.

4. a first analog-to-digital converter (ADC) circuit coupled to the first signal output circuit; a second ADC circuit connected to the second signal output circuit; The pixel array device of claim 1 .

5. 5. The pixel array device of claim 4, wherein the first ADC circuit and the second ADC circuit are configured to receive the readout signals in parallel from the first signal output circuit and the second signal output circuit, respectively.

6. a first row addressing circuit coupled to an input of the one photodiode in the first set of pixel structures; a second row addressing circuit coupled to inputs of the two photodiodes in the second set of pixel structures. The pixel array device of claim 1 .

7. The pixel array device of claim 1 , wherein the array comprises the first set of pixel structures and the second set of pixel structures arranged in a repeating regular pattern.

8. 10. The pixel array device of claim 1, wherein the array is a color filter array, and the first type of pixel structures are configured to accumulate photoelectrons when exposed to green light, and the second type of pixel structures are configured to accumulate photoelectrons when exposed to blue light or red light.

9. The pixel array device of claim 1 , further comprising microlens structures disposed above the pixel structures, one microlens structure per pixel structure.

10. 10. The pixel array device of claim 1, further comprising an optical shield disposed over at least some of the first set of pixel structures, the optical shield disposed over half of the corresponding pixel structures.

11. The pixel array device of claim 10 , wherein some of the optical shields are disposed on the left half of the corresponding pixel structure and some of the optical shields are disposed on the right half of the corresponding pixel structure.

12. 1. An image sensor device, comprising: A silicon substrate; a plurality of square pixel structures formed in the substrate, the pixel structures configured to generate a signal based on photoelectrons accumulated by the pixel structures upon exposure to light, the pixel structures comprising: a set of square photodiode pixel structures having one photodiode formed in the substrate per square pixel structure; a set of split photodiode pixel structures having two photodiodes formed in the substrate per square pixel structure; and a first row addressing circuit coupled to the set of square photodiode pixel structures, the first row addressing circuit configured to provide a first control signal to the one photodiode in the set of square photodiode pixel structures; a second row addressing circuit coupled to the set of split photodiode pixel structures, the second row addressing circuit configured to provide a second control signal to the two photodiodes in the set of split photodiode pixel structures; an image signal processing circuit coupled to signal outputs of the set of square photodiode pixel structures and the set of split photodiode pixel structures, the image signal processing circuit configured to generate a digital image based on a combination of output signals from the set of square photodiode pixel structures and output signals from the set of split photodiode pixel structures. Image sensor device.

13. a first analog-to-digital converter (ADC) circuit coupled to the signal outputs of the set of square photodiode pixel structures, the first ADC circuit configured to generate a first digital signal output corresponding to an analog signal output from the set of square photodiode pixel structures; a second ADC circuit coupled to the signal outputs of the set of split photodiode pixel structures, the second ADC circuit configured to generate a second digital signal output corresponding to an analog signal output from the set of split photodiode pixel structures; The image sensor device of claim 12 further comprising:

14. The image sensor device of claim 13 , wherein the image signal processing circuitry is configured to generate a digital image based on a combination of the first digital signal output and the second digital signal output.

15. The image sensor device of claim 12 , wherein the set of square photodiode pixel structures and the set of split photodiode pixel structures are arranged in a regular, alternating pattern of pixel structures within the substrate.

16. 1. A system comprising: A camera, one or more lenses; an image sensor configured to receive light that has passed through the lens and reached the image sensor, the image sensor comprising: a plurality of square pixel structures formed in a substrate, the plurality of square pixel structures configured to generate a signal based on photoelectrons accumulated by the pixel structures upon exposure to light, the pixel structures comprising: a set of square photodiode pixel structures having one photodiode formed in the substrate per pixel structure; a set of split photodiode pixel structures having two photodiodes formed in the substrate per square pixel structure; and a first signal output circuit coupled to the set of square photodiode pixel structures, the first signal output circuit configured to receive a readout signal from the one photodiode in the set of square photodiode pixel structures; a second signal output circuit coupled to the set of split photodiode pixel structures, the second signal output circuit configured to receive readout signals from the two photodiodes in the set of split photodiode pixel structures; an image signal processor configured to process the readout signals from the first signal output circuit and the second signal output circuit to generate one or more images; system.

17. 17. The system of claim 16, wherein the set of square photodiode pixel structures is configured to generate a readout signal when exposed to green light, and the set of split photodiode pixel structures is configured to generate a readout signal when exposed to blue light or red light.

18. 17. The system of claim 16, wherein the first signal output circuit is configured to output a first signal to the image signal processor, the second signal output circuit is configured to output a second signal to the image signal processor, and the image signal processor is configured to generate the one or more images by processing both the first signal and the second signal.

19. 20. The system of claim 18, wherein the first signal output circuit is configured to output the first signal synchronously with the second signal output by the second signal output circuit.

20. a first row addressing circuit coupled to an input of the one photodiode in the set of square photodiode pixel structures; a second row addressing circuit coupled to inputs of the two photodiodes in the set of split-photodiode pixel structures.

17. The system of claim 16.

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