LOW-STRAIN Si / SiGe HETEROEPITAXY STACKS FOR 3D DRAM

Abstract

To provide a Si / SiGe 3D memory structure and a method for forming the structure that reduces or eliminates relaxation or wafer bow.SOLUTION: In a three-dimensional dynamic random access memory (3D DRAM) structure, a 3D DRAM stack 100 includes alternating silicon (Si) layers 102 and silicon germanium (SiGe) layers 104. Each of the multiple Si layers 102 has a height greater than the height of each of the multiple SiGe layers 104.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present principles relate generally to semiconductor manufacturing. [Background technology]

[0002] Data storage and retrieval have been limiting factors for many aspects of the computing industry. Memory devices can easily degrade the overall performance of modern computing devices. To make memory faster, memory structures have been scaled down to very small sizes, dramatically increasing the density of memory structures. Three-dimensional memory structures, such as three-dimensional dynamic random access memory (3D DRAM), can be used to achieve even higher memory densities. In some three-dimensional memory structures, alternating layers of Si and SiGe are epitaxially grown from a crystalline silicon substrate. However, as shown in FIG. 1 , in a typical 3D DRAM stack 100, the height of the Si layer 102 is substantially equal to the height of the SiGe layer 104. For some memory applications, the final gap width of the recessed region must be similar in dimension to, or even wider than, the final silicon channel width. However, the inventors have observed that strain induced by the lattice mismatch between Si and Ge exists. For thin layers, the induced strain is not an issue. However, for thick layers, the induced strain can be large enough to cause defects in the single crystal structure known as "relaxation."

[0003] Accordingly, the present inventors have provided a Si / SiGe 3D memory structure and method for making the structure that reduces or eliminates relaxation or wafer bow. Summary of the Invention

[0004] Provided herein are three-dimensional dynamic random access memory (3D DRAM) structures and methods and apparatus for forming such structures.

[0005] As used herein, "layer" means and refers to a single crystalline layer of a material, as well as multiple crystalline layers of the same material that in combination form a single crystalline layer.

[0006] In some embodiments, the 3D DRAM structure includes a stack of alternating silicon (Si) and silicon germanium (SiGe) layers, where the height of each Si layer is greater than the height of each SiGe layer.

[0007] In some embodiments, the 3D DRAM structure includes a stack of alternating Si and SiGe layers, where each Si layer has a height greater than the height of each SiGe layer, and at least one Si layer has a height less than the height of at least one other Si layer.

[0008] In some embodiments, the 3D DRAM structure includes a stack of alternating Si and SiGe layers, wherein the height of each Si layer is greater than the height of each SiGe layer, and at least one SiGe layer includes at least one dopant, wherein the at least one dopant is at least one of boron, carbon, nitrogen, oxygen, and phosphorus.

[0009] In some embodiments, the 3D DRAM structure includes a stack of alternating undoped Si layers, doped Si layers, and doped SiGe layers, each doped Si layer disposed immediately adjacent to and opposite a doped SiGe layer, each undoped Si layer having a height greater than a height of each doped Si layer and greater than a height of each doped SiGe layer, and each doped Si layer and each doped SiGe layer including at least one dopant, wherein the at least one dopant is at least one of boron, carbon, nitrogen, oxygen, and phosphorus.

[0010] In some embodiments, the 3D DRAM structure includes a stack of alternating undoped Si layers, doped Si layers, and doped SiGe layers, each doped SiGe layer disposed immediately adjacent to and opposite the doped Si layer, each undoped Si layer having a height greater than a height of each doped Si layer and greater than a height of each doped SiGe layer, and each doped Si layer and each doped SiGe layer including at least one dopant, wherein the at least one dopant is at least one of boron, carbon, nitrogen, oxygen, and phosphorus.

[0011] In some embodiments, the 3D DRAM structure includes a stack of alternating undoped Si layers, doped Si layers, and doped SiGe layers, and a doped separation layer at the bottom of the stack of alternating layers, each doped SiGe layer being disposed immediately adjacent to and opposite the doped Si layer, each undoped Si layer having a height greater than a height of each doped Si layer and greater than a height of each doped SiGe layer, the doped Si layers and the doped SiGe layers including at least one dopant, the at least one dopant being at least one of boron, carbon, nitrogen, oxygen, and phosphorus, and the doped separation layer including at least one dopant different from the at least one dopant in the doped Si layers and the doped SiGe layers.

[0012] In some embodiments, the 3D DRAM structure includes a stack of alternating Si and SiGe layers, wherein a height of each Si layer is greater than a height of each SiGe layer, at least one SiGe layer includes at least one dopant, the at least one SiGe layer has a central region having a dopant concentration that is greater than a dopant concentration in an outer region of the at least one SiGe layer, and the at least one dopant is at least one of boron, carbon, nitrogen, oxygen, and phosphorus.

[0013] In some embodiments, a method of forming a three-dimensional dynamic random access memory (3D DRAM) structure includes forming a stack of alternating silicon (Si) and silicon germanium (SiGe) layers, wherein a height of the Si layers is greater than a height of the SiGe layers; optionally adding dopants to one or more of the plurality of Si layers; optionally adding dopants to one or more of the plurality of SiGe layers; optionally creating a dopant gradient in the one or more SiGe layers; anisotropically etching vertical slits or holes in the stack; isotropically etching a horizontal recess in at least one of the plurality of SiGe layers; and isotropically etching a horizontal recess in at least one of the plurality of Si layers.

[0014] In some embodiments, a method of forming a three-dimensional dynamic random access memory (3D DRAM) structure includes forming a stack of alternating silicon (Si) and silicon germanium (SiGe) layers, wherein the height of the Si layers is greater than the height of the SiGe layers; anisotropically etching vertical slits or holes in the stack; isotropically etching at least one of the plurality of SiGe layers to form a first horizontal recess, wherein the SiGe layer is substantially completely removed between a portion of the plurality of Si layers; and isotropically etching a second horizontal recess in that portion of the Si layer adjacent to the at least one etched SiGe layer to form a thinner portion of the Si layer, wherein the first horizontal recess and the second horizontal recess together form a cavity between adjacent Si layers.

[0015] In some embodiments, a non-transitory computer-readable medium is provided having instructions formed thereon that, when executed, cause a processing chamber to perform a method of forming a three-dimensional dynamic random access memory (3D DRAM) structure according to any of the embodiments disclosed herein.

[0016] In some embodiments, an apparatus and system for forming a three-dimensional dynamic random access memory (3D DRAM) structure according to any of the embodiments disclosed herein is provided.

[0017] Other and further embodiments of the present disclosure are described below.

[0018] Embodiments of the present disclosure, briefly summarized above and discussed in more detail below, can be understood by reference to exemplary embodiments of the present disclosure as illustrated in the accompanying drawings, which, however, depict merely typical embodiments of the present disclosure and should not be considered limiting in scope, as the present disclosure may admit of other equally effective embodiments. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a schematic side view of a three-dimensional dynamic random access memory (3D DRAM) structure according to the prior art. [Figures 2A-2C] 1A-1D are schematic side views of stages in the fabrication of a three-dimensional dynamic random access memory (3D DRAM) structure in accordance with at least some embodiments of the present disclosure. [Figure 3A-3C] 1A-1D are schematic side views of stages in the fabrication of a three-dimensional dynamic random access memory (3D DRAM) structure in accordance with at least some embodiments of the present disclosure. [Figures 4A-4C] 1A-1D are schematic side views of stages in the fabrication of a three-dimensional dynamic random access memory (3D DRAM) structure in accordance with at least some embodiments of the present disclosure. [Figures 5A-5C] 1A-1D are schematic side views of stages in the fabrication of a three-dimensional dynamic random access memory (3D DRAM) structure in accordance with at least some embodiments of the present disclosure. [Figures 6A-6C]1A-1D are schematic side views of stages in the fabrication of a three-dimensional dynamic random access memory (3D DRAM) structure in accordance with at least some embodiments of the present disclosure. [Figure 7A-7C] 1A-1D are schematic side views of stages in the fabrication of a three-dimensional dynamic random access memory (3D DRAM) structure in accordance with at least some embodiments of the present disclosure. [Figure 8] 1 is a flowchart illustrating a method of forming a three-dimensional dynamic random access memory (3D DRAM) structure in accordance with at least some embodiments of the present disclosure. [Figure 9] 1 is a schematic diagram of an apparatus for processing a substrate according to at least some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0020] For ease of understanding, identical reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0021] The methods and structures provided herein enable the fabrication of three-dimensional (3D) dynamic random access memory (DRAM) stacks. For example, the methods and structures provided herein enable the fabrication of 3D DRAM cells including a gate-all-around (GAA) structure around a crystalline silicon (c-Si) channel. For example, embodiments of the present disclosure provide improved enabling structures suitable for further use in fabricating 3D DRAM cells including a gate-all-around (GAA) structure or as part of a process sequence for fabricating 3D DRAM cells including a gate-all-around (GAA) structure. The Si / SiGe 3D memory structures provided herein advantageously reduce or eliminate relaxation or wafer bow observed in some other 3D memory structures.

[0022] 2A-2C illustrate schematic side views of stages in the fabrication of a 3D DRAM stack 200 in accordance with at least some embodiments of the present disclosure. The stack 200 includes alternating silicon (Si) layers 201 and silicon germanium (SiGe) layers 202. One or more of the SiGe layers 202 may have about 5 atomic percent to about 40 atomic percent, or about 10 atomic percent, of Ge present.

[0023] In an embodiment, one Si layer 201 may be vertically alternating with one SiGe layer 202. Although Figures 2A-2C (and each of the embodiments disclosed herein) illustrate only three alternating pairs of Si layer 201 and SiGe layer 202, a different number of alternating layers may be present in any of the disclosed embodiments. For example, in a typical 3D DRAM structure, there may be between 32 and about 128 repeating memory layers, or a total of about 250 or more layers.

[0024] In an embodiment, each of the Si layers 201 can have a height (e.g., thickness) that is greater than the height (e.g., thickness) of each of the SiGe layers 202. In an embodiment, one or more of the plurality of Si layers 201, including each of the plurality of Si layers 201, may be about 25 nm to about 50 nm high. In an embodiment, one or more of the plurality of SiGe layers 202, including all of the plurality of SiGe layers, may be about 3 nm to about 30 nm high.

[0025] 2A, stack 200 may be anisotropically etched to create vertical slits or holes (indicated by arrows 211) through alternating Si layers 201 and SiGe layers 202. The anisotropic etching may be performed in any suitable manner to form holes through each of alternating Si layers 201 and SiGe layers 202. While the holes are shown along the edges of the figure, those skilled in the art will recognize that holes are typically formed through layers having material on all sides, and that the exemplary features and processes described herein are typically performed to simultaneously fabricate multiple such features (holes, recesses, etc.) on a substrate such as a semiconductor wafer.

[0026] 2B, stack 200 may then be laterally isotropically etched (indicated by arrows 205) into one or more of the SiGe layers 202 to form recesses 206 in the SiGe layers 202 in areas adjacent to the holes (e.g., arrows 211). The lateral isotropic etching of SiGe layers 202 is selective to SiGe layers 202 compared to Si layers 201, and thus recesses 206 may be formed with little or no etching of Si layers 201.

[0027] Next, according to an embodiment, one or more of the Si layers 201 of the stack 200 may be isotropically etched (indicated by arrows 208), as shown in FIG. 2C . For example, the Si layer 201 may be isotropically etched to thin the Si layer 201 and form a thin portion 204 of the Si layer 201 adjacent the recess 206 formed in the SiGe layer 202. Such a thin portion 204 of the Si layer 201 may correspond to a Si channel region in a fully fabricated 3D DRAM device. In an embodiment, the one or more thin portions 204 may have a height (e.g., thickness) of about 10 nm to about 40 nm.

[0028] Thus, one or more cavities or openings 203 may be formed (e.g., as defined by recessed SiGe layer 202 and adjacent thinned portions 204 of Si layer 201). Opening 203 thus has a height approximately equal to the height of SiGe layer 202 and the height of the etched portions of Si layer 201 on opposite sides of opening 203. In an embodiment, one or more of the plurality of openings 203 may have a height (e.g., thickness) of about 10 nm to about 40 nm.

[0029] 3A-3C illustrate schematic side views of stages in the fabrication of a 3D DRAM structure according to at least some embodiments of the present disclosure. Similar layers and features may be those described above in connection with FIGS. 2A-2C. The structure may include a stack 300 of alternating Si layers 301 a,b and SiGe layers 302. One or more of the SiGe layers 302 may have about 5 atomic percent to about 40 atomic percent, or about 10 atomic percent, Ge present.

[0030] In an embodiment, stack 300 may include a vertically repeating series of layers, which may include one Si layer 301a, one SiGe layer 302 immediately adjacent to the Si layer 301a, one other Si layer 301b immediately adjacent to the SiGe layer 302, and one other SiGe layer 302 immediately adjacent to the Si layer 301b.

[0031] In embodiments, each of the Si layers 301 a,b may have a height greater than the height of each of the SiGe layers 302. In embodiments, one or more of the Si layers 301 b may have a height less than the height of one or more of the Si layers 301 a. One or more of the Si layers 301 a may be approximately 40 nm high. One or more of the Si layers 301 b may be approximately 20 nm high. One or more of the SiGe layers 302 may be approximately 3 nm to approximately 20 nm high.

[0032] 3A, the stack 300 may be anisotropically etched to create vertical slits or holes (indicated by arrows 311) through the alternating Si layers 301 a,b and SiGe layers 302. The anisotropic etching may be performed in any suitable manner to form holes through each of the alternating Si layers 301 a,b and SiGe layers 302. While the holes are shown along the edges of the figure, those skilled in the art will recognize that holes are typically formed through layers having material on all sides, and that the exemplary features and processes described herein are typically performed to simultaneously fabricate multiple such features (holes, recesses, etc.) on a substrate such as a semiconductor wafer.

[0033] 3B, one or more of the SiGe layers 302 of the stack 300 may then be isotropically etched laterally (indicated by arrows 305) to form recesses 306 in the SiGe layers 302 in areas adjacent the holes (e.g., arrows 311). The isotropic lateral etching of the SiGe layers 302 is selective to the SiGe layers 302 compared to the Si layers 301 a,b, and thus the recesses 306 may be formed with little or no etching of the Si layers 301 a,b.

[0034] Next, according to an embodiment, as shown in FIG. 3C , one or more of the Si layers 301 a and / or one or more of the Si layers 301 b of the stack 300 may be isotropically etched (indicated by arrows 308). For example, the Si layers 301 a, b may be isotropically etched to thin the Si layers 301 a, b to form a thinned portion 304 of the Si layer 301 a adjacent to the recess 306 formed in the SiGe layer 302. Furthermore, that portion of the Si layer 301 b adjacent to the recess 306 may be completely removed (e.g., due to a thinner thickness of the Si layer 301 b compared to the Si layer 301 a). Such thinned portion 304 of the Si layer 301 a may correspond to a Si channel region in a fully fabricated 3D DRAM device. In an embodiment, the one or more thinned portions 304 may be about 10 nm to about 40 nm in height.

[0035] One or more cavities or openings 303 can thus be formed (e.g., as defined by recessed SiGe layer 302, removed portions of Si layer 301b, and thinned portions 304 of adjacent Si layer 301a). Opening 303 thus has a height approximately equal to the height of the two SiGe layers 302 on either side of Si layer 301b, the height of Si layer 301b, and the height of the etched portions of Si layer 301a on opposite sides of opening 303. In an embodiment, one or more of the plurality of openings 303 may be about 30 nm to about 90 nm in height.

[0036] 4A-4C illustrate schematic side views of a 3D DRAM stack 400 in accordance with at least some embodiments of the present disclosure. Similar layers and features may be those described above in connection with FIGS. 2A-2C and 3A-3C. The stack 400 includes alternating undoped Si layers 401 a, doped Si layers 401 b, and doped SiGe layers 402. In embodiments, each doped Si layer 401 b may be positioned immediately adjacent to and opposite a doped SiGe layer 402. One or more of the SiGe layers 402 may have about 5 atomic percent to about 40 atomic percent, or about 10 atomic percent, of Ge present.

[0037] In an embodiment, the stack 400 may include a vertically repeating series of layers, the series of layers may include one undoped Si layer 401 a, one doped Si layer 401 b immediately adjacent to the undoped Si layer 401 a, one doped SiGe layer 402 immediately adjacent to the doped Si layer 401 b, and one other doped Si layer 401 b immediately adjacent to the doped SiGe layer 402.

[0038] In embodiments, the height of each undoped Si layer 401 a can be greater than the height of each doped Si layer 401 b and can also be greater than the height of each doped SiGe layer 402. One or more of the plurality of undoped Si layers 401 a can be about 25 nm to about 60 nm high, such as about 40 nm high. One or more of the plurality of doped Si layers 401 b can be sufficiently thin, such as about 5 nm to about 35 nm high, or about 5 nm high, so that the doped Si layer 401 b can be removed in subsequent processing, as discussed below. One or more of the plurality of doped SiGe layers 402 can be about 3 nm to about 15 nm high.

[0039] In embodiments, one or more of the plurality of doped Si layers 401b and one or more of the plurality of doped SiGe layers 402 may include one or more dopants. In embodiments, the dopant may be one or more of boron, carbon, nitrogen, oxygen, or phosphorus. The dopants in one or more of the plurality of doped Si layers 401b and one or more of the plurality of doped SiGe layers 402 may be the same or different dopants. In some embodiments, the dopant is the same in one or more of the plurality of doped Si layers 401b and one or more of the plurality of doped SiGe layers 402. In some embodiments, the dopant is carbon. In embodiments where the dopant is carbon, the dopant in one or more of the plurality of doped Si layers 401b and / or one or more of the plurality of doped SiGe layers 402 may be at a concentration of about 0.3 to about 1.5 atomic percent, such as about 1 atomic percent. In embodiments in which the dopant is boron or phosphorus, the dopant in one or more of the plurality of doped Si layers 401b and / or one or more of the plurality of doped SiGe layers 402 may be at a concentration of up to about 0.01 atomic percent. In embodiments in which the dopant is nitrogen or oxygen, the dopant in one or more of the plurality of doped Si layers 401b and / or one or more of the plurality of doped SiGe layers 402 may be at a concentration of up to about 100 ppm.

[0040] 4A, the stack 400 may be anisotropically etched to create vertical slits or holes (indicated by arrows 411) through the alternating Si layers 401 a,b and SiGe layers 402. The anisotropic etching may be performed in any suitable manner to form holes through each of the alternating Si layers 401 a,b and SiGe layers 402. While the holes are shown along the edges of the figure, those skilled in the art will recognize that holes are typically formed through layers that have material on all sides, and that the exemplary features and processes described herein are typically performed to simultaneously fabricate multiple such features (holes, recesses, etc.) on a substrate such as a semiconductor wafer.

[0041] 4B, one or more of the doped SiGe layers 402 of the stack 400 may then be isotropically etched laterally (indicated by arrows 405) to form recesses 406 in the doped SiGe layers 402 in areas adjacent the holes (e.g., arrows 411). The isotropic lateral etching of the SiGe layers 402 is selective to the SiGe layers 402 compared to the Si layers 401 a,b, and thus the recesses 406 may be formed with little or no etching of the Si layers 401 a,b.

[0042] Next, according to an embodiment, one or more of the plurality of undoped Si layers 401 a and one or more of the plurality of doped Si layers 401 b of the stack 400 may be isotropically etched (indicated by arrows 408), as shown in FIG. 4C . For example, the doped Si layer 401 b may be isotropically etched to remove that portion of the doped Si layer 401 b adjacent to the recess 406, and the undoped Si layer 401 a may be isotropically etched to thin the undoped Si layer 401 a to form a thin portion 404 of the undoped Si layer 401 a adjacent to the recess 406. Such a thin portion 404 of the undoped Si layer 401 a may correspond to a Si channel region in a fully fabricated 3D DRAM device. In an embodiment, the one or more thin portions 404 may be about 10 nm to about 40 nm in height.

[0043] One or more cavities or openings 403 can thus be formed (e.g., as defined by the doped SiGe layer 402, the doped Si layer 401b on opposite sides of the doped SiGe layer 402, and adjacent thin portions 404 of the undoped Si layer 401a on either side of the doped Si layer 401b). The openings 403 thus have a height approximately equal to the height of the doped SiGe layer 402 plus the height of the doped Si layer 401b on opposite sides of the doped SiGe layer 402 plus the height of the etched portions of the undoped Si layer 401a on either side of the doped Si layer 401b. In an embodiment, one or more of the plurality of openings 403 may be about 30 nm to about 90 nm in height.

[0044] 5A-5C illustrate schematic side views of a 3D DRAM stack 500 in accordance with at least some embodiments of the present disclosure. Similar layers and features may be those described above in connection with FIGS. 2A-2C, 3A-3C, and 4A-4C. The stack 500 may include alternating undoped Si layers 501 a, doped Si layers 501 b, and doped SiGe layers 502. In embodiments, each doped SiGe layer 502 may be positioned immediately adjacent to and opposite the doped Si layer 501 b. One or more of the SiGe layers 502 may have about 5 atomic percent to about 40 atomic percent, or about 10 atomic percent, Ge present.

[0045] In an embodiment, the stack 500 may include a vertically repeating series of layers, which may include one undoped Si layer 501 a, one doped SiGe layer 502 immediately adjacent to the undoped Si layer 501 a, one doped Si layer 501 b immediately adjacent to the doped SiGe layer 502, and one other doped SiGe layer 502 immediately adjacent to the doped Si layer 501 b.

[0046] In embodiments, the height of each undoped Si layer 501 a may be greater than the height of each doped Si layer 501 b, and may also be greater than the height of each doped SiGe layer 502. In embodiments, one or more of the plurality of undoped Si layers 501 a may be about 25 nm to about 60 nm high, such as about 40 nm high. In embodiments, one or more of the plurality of doped Si layers 501 b may be sufficiently thin, such as about 5 nm to about 35 nm high, or about 20 nm high, so that the doped Si layer 501 b can be removed in subsequent processing discussed below. In embodiments, one or more of the plurality of doped SiGe layers 502 may be about 3 nm to about 15 nm high, or about 10 nm high.

[0047] In embodiments, one or more of the plurality of doped Si layers 501b and one or more of the plurality of doped SiGe layers 502 may include one or more dopants. In embodiments, the dopant may be one or more of boron, carbon, nitrogen, oxygen, or phosphorus. The dopants in the doped Si layer and the doped SiGe layer may be the same or different dopants. In some embodiments, the dopant is the same in one or more of the plurality of doped Si layers and one or more of the plurality of doped SiGe layers. In some embodiments, the dopant is carbon. In embodiments, the dopant in one or more of the plurality of doped Si layers 501b and / or one or more of the plurality of doped SiGe layers 502 may be a dopant at a concentration described above in connection with FIG. 4 .

[0048] 5A, the stack 500 may be anisotropically etched to create vertical slits or holes (indicated by arrows 511) through the alternating undoped Si layers 501 a, doped Si layers 501 b, and doped SiGe layers 502. The anisotropic etching may be performed in any suitable manner to form holes through each of the alternating undoped Si layers 501 a, doped Si layers 501 b, and doped SiGe layers 502. While the holes are shown along the edges of the figure, those skilled in the art will recognize that holes are typically formed through layers having material on all sides, and that the exemplary features and processes described herein are typically performed to simultaneously fabricate multiple such features (holes, recesses, etc.) on a substrate such as a semiconductor wafer.

[0049] 5B, one or more of the doped SiGe layers 502 of the stack 500 may be laterally isotropically etched (indicated by arrows 505) to form recesses 506 in the doped SiGe layers 502 in areas adjacent the holes (e.g., arrows 511). The lateral isotropic etching of the doped SiGe layers 502 may be selective to the doped SiGe layers 502 compared to the Si layers 501 a,b, such that the recesses 506 may be formed with little or no etching of the Si layers 501 a,b.

[0050] Next, according to an embodiment, as shown in FIG. 5C , one or more of the plurality of undoped Si layers 501 a and / or one or more of the plurality of doped Si layers 501 b of the stack 500 may be isotropically etched (indicated by arrows 508). For example, the doped Si layer 501 b may be isotropically etched to remove that portion of the doped Si layer 501 b adjacent to the recess 506, and the undoped Si layer 501 a may be isotropically etched to thin the undoped Si layer 501 a to form a thin portion 504 of the undoped Si layer 501 a adjacent to the recess 506. Such a thin portion 504 of the undoped Si layer 501 a may correspond to a Si channel region in a fully fabricated 3D DRAM device. In an embodiment, the one or more thin portions 504 may be about 10 nm to about 40 nm in height.

[0051] Thus, one or more cavities or openings 503 can be formed (e.g., as defined by the doped SiGe layers 502, the doped Si layers 501b between the doped SiGe layers 502, and adjacent thin portions 504 of the undoped Si layer 501a on either side of the doped SiGe layers 502). The openings 503 thus have a height approximately equal to the height of the doped Si layer 501b plus the height of the doped SiGe layers 502 on opposite sides of the doped Si layer 501b plus the height of the etched portions of the undoped Si layer 501a on either side of the opening 503. In an embodiment, one or more of the plurality of openings 503 may be about 30 nm to about 90 nm in height.

[0052] 6A-6C illustrate schematic side views of a 3D DRAM stack 600 in accordance with at least some embodiments of the present disclosure. Similar layers and features may be those described above in connection with FIGS. 2A-2C, 3A-3C, 4A-4C, and 5A-5C. The stack 600 may include alternating undoped Si layers 601 a, doped Si layers 601 b, and doped SiGe layers 602. In embodiments, each doped SiGe layer 602 may be positioned immediately adjacent to and opposite the doped Si layer 601 b. One or more of the SiGe layers 602 may have about 5 atomic percent to about 40 atomic percent, or about 10 atomic percent, Ge present.

[0053] In an embodiment, the stack 600 may include a vertically repeating series of layers, which may include one undoped Si layer 601 a, one doped SiGe layer 602 immediately adjacent to the undoped Si layer 601 a, one doped Si layer 601 b immediately adjacent to the doped SiGe layer 602, and one other doped SiGe layer 602 immediately adjacent to the doped Si layer 601 b.

[0054] In embodiments, the height of each undoped Si layer 601 a may be greater than the height of each doped Si layer 601 b, and may also be greater than the height of each doped SiGe layer 602. In embodiments, one or more of the plurality of undoped Si layers 601 a may be about 25 nm to about 60 nm high, such as about 40 nm. In embodiments, one or more of the plurality of doped Si layers 601 b may be about 5 nm to about 35 nm high, such as about 20 nm high. In embodiments, one or more of the plurality of doped SiGe layers 602 may be about 3 nm to about 15 nm high, such as about 10 nm high.

[0055] In embodiments, one or more of the plurality of doped Si layers 601b and one or more of the plurality of doped SiGe layers 602 may include one or more dopants. In embodiments, the dopant may be one or more of boron, carbon, nitrogen, oxygen, or phosphorus. The dopants in the doped Si layer and the doped SiGe layer may be the same or different dopants. In some embodiments, the dopant is the same in one or more of the plurality of doped Si layers and one or more of the plurality of doped SiGe layers. In some embodiments, the dopant is carbon. In embodiments, the dopant in one or more of the plurality of doped Si layers 601b and / or one or more of the plurality of doped SiGe layers 602 may be a dopant at the concentrations described above.

[0056] In an embodiment, stack 600 may also include isolation layer 615, which may be immediately adjacent to and below doped SiGe layer 602. Additionally, isolation layer 615 may be near the lowest region of stack 600 (e.g., above substrate 613).

[0057] In an embodiment, the isolation layer 615 may include a vertically repeating series of layers, which may include one doped SiGe layer 615a and one doped Si layer 615b immediately adjacent to the doped SiGe layer 615a.

[0058] In embodiments, the height of each doped Si layer 615b may be greater than the height of each doped SiGe layer 615a. In embodiments, one or more of the plurality of doped Si layers 615b may be about 5 nm to about 35 nm, or about 20 nm high. In embodiments, one or more of the plurality of doped SiGe layers 615a may be about 3 nm to about 55 nm high, or about 10 nm high.

[0059] In an embodiment, one or more of the plurality of doped Si layers 615b and one or more of the plurality of doped SiGe layers 615a may include one or more dopants. In an embodiment, the dopants may be one or more of boron, carbon, nitrogen, oxygen, or phosphorus. In an embodiment, the dopants in one or more of the doped Si layers 615b and / or one or more of the plurality of doped SiGe layers 615a may be dopants at concentrations described above in connection with FIG. 4. The dopants in the doped Si layer 615b and the doped SiGe layer 615a, if present, are different from the dopants in any of the other Si or SiGe layers in the stack 600.

[0060] 6A , stack 600 may be anisotropically etched to create vertical slits or holes 610 at or near the bottom of stack 600, including through isolation layer 615. Then, according to an embodiment, isolation layer 615 of stack 600 may be selectively anisotropically etched to create vertical slits or holes (indicated by arrows 611) that may extend into, but not beyond, isolation layer 615. The anisotropic etching to form the holes may be performed in any suitable manner to form holes through each of the alternating undoped Si layers 601 a, doped Si layers 601 b, and doped SiGe layers 602, and may be etched partially into, but not through, isolation layer 615. Although holes are shown along the edges of the figures, those skilled in the art will recognize that holes are typically formed through layers with material on all sides, and that the exemplary features and processes described herein are typically performed to simultaneously fabricate multiple such features (holes, recesses, etc.) on a substrate such as a semiconductor wafer.

[0061] 6B, one or more of the plurality of doped SiGe layers 602 and / or one or more of the plurality of doped SiGe layers 615a of stack 600 may be laterally isotropically etched (indicated by arrows 605) to form a recess 606 in each of the etched layers in an area adjacent to the hole (e.g., arrow 611). The lateral isotropic etching of doped SiGe layer 602 and / or doped SiGe layer 615a may be selective to doped SiGe layer 602 and doped SiGe layer 615a compared to Si layers 601a,b and Si layer 615b, and thus recess 606 may be formed without significant or no etching of Si layers 601a,b or Si layer 615a.

[0062] 6C , one or more of the plurality of undoped Si layers 601 a, one or more of the plurality of doped Si layers 601 b, and one or more of the plurality of doped Si layers 615 b of the stack 600 may be isotropically etched (indicated by arrows 608). This isotropic etch may remove portions of the doped Si layer 601 b and the doped Si layer 615 b adjacent to the recess 606. This isotropic etch further thins the undoped Si layer 601 a to form a thin portion 604 of the undoped Si layer 601 a adjacent to the recess 606. This thin portion 604 of the undoped Si layer 601 a may correspond to a Si channel region in a fully fabricated 3D DRAM device. In an embodiment, the one or more thin portions 604 may be about 10 nm to about 40 nm in height.

[0063] One or more cavities or openings 603 can thus be formed (e.g., as defined by the doped SiGe layers 602, the doped Si layers 601b between the doped SiGe layers 502, and adjacent thin portions 604 of the undoped Si layer 601a on either side of the doped SiGe layers 602). The openings 603 thus have a height approximately equal to the height of the doped Si layer 601b plus the height of the doped SiGe layers 602 on opposite sides of the doped Si layer 601b plus the height of the etched portions of the undoped Si layer 601a on either side of the opening 603. In an embodiment, one or more of the plurality of openings 503 may be about 30 nm to about 90 nm in height.

[0064] 6C , the doped Si layer 615b adjacent to the recesses on either side of the doped Si layer 615b can be completely removed, while the bottommost one or more of the doped Si layers 615b can be thinned to leave a portion of the layer disposed on top of the substrate 613. Such a structure advantageously facilitates subsequent formation of bit lines 612 (shown by dashed lines in FIG. 6C ) that do not contact the substrate 613, thus preventing shorting of the bit lines 612 to the substrate 613 while still connecting to the openings 603. Although shown only in connection with FIGS. 6A-6C , a bottom isolation layer 615 can be provided in any of the embodiments described herein.

[0065] 7A-7C illustrate schematic side views of a 3D DRAM stack 700 in accordance with at least some embodiments of the present disclosure. Similar layers and features may be those described above in connection with FIGS. 2A-2C, 3A-3C, 4A-4C, 5A-5C, and 6A-6C. The stack 700 may include alternating undoped Si layers 701 and doped SiGe layers 702. In embodiments, one or more of the doped SiGe layers 702 may include a dopant gradient, which may have a doped central region 702a and doped outer regions 702b on either side of the central region 702a (e.g., doped outer SiGe layers and a central doped SiGe layer). Ge may be present in one or more of the doped SiGe layers 702 at about 5 atomic percent to about 40 atomic percent, or about 10 atomic percent.

[0066] In an embodiment, the stack 700 may include a repeating series of layers that may include one undoped Si layer 701, one doped SiGe outer region 702b immediately adjacent to the undoped Si layer 701, one doped SiGe central region 702a immediately adjacent to the doped SiGe outer region 702b, and one other doped SiGe outer region 702b immediately adjacent to the doped SiGe central region 702a.

[0067] In embodiments, the height of each Si layer 701 may be approximately equal to the height of each SiGe layer 702, may be greater than the height of each SiGe central region 702a, and may be greater than the height of each SiGe outer region 702b. In embodiments, one or more of the plurality of undoped Si layers 701 may be about 25 nm to about 50 nm high. In embodiments, one or more of the plurality of doped SiGe layers 702 may be about 3 nm to about 30 nm high. In embodiments, one or more of the plurality of doped SiGe central regions 702a may be about 1 nm to about 10 nm high. In embodiments, one or more of the plurality of doped SiGe outer regions may be about 1 nm to about 10 nm high.

[0068] In embodiments, one or more of the plurality of doped SiGe layers 702 may include one or more dopants. In embodiments, the dopants may be one or more of boron, carbon, nitrogen, oxygen, or phosphorus. In some embodiments, the dopant is carbon. The dopant in one or more of the plurality of doped SiGe central regions 702a may be at a higher concentration of dopant than the concentration in one or more of the plurality of doped SiGe outer regions 702b. In embodiments, the dopant in the central region 702a may be at a concentration of dopant described above in connection with FIG. 4.

[0069] 7A , stack 700 may be anisotropically etched to create vertical slits or holes (indicated by arrows 711) through alternating undoped Si layers 701 and doped SiGe layers 702. The anisotropic etching may be performed in any suitable manner to form holes through each of the alternating undoped Si layers 701 and doped SiGe layers 702. While the holes are shown along the edges of the figure, those skilled in the art will recognize that holes are typically formed through layers having material on all sides, and that the exemplary features and processes described herein are typically performed to simultaneously fabricate multiple such features (holes, recesses, etc.) on a substrate such as a semiconductor wafer.

[0070] 7B, one or more of the doped SiGe layers 702 of the stack 700 may then be isotropically etched laterally (indicated by arrows 705) to form recesses 706 in the doped SiGe layers 702 in areas adjacent the holes (e.g., arrows 711). The isotropic lateral etching of the doped SiGe layers 702 is selective to the doped SiGe layers 702 compared to the Si layers 701, and thus the recesses 706 may be formed with little or no etching of the Si layers 701.

[0071] Next, according to an embodiment, one or more of the undoped Si layers 701 of the stack 700 may be isotropically etched (indicated by arrows 708), as shown in FIG. 7C . For example, the Si layer 701 may be isotropically etched to thin the Si layer 701 and form a thin portion 704 of the Si layer 701 adjacent the recess 706. Such a thin portion 704 of the Si layer 701 may correspond to a Si channel region in a fully fabricated 3D DRAM device. In an embodiment, the one or more thin portions 704 may be about 5 nm to about 35 nm in height.

[0072] Thus, one or more cavities or openings 703 may be formed (e.g., as defined by the doped SiGe layer 702 adjacent to the thin portions 704 of the Si layer 701 on either side of the doped SiGe layer 702). The openings 703 thus have a height approximately equal to the height of the doped SiGe layer 702 and the height of the etched portions of the Si layer 701 on either side of the doped SiGe layer 702. In an embodiment, one or more of the plurality of openings 703 may be from about 30 nm to about 90 nm in height.

[0073] 8 illustrates a flowchart of a method 800 for forming a three-dimensional dynamic random access memory (3D DRAM) structure, such as by a heteroepitaxy process involving chemical vapor deposition or other known deposition techniques. Method 800 is suitable for use in fabricating the structures described above in connection with FIGS. 2A-2C, 3A-3C, 4A-4C, 5A-5C, 6A-6C, and 7A-7C, which respectively illustrate corresponding fabrication stages of various embodiments of the present disclosure.

[0074] Method 800 generally begins at 802 with the formation of a stack of alternating Si and SiGe layers (see, e.g., FIGS. 2A, 3A, 4A, 5A, 6A, and 7A). The stack of alternating Si and SiGe layers can be formed by any suitable process, such as chemical vapor deposition (CVD). For example, the stack can be formed by forming a first Si layer, followed by a first SiGe layer. The process can be repeated using a second Si layer, followed by a second SiGe layer. Similarly, alternating layers can continue to form as many layers as needed for one or more specific structures, thereby enabling highly flexible memory structure designs. For example, although only a few repeating layers are shown in the figures herein, the stack can include many more layers, such as 50 or more layers. In some embodiments, the concentration of germanium in the SiGe layer can be between about 5 atomic percent and about 40 atomic percent. While fabricating alternating Si and SiGe layers, the height (eg, thickness) of the Si layers is greater than the height of the SiGe layers.

[0075] At 802, the method 800 may optionally include adding a dopant to one or more of the plurality of Si layers (see, e.g., FIGS. 4A, 5A, 6A, and 7A). At 802, the method 800 may also optionally include adding a dopant to one or more of the plurality of SiGe layers (see, e.g., FIGS. 4A, 5A, 6A, and 7A). The dopant may be added in any suitable manner, such as by providing a desired amount of a gas including a dopant element during deposition of the doped layer.

[0076] In embodiments, at 804, method 800 may optionally include creating a dopant gradient in the one or more SiGe layers. The gradient may be stepped or continuous. For example, as shown in FIGS. 7A-7C , the doped SiGe layer may include a doped SiGe central region 702 a and a doped SiGe outer region 702 b, where the doped SiGe central region 702 a has a dopant concentration that is higher than the dopant concentration of the doped SiGe outer region 702 b. In some embodiments, the doped SiGe central region 702 a may be stepped up to a higher concentration. Alternatively, in some embodiments, the dopant concentration of the doped SiGe layer 702 may be gradually increased from the doped SiGe outer region 702 b below the doped SiGe central region 702 a to achieve a higher concentration.

[0077] At 806, the method 800 may include anisotropically etching vertical slits or holes in the stack. The anisotropic etching may be performed in a suitable etching chamber, such as a plasma etching chamber.

[0078] In embodiments, the method 800 may include isotropically etching a horizontal recess in at least one of the plurality of SiGe layers at 808. The isotropic etching at 808 may be performed in a suitable etch chamber, such as a plasma etch chamber. In some embodiments, the anisotropic etching at 806 and the isotropic etching at 808 may be performed in the same chamber. In some embodiments, the anisotropic etching at 806 and the isotropic etching at 808 may be performed in different chambers.

[0079] At 810, the method 800 may also include isotropically etching a horizontal recess in at least one of the plurality of Si layers and / or at least one of the plurality of SiGe layers. The isotropic etching at 810 may be performed in a suitable etching chamber, such as a plasma etching chamber. The isotropic etching at 808 and 810 may be performed in the same chamber or in different chambers. In some embodiments, the anisotropic etching at 806 and the isotropic etching at 808 and 810 may be performed in the same chamber. In some embodiments, the anisotropic etching at 806 and the isotropic etching at 808 and 810 may be performed in different chambers. The isotropic etching of the horizontal recesses in at least one of the plurality of Si layers and / or at least one of the plurality of SiGe layers can be performed in a sequence of several processes, such as first forming the recesses 206, 306, 406, 506, 606 and 706 described above, and then subsequently forming the openings 203, 303, 403, 503, 603 and 703.

[0080] The method typically ends at 810. However, the resulting structures shown in Figures 2C, 3C, 4C, 5C, 6C, and 7C can advantageously be further processed to continue fabricating 3D DRAM devices with reduced stress-induced defects compared to conventional 3D DRAM devices.

[0081] Although not shown in the figures described above, a base or substrate Si layer may be provided below one or more of the stacks 200, 300, 400, 500, 600, and 700. Additionally, lithography stacks may be provided on top of one or more of the stacks at various etching stages. Also, while the stacks are shown in the figures as having an exemplary number of repeating layers in the vertical / height direction, this exemplary number is provided for clarity of explanation and is not intended to limit the number of repeating sequences. Similarly, any one of the stacks, holes, recesses, etc. may be repeated in the horizontal / width direction.

[0082] The method 800 described above can be performed in a tool 900 (e.g., an integrated tool, i.e., a cluster tool) that includes suitable processing chambers configured for one or more of chemical vapor deposition (CVD) and plasma etching. Exemplary processing systems that can be used to perform the inventive methods disclosed herein include, but are not limited to, the ENDURA® line, CENTURA® line, or PRODUCER® line processing systems, commercially available from Applied Materials, Inc. of Santa Clara, California. Other processing chambers, including processing chambers from other manufacturers, can also be suitably used in conjunction with the teachings provided herein.

[0083] For example, the integrated tools described below (e.g., tool 900) facilitate operation of the methods described herein so that there is limited or no vacuum break between processes. Less vacuum braking can limit or prevent contamination (e.g., oxidation) of the tungsten liner layer or other portions of the substrate, can further improve throughput by shortening the amount of time between processes, and can reduce or eliminate certain processes, such as pre-cleaning or other operations, that would otherwise require sequential processes to be performed in stand-alone processing chambers.

[0084] Tool 900 includes a vacuum-tight processing platform (processing platform 901), a factory interface 904, and a system controller 902. Processing platform 901 includes multiple processing chambers, such as 914A, 914B, 914C, and 914D, operatively coupled to a vacuum substrate transfer chamber (transfer chamber 903). Factory interface 904 is operatively coupled to transfer chamber 903 by one or more load lock chambers (two load lock chambers, such as 906A and 906B, shown in FIG. 9).

[0085] In some embodiments, the factory interface 904 includes at least one docking station 907 and at least one factory interface robot 938 for facilitating the transfer of one or more semiconductor substrates (e.g., wafers). The docking station 907 is configured to receive one or more front-opening unified pods (FOUPs). Four FOUPs, such as 905A, 905B, 905C, and 905D, are shown in the embodiment of FIG. 9. The factory interface robot 938 is configured to transfer substrates from the factory interface 904 to the processing platform 901 via load lock chambers, such as 906A and 906B. Each of the load lock chambers 906A and 906B has a first port coupled to the factory interface 904 and a second port coupled to the transfer chamber 903. The load lock chambers 906A and 906B are coupled to a pressure control system (not shown) that pumps down and vents the load lock chambers 906A and 906B to facilitate the transfer of substrates between the vacuum environment of the transfer chamber 903 and the substantially ambient (e.g., atmospheric) environment of the factory interface 904. The transfer chamber 903 has a vacuum robot 942 disposed therein. The vacuum robot 942 is capable of transferring substrates 921 between the load lock chambers 906A and 906B and the processing chambers 914A, 914B, 914C, and 914D.

[0086] In some embodiments, processing chambers 914A, 914B, 914C, and 914D are coupled to transfer chamber 903. Processing chambers 914A, 914B, 914C, and 914D include at least a CVD chamber and a plasma etch chamber. Additional CVD chambers and / or etch chambers may also be provided.

[0087] In some embodiments, at least one deposition chamber configured to deposit a stack of alternating silicon (Si) and silicon germanium (SiGe) layers is provided, wherein a height of each Si layer is greater than a height of each SiGe layer as described above in any of Figures 2A, 3A, 4A, 5A, 6A, or 7A. In some embodiments, the at least one deposition chamber is further configured to provide one or more dopants in one or more of the plurality of Si layers and the plurality of SiGe layers as described above in any of Figures 4A, 5A, 6A, or 7A.

[0088] In some embodiments, a first plasma etch chamber is provided that is configured to anisotropically etch vertical holes (e.g., holes indicated by arrows 211, 311, 411, 511, 611, or 711) through a stack of alternating silicon (Si) and silicon germanium (SiGe) layers.

[0089] In some embodiments, a second plasma etch chamber is provided that is configured to isotropically etch the recesses described above in any of Figures 2B, 3B, 4B, 5B, 6B, or 7B (e.g., recesses 206, 306, 406, 506, 606, or 706). In some embodiments, the first plasma etch chamber is the same as the second plasma etch chamber. In some embodiments, the first plasma etch chamber is different from the second plasma etch chamber.

[0090] In some embodiments, a third plasma etch chamber is provided that is configured to isotropically etch the openings described above in any of Figures 2C, 3C, 4C, 5C, 6C, or 7C (e.g., openings 203, 303, 403, 503, 603, or 703). In some embodiments, the third plasma etch chamber is the same as the second plasma etch chamber. In some embodiments, the third plasma etch chamber is the same as the first plasma etch chamber and the second plasma etch chamber. In some embodiments, the third plasma etch chamber is different from the first plasma etch chamber and the second plasma etch chamber.

[0091] In some embodiments, one or more optional service chambers (shown as 916A and 916B) can be coupled to the transfer chamber 903. Service chambers 916A and 916B can be configured to perform other substrate processes such as degassing, bonding, chemical mechanical polishing (CMP), wafer cleaving, etching, plasma dicing, orientation, substrate metrology, cooling, etc.

[0092] The system controller 902 controls the operation of the tool 900 using direct control of the processing chambers 914A, 914B, 914C, and 914D, or alternatively, by controlling the processing chambers 914A, 914B, 914C, and 914D and a computer (or controller) associated with the tool 900. During operation, the system controller 902 enables data collection and feedback from the respective chambers and systems to optimize the performance of the tool 900. The system controller 902 typically includes a central processing unit (CPU) 930, memory 934, and support circuits 932. The CPU 930 may be any form of general-purpose computer processor that can be used in an industrial setting. The support circuits 932 are conventionally coupled to the CPU 930 and may include cache, clock circuits, input / output subsystems, power supplies, etc. Software routines, such as the processing methods described above, can be stored in memory 934 (e.g., a non-transitory computer-readable storage medium) and, when executed by CPU 930, transform the CPU 930 into a special-purpose computer (system controller 902). The software routines can also be stored in and / or executed by a second controller (not shown) located remotely from tool 900.

[0093] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof.

Claims

1. A stack of alternating silicon (Si) and silicon germanium (SiGe) layers, wherein the height of each Si layer is greater than the height of each SiGe layer.

1. A structure for fabricating a three-dimensional dynamic random access memory (3D DRAM) comprising:

2. 10. The structure for fabricating a 3D DRAM as claimed in claim 1, wherein at least one Si layer has a height that is less than a height of at least one other Si layer.

3. a doped separation layer disposed at the bottom of said stack of alternating layers; 10. The structure for manufacturing a 3D DRAM of claim 1, further comprising:

4. 4. The structure for fabricating a 3D DRAM according to claim 1, wherein at least one SiGe layer is a doped SiGe layer comprising at least one dopant comprising at least one of boron, carbon, nitrogen, oxygen or phosphorus.

5. 5. The structure for fabricating a 3D DRAM of claim 4, further comprising doped Si layers disposed on both sides of the doped SiGe layer, the doped Si layers having a height less than a height of the doped SiGe layers.

6. 4. The structure for fabricating a 3D DRAM according to claim 1, wherein the SiGe layers are doped SiGe layers including at least one dopant including at least one of boron, carbon, nitrogen, oxygen, or phosphorus, and the alternating Si layers are doped Si layers, and the height of each Si layer is greater than the height of each doped Si layer.

7. 4. The 3D DRAM structure of claim 1, wherein at least one pair of SiGe layers includes at least one dopant including at least one of boron, carbon, nitrogen, oxygen, or phosphorus, and further comprising a central SiGe layer disposed between each pair of SiGe layers of the at least one pair of SiGe layers, the central SiGe layer being doped and having a dopant concentration higher than a dopant concentration of the at least one pair of SiGe layers.

8. 1. A method of forming a three-dimensional dynamic random access memory (3D DRAM) structure, comprising: forming a stack of alternating silicon (Si) and silicon germanium (SiGe) layers, wherein the height of the Si layers is greater than the height of the SiGe layers; anisotropically etching vertical slits or holes in the stack; isotropically etching at least one of the plurality of SiGe layers to form a first horizontal recess, wherein the at least one SiGe layer is substantially completely removed between portions of the Si layer; isotropically etching a second horizontal recess in the portion of the Si layer adjacent the at least one etched SiGe layer to form a thinned portion of the Si layer, the first horizontal recess and the second horizontal recess together forming a cavity between adjacent Si layers; A method comprising:

9. The method of claim 8 , wherein forming the stack further comprises forming alternating Si layers at a height that is less than the height of other Si layers.

10. The method of claim 8 , wherein forming the stack further comprises forming a doped isolation layer disposed at the bottom of the stack of alternating layers.

11. 11. The method of claim 8, wherein forming the stack further comprises forming at least one SiGe layer as a doped SiGe layer including at least one dopant comprising at least one of boron, carbon, nitrogen, oxygen, or phosphorus.

12. 12. The method of claim 11, wherein forming the stack further comprises forming doped Si layers disposed on both sides of the doped SiGe layer, the doped Si layers having a height less than a height of the doped SiGe layer.

13. 11. The method of claim 8, wherein forming the stack further comprises forming the SiGe layers as doped SiGe layers including at least one dopant including at least one of boron, carbon, nitrogen, oxygen, or phosphorus, wherein the alternating Si layers are doped Si layers, and a height of each individual Si layer is greater than a height of each individual doped Si layer.

14. forming the stack forming at least one pair of SiGe layers having at least one dopant including at least one of boron, carbon, nitrogen, oxygen, or phosphorus; forming a central SiGe layer disposed between each pair of SiGe layers of the at least one pair of SiGe layers, the central SiGe layer being doped with a dopant concentration higher than a dopant concentration of the at least one pair of SiGe layers; 11. The method of any one of claims 8 to 10, further comprising:

15. A non-transitory computer readable medium having instructions formed thereon that, when executed, cause a processing chamber to perform a method, the method comprising: forming a stack of alternating silicon (Si) and silicon germanium (SiGe) layers, wherein the height of the Si layers is greater than the height of the SiGe layers; anisotropically etching vertical slits or holes in the stack; isotropically etching at least one of the plurality of SiGe layers to form a first horizontal recess, wherein the at least one SiGe layer is substantially completely removed between portions of the Si layer; isotropically etching a second horizontal recess in the portion of the Si layer adjacent the at least one etched SiGe layer to form a thinned portion of the Si layer, the first horizontal recess and the second horizontal recess together forming a cavity between adjacent Si layers; 1. A non-transitory computer-readable medium comprising:

16. 16. The computer-readable medium of claim 15, wherein forming the stack further comprises forming alternating Si layers at a height that is less than a height of other Si layers.

17. 16. The computer-readable medium of claim 15, wherein forming the stack further comprises forming a doped separation layer disposed at the bottom of the stack of alternating layers.

18. 18. The computer-readable medium of claim 15, wherein forming the stack further comprises forming at least one SiGe layer as a doped SiGe layer including at least one dopant comprising at least one of boron, carbon, nitrogen, oxygen, or phosphorus, and optionally, forming the stack further comprises forming doped Si layers disposed on both sides of the doped SiGe layer, the doped Si layers having a height less than a height of the doped SiGe layer.

19. 18. The computer-readable medium of claim 15, wherein forming the stack further comprises forming the SiGe layers as doped SiGe layers including at least one dopant including at least one of boron, carbon, nitrogen, oxygen, or phosphorus, wherein the alternating Si layers are doped Si layers, and a height of each individual Si layer is greater than a height of each individual doped Si layer.

20. forming the stack forming at least one pair of SiGe layers having at least one dopant including at least one of boron, carbon, nitrogen, oxygen, or phosphorus; forming a central SiGe layer disposed between each pair of SiGe layers of the at least one pair of SiGe layers, the central SiGe layer being doped with a dopant concentration higher than a dopant concentration of the at least one pair of SiGe layers; 18. The computer-readable medium of claim 15, further comprising:

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