Field effect transistor

Abstract

To suppress the dielectric breakdown of a gate insulating film when a current diffusion n-layer is provided.SOLUTION: A field effect transistor has a semiconductor substrate having a trench on an upper surface, a gate insulating film, and a gate electrode. The semiconductor substrate has a p-type body layer, and a lower n-layer disposed on a lower side of the body layer. The lower n-layer has a current diffusion n-layer being in contact with the body layer from below, and a low concentration n-layer being in contact with the current diffusion n-layer from below and having the n-type impurity concentration lower than that of the current diffusion n-layer. An inner surface of the trench has a side surface formed of a surface with a radius of curvature of 0.7 μm or more, and a bottom connection surface connecting the side surface and a lower end of the trench and formed of a concave curved surface with a radius of curvature of less than 0.7 μm. A portion having a peak value of the current diffusion n-layer is in contact with the gate insulating film on the side surface.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a field effect transistor.

[0002] The field-effect transistor disclosed in Patent Document 1 has a trench-type gate electrode. This field-effect transistor also has an n-type source layer, a p-type body layer, and a lower n-layer disposed below the body layer in an area adjacent to the gate insulating film. When a predetermined potential is applied to the gate electrode, a channel is formed in the body layer, and the source layer and the lower n-layer are connected by the channel. This turns on the field-effect transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-235546 Summary of the Invention [Problem to be solved by the invention]

[0004] A current-spreading n-layer with a high n-type impurity concentration may be provided in the area adjacent to the body layer in the lower n-layer. With this configuration, electrons that flow from the channel into the lower n-layer diffuse laterally within the current-spreading n-layer. This facilitates current diffusion and flow in the region of the lower n-layer below the current-spreading n-layer (the so-called drift layer), thereby reducing the on-resistance of the field-effect transistor. However, providing a current-spreading n-layer makes it easier for a high electric field to be generated in the gate insulating film in the area adjacent to the current-spreading n-layer. This specification proposes a technology for suppressing dielectric breakdown of the gate insulating film when a current-spreading n-layer is provided. [Means for solving the problem]

[0005] The field-effect transistor disclosed in this specification includes a semiconductor substrate having a trench on its upper surface, a gate insulating film covering the inner surface of the trench, and a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate includes an n-type source layer in contact with the gate insulating film, a p-type body layer below the source layer and in contact with the gate insulating film, and a lower n-layer disposed below the body layer. The lower n-layer includes a current spreading n-layer in contact with the body layer from below, and a low-concentration n-layer in contact with the current spreading n-layer from below and having a lower n-type impurity concentration than the current spreading n-layer. The n-type impurity concentration distribution in the current spreading n-layer in the depth direction of the semiconductor substrate is distributed so as to have a peak value. The inner surface of the trench includes a side surface formed by a surface with a curvature radius of 0.7 μm or more, and a bottom connection surface connecting the side surface to the bottom end of the trench and formed by a concave curved surface with a curvature radius of less than 0.7 μm. The portion of the current spreading n-layer having the peak value is in contact with the gate insulating film at the side surface.

[0006] A high electric field is likely to be applied to the gate insulating film in the area covering the bottom contact surface. Therefore, if a high-concentration n-layer is in contact with the gate insulating film in the area covering the bottom contact surface, an excessively high electric field is likely to be applied to that area of ​​the gate insulating film, making the gate insulating film prone to dielectric breakdown. In contrast, in the field-effect transistor disclosed in this specification, the portion of the current-spreading n-layer having a peak value is in contact with the gate insulating film on the side of the trench. The side of the trench has a relatively flat surface with a curvature radius of 0.7 μm or more. Therefore, even if the portion of the current-spreading n-layer having a peak value is in contact with the gate insulating film on the side of the trench, the electric field applied to the gate insulating film can be prevented from becoming excessively high. Therefore, in this field-effect transistor, the gate insulating film is less likely to undergo dielectric breakdown. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional perspective view of a MOSFET according to a first embodiment. [Figure 2] FIG. 2 is an enlarged cross-sectional view of the upper part of the MOSFET of Example 1. [Figure 3] FIG. 10 is an enlarged cross-sectional view of the upper part of the MOSFET of Example 2. [Figure 4] FIG. 10 is an enlarged cross-sectional view of an upper portion of a MOSFET according to a third embodiment. [Figure 5] FIG. 10 is an enlarged cross-sectional view of the upper portion of a MOSFET according to a fourth embodiment. [Figure 6] FIG. 10 is an enlarged cross-sectional view of the upper portion of a MOSFET according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the above-described field effect transistor, the current spreading n-layer may not be in contact with the gate insulating film at the bottom contact surface.

[0009] According to this configuration, it is possible to more effectively suppress the dielectric breakdown of the gate insulating film.

[0010] The above-described field effect transistor may further include a bottom p-layer in contact with the gate insulating film at the lower end of the trench.

[0011] This configuration can suppress the electric field applied to the gate insulating film around the bottom end of the trench.

[0012] In the above-described field-effect transistor, the bottom p layer may be in contact with the current spreading n layer within a range where the bottom p layer is in contact with the gate insulating film, and the thickness of the current spreading n layer between the body layer and the bottom p layer may be 0.1 μm or more.

[0013] This configuration ensures that the body layer and the bottom p-layer are separated by the current-spreading n-layer. [Example]

[0014] A MOSFET (metal-oxide-semiconductor field effect transistor) 10 shown in FIGS. 1 and 2 includes a semiconductor substrate 12. In FIGS. 1 and 2, the x direction is a direction parallel to an upper surface 12a of the semiconductor substrate 12, and the y direction is a direction parallel to the upper surface 12a and perpendicular to the x direction. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductors such as Si or GaN. The upper surface 12a of the semiconductor substrate 12 has a plurality of trenches 14. Each trench 14 extends in the y direction on the upper surface 12a. The trenches 14 are spaced apart in the x direction. The inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is disposed within each trench 14. The gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of the gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is disposed on the upper surface of the semiconductor substrate 12. The source electrode 22 covers the upper surface 12a of the semiconductor substrate 12 and the interlayer insulating film 20. The gate electrode 18 is insulated from the source electrode 22 by the interlayer insulating film 20. The lower surface 12b of the semiconductor substrate 12 is covered by a drain electrode 24.

[0015] 2, the trench 14 has a side surface 14a, a bottom connection surface 14b, and a bottom surface 14c. The side surface 14a is a flat surface (more specifically, a surface having a cross-sectional radius of curvature of 0.7 μm or more) extending along the depth direction (i.e., the thickness direction) of the semiconductor substrate 12. The bottom surface 14c is a surface extending approximately parallel to the upper surface 12a of the semiconductor substrate 12 and forms the lower end of the trench 14. The bottom connection surface 14b is a concave curved surface connecting the lower end of the side surface 14a and the bottom surface 14c. In cross section, the radius of curvature of the bottom connection surface 14b is less than 0.7 μm.

[0016] The semiconductor substrate 12 includes a source layer 30 , a body contact layer 32 , a body layer 34 , a bottom p-layer 36 , a connection p-layer 38 , and a lower n-layer 40 .

[0017] The source layer 30 is an n-type layer, and is in contact with the gate insulating film 16 at the upper end of the side surface 14a of the trench 14. The source layer 30 is in ohmic contact with the source electrode 22.

[0018] The body contact layer 32 is a p-type layer, and is in ohmic contact with the source electrode 22 at a position adjacent to the source layer 30 .

[0019] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the body contact layer 32. The body layer 34 contacts the source layer 30 and the body contact layer 32 from below. The body layer 34 contacts the gate insulating film 16 below the source layer 30. The body layer 34 contacts the gate insulating film 16 on the side surface 14a of the trench 14.

[0020] The bottom p-layer 36 is a p-type layer and is in contact with the gate insulating film 16 at the bottom surface 14c of the trench 14. The bottom p-layer 36 extends along the bottom surface 14c of the trench 14 in the y direction.

[0021] The connection p layer 38 is a p-type layer that protrudes downward from the body layer 34. When the semiconductor substrate 12 is viewed from above, the connection p layer 38 extends linearly along the x direction. The connection p layer 38 extends in the depth direction to the depth of the bottom p layer 36. The connection p layer 38 connects the body layer 34 and the bottom p layer 36.

[0022] The lower n layer 40 is disposed below the body layer 34. The lower n layer 40 is separated from the source layer 30 by the body layer 34. The lower n layer 40 is distributed from the lower end of the body layer 34 to the lower surface 12b of the semiconductor substrate 12. The lower n layer 40 includes a current spreading n layer 40a, an electric field relaxation n layer 40b, a drift layer 40c, a buffer layer 40d, and a drain layer 40e.

[0023] The current spreading n-layer 40a is an n-type layer having a relatively high concentration of n-type impurities. The current spreading n-layer 40a is in contact with the body layer 34 from below. The current spreading n-layer 40a is in contact with the gate insulating film 16 on the underside of the body layer 34.

[0024] The electric field relaxation n-layer 40b is an n-type layer having a lower n-type impurity concentration than the current spreading n-layer 40a. The electric field relaxation n-layer 40b contacts the current spreading n-layer 40a from below. The electric field relaxation n-layer 40b is distributed from the lower end of the current spreading n-layer 40a to a position below the bottom p-layer 36. The electric field relaxation n-layer 40b contacts the gate insulating film 16 below the current spreading n-layer 40a. The electric field relaxation n-layer 40b contacts the side and bottom surfaces of the bottom p-layer 36.

[0025] The drift layer 40c is an n-type layer having a lower n-type impurity concentration than the electric field relaxation n-layer 40b. The drift layer 40c is in contact with the electric field relaxation n-layer 40b from below.

[0026] The buffer layer 40d is an n-type layer having a higher n-type impurity concentration than the drift layer 40c. The buffer layer 40d is in contact with the drift layer 40c from below.

[0027] The drain layer 40e is an n-type layer having a higher n-type impurity concentration than the buffer layer 40d. The drain layer 40e is in contact with the buffer layer 40d from below. The drain layer 40e is in ohmic contact with the drain electrode 24.

[0028] 2, in the current spreading n-layer 40a, the n-type impurity concentration is distributed in a normal distribution pattern in the depth direction of the semiconductor substrate 12. In the current spreading n-layer 40a, the n-type impurity concentration is distributed in the depth direction of the semiconductor substrate 12 so as to have a peak value nmax. In other words, the current spreading n-layer 40a is the region where the n-type impurity concentration is distributed in a normal distribution pattern so as to have a peak value nmax. In the electric field relaxation n-layer 40b, the n-type impurity concentration is distributed at a substantially constant value that is lower than that in the current spreading n-layer 40a. In the drift layer 40c, the n-type impurity concentration is distributed at a substantially constant value that is lower than that in the electric field relaxation n-layer 40b.

[0029] The portion of the current spreading n-layer 40a having the peak value nmax is in contact with the gate insulating film 16 at the side surface 14a of the trench 14 (i.e., the surface having a radius of curvature of 0.7 μm or more). In Example 1, the entire current spreading n-layer 40a is in contact with the gate insulating film 16 at the side surface 14a of the trench 14. That is, the current spreading n-layer 40a is not in contact with the gate insulating film 16 at the bottom connection surface 14b of the trench 14. The electric field relaxation n-layer 40b is in contact with the gate insulating film 16 in the range between the current spreading n-layer 40a and the bottom p-layer 36. The electric field relaxation n-layer 40b is in contact with the gate insulating film 16 at the bottom connection surface 14b.

[0030] When the MOSFET 10 is in use, a higher potential is applied to the drain electrode 24 than to the source electrode 22. The potential of the gate electrode 18 is controlled independently of the potentials of the drain electrode 24 and the source electrode 22. When a potential higher than the gate threshold is applied to the gate electrode 18, a channel is formed in the body layer 34 adjacent to the gate insulating film 16, connecting the source layer 30 and the current-spreading n-layer 40a through the channel. Electrons then flow from the source layer 30 to the drain layer 40e via the channel, the current-spreading n-layer 40a, the field-relief n-layer 40b, the drift layer 40c, and the buffer layer 40d. This turns on the MOSFET 10. The current-spreading n-layer 40a has a relatively high n-type impurity concentration and thus low resistance. Therefore, electrons that flow from the channel into the current-spreading n-layer 40a tend to flow in the x-direction within the current-spreading n-layer 40a. Therefore, in the drift layer 40c located below the current-spreading n-layer 40a, electrons flow toward the drain layer 40e while being dispersed in the x direction. Since the electrons flow dispersedly in the drift layer 40c, the on-resistance of the MOSFET 10 is low.

[0031] When the potential of the gate electrode 18 is reduced to a potential below the gate threshold, the channel disappears and the flow of electrons stops. In other words, the MOSFET 10 is turned off. Then, a depletion layer extends from the body layer 34 into the current spreading n-layer 40a, the field relaxation n-layer 40b, and the drift layer 40c. The depletion layer extending into the current spreading n-layer 40a, the field relaxation n-layer 40b, and the drift layer 40c maintains the voltage between the drain electrode 24 and the source electrode 22. Furthermore, when the MOSFET 10 is turned off, a depletion layer also extends from the bottom p-layer 36 to the surrounding field relaxation n-layer 40b. The depletion layer extending from the bottom p-layer 36 suppresses electric field concentration near the bottom end of the trench 14.

[0032] When the current spreading n-layer 40a and the electric field relaxation n-layer 40b are depleted, an electric field is applied to the gate insulating film 16. The electric field is likely to concentrate in the curved portion of the gate insulating film 16. That is, the electric field is more likely to concentrate in the gate insulating film 16 covering the bottom connection surface 14b than in the gate insulating film 16 covering the side surface 14a. On the other hand, when the density of fixed charges in the depletion layer in contact with the gate insulating film 16 is high, the electric field applied to the gate insulating film 16 becomes stronger. That is, the higher the n-type impurity concentration in the n-type layer in contact with the gate insulating film 16, the stronger the electric field applied to the gate insulating film 16. In this embodiment, the electric field relaxation n-layer 40b, which has a low n-type impurity concentration, is in contact with the gate insulating film 16 at the bottom connection surface 14b, where electric field concentration is likely to occur. This prevents an excessively high electric field from being applied to the gate insulating film 16 covering the bottom connection surface 14b, thereby suppressing dielectric breakdown of the gate insulating film 16 in this portion. Furthermore, the current spreading n-layer 40a, which has a high concentration of n-type impurities, is connected to the gate insulating film 16 at the side surface 14a, where electric field concentration is unlikely to occur. This prevents an excessively high electric field from being applied to the gate insulating film 16 in the area in contact with the current spreading n-layer 40a, and suppresses dielectric breakdown of the gate insulating film 16 in this area.

[0033] As described above, according to the MOSFET 10 of this embodiment, the on-resistance of the MOSFET 10 can be reduced by the current-spreading n-layer 40a while the dielectric breakdown of the gate insulating film 16 is suppressed. [Example]

[0034] 3, the thickness of the current-spreading n-layer 40a is greater than that of the MOSFET 10 of Example 1. The other configurations of the MOSFET of Example 2 are the same as those of the MOSFET 10 of Example 1.

[0035] In Example 2, the lower end of the current spreading n-layer 40a is in contact with the gate insulating film 16 at the bottom connecting surface 14b. However, the portion of the current spreading n-layer 40a having the peak value nmax is in contact with the gate insulating film 16 at the side surface 14a. That is, the portion having the peak value nmax is not in contact with the gate insulating film 16 at the bottom connecting surface 14b, and the portion of the current spreading n-layer 40a having a low n-type impurity concentration is in contact with the gate insulating film 16 at the bottom connecting surface 14b. Therefore, even with this configuration, the electric field applied to the portion of the gate insulating film 16 covering the bottom connecting surface 14b can be suppressed. [Example]

[0036] The bottom p-layer 36 can be formed by ion implantation of p-type impurities into the bottom of the trench 14 before the formation of the gate electrode 18. In this case, as shown in FIG. 4, the bottom p-layer 36 may be formed so that the bottom p-layer 36 contacts the current spreading n-layer 40a from below in the area in contact with the gate insulating film 16. In this configuration, the bottom p-layer 36 contacts the gate insulating film 16 over the entire bottom connection surface 14b. This configuration also reduces the electric field applied to the gate insulating film 16 covering the bottom connection surface 14b.

[0037] 4, if the thickness T of the current-spreading n-layer 40a is too thin, the body layer 34 and the bottom p-layer 36 will not be sufficiently separated, resulting in poor MOSFET performance. To ensure separation between the body layer 34 and the bottom p-layer 36, the thickness T of the current-spreading n-layer 40a between the body layer 34 and the bottom p-layer 36 can be made thicker than the width W of the depletion layer that occurs in the current-spreading n-layer 40a when no voltage is applied to the MOSFET. The width W of the depletion layer can be calculated using the following formula: W=(2εVbi / qNd) -1 / 2 In the above equation, ε is the dielectric constant of the semiconductor substrate 12, Vbi is the built-in potential, q is the elementary charge, and Nd is the n-type impurity concentration of the current-spreading n-layer 40a. The built-in potential Vbi can be calculated using the following equation: Vbi = (kT / q) × ln(NaNd / ni 2 ) In the above equation, k is the Boltzmann constant, T is the temperature, Na is the p-type impurity concentration of the body layer 34, and ni is the intrinsic carrier density. More specifically, Na = 4 × 10 17 cm -3 , Nd=3×10 17 cm -3 , ni=1×10 -8 cm -3 In this case, the thickness T can be set to 0.1 μm or more. [Example]

[0038] 5, the MOSFET of Example 4 does not include an electric field relaxation n-layer 40b, and the drift layer 40c contacts the current spreading n-layer 40a from below. The other configurations of the MOSFET of Example 4 are the same as those of the MOSFET 10 of Example 1. In Example 4, the drift layer 40c, which has an even lower n-type impurity concentration than the electric field relaxation n-layer 40b, contacts the gate insulating film 16 at the bottom connection surface 14b. This makes it possible to more effectively suppress the electric field applied to the gate insulating film 16 covering the bottom connection surface 14b. [Example]

[0039] In the MOSFET of Example 5 shown in FIG. 6, the bottom p-layer 36 is not present. In this case, the connection p-layer 38 may not be provided. The other configurations of the MOSFET of Example 5 are the same as those of the MOSFET of Example 4. Even with this configuration, the electric field applied to the gate insulating film 16 covering the bottom connection surface 14b can be suppressed. In Examples 1 and 2, the bottom p-layer 36 may not be provided.

[0040] The electric field relaxation n-layer 40b in Examples 1 to 3 and the drift layer 40c in Examples 4 and 5 are examples of low-concentration n-layers.

[0041] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0042] 10: MOSFET, 12: semiconductor substrate, 14: trench, 14a: side surface, 14b: bottom connection surface, 16: gate insulating film, 18: gate electrode, 34: body layer, 40a: current diffusion n-layer, 40b: electric field relaxation n-layer, 40c: drift layer

Claims

1. A field effect transistor, a semiconductor substrate having a trench on an upper surface; a gate insulating film covering the inner surface of the trench; a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film; and The semiconductor substrate is an n-type source layer in contact with the gate insulating film; a p-type body layer in contact with the gate insulating film below the source layer; a lower n-layer disposed below the body layer; and the lower n-layer is a current spreading n-layer in contact with the body layer from below; a low-concentration n-layer that is in contact with the current-spreading n-layer from below and has a lower n-type impurity concentration than the current-spreading n-layer; and the n-type impurity concentration distribution in the current spreading n-layer in the depth direction of the semiconductor substrate is distributed so as to have a peak value, The inner surface of the trench is A side surface having a curvature radius of 0.7 μm or more; a bottom connection surface that connects the side surface and the bottom end of the trench and is formed by a concave curved surface with a curvature radius of less than 0.7 μm; and the portion of the current spreading n-layer having the peak value is in contact with the gate insulating film at the side surface; Field effect transistor.

2. 2. The field effect transistor of claim 1, wherein said current spreading n-layer does not contact said gate insulating film at said bottom connection surface.

3. 3. The field effect transistor according to claim 1, further comprising a bottom p-layer in contact with said gate insulating film at said lower end of said trench.

4. the bottom p-layer is in contact with the current spreading n-layer in a region where the bottom p-layer is in contact with the gate insulating film, the current spreading n-layer between the body layer and the bottom p-layer has a thickness of 0.1 μm or more; 4. The field effect transistor of claim 3.

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