Semiconductor device and vehicle

Abstract

To provide a semiconductor device capable of improving a degree of freedom in arrangement of constituents of the device.SOLUTION: A semiconductor device A10 comprises a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, a first power terminal 41, a second power terminal 42, and a third power terminal 43. The first power terminal 41 and the second power terminal 42 are separated from each other in a first direction x. The plurality of first semiconductor elements 31 is positioned between the first power terminal 41 and the second power terminal 42 in the first direction x and arrayed in the first direction x. The plurality of second semiconductor elements 32 is positioned between the second power terminal 42 and the plurality of first semiconductor elements 31 in the first direction x and arrayed in the first direction x. A voltage applied to the first power terminal 41 is higher than a voltage applied to the third power terminal 43.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a vehicle equipped with the semiconductor device. [Background technology]

[0002] Conventionally, semiconductor devices incorporating multiple semiconductor elements with switching functions, such as MOSFETs and IGBTs, have been widely known. Such semiconductor devices are primarily used for power conversion. Patent Document 1 discloses an example of such a semiconductor device. The semiconductor device disclosed in this document includes multiple first semiconductor elements and multiple second semiconductor elements, each of which is electrically connected to the multiple first semiconductor elements. The semiconductor device further includes a first terminal electrically connected to the multiple second semiconductor elements, a second terminal electrically connected to the multiple first semiconductor elements, and a third terminal electrically connected to the multiple first semiconductor elements and the multiple second semiconductor elements. The second terminal and the third terminal are located on opposite sides of the multiple first semiconductor elements and the multiple second semiconductor elements in a first direction.

[0003] In the semiconductor device disclosed in Patent Document 1, multiple first semiconductor elements are arranged in a second direction perpendicular to the first direction. Similarly, multiple second semiconductor elements are also arranged in the second direction. As a result, in this semiconductor device, the distance between the second terminal and the third terminal in the first direction x tends to become shorter. However, depending on the application of this semiconductor device, it may be necessary to increase the distance between the second terminal and the third terminal in the first direction x. In this case, it is difficult to meet this requirement with the configuration of this semiconductor device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-53801

[0005] [overview] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that allows for improved freedom in arranging the components of the device.

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: a plurality of first semiconductor elements, each having a first electrode and a second electrode; a plurality of second semiconductor elements, each having a third electrode and a fourth electrode; a first power terminal conducting to the first electrode; a second power terminal conducting to the second electrode and the third electrode; and a third power terminal conducting to the fourth electrode. The polarity of the third electrode is different from the polarity of the second electrode. The first power terminal and the second power terminal are spaced apart from each other in a first direction. The plurality of first semiconductor elements are located between the first power terminal and the second power terminal in the first direction and are arranged in the first direction. The plurality of second semiconductor elements are located between the second power terminal and the plurality of first semiconductor elements in the first direction and are arranged in the first direction. A voltage applied to the first power terminal is higher than a voltage applied to the third power terminal.

[0007] A second aspect of the present disclosure provides a vehicle including a drive source and a semiconductor device. The semiconductor device is electrically connected to the drive source. Compared to the semiconductor device provided by the first aspect of the present disclosure, the semiconductor device further includes a first conductive layer, a second conductive layer, a first conductive member, a second conductive member, an insulating layer, a first signal terminal, and a second signal terminal.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view corresponding to FIG. 1, seen through the sealing resin. [Figure 3]FIG. 3 is a plan view corresponding to FIG. 2, further showing the second conductive member. [Figure 4] FIG. 4 is a plan view corresponding to FIG. 2, in which the first conductive member and the second conductive member are omitted. [Figure 5] FIG. 5 is a bottom view of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a partially enlarged view of FIG. 8, showing the first semiconductor element and its vicinity. [Figure 11] FIG. 11 is a partially enlarged view of FIG. 9, showing the second semiconductor element and its vicinity. [Figure 12] FIG. 12 is a schematic diagram of a vehicle equipped with the semiconductor device shown in FIG. [Figure 13] FIG. 13 is a plan view of the semiconductor device according to the second embodiment of the present disclosure, showing the sealing resin and the second conductive member. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. [Figure 17] FIG. 17 is a plan view of the semiconductor device according to the third embodiment of the present disclosure, seen through the sealing resin. [Figure 18] FIG. 18 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure. [Figure 19] FIG. 19 is a plan view corresponding to FIG. 18, seen through the sealing resin. [Figure 20]FIG. 20 is a cross-sectional view taken along the line XX-XX in FIG. [Figure 21] FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. [Figure 22] FIG. 22 is a plan view of a semiconductor module according to an embodiment of the present disclosure. [Figure 23] FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. [Figure 24] FIG. 24 is a plan view of the semiconductor device according to the fifth embodiment of the present disclosure, seen through the sealing resin. [Figure 25] 25 is a partially enlarged cross-sectional view taken along line XXV-XXV in FIG. 24. FIG. [Figure 26] FIG. 26 is a partially enlarged cross-sectional view taken along line XXVI-XXVI in FIG. 24. [Figure 27] FIG. 27 is a plan view of a semiconductor device according to a first modified example of the fifth embodiment of the present disclosure, seen through a sealing resin. [Figure 28] FIG. 28 is a plan view of a semiconductor device according to a second modified example of the fifth embodiment of the present disclosure, seen through a sealing resin. [Figure 29] FIG. 29 is a plan view of a semiconductor device according to a third modified example of the fifth embodiment of the present disclosure, seen through a sealing resin. [Figure 30] FIG. 30 is a plan view of the semiconductor device according to the sixth embodiment of the present disclosure, seen through the sealing resin. [Figure 31] FIG. 31 is a plan view of a semiconductor device according to a first modified example of the sixth embodiment of the present disclosure, seen through a sealing resin. [Figure 32] FIG. 32 is a plan view of a semiconductor device according to a second modified example of the sixth embodiment of the present disclosure, seen through a sealing resin. [Figure 33] FIG. 33 is a plan view of a semiconductor device according to a third modified example of the sixth embodiment of the present disclosure, seen through a sealing resin.

[0010] [Detailed explanation] The details of the present disclosure will be described with reference to the accompanying drawings.

[0011] [First embodiment] A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 11. The semiconductor device A10 includes an insulating layer 11, a heat dissipation layer 12, a first conductive layer 13 to a fourth conductive layer 16, a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, a first power terminal 41 to a fourth power terminal 44, a first conductive member 55, a second conductive member 56, and a sealing resin 60. The semiconductor device A10 further includes first signal wiring 21 to a fourth signal wiring 24, a first substrate 27, a second substrate 28, a plurality of sleeves 29, a plurality of first protection elements 33, a plurality of second protection elements 34, a first signal terminal 45 to a fourth signal terminal 48, and a first wire 51 to a fourth wire 54. For ease of understanding, FIG. 2 shows the sealing resin 60 in a see-through manner. For ease of understanding, FIG. 3 shows the second conductive member 56 in a see-through manner in comparison with FIG. 2. For ease of understanding, Fig. 4 omits the first conductive member 55 and the second conductive member 56 from Fig. 2. In Figs. 2 to 4, the outline of the transmitted sealing resin 60 is shown by an imaginary line (two-dot chain line). In Fig. 3, the transmitted second conductive member 56 is shown by an imaginary line.

[0012] In the description of the semiconductor device A10, for convenience, a "first direction x," a "second direction z," and a "third direction y" are defined. The first direction x refers to a certain predetermined direction. The second direction z refers to a direction perpendicular to the first direction x. The second direction z corresponds to the normal direction of the first mounting surface 131 of the first conductive layer 13 described below. The third direction y refers to a direction perpendicular to each of the first direction x and the second direction z. Furthermore, in the description of the semiconductor device A10, "overlapping" refers to two different elements, and includes cases where one element entirely overlaps the other, as well as cases where one element partially overlaps the other.

[0013] The semiconductor device A10 converts DC power applied to the first power terminal 41, the third power terminal 43, and the fourth power terminal 44 into AC power using a plurality of first semiconductor elements 31 and a plurality of second semiconductor elements 32. The converted AC power is input to a power supply target such as a motor from the second power terminal 42. The semiconductor device A10 constitutes part of a power conversion circuit such as an inverter.

[0014] As shown in FIGS. 6 to 9 , the sealing resin 60 covers the plurality of first semiconductor elements 31, the plurality of second semiconductor elements 32, the plurality of first protective elements 33, and the plurality of second protective elements 34. The sealing resin 60 has electrical insulating properties. The sealing resin 60 is made of a material containing, for example, black epoxy resin. The sealing resin 60 has a top surface 61, a bottom surface 62, a first side surface 63, and a second side surface 64.

[0015] 6 to 9, the top surface 61 faces the same side in the second direction z as a first mounting surface 131 of the first conductive layer 13, which will be described later. The bottom surface 62 faces the opposite side to the top surface 61 in the second direction z.

[0016] 1 and 5 to 7, the first side surface 63 and the second side surface 64 face in opposite directions in the first direction x. The first side surface 63 and the second side surface 64 are connected to the top surface 61 and the bottom surface 62, respectively.

[0017] As shown in FIGS. 6 to 9 , the insulating layer 11 is located on the opposite side of the first semiconductor elements 31 and the second semiconductor elements 32 in the second direction z, with the first conductive layer 13 and the second conductive layer 14 as references. The insulating layer 11 carries the first conductive layer 13, the second conductive layer 14, the third conductive layer 15, and the fourth conductive layer 16. The elements including the insulating layer 11, the heat dissipation layer 12, and the first conductive layer 13 to the fourth conductive layer 16 are composed of a substrate formed by, for example, active metal brazing (AMB). The dimension of the insulating layer 11 in the second direction z is smaller than the dimensions of the heat dissipation layer 12, the first conductive layer 13, and the second conductive layer 14 in the second direction z. The insulating layer 11 is covered with a sealing resin 60.

[0018] As shown in FIGS. 6 to 9, the heat dissipation layer 12 is located on the opposite side of the insulating layer 11 from the first conductive layer 13 and the second conductive layer 14 in the second direction z. The heat dissipation layer 12 is bonded to the insulating layer 11. As shown in FIG. 5, the heat dissipation layer 12 is exposed from the bottom surface 62 of the sealing resin 60. When the semiconductor device A10 is in use, the heat dissipation layer 12 is bonded to a heat dissipation member 71, which will be described later. The composition of the heat dissipation layer 12 includes copper (Cu). As shown in FIG. 4, the heat dissipation layer 12 is located inward from the periphery 111 of the insulating layer 11 when viewed in the second direction z.

[0019] As shown in FIGS. 6 and 8, the first conductive layer 13 is located between the insulating layer 11 and the multiple first semiconductor elements 31 in the second direction z. The first conductive layer 13 is bonded to the insulating layer 11. The multiple first semiconductor elements 31 and the multiple first protective elements 33 are mounted on the first conductive layer 13. The first conductive layer 13 contains copper. The first conductive layer 13 is covered with a sealing resin 60. As shown in FIG. 4, the first conductive layer 13 overlaps the heat dissipation layer 12 as viewed in the second direction z. The first conductive layer 13 is located inward from the periphery 111 of the insulating layer 11 as viewed in the second direction z. As shown in FIGS. 6 to 8, the first conductive layer 13 has a first mounting surface 131 facing the side opposite to the side facing the insulating layer 11 in the second direction z.

[0020] As shown in FIGS. 6 and 9 , the second conductive layer 14 is located between the insulating layer 11 and the plurality of second semiconductor elements 32 in the second direction z. As shown in FIG. 4 , the second conductive layer 14 is spaced apart from the first conductive layer 13 in the first direction x. The second conductive layer 14 is bonded to the insulating layer 11. The second conductive layer 14 carries the plurality of second semiconductor elements 32 and the plurality of second protective elements 34. The second conductive layer 14 contains copper. The second conductive layer 14 is covered with a sealing resin 60. As shown in FIG. 4 , the second conductive layer 14 overlaps the heat dissipation layer 12 as viewed in the second direction z. As viewed in the second direction z, the second conductive layer 14 is located inward from the periphery 111 of the insulating layer 11. As shown in FIGS. 6 , 7 , and 9 , the second conductive layer 14 has a second mounting surface 141 facing the same side as the first mounting surface 131 of the first conductive layer 13 in the second direction z.

[0021] As shown in FIG. 6, the third conductive layer 15 is located on the same side as the first conductive layer 13 with respect to the insulating layer 11 in the second direction z. As shown in FIG. 4, the third conductive layer 15 is located on the opposite side of the second conductive layer 14 with respect to the first conductive layer 13 in the first direction x. The third conductive layer 15 is bonded to the insulating layer 11. The third conductive layer 15 supports the third power terminal 43. The third conductive layer 15 contains copper. The third conductive layer 15 is covered with a sealing resin 60. As shown in FIG. 4, the third conductive layer 15 overlaps the heat dissipation layer 12 with respect to the second direction z. The third conductive layer 15 is located inward of the periphery 111 of the insulating layer 11 with respect to the second direction z.

[0022] As shown in FIG. 4 , the fourth conductive layer 16 is located on the opposite side of the second conductive layer 14 from the first conductive layer 13 in the first direction x. The fourth conductive layer 16 is located on the opposite side of the third conductive layer 15 from the first conductive layer 13 in the third direction y. The fourth conductive layer 16 is located on the same side as the first conductive layer 13 from the insulating layer 11 in the second direction z. The fourth conductive layer 16 is bonded to the insulating layer 11. The fourth conductive layer 16 supports the fourth power terminal 44. The fourth conductive layer 16 contains copper. The fourth conductive layer 16 is covered with a sealing resin 60. As shown in FIG. 4 , the fourth conductive layer 16 overlaps the heat dissipation layer 12 as viewed in the second direction z. The fourth conductive layer 16 is located inward from the periphery 111 of the insulating layer 11 as viewed in the second direction z.

[0023] As shown in FIGS. 7 and 8, the first substrate 27 is located on the opposite side of the insulating layer 11 from the heat dissipation layer 12 in the second direction z. As shown in FIG. 4, the first substrate 27 is located between the first power terminal 41 and the second power terminal 42 in the first direction x. The first substrate 27 extends in the first direction x. The first substrate 27 includes an insulator. The first substrate 27 has a first insulating layer 271 as the insulator.

[0024] As shown in FIGS. 4 and 8, the first insulating layer 271 carries the first signal wiring 21 and the third signal wiring 23. The first insulating layer 271 is made of, for example, ceramics. Alternatively, the first insulating layer 271 may be made of a resin sheet. The first insulating layer 271 is bonded to the insulating layer 11 via a bonding layer 26. The bonding layer 26 is made of, for example, a material containing epoxy resin.

[0025] As shown in FIGS. 7 and 9, the second substrate 28 is located on the opposite side of the insulating layer 11 from the heat dissipation layer 12 in the second direction z. As shown in FIG. 4, the second substrate 28 is located between the first substrate 27 and the second power terminal 42 in the first direction x. The second substrate 28 extends in the first direction x. The second substrate 28 includes an insulator. The second substrate 28 has a second insulating layer 281 as the insulator. In the semiconductor device A10, the second substrate 28 is spaced apart from the first substrate 27 in the first direction x. Alternatively, the second substrate 28 may be connected to the first substrate 27.

[0026] 4 and 9, the second insulating layer 281 carries the second signal wiring 22 and the fourth signal wiring 24. The second insulating layer 281 is made of, for example, ceramics. Alternatively, the second insulating layer 281 may be made of a resin sheet. The second insulating layer 281 is bonded to the insulating layer 11 via the bonding layer 26.

[0027] As shown in FIGS. 6 and 8 , the multiple first semiconductor elements 31 are conductively bonded to the first mounting surface 131 of the first conductive layer 13. Each of the multiple first semiconductor elements 31 is the same element. Here, each of the multiple first semiconductor elements 31 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In addition, each of the multiple first semiconductor elements 31 includes a field-effect transistor including a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) or a bipolar transistor such as an IGBT (Insulated Gate Bipolar Transistor). In the description of the semiconductor device A10, each of the multiple first semiconductor elements 31 is an n-channel MOSFET with a vertical structure. Each of the multiple first semiconductor elements 31 includes a compound semiconductor substrate. The compound semiconductor substrate contains silicon carbide (SiC).

[0028] As shown in FIG. 4 , the multiple first semiconductor elements 31 are positioned between the first power terminal 41 and the second power terminal 42 in the first direction x and are arranged in the first direction x. The multiple first semiconductor elements 31 include first elements 31A and second elements 31B that are spaced apart from each other in the third direction y. The multiple first semiconductor elements 31 further include two groups that are spaced apart from each other in the third direction y with respect to the first substrate 27. Each of the two groups is arranged in the first direction x. One of the two groups includes the first element 31A. The other of the two groups includes the second element 31B.

[0029] As shown in FIGS. 4 and 10, each of the plurality of first semiconductor elements 31 has a first electrode 311, a second electrode 312 and a first gate electrode 313.

[0030] As shown in FIG. 10 , the first electrode 311 faces the first mounting surface 131 of the first conductive layer 13. In the semiconductor device A10, a current corresponding to the power before being converted by the first semiconductor element 31 flows through the first electrode 311. That is, the first electrode 311 corresponds to the drain of the first semiconductor element 31. The first electrode 311 is conductively bonded to the first mounting surface 131 via a bonding layer 39. As a result, the first electrode 311 of each of the multiple first semiconductor elements 31 is electrically connected to the first conductive layer 13. The bonding layer 39 is, for example, solder. Alternatively, the bonding layer 39 may be a sintered body of metal particles. In this case, the metal particles include, for example, silver (Ag).

[0031] 10 , the second electrode 312 is located on the opposite side to the first electrode 311 in the second direction z. In the semiconductor device A10, a current corresponding to the power converted by the first semiconductor element 31 flows through the second electrode 312. In other words, the second electrode 312 corresponds to the source of the first semiconductor element 31.

[0032] 10, the first gate electrode 313 is located on the same side as the second electrode 312 in the second direction z. A gate voltage for driving the first semiconductor element 31 is applied to the first gate electrode 313. As shown in FIG. 4, the area of ​​the first gate electrode 313 is smaller than the area of ​​the second electrode 312 when viewed in the second direction z.

[0033] As shown in FIG. 8 , the multiple first protection elements 33 are conductively bonded to the first mounting surface 131 of the first conductive layer 13. The multiple first protection elements 33 are individually connected in parallel to the multiple first semiconductor elements 31. Each of the multiple first protection elements 33 is a free wheel diode associated with one of the multiple first semiconductor elements 31. Each of the multiple first protection elements 33 is, for example, a Schottky barrier diode. As shown in FIG. 4 , the multiple first protection elements 33 are located between the first power terminal 41 and the second power terminal 42 in the first direction x and are arranged in the first direction x.

[0034] As shown in FIGS. 4 and 10 , each of the multiple first protection elements 33 has a first anode electrode 331 and a first cathode electrode 332. The first anode electrode 331 is located on the side of the first conductive layer 13 opposite the side facing the first mounting surface 131 in the second direction z. The first anode electrode 331 corresponds to the positive electrode of the first protection element 33. The first cathode electrode 332 is located on the side opposite the first anode electrode 331 in the second direction z. The first cathode electrode 332 corresponds to the negative electrode of the first protection element 33. The first cathode electrode 332 is conductively bonded to the first mounting surface 131 via the bonding layer 39. As a result, the first cathode electrode 332 of each of the multiple first protection elements 33 is individually electrically connected to the first electrode 311 of each of the multiple first semiconductor elements 31 via the first conductive layer 13.

[0035] 6 and 9, the multiple second semiconductor elements 32 are conductively bonded to the second mounting surface 141 of the second conductive layer 14. Each of the multiple second semiconductor elements 32 is the same element as each of the multiple first semiconductor elements 31. Therefore, each of the multiple second semiconductor elements 32 is an n-channel type MOSFET with a vertical structure.

[0036] As shown in FIG. 4 , the multiple second semiconductor elements 32 are positioned between the second power terminal 42 and the multiple first semiconductor elements 31 in the first direction x, and are arranged in the first direction x. The multiple second semiconductor elements 32 include a third element 32A and a fourth element 32B that are spaced apart from each other in the third direction y. The multiple second semiconductor elements 32 further include two groups that are spaced apart from each other in the third direction y with the second substrate 28 as the reference. Each of the two groups is arranged in the first direction x. One of the two groups includes the third element 32A. The other of the two groups includes the fourth element 32B.

[0037] As shown in FIGS. 4 and 11, each of the plurality of second semiconductor elements 32 has a third electrode 321, a fourth electrode 322 and a second gate electrode 323.

[0038] 11 , the third electrode 321 faces the second mounting surface 141 of the second conductive layer 14. In the semiconductor device A10, a current corresponding to the power before being converted by the second semiconductor element 32 flows through the third electrode 321. That is, the third electrode 321 corresponds to the drain of the second semiconductor element 32. Therefore, the polarity of the third electrode 321 is different from the polarity of the second electrode 312 of each of the multiple first semiconductor elements 31. The third electrode 321 is conductively bonded to the second mounting surface 141 via the bonding layer 39. As a result, the third electrode 321 of each of the multiple second semiconductor elements 32 is electrically connected to the second conductive layer 14.

[0039] 11 , the fourth electrode 322 is located on the opposite side to the third electrode 321 in the second direction z. In the semiconductor device A10, a current corresponding to the power converted by the second semiconductor element 32 flows through the fourth electrode 322. That is, the fourth electrode 322 corresponds to the source of the second semiconductor element 32.

[0040] 11, the second gate electrode 323 is located on the same side as the fourth electrode 322 in the second direction z. A gate voltage for driving the second semiconductor element 32 is applied to the second gate electrode 323. As shown in FIG. 4, the area of ​​the second gate electrode 323 is smaller than the area of ​​the fourth electrode 322 when viewed in the second direction z.

[0041] As shown in FIG. 9 , the multiple second protection elements 34 are conductively bonded to the second mounting surface 141 of the second conductive layer 14. The multiple second protection elements 34 are individually connected in parallel to the multiple second semiconductor elements 32. Each of the multiple second protection elements 34 is a freewheeling diode associated with one of the multiple second semiconductor elements 32. Each of the multiple second protection elements 34 is the same diode as each of the multiple first protection elements 33. As shown in FIG. 4 , the multiple second protection elements 34 are located between the second power terminal 42 and the multiple first semiconductor elements 31 in the first direction x, and are arranged in the first direction x.

[0042] As shown in FIGS. 4 and 11 , each of the multiple second protection elements 34 has a second anode electrode 341 and a second cathode electrode 342. The second anode electrode 341 is located on the side of the second conductive layer 14 opposite the side facing the second mounting surface 141 in the second direction z. The second anode electrode 341 corresponds to the positive electrode of the second protection element 34. The second cathode electrode 342 is located on the side opposite the second anode electrode 341 in the second direction z. The second cathode electrode 342 corresponds to the negative electrode of the second protection element 34. The second cathode electrode 342 is conductively bonded to the second mounting surface 141 via the bonding layer 39. As a result, the second cathode electrode 342 of each of the multiple second protection elements 34 is individually electrically connected to the third electrode 321 of each of the multiple second semiconductor elements 32 via the second conductive layer 14.

[0043] As shown in FIG. 8 , the first signal wiring 21 is located on the opposite side of the first conductive layer 13 in the second direction z with the first insulating layer 271 of the first substrate 27 as a reference. The first signal wiring 21 is bonded to the first insulating layer 271. The first signal wiring 21 extends in the first direction x. The first signal wiring 21 contains copper. The first signal wiring 21 is covered with a sealing resin 60.

[0044] As shown in FIG. 9 , the second signal wiring 22 is located on the opposite side of the second insulating layer 281 of the second substrate 28 from the second conductive layer 14 in the second direction z. The second signal wiring 22 is bonded to the second insulating layer 281. The second signal wiring 22 extends in the first direction x. The second signal wiring 22 contains copper. The second signal wiring 22 is covered with a sealing resin 60.

[0045] As shown in FIG. 8 , the third signal wiring 23 is located on the opposite side of the first conductive layer 13 in the second direction z with the first insulating layer 271 of the first substrate 27 as a reference. The third signal wiring 23 is located next to the first signal wiring 21 in the third direction y. The third signal wiring 23 is bonded to the first insulating layer 271. The third signal wiring 23 extends in the first direction x. The composition of the third signal wiring 23 includes copper. The third signal wiring 23 is covered with a sealing resin 60.

[0046] As shown in FIG. 9 , the fourth signal wiring 24 is located on the opposite side of the second conductive layer 14 in the second direction z with the second insulating layer 281 of the second substrate 28 as a reference. The fourth signal wiring 24 is located next to the second signal wiring 22 in the third direction y. The fourth signal wiring 24 is bonded to the second insulating layer 281. The fourth signal wiring 24 extends in the first direction x. The composition of the fourth signal wiring 24 includes copper. The fourth signal wiring 24 is covered with a sealing resin 60.

[0047] 7, the multiple sleeves 29 are individually conductively bonded to the first signal wiring 21, the second signal wiring 22, the third signal wiring 23, and the fourth signal wiring 24 via bonding layers 39. Each of the multiple sleeves 29 has a cylindrical shape extending in the second direction z. The multiple sleeves 29 are made of a conductive material such as metal.

[0048] 4 and 7, the first power terminal 41 is conductively bonded to the first mounting surface 131 of the first conductive layer 13. As a result, the first power terminal 41 is electrically connected to the first electrodes 311 of the multiple first semiconductor elements 31 via the first conductive layer 13. A portion of the first power terminal 41 protrudes from the first side surface 63 of the sealing resin 60. In the semiconductor device A10, the first power terminal 41 is a P terminal (positive electrode) to which DC power to be converted is applied. The composition of the first power terminal 41 includes copper.

[0049] As shown in FIGS. 4 and 6 , the third power terminal 43 is conductively bonded to the third conductive layer 15. Therefore, the third power terminal 43 is located adjacent to the first power terminal 41 in the third direction y. The fourth power terminal 44 is conductively bonded to the fourth conductive layer 16 as shown in FIG. 4. Therefore, the fourth power terminal 44 is located on the opposite side of the first power terminal 41 from the third power terminal 43 in the third direction y. A portion of each of the third power terminal 43 and the fourth power terminal 44 protrudes from the first side surface 63 of the sealing resin 60. In the semiconductor device A10, the third power terminal 43 and the fourth power terminal 44 are N terminals (negative electrodes) to which DC power to be converted is applied. Therefore, the voltage applied to the first power terminal 41 is higher than the voltage applied to each of the third power terminal 43 and the fourth power terminal 44. The composition of each of the third power terminal 43 and the fourth power terminal 44 includes copper.

[0050] As shown in FIGS. 4 and 7 , the second power terminal 42 is conductively bonded to the second mounting surface 141 of the second conductive layer 14. As a result, the second power terminal 42 is electrically connected to the third electrodes 321 of the second semiconductor elements 32 via the second conductive layer 14. The second power terminal 42 is spaced apart from the first power terminal 41 in the first direction x and is located on the opposite side of the first power terminal 41 from the first power terminal 41 in the first direction x relative to the first semiconductor elements 31 and the second semiconductor elements 32. A portion of the second power terminal 42 protrudes from the second side surface 64 of the sealing resin 60. The AC power converted from DC power by the first semiconductor elements 31 and the second semiconductor elements 32 is output from the second power terminal 42. The second power terminal 42 contains copper.

[0051] As shown in FIG. 6 , the first conductive member 55 is located on the opposite side of the first semiconductor elements 31 from the first conductive layer 13 in the second direction z. The first conductive member 55 is a metal clip. The first conductive member 55 contains copper. The first conductive member 55 is covered with a sealing resin 60. The first conductive member 55 is conductively bonded to the second electrode 312 of each of the first semiconductor elements 31, the first anode electrode 331 of each of the first protection elements 33, and the second mounting surface 141 of the second conductive layer 14 via the bonding layer 39. As a result, the second electrode 312 of each of the first semiconductor elements 31 is electrically connected to the second power terminal 42 via the second conductive layer 14. In addition, the first anode electrode 331 of each of the first protection elements 33 is individually electrically connected to the second electrode 312 of each of the first semiconductor elements 31.

[0052] As shown in FIG. 6 , the second conductive member 56 is located on the opposite side of the first conductive layer 13 in the second direction z with respect to the first conductive member 55. As shown in FIG. 2 , the second conductive member 56 overlaps the first conductive member 55 when viewed in the second direction z. The second conductive member 56 is a metal clip. The second conductive member 56 contains copper. The second conductive member 56 is covered with a sealing resin 60. The second conductive member 56 is conductively bonded to the fourth electrodes 322 of the second semiconductor elements 32 and the second anode electrodes 341 of the second protection elements 34 via the bonding layer 39. The second conductive member 56 is also conductively bonded to the third power terminal 43 and the fourth power terminal 44. As a result, the fourth electrodes 322 of the second semiconductor elements 32 are electrically connected to the third power terminal 43 and the fourth power terminal 44. In addition, the second anode electrode 341 of each of the plurality of second protection elements 34 is individually connected to the fourth electrode 322 of each of the plurality of second semiconductor elements 32.

[0053] 2, when viewed in the second direction z, the second conductive member 56 overlaps each of the third conductive layer 15 and the third power terminal 43. When viewed in the second direction z, the second conductive member 56 overlaps each of the fourth conductive layer 16 and the fourth power terminal 44.

[0054] As shown in FIGS. 4 and 7 , the first signal terminal 45 is press-fitted into one of the multiple sleeves 29 that is conductively joined to the first signal wiring 21. This allows the first signal terminal 45 to be electrically connected to the first signal wiring 21. A gate voltage for driving the multiple first semiconductor elements 31 is applied to the first signal terminal 45. The first signal terminal 45 is a metal pin that extends in the second direction z. A portion of the first signal terminal 45 protrudes from the top surface 61 of the sealing resin 60. The first signal terminal 45 is located between the first element 31A and the second element 31B that constitute the multiple first semiconductor elements 31 in the third direction y.

[0055] 4 and 10, each of the multiple first wires 51 is conductively bonded to the first gate electrode 313 of each of the multiple first semiconductor elements 31 and the first signal wiring 21. As a result, the first signal terminal 45 and the first signal wiring 21 are electrically connected to the first gate electrode 313 of each of the multiple first semiconductor elements 31. As shown in FIG. 8, the multiple first wires 51 are covered with a sealing resin 60. The composition of the multiple first wires 51 includes aluminum (Al). Alternatively, the composition of the multiple first wires 51 may include either gold (Au) or copper.

[0056] As shown in FIGS. 4 and 7 , the second signal terminal 46 is press-fitted into one of the multiple sleeves 29 that is conductively bonded to the second signal wiring 22. This electrically connects the second signal terminal 46 to the second signal wiring 22. A gate voltage for driving the multiple second semiconductor elements 32 is applied to the second signal terminal 46. The second signal terminal 46 is a metal pin extending in the second direction z. A portion of the second signal terminal 46 protrudes from the top surface 61 of the sealing resin 60. The second signal terminal 46 is located between a third element 32A and a fourth element 32B that constitute the multiple second semiconductor elements 32 in the third direction y.

[0057] As shown in FIGS. 4 and 11 , each of the multiple second wires 52 is conductively bonded to the second gate electrode 323 of each of the multiple second semiconductor elements 32 and the second signal wiring 22. As a result, the second signal terminal 46 and the second signal wiring 22 are electrically connected to the second gate electrode 323 of each of the multiple second semiconductor elements 32. As shown in FIG. 9 , the multiple second wires 52 are covered with a sealing resin 60. The composition of the multiple second wires 52 includes aluminum. Alternatively, the composition of the multiple second wires 52 may include either gold or copper.

[0058] 4 and 7 , the third signal terminal 47 is press-fitted into one of the multiple sleeves 29 that is conductively joined to the third signal wiring 23. This allows the third signal terminal 47 to be electrically connected to the third signal wiring 23. A voltage having the same potential as the voltage applied to each second electrode 312 of the multiple first semiconductor elements 31 is applied to the third signal terminal 47. The third signal terminal 47 is a metal pin that extends in the second direction z. A portion of the third signal terminal 47 protrudes from the top surface 61 of the sealing resin 60.

[0059] 4, each of the multiple third wires 53 is conductively bonded to the second electrode 312 of each of the multiple first semiconductor elements 31 and the third signal wiring 23. As a result, the third signal terminal 47 and the third signal wiring 23 are electrically connected to the second electrode 312 of each of the multiple first semiconductor elements 31. The multiple third wires 53 are covered with a sealing resin 60. The composition of the multiple third wires 53 includes aluminum. Alternatively, the composition of the multiple third wires 53 may include either gold or copper.

[0060] 4 and 7 , the fourth signal terminal 48 is press-fitted into one of the multiple sleeves 29 that is conductively joined to the fourth signal wiring 24. This allows the fourth signal terminal 48 to be electrically connected to the fourth signal wiring 24. A voltage having the same potential as the voltage applied to each of the fourth electrodes 322 of the multiple second semiconductor elements 32 is applied to the fourth signal terminal 48. The fourth signal terminal 48 is a metal pin that extends in the second direction z. A portion of the fourth signal terminal 48 protrudes from the top surface 61 of the sealing resin 60.

[0061] 4, each of the multiple fourth wires 54 is conductively bonded to the fourth electrode 322 of each of the multiple second semiconductor elements 32 and the fourth signal wiring 24. As a result, the fourth signal terminal 48 and the fourth signal wiring 24 are electrically connected to the fourth electrode 322 of each of the multiple second semiconductor elements 32. The multiple fourth wires 54 are covered with a sealing resin 60. The composition of the multiple fourth wires 54 includes aluminum. Alternatively, the composition of the multiple fourth wires 54 may include either gold or copper.

[0062] 1, the first signal terminal 45, the second signal terminal 46, the third signal terminal 47, and the fourth signal terminal 48 are arranged in a first direction x. As shown in Fig. 2, the first signal terminal 45 to the fourth signal terminal 48 are surrounded by a first conductive member 55 and a second conductive member 56 when viewed in a second direction z.

[0063] Next, a vehicle C equipped with the semiconductor device A10 will be described with reference to Fig. 12. The vehicle C is, for example, an electric vehicle (EV).

[0064] As shown in FIG. 12, vehicle C includes an on-board charger 91, a storage battery 92, and a drive system 93. Power is supplied to the on-board charger 91 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 91 via a wired connection. The on-board charger 91 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 91 is stepped up by the converter and then supplied to the storage battery 92. The stepped-up voltage is, for example, 600V.

[0065] The drive system 93 drives the vehicle C. The drive system 93 includes an inverter 931 and a drive source 932. The semiconductor device A10 constitutes a part of the inverter 931. Alternatively, the inverter 931 may include a plurality of the aforementioned semiconductor modules B. Power stored in the storage battery 92 is supplied to the inverter 931. The power supplied from the storage battery 92 to the inverter 931 is DC power. Alternatively, unlike the power system shown in FIG. 12 , a step-up DC-DC converter may be further provided between the storage battery 92 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 including the semiconductor device A10 is electrically connected to the drive source 932. The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates, and the rotation is transmitted to the transmission. The transmission rotates the drive shaft of vehicle C after appropriately reducing the rotation speed transmitted from the AC motor. This drives vehicle C. To drive vehicle C, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, semiconductor device A10 in inverter 931 is necessary to output AC power whose frequency is appropriately changed to correspond to the required rotation speed of the AC motor.

[0066] Next, the effects of the semiconductor device A10 will be described.

[0067] The semiconductor device A10 includes a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, a first power terminal 41, a second power terminal 42, and a third power terminal 43. The first power terminal 41 and the second power terminal 42 are spaced apart from each other in the first direction x. The plurality of first semiconductor elements 31 are positioned between the first power terminal 41 and the second power terminal 42 in the first direction x and are arranged in the first direction x. The plurality of second semiconductor elements 32 are positioned between the second power terminal 42 and the plurality of first semiconductor elements 31 in the first direction x and are arranged in the first direction x. The voltage applied to the first power terminal 41 is higher than the voltage applied to the third power terminal 43. This configuration allows the semiconductor device A10 to exhibit its power conversion function while increasing the distance between the first power terminal 41 and the second power terminal 42 in the first direction x. Therefore, this configuration allows the semiconductor device A10 to have greater flexibility in the arrangement of its components.

[0068] The semiconductor device A10 includes a first signal terminal 45 electrically connected to the first gate electrode 313 of each of the plurality of first semiconductor elements 31 and a second signal terminal 46 electrically connected to the second gate electrode 323 of each of the plurality of second semiconductor elements 32. The first signal terminal 45 is located between the first element 31A and the second element 31B constituting the plurality of first semiconductor elements 31 in the third direction y. The second signal terminal 46 is located between the third element 32A and the fourth element 32B constituting the plurality of second semiconductor elements 32 in the third direction y. With this configuration, the first signal terminal 45 and the second signal terminal 46 are each located near the center of the semiconductor device A10 in the third direction y. This allows for the integration of circuits on the wiring board when the first signal terminal 45 and the second signal terminal 46 are connected to the wiring board.

[0069] The semiconductor device A10 further includes an insulating layer 11, a heat dissipation layer 12, a first conductive layer 13, and a second conductive layer 14. The plurality of first semiconductor elements 31 are conductively joined to the first conductive layer 13. The plurality of second semiconductor elements 32 are conductively joined to the second conductive layer 14. With this configuration, heat generated from each of the plurality of first semiconductor elements 31 and the plurality of second semiconductor elements 32 can be conducted from either the first conductive layer 13 or the second conductive layer 14 to the heat dissipation layer 12 via the insulating layer 11. This improves the heat dissipation performance of the semiconductor device A10.

[0070] The semiconductor device A10 further includes a third conductive layer 15 and a second conductive member 56. As viewed in the second direction z, the third conductive layer 15 overlaps the heat dissipation layer 12. The third power terminal 43 is conductively joined to the third conductive layer 15. The second conductive member 56 is conductively joined to the third power terminal 43. As viewed in the second direction z, the second conductive member 56 overlaps each of the third conductive layer 15 and the third power terminal 43. With this configuration, heat generated from the second electrode 312 of each of the multiple second semiconductor elements 32 can be conducted from the third power terminal 43 to the heat dissipation layer 12 via the third conductive layer 15 and the insulating layer 11.

[0071] Second Embodiment A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 13 to 16. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Figure 13 shows the sealing resin 60 and the second conductive member 56 in a see-through view. In Figure 13, the outlines of the sealing resin 60 and the second conductive member 56 are shown by imaginary lines.

[0072] In the semiconductor device A20, the configurations of the first substrate 27 and the second substrate 28 are different from those of the semiconductor device A10.

[0073] As shown in FIGS. 14 and 15 , the first substrate 27 has a first insulating layer 271 and a first metal layer 272. The configuration of the first insulating layer 271 is similar to the configuration of the first insulating layer 271 of the first substrate 27 included in the semiconductor device A10. The first metal layer 272 is located between the first mounting surface 131 of the first conductive layer 13 and the first insulating layer 271 in the second direction z. The first metal layer 272 is bonded to the first insulating layer 271. The first metal layer 272 contains copper. The first metal layer 272 is bonded to the first mounting surface 131 via a bonding layer 39.

[0074] As shown in FIGS. 14 and 16 , the second substrate 28 has a second insulating layer 281 and a second metal layer 282. The configuration of the second insulating layer 281 is similar to the configuration of the second insulating layer 281 of the second substrate 28 included in the semiconductor device A10. The second metal layer 282 is located between the second mounting surface 141 of the second conductive layer 14 and the second insulating layer 281 in the second direction z. The second metal layer 282 is bonded to the second insulating layer 281. The second metal layer 282 contains copper. The second metal layer 282 is bonded to the second mounting surface 141 via a bonding layer 39.

[0075] Next, the effects of the semiconductor device A20 will be described.

[0076] The semiconductor device A20 includes a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, a first power terminal 41, a second power terminal 42, and a third power terminal 43. The first power terminal 41 and the second power terminal 42 are spaced apart from each other in the first direction x. The plurality of first semiconductor elements 31 are located between the first power terminal 41 and the second power terminal 42 in the first direction x and are arranged in the first direction x. The plurality of second semiconductor elements 32 are located between the second power terminal 42 and the plurality of first semiconductor elements 31 in the first direction x and are arranged in the first direction x. The voltage applied to the first power terminal 41 is higher than the voltage applied to the third power terminal 43. Therefore, this configuration allows the semiconductor device A20 to have greater flexibility in the arrangement of its own components. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0077] In the semiconductor device A20, the first substrate 27 has a first insulating layer 271 and a first metal layer 272. The first metal layer 272 is located between the first mounting surface 131 of the first conductive layer 13 and the first insulating layer 271. The first metal layer 272 is bonded to the first mounting surface 131. This configuration allows the volume of the first conductive layer 13 to be increased compared to the configuration of the first conductive layer 13 included in the semiconductor device A10. This makes it easier for heat conducted from the multiple first semiconductor elements 31 to the first conductive layer 13 to be diffused in the first conductive layer 13.

[0078] Third Embodiment A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to FIG. 17. In this figure, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, FIG. 17 is viewed through the sealing resin 60. In FIG. 17, the outline of the sealing resin 60 is shown by imaginary lines.

[0079] In the semiconductor device A30, the configuration of the second conductive member 56 is different from that of the semiconductor device A10.

[0080] As shown in FIG. 17, the second conductive member 56 is spaced apart from the first conductive member 55 when viewed in the second direction z.

[0081] Next, the effects of the semiconductor device A30 will be described.

[0082] The semiconductor device A30 includes a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, a first power terminal 41, a second power terminal 42, and a third power terminal 43. The first power terminal 41 and the second power terminal 42 are spaced apart from each other in the first direction x. The plurality of first semiconductor elements 31 are located between the first power terminal 41 and the second power terminal 42 in the first direction x and are arranged in the first direction x. The plurality of second semiconductor elements 32 are located between the second power terminal 42 and the plurality of first semiconductor elements 31 in the first direction x and are arranged in the first direction x. The voltage applied to the first power terminal 41 is higher than the voltage applied to the third power terminal 43. Therefore, this configuration allows the semiconductor device A30 to have greater flexibility in the arrangement of its own components. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0083] In the semiconductor device A30, the second conductive member 56 is spaced apart from the first conductive member 55 when viewed in the second direction z. This configuration reduces the flow obstruction of the molten resin in the mold caused by the first conductive member 55 and the second conductive member 56 when forming the sealing resin 60 in the manufacture of the semiconductor device A30. This makes the formed sealing resin 60 denser.

[0084] [Fourth embodiment] A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to Figures 18 to 21. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Figure 19 shows a perspective view of the sealing resin 60. In Figure 19, the outline of the sealing resin 60 is shown by imaginary lines.

[0085] The semiconductor device A40 differs from the semiconductor device A10 in the configuration of the sealing resin 60 and in that it further includes a first dummy terminal 58 and a second dummy terminal 59.

[0086] 18 and 20, a first opening 65 is provided in the sealing resin 60, penetrating from the top surface 61 to the bottom surface 62. When viewed in the second direction z, the first opening 65 is spaced apart from the insulating layer 11. As shown in FIGS. 18 and 21, a second opening 66 is provided in the sealing resin 60, penetrating from the top surface 61 to the bottom surface 62. When viewed in the second direction z, the second opening 66 is spaced apart from the insulating layer 11. The second opening 66 is located on the opposite side of the second power terminal 42 from the first opening 65 in the third direction y.

[0087] As shown in FIG. 19 , the first dummy terminal 58 and the second dummy terminal 59 are located on opposite sides of the second power terminal 42 in the third direction y. The first dummy terminal 58 and the second dummy terminal 59 are each separated from the insulating layer 11, the first conductive layer 13, the second conductive layer 14, the first conductive member 55, and the second conductive member 56. Therefore, the first dummy terminal 58 and the second dummy terminal 59 are not included in the conductive path of the semiconductor device A40. During the manufacture of the semiconductor device A40, the first dummy terminal 58 and the second dummy terminal 59 are included in the same lead frame as the first power terminal 41, the second power terminal 42, the third power terminal 43, and the fourth power terminal 44. Therefore, the composition of each of the first dummy terminal 58 and the second dummy terminal 59 is the same as the composition of each of the first to fourth power terminals 41 to 44.

[0088] 19 and 20 , the first dummy terminal 58 has a first engagement portion 581. The first engagement portion 581 is exposed from a first opening 65 of the sealing resin 60. The first engagement portion 581 penetrates the first dummy terminal 58 in the second direction z. When viewed in the second direction z, the first engagement portion 581 is located inward from a periphery 651 of the first opening 65 and is spaced apart from the insulating layer 11. In the second direction z, the first engagement portion 581 is spaced apart from each of the top surface 61 and the bottom surface 62 of the sealing resin 60.

[0089] 19 and 21, the second dummy terminal 59 has a second engagement portion 591. The second engagement portion 591 is exposed from the second opening 66 of the sealing resin 60. The second engagement portion 591 penetrates the second dummy terminal 59 in the second direction z. As viewed in the second direction z, the second engagement portion 591 is located inward from the periphery 661 of the second opening 66 and is spaced apart from the insulating layer 11. In the second direction z, the second engagement portion 591 is spaced apart from each of the top surface 61 and the bottom surface 62 of the sealing resin 60.

[0090] 18, 20, and 21, a portion of each of the first dummy terminal 58 and the second dummy terminal 59 protrudes from the second side surface 64 of the sealing resin 60. As shown in Fig. 19, when viewed in the second direction z, the shape of the second engagement portion 591 differs from the shape of the first engagement portion 581. In the semiconductor device A40, the first engagement portion 581 is circular, while the second engagement portion 591 is oval in shape extending in the third direction y.

[0091] Next, a semiconductor module B according to an embodiment of the present disclosure will be described with reference to Figures 22 and 23. The semiconductor module B includes a plurality of semiconductor devices A40, a heat dissipation member 71, and a bonding layer 72.

[0092] The plurality of semiconductor devices A40 are mounted on a heat dissipation member 71. The plurality of semiconductor devices A40 are arranged along the third direction y on the heat dissipation member 71. In describing the semiconductor module B, one semiconductor device A40 will be extracted and described from the plurality of semiconductor devices A40.

[0093] The heat dissipation member 71 is used to cool the semiconductor device A40. The heat dissipation member 71 contains metal. For example, the heat dissipation member 71 is made of a material containing aluminum. In the semiconductor module B, the heat dissipation member 71 is flat. Additionally, the heat dissipation member 71 may be provided with fins or the like on one side in the second direction z to improve heat dissipation.

[0094] 22 and 23, the heat dissipation member 71 has a mounting surface 71A, a first protrusion 711, and a second protrusion 712. The mounting surface 71A faces the bottom surface 62 of the sealing resin 60 of the semiconductor device A40. The first protrusion 711 and the second protrusion 712 protrude from the mounting surface 71A. The first protrusion 711 is inserted into the first opening 65 of the semiconductor device A40 and engages with the first engagement portion 581 of the semiconductor device A40. The second protrusion 712 is inserted into the second opening 66 of the semiconductor device A40 and engages with the second engagement portion 591 of the semiconductor device A40. This allows the semiconductor device A40 to be positioned relative to the heat dissipation member 71 in the semiconductor module B.

[0095] 23, the bonding layer 72 bonds the mounting surface 71A of the heat dissipation member 71 to the heat dissipation layer 12 of the semiconductor device A40. The bonding layer 72 includes a sintered body of metal particles. The metal particles include silver. Alternatively, the metal particles may include copper.

[0096] Next, the effects of the semiconductor device A40 will be described.

[0097] The semiconductor device A40 includes a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, a first power terminal 41, a second power terminal 42, and a third power terminal 43. The first power terminal 41 and the second power terminal 42 are spaced apart from each other in the first direction x. The plurality of first semiconductor elements 31 are located between the first power terminal 41 and the second power terminal 42 in the first direction x and are arranged in the first direction x. The plurality of second semiconductor elements 32 are located between the second power terminal 42 and the plurality of first semiconductor elements 31 in the first direction x and are arranged in the first direction x. The voltage applied to the first power terminal 41 is higher than the voltage applied to the third power terminal 43. Therefore, this configuration allows the semiconductor device A40 to have greater flexibility in the arrangement of its own components. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A40 achieves the same effects as the semiconductor device A10.

[0098] The semiconductor device A40 further includes a first dummy terminal 58 spaced apart from the first conductive layer 13 and the second conductive layer 14. The sealing resin 60 has a first opening 65 penetrating from the top surface 61 to the bottom surface 62. The first dummy terminal 58 has a first engagement portion 581 exposed through the first opening 65. This configuration allows the first protrusion 711 of the heat dissipation member 71 to be inserted into the first opening 65 and engage with the first engagement portion 581 in the semiconductor module B, as shown in FIGS. 22 and 23 . This reduces misalignment of the semiconductor device A40 relative to the heat dissipation member 71. Furthermore, during manufacturing of the semiconductor device A40, the first dummy terminal 58 and the second power terminal 42 are included in the same lead frame, allowing the first engagement portion 581 to be set based on the position of the lead frame. This makes it possible to effectively reduce misalignment between the second power terminal 42 and the connection target (such as a motor) in the semiconductor module B, compared to when the first engagement portion 581 is set based on the insulating layer 11.

[0099] As viewed in the second direction z, the first engagement portion 581 is located inward of the periphery 651 of the first opening 65 of the sealing resin 60. In the second direction z, the first engagement portion 581 is spaced apart from both the top surface 61 and the bottom surface 62 of the sealing resin 60. The first engagement portion 581 penetrates the first dummy terminal 58 in the second direction z. This configuration allows ejector pins to be inserted into both sides of the first opening 65 in the second direction z when forming the sealing resin 60 in the manufacture of the semiconductor device A40. This prevents molten resin from flowing into the first engagement portion 581 when forming the sealing resin 60. Furthermore, in the semiconductor module B, the dimension of the first protrusion 711 of the heat dissipation member 71 in the second direction z can be freely set.

[0100] The semiconductor device A40 further includes a second dummy terminal 59 spaced apart from each of the first conductive layer 13 and the second conductive layer 14. A second opening 66 is provided in the sealing resin 60, penetrating from the top surface 61 to the bottom surface 62. The second dummy terminal 59 has a second engagement portion 591 exposed from the second opening 66. As viewed in the second direction z, the size of the second engagement portion 591 is different from the size of the first engagement portion 581. With this configuration, when positioning the semiconductor device A40 relative to the heat dissipation member 71, it becomes easier to adjust the position of the semiconductor device A40 in a direction perpendicular to the second direction z, and rotation of the semiconductor device A40 around the second direction z can be restricted.

[0101] Fifth Embodiment A semiconductor device A50 according to a fifth embodiment of the present disclosure will be described with reference to FIGS. 24 to 26. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, FIG. 24 shows a perspective view of the sealing resin 60. In FIG. 24, the outline of the sealing resin 60 is shown by imaginary lines.

[0102] The semiconductor device A50 differs from the semiconductor device A10 in that it further comprises a plurality of third semiconductor elements 35, a plurality of fourth semiconductor elements 36, a plurality of third protective elements 37, and a plurality of fourth protective elements 38.

[0103] As shown in FIGS. 24 and 25 , the multiple third semiconductor elements 35 are conductively bonded to the first mounting surface 131 of the first conductive layer 13. Each of the multiple third semiconductor elements 35 is an IGBT. On the other hand, each of the multiple first semiconductor elements 31 is a MOSFET with a vertical structure. Therefore, the structure of each of the multiple third semiconductor elements 35 is different from the structure of each of the multiple first semiconductor elements 31.

[0104] 24, the multiple third semiconductor elements 35 are located between the first power terminal 41 and the second power terminal 42 in the first direction x and are arranged in the first direction x. The multiple third semiconductor elements 35 are located on the opposite side of the multiple first semiconductor elements 31 with respect to the first substrate 27 in the third direction y.

[0105] As shown in FIG. 25, each of the plurality of third semiconductor elements 35 has a fifth electrode 351, a sixth electrode 352 and a third gate electrode 353.

[0106] 25 , the fifth electrode 351 faces the first mounting surface 131 of the first conductive layer 13. In the semiconductor device A50, a current corresponding to the power before being converted by the third semiconductor element 35 flows through the fifth electrode 351. That is, the fifth electrode 351 corresponds to the collector of the third semiconductor element 35. The fifth electrode 351 is conductively bonded to the first mounting surface 131 via the bonding layer 39. As a result, the fifth electrode 351 of each of the multiple third semiconductor elements 35 is electrically connected to the first conductive layer 13 and the first electrode 311 of each of the multiple first semiconductor elements 31.

[0107] 25 , the sixth electrode 352 is located on the opposite side to the fifth electrode 351 in the second direction z. In the semiconductor device A50, a current corresponding to the power converted by the third semiconductor element 35 flows through the sixth electrode 352. That is, the sixth electrode 352 corresponds to the emitter of the third semiconductor element 35. The sixth electrode 352 is conductively bonded to the first conductive member 55 via the bonding layer 39. As a result, the sixth electrode 352 of each of the multiple third semiconductor elements 35 is electrically connected to the second power terminal 42 via the second conductive layer 14, and is also electrically connected to the second electrode 312 of each of the multiple first semiconductor elements 31.

[0108] 25, the third gate electrode 353 is located on the same side in the second direction z as the sixth electrode 352. A gate voltage for driving the third semiconductor element 35 is applied to the third gate electrode 353.

[0109] 25 , some of the multiple first wires 51 are individually conductively bonded to the third gate electrodes 353 of the multiple third semiconductor elements 35, and are also conductively bonded to the first signal wiring 21. As a result, the third gate electrodes 353 of each of the multiple third semiconductor elements 35 are electrically connected to the first signal terminal 45. Among the multiple third wires 53, some of the third wires 53 are individually conductively bonded to the sixth electrodes 352 of each of the multiple third semiconductor elements 35, and are also conductively bonded to the third signal wiring 23. As a result, the sixth electrodes 352 of each of the multiple third semiconductor elements 35 are electrically connected to the third signal terminal 47.

[0110] As shown in FIGS. 24 and 25 , the multiple third protection elements 37 are conductively bonded to the first mounting surface 131 of the first conductive layer 13. The multiple third protection elements 37 are individually connected in parallel to the multiple third semiconductor elements 35. Each of the multiple third protection elements 37 is a freewheeling diode associated with one of the multiple third semiconductor elements 35. Each of the multiple third protection elements 37 is, for example, either a fast recovery diode or a Schottky barrier diode. As shown in FIG. 24 , the multiple third protection elements 37 are located between the first power terminal 41 and the second power terminal 42 in the first direction x and are arranged in the first direction x.

[0111] As shown in FIG. 25 , each of the multiple third protection elements 37 has a third anode electrode 371 and a third cathode electrode 372. The third anode electrode 371 is located on the side of the first conductive layer 13 opposite to the side facing the first mounting surface 131 in the second direction z. The third anode electrode 371 corresponds to the positive electrode of the third protection element 37. The third anode electrode 371 is conductively bonded to the first conductive member 55 via the bonding layer 39. As a result, the third anode electrode 371 of each of the multiple third protection elements 37 is individually conductively connected to the sixth electrode 352 of each of the multiple third semiconductor elements 35. The third cathode electrode 372 is located on the side opposite to the third anode electrode 371 in the second direction z. The third cathode electrode 372 corresponds to the negative electrode of the third protection element 37. The third cathode electrode 372 is conductively bonded to the first mounting surface 131 via the bonding layer 39. As a result, the third cathode electrode 372 of each of the plurality of third protection elements 37 is individually electrically connected to the fifth electrode 351 of each of the plurality of third semiconductor elements 35 via the first conductive layer 13.

[0112] As shown in FIGS. 24 and 26 , the multiple fourth semiconductor elements 36 are conductively bonded to the second mounting surface 141 of the second conductive layer 14. Each of the multiple fourth semiconductor elements 36 is an IGBT. On the other hand, each of the multiple second semiconductor elements 32 is a MOSFET with a vertical structure. Therefore, the structure of each of the multiple fourth semiconductor elements 36 is different from the structure of each of the multiple second semiconductor elements 32.

[0113] 24, the multiple fourth semiconductor elements 36 are located between the second power terminal 42 and the multiple first semiconductor elements 31 in the first direction x, and are arranged in the first direction x. The multiple fourth semiconductor elements 36 are located on the opposite side of the multiple second semiconductor elements 32 with respect to the second substrate 28 in the third direction y. Furthermore, in the semiconductor device A50, the multiple fourth semiconductor elements 36 face the multiple third semiconductor elements 35 in the first direction x.

[0114] As shown in FIG. 26, each of the plurality of fourth semiconductor elements 36 has a seventh electrode 361, an eighth electrode 362 and a fourth gate electrode 363.

[0115] 26 , the seventh electrode 361 faces the second mounting surface 141 of the second conductive layer 14. In the semiconductor device A50, a current corresponding to the power before being converted by the fourth semiconductor element 36 flows through the seventh electrode 361. That is, the seventh electrode 361 corresponds to the collector of the fourth semiconductor element 36. Therefore, the polarity of the seventh electrode 361 is different from the polarity of the sixth electrode 352 of each of the multiple third semiconductor elements 35. The seventh electrode 361 is conductively bonded to the second mounting surface 141 via the bonding layer 39. As a result, the seventh electrode 361 of each of the multiple fourth semiconductor elements 36 is electrically connected to the second conductive layer 14 and the third electrode 321 of each of the multiple second semiconductor elements 32.

[0116] 26 , the eighth electrode 362 is located on the opposite side to the seventh electrode 361 in the second direction z. In the semiconductor device A50, a current corresponding to the power converted by the fourth semiconductor element 36 flows through the eighth electrode 362. That is, the eighth electrode 362 corresponds to the emitter of the fourth semiconductor element 36. The eighth electrode 362 is conductively bonded to the second conductive member 56 via the bonding layer 39. As a result, the eighth electrode 362 of each of the multiple fourth semiconductor elements 36 is electrically connected to the third power terminal 43 and the fourth power terminal 44, and is also electrically connected to the fourth electrode 322 of each of the multiple second semiconductor elements 32.

[0117] 26, the fourth gate electrode 363 is located on the same side in the second direction z as the eighth electrode 362. A gate voltage for driving the fourth semiconductor element 36 is applied to the fourth gate electrode 363.

[0118] 26 , some of the second wires 52 are individually conductively bonded to the fourth gate electrodes 363 of the plurality of fourth semiconductor elements 36, and are also conductively bonded to the second signal wiring 22. As a result, the fourth gate electrodes 363 of the plurality of fourth semiconductor elements 36 are electrically connected to the second signal terminal 46. Among the plurality of fourth wires 54, some of the fourth wires 54 are individually conductively bonded to the eighth electrodes 362 of the plurality of fourth semiconductor elements 36, and are also conductively bonded to the fourth signal wiring 24. As a result, the eighth electrodes 362 of the plurality of fourth semiconductor elements 36 are electrically connected to the fourth signal terminal 48.

[0119] As shown in FIGS. 24 and 26 , the multiple fourth protection elements 38 are conductively bonded to the second mounting surface 141 of the second conductive layer 14. The multiple fourth protection elements 38 are individually connected in parallel to the multiple fourth semiconductor elements 36. Each of the multiple fourth protection elements 38 is a freewheeling diode associated with one of the multiple fourth semiconductor elements 36. Each of the multiple fourth protection elements 38 is, for example, either a fast recovery diode or a Schottky barrier diode. As shown in FIG. 24 , the multiple fourth protection elements 38 are located between the second power terminal 42 and the multiple first semiconductor elements 31 in the first direction x and are arranged in the first direction x.

[0120] As shown in FIG. 26 , each of the multiple fourth protection elements 38 has a fourth anode electrode 381 and a fourth cathode electrode 382. The fourth anode electrode 381 is located on the side of the second conductive layer 14 opposite to the side facing the second mounting surface 141 in the second direction z. The fourth anode electrode 381 corresponds to the positive electrode of the fourth protection element 38. The fourth anode electrode 381 is conductively bonded to the second conductive member 56 via the bonding layer 39. As a result, the fourth anode electrode 381 of each of the multiple fourth protection elements 38 is individually conductively connected to the eighth electrode 362 of each of the multiple fourth semiconductor elements 36. The fourth cathode electrode 382 is located on the side opposite to the fourth anode electrode 381 in the second direction z. The fourth cathode electrode 382 corresponds to the negative electrode of the fourth protection element 38. The fourth cathode electrode 382 is conductively bonded to the second mounting surface 141 via the bonding layer 39. As a result, the fourth cathode electrode 382 of each of the plurality of fourth protection elements 38 is individually connected to the seventh electrode 361 of each of the plurality of fourth semiconductor elements 36 via the second conductive layer 14.

[0121] Next, a semiconductor device A51 according to a first modified example of the fifth embodiment of the present disclosure will be described with reference to Fig. 27. Fig. 27 corresponds to Fig. 24 showing the semiconductor device A50.

[0122] 27, the semiconductor device A51 does not include a plurality of first protection elements 33 and a plurality of second protection elements 34. Therefore, in the semiconductor device A51, the function of the free wheel diode corresponding to each of the plurality of first semiconductor elements 31 is performed by a diode configured inside each of the plurality of first semiconductor elements 31. In addition, the function of the free wheel diode corresponding to each of the plurality of second semiconductor elements 32 is performed by a diode configured inside each of the plurality of second semiconductor elements 32.

[0123] Next, a semiconductor device A52 according to a second modified example of the fifth embodiment of the present disclosure will be described with reference to Fig. 28. Fig. 28 corresponds to Fig. 24 showing the semiconductor device A50.

[0124] 28, the semiconductor device A52 includes one first protection element 33 instead of the multiple first protection elements 33. The one first protection element 33 is electrically connected to the first semiconductor element 31, of the multiple first semiconductor elements 31, that is located closest to the first power terminal 41. Furthermore, the semiconductor device A52 includes one second protection element 34 instead of the multiple second protection elements 34. The one second protection element 34 is electrically connected to the second semiconductor element 32, of the multiple second semiconductor elements 32, that is located closest to the multiple first semiconductor elements 31.

[0125] Next, a semiconductor device A53 according to a third modified example of the fifth embodiment of the present disclosure will be described with reference to Fig. 29. Fig. 29 corresponds to Fig. 24 showing the semiconductor device A50.

[0126] 29, in the semiconductor device A53, the second semiconductor elements 32 face the third semiconductor elements 35 in the first direction x. In addition, the fourth semiconductor elements 36 face the first semiconductor elements 31 in the first direction x.

[0127] Next, the effects of the semiconductor device A50 will be described.

[0128] The semiconductor device A50 includes a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, a first power terminal 41, a second power terminal 42, and a third power terminal 43. The first power terminal 41 and the second power terminal 42 are spaced apart from each other in the first direction x. The plurality of first semiconductor elements 31 are positioned between the first power terminal 41 and the second power terminal 42 in the first direction x and are arranged in the first direction x. The plurality of second semiconductor elements 32 are positioned between the second power terminal 42 and the plurality of first semiconductor elements 31 in the first direction x and are arranged in the first direction x. The voltage applied to the first power terminal 41 is higher than the voltage applied to the third power terminal 43. Therefore, this configuration allows the semiconductor device A50 to have greater flexibility in the arrangement of its own components. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A50 achieves the same effects as the semiconductor device A10.

[0129] The semiconductor device A50 further includes a plurality of third semiconductor elements 35 and a plurality of fourth semiconductor elements 36. The plurality of third semiconductor elements 35 are electrically connected to the plurality of first semiconductor elements 31. The structure of each of the plurality of third semiconductor elements 35 is different from the structure of each of the plurality of first semiconductor elements 31. The plurality of fourth semiconductor elements 36 are electrically connected to the plurality of second semiconductor elements 32. The structure of each of the plurality of fourth semiconductor elements 36 is different from the structure of each of the plurality of second semiconductor elements 32. With this configuration, the plurality of first semiconductor elements 31 and the plurality of third semiconductor elements 35 are complementary to each other, and the plurality of second semiconductor elements 32 and the plurality of fourth semiconductor elements 36 are also complementary to each other, thereby effectively improving the power conversion efficiency of the semiconductor device A50.

[0130] Sixth Embodiment A semiconductor device A60 according to a sixth embodiment of the present disclosure will be described with reference to FIG. 30. In these figures, elements that are the same as or similar to those of the semiconductor device A10 and the semiconductor device A50 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, FIG. 30 shows a perspective view of the sealing resin 60. In FIG. 30, the outline of the sealing resin 60 is shown by imaginary lines.

[0131] The semiconductor device A60 differs from the semiconductor device A10 in that it further includes two third semiconductor elements 35, two fourth semiconductor elements 36, two third protective elements 37, and two fourth protective elements 38.

[0132] As shown in FIG. 30 , the two third semiconductor elements 35 are located on opposite sides of each other in the third direction y with the first substrate 27 as the reference. The two third semiconductor elements 35 are located between the multiple first semiconductor elements 31 and the multiple second semiconductor elements 32 in the first direction x. The two fourth semiconductor elements 36 are located on opposite sides of each other with the second substrate 28 as the reference. The two fourth semiconductor elements 36 are located between the second power terminal 42 and the multiple second semiconductor elements 32 in the first direction x. The two third protection elements 37 are individually conductive to the two third semiconductor elements 35. The two fourth protection elements 38 are individually conductive to the two fourth semiconductor elements 36.

[0133] Next, a semiconductor device A61 according to a first modified example of the sixth embodiment of the present disclosure will be described with reference to Fig. 31. Fig. 31 corresponds to Fig. 30 showing the semiconductor device A60.

[0134] 31 , in the semiconductor device A61, the two third semiconductor elements 35 are located between the multiple first semiconductor elements 31 and the multiple second semiconductor elements 32 in the first direction x. The two fourth semiconductor elements 36 are located between the two third semiconductor elements 35 and the multiple second semiconductor elements 32 in the first direction x.

[0135] Next, a semiconductor device A62 according to a second modified example of the sixth embodiment of the present disclosure will be described with reference to Fig. 32. Fig. 32 corresponds to Fig. 30 showing the semiconductor device A60.

[0136] 32, in the semiconductor device A62, the two third semiconductor elements 35 are located between the first power terminal 41 and the multiple first semiconductor elements 31 in the first direction x. The two fourth semiconductor elements 36 are located between the multiple first semiconductor elements 31 and the multiple second semiconductor elements 32 in the first direction x.

[0137] 32, the semiconductor device A62 includes two first protection elements 33 instead of the multiple first protection elements 33. The two first protection elements 33 are individually conductive to two first semiconductor elements 31 that are located closest to two third semiconductor elements 35 among the multiple first semiconductor elements 31. Furthermore, the semiconductor device A62 includes two second protection elements 34 instead of the multiple second protection elements 34. The two second protection elements 34 are individually conductive to two second semiconductor elements 32 that are located closest to two fourth semiconductor elements 36 among the multiple second semiconductor elements 32.

[0138] Next, a semiconductor device A63 according to a third modified example of the sixth embodiment of the present disclosure will be described with reference to Fig. 33. Fig. 33 corresponds to Fig. 30 showing the semiconductor device A60. In the semiconductor device A63, the configurations of the two fourth semiconductor elements 36 and the two second protection elements 34 differ from those of the semiconductor device A62 described above.

[0139] 33 , the two fourth semiconductor elements 36 are located between the second power terminal 42 and the plurality of second semiconductor elements 32 in the first direction x. The two second protection elements 34 are individually connected to two of the plurality of second semiconductor elements 32 that are located closest to the plurality of first semiconductor elements 31.

[0140] Next, the effects of the semiconductor device A60 will be described.

[0141] The semiconductor device A60 includes a plurality of first semiconductor elements 31, a plurality of second semiconductor elements 32, a first power terminal 41, a second power terminal 42, and a third power terminal 43. The first power terminal 41 and the second power terminal 42 are spaced apart from each other in the first direction x. The plurality of first semiconductor elements 31 are located between the first power terminal 41 and the second power terminal 42 in the first direction x and are arranged in the first direction x. The plurality of second semiconductor elements 32 are located between the second power terminal 42 and the plurality of first semiconductor elements 31 in the first direction x and are arranged in the first direction x. The voltage applied to the first power terminal 41 is higher than the voltage applied to the third power terminal 43. Therefore, this configuration allows the semiconductor device A60 to have greater flexibility in the arrangement of its own components. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A60 achieves the same effects as the semiconductor device A10.

[0142] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0143] The present disclosure includes the embodiments described in the appendix below. [Appendix 1] a plurality of first semiconductor elements (31) each having a first electrode (311) and a second electrode (312); a plurality of second semiconductor elements (32) each having a third electrode (321) and a fourth electrode (322); a first power terminal (41) electrically connected to the first electrode; a second power terminal (42) electrically connected to the second electrode and the third electrode; a third power terminal (43) electrically connected to the fourth electrode, the polarity of the third electrode is different from the polarity of the second electrode; the first power terminal and the second power terminal are spaced apart from each other in a first direction (x); the plurality of first semiconductor elements are positioned between the first power terminal and the second power terminal in the first direction and are arranged in the first direction; the plurality of second semiconductor elements are positioned between the second power terminal and the plurality of first semiconductor elements in the first direction and are arranged in the first direction; A semiconductor device (A10) in which the voltage applied to the first power terminal is higher than the voltage applied to the third power terminal. [Appendix 2] The power supply further includes a first conductive layer (13) that is electrically connected to the first power terminal (41), In each of the plurality of first semiconductor elements (31), the first electrode (311) and the second electrode (312) are located on opposite sides to each other in a second direction (z) perpendicular to the first direction (x), The semiconductor device (A10) according to Appendix 1, wherein the first electrode is conductively joined to the first conductive layer. [Appendix 3] The power supply further includes a second conductive layer (14) that is electrically connected to the second power terminal (42), In each of the plurality of second semiconductor elements (32), the third electrode (321) and the fourth electrode (322) are located on opposite sides to each other in the second direction (z), The semiconductor device (A10) according to Appendix 2, wherein the third electrode is conductively joined to the second conductive layer. [Appendix 4] The semiconductor device (A10) according to appendix 3, further comprising a first conductive member (55) conductively joined to the second electrode (312) and the second conductive layer (14). [Appendix 5] The semiconductor device (A10) according to appendix 4, further comprising a second conductive member (56) conductively joined to the fourth electrode (322) and electrically connected to the third power terminal (43). [Appendix 6] The semiconductor device (A10) according to Appendix 5, wherein the second conductive member (56) overlaps the first conductive member (55) when viewed in the second direction (z). [Appendix 7] Further provided with an insulating layer (11), The semiconductor device (A10) according to Appendix 5, wherein the first conductive layer (13) and the second conductive layer (14) are joined to one side of the insulating layer in the second direction (z). [Appendix 8] A semiconductor device (A10) described in Appendix 7, wherein the third power terminal (43) is located adjacent to the first power terminal (41) in a third direction (y) perpendicular to each of the first direction (x) and the second direction (z). [Appendix 9] a third conductive layer (15) located on the same side as the first conductive layer (13) and the second conductive layer (14) with respect to the insulating layer (11) in the second direction (z), the third conductive layer is bonded to the insulating layer; the third power terminal (43) is conductively joined to the third conductive layer; The semiconductor device (A10) according to appendix 8, wherein the second conductive member (56) is electrically connected to the third conductive layer. [Appendix 10] the second conductive member (56) is conductively connected to the third power terminal (43); The semiconductor device (A10) according to appendix 9, wherein, when viewed in the second direction (z), the second conductive member overlaps each of the third conductive layer (15) and the third power terminal. [Appendix 11] a fourth power terminal (44) electrically connected to the fourth electrode (322); The semiconductor device (A10) according to Appendix 9, wherein the fourth power terminal is located on the opposite side of the third power terminal (43) relative to the first power terminal (41) in the third direction (y). [Appendix 12] a first signal terminal (45) located between the first power terminal (41) and the second power terminal (42) in the first direction (x); Each of the plurality of first semiconductor elements (31) has a first gate electrode (313) located on the same side as the second electrode (312) in the first direction, The semiconductor device (A10) according to any one of appendices 8 to 11, wherein the first signal terminal is electrically connected to the first gate electrode. [Appendix 13] a second signal terminal (46) located between the second power terminal (42) and the first signal terminal (45) in the first direction (x), Each of the plurality of second semiconductor elements (32) has a second gate electrode (323) located on the same side as the fourth electrode (322) in the first direction, The semiconductor device (A10) according to Appendix 12, wherein the second signal terminal is electrically connected to the second gate electrode. [Appendix 14] the plurality of first semiconductor elements (31) include first elements (31A) and second elements (31B) spaced apart from each other in the third direction (y); The semiconductor device (A10) according to appendix 13, wherein the first signal terminal (45) is located between the first element and the second element in the third direction. [Appendix 15] the plurality of second semiconductor elements (32) include a third element (32A) and a fourth element (32B) spaced apart from each other in the third direction (y); The semiconductor device (A10) according to appendix 14, wherein the second signal terminal (46) is located between the third element and the fourth element in the third direction. [Appendix 16] A semiconductor device (A10) described in Appendix 15, wherein, when viewed in the first direction (z), the first conductive member (55) and the second conductive member (56) surround the first signal terminal (45) and the second signal terminal (46). [Appendix 17] Further provided with a first signal wiring (21) and a second signal wiring (22), the first signal terminal (45) is electrically connected to the first gate electrode (313) via the first signal wiring (21); the second signal terminal (46) is electrically connected to the second gate electrode (323) via the second signal wiring (22); the first signal wiring is located between the first element (31A) and the second element (31B) in the third direction (y), The semiconductor device (A10) according to appendix 15, wherein the second signal wiring is located between the third element (32A) and the fourth element (32B) in the third direction. [Appendix 18] The semiconductor device further includes a sealing resin (60) that covers the plurality of first semiconductor elements (31) and the plurality of second semiconductor elements (32), the sealing resin has a top surface (61) facing a side where the first conductive layer (13) and the second conductive layer (14) are located with respect to the insulating layer (11) in the second direction (z); The semiconductor device (A10) according to Appendix 17, wherein a portion of each of the first signal terminal (45) and the second signal terminal (46) protrudes from the top surface. [Appendix 19] a plurality of third semiconductor elements (35) each having a fifth electrode (351) and a sixth electrode (352); a plurality of fourth semiconductor elements (36), each having a seventh electrode (361) and an eighth electrode (362); the polarity of the seventh electrode is different from the polarity of the sixth electrode; the fifth electrode is conductively joined to the first conductive layer (13); the sixth electrode is conductively joined to the first conductive member (55); the seventh electrode is conductively joined to the second conductive layer (14); the eighth electrode is conductively joined to the second conductive member (56); The structure of each of the plurality of third semiconductor elements is different from the structure of each of the plurality of first semiconductor elements (31); The semiconductor device (A50, A60) according to Appendix 5, wherein the structure of each of the plurality of fourth semiconductor elements is different from the structure of each of the plurality of second semiconductor elements (32). [Appendix 20] A driving source (932), The semiconductor device (A10) according to Supplementary Note 13, The semiconductor device is electrically connected to the drive source. [Appendix 21] The semiconductor device (A30) according to appendix 5, wherein the second conductive member (56) is spaced apart from the first conductive member (55) when viewed in the second direction (z). [Appendix 22] The semiconductor device further includes a plurality of first protection elements (33) that are individually connected to the plurality of first semiconductor elements (31), A semiconductor device (A10) described in Appendix 7, wherein the plurality of first protection elements are located on one side of the plurality of first semiconductor elements in the third direction (y) and are arranged in the first direction (x). [Appendix 23] The semiconductor device further includes a plurality of second protection elements (34) that are individually connected to the plurality of second semiconductor elements (32), A semiconductor device (A10) described in Appendix 22, wherein the plurality of second protection elements are located on one side of the plurality of second semiconductor elements in the third direction (y) and are arranged in the first direction (x). [Appendix 24] The semiconductor device (A10) according to appendix 11, wherein the fourth power terminal (44) is electrically connected to the fourth electrode (322) via the second conductive member (56). [Appendix 25] Further provided is a first substrate (27) including an insulator; The semiconductor device (A10) according to Appendix 17, wherein the first signal wiring (21) is mounted on the first substrate. [Appendix 26] The semiconductor device (A10) according to Appendix 25, wherein the first substrate (27) is bonded to the insulating layer (11). [Appendix 27] The semiconductor device (A20) according to Appendix 25, wherein the first substrate (27) is bonded to the first conductive layer (13). [Appendix 28] The semiconductor device further includes a heat dissipation layer (12) located on the opposite side of the insulating layer (11) from the first conductive layer (13) and the second conductive layer (14), the heat dissipation layer is bonded to the insulating layer, The sealing resin (60) has a bottom surface (62) facing the opposite side to the top surface (61) in the second direction (z), The semiconductor device (A10) according to Appendix 19, wherein the heat dissipation layer is exposed from the bottom surface. [Appendix 29] The semiconductor device further includes a first dummy terminal (58) spaced apart from each of the first conductive layer (13) and the second conductive layer (14), A portion of the first dummy terminal is covered with the sealing resin (60), The sealing resin is provided with a first opening (65) that penetrates from the top surface (61) to the bottom surface (62), The semiconductor device (A40) according to Appendix 28, wherein the first dummy terminal has a first engagement portion (581) exposed from the first opening. [Appendix 30] Further provided is a second dummy terminal (59) spaced apart from each of the first conductive layer (13) and the second conductive layer (14), A portion of the second dummy terminal is covered with the sealing resin (60), When viewed in the second direction (z), the second dummy terminal is spaced apart from the first dummy terminal (58), The sealing resin is provided with a second opening (66) that penetrates from the top surface (61) to the bottom surface (62), The second dummy terminal has a second engagement portion (591) exposed from the second opening, The semiconductor device (A40) according to Appendix 29, wherein the second engagement portion has a size different from the size of the first engagement portion (581) when viewed in the first direction. [Appendix 31] The semiconductor device described in Appendix 30, wherein, when viewed in the second direction (z), the first dummy terminal (58) and the second dummy terminal (59) are located on opposite sides of the second power terminal (42). [Explanation of symbols]

[0144] A10 to A40, A50 to A53, A60 to A63: Semiconductor device B: Semiconductor module C: Vehicle 11: Insulating layer 111: Periphery 12: Heat dissipation layer 13: First conductive layer 131: First mounting surface 13A, 13B: 1st area, 2nd area 14: Second conductive layer 141: Second mounting surface 15, 16: Third conductive layer, fourth conductive layer 21 to 24: 1st signal wiring to 4th signal wiring 26: Bonding layer 27: First board 271: First insulating layer 272: 1st metal layer 28: Second board 281: Second insulating layer 282: 2nd metal layer 29: Sleeve 31: First semiconductor element 311,312: 1st electrode, 2nd electrode 313: First gate electrode 31A, 31B: First element, second element 32: Second semiconductor element 321,322: 3rd electrode, 4th electrode 323: Second gate electrode 32A, 32B: third element, fourth element 33: First protection element 331: First anode electrode 332: First cathode electrode 34: Second protection element 341: Second anode electrode 342: second cathode electrode 35: Third semiconductor element 351,352: 5th electrode, 6th electrode 353: Third gate electrode 36: Fourth semiconductor element 361,362: 7th electrode, 8th electrode 363: Fourth gate electrode 37: Third protection element 371: Third anode electrode 372: Third cathode electrode 38: Fourth protection element 381: Fourth anode electrode 382: Fourth cathode electrode 39: Bonding layer 41~44: 1st power terminal ~ 4th power terminal 45~48: 1st signal terminal ~ 4th signal terminal 51-54: 1st wire to 4th wire 55, 56: First conductive member, second conductive member 58: First dummy terminal 581: First engagement part 59: Second dummy terminal 591: Second engagement part 60: Sealing resin 61:Top surface 62: Bottom 63,64: 1st side, 2nd side 65,66: 1st opening, 2nd opening 651,661: Periphery 71: Heat dissipation material 71A: Mounting surface 711, 712: First convex part, second convex part 72: Bonding layer 91: Vehicle charger 92: Storage battery 93: Drive system 931: Inverter 932: Power source x, z, y: 1st direction, 2nd direction, 3rd direction

Claims

1. a plurality of first semiconductor elements each having a first electrode and a second electrode; a plurality of second semiconductor elements each having a third electrode and a fourth electrode; a first power terminal connected to the first electrode; a second power terminal electrically connected to the second electrode and the third electrode; a third power terminal in electrical communication with the fourth electrode; the polarity of the third electrode is different from the polarity of the second electrode; the first power terminal and the second power terminal are spaced apart from each other in a first direction; the plurality of first semiconductor elements are positioned between the first power terminal and the second power terminal in the first direction and are arranged in the first direction; the plurality of second semiconductor elements are positioned between the second power terminal and the plurality of first semiconductor elements in the first direction and are arranged in the first direction; The semiconductor device, wherein the voltage applied to the first power terminal is higher than the voltage applied to the third power terminal.

2. a first conductive layer electrically connected to the first power terminal; In each of the plurality of first semiconductor elements, the first electrode and the second electrode are located on opposite sides to each other in a second direction perpendicular to the first direction, The semiconductor device according to claim 1 , wherein the first electrode is conductively connected to the first conductive layer.

3. a second conductive layer electrically connected to the second power terminal; In each of the plurality of second semiconductor elements, the third electrode and the fourth electrode are located on opposite sides to each other in the second direction, The semiconductor device according to claim 2 , wherein the third electrode is conductively connected to the second conductive layer.

4. The semiconductor device according to claim 3 , further comprising a first conductive member conductively joined to said second electrode and said second conductive layer.

5. The semiconductor device according to claim 4 , further comprising a second conductive member conductively joined to said fourth electrode and electrically connected to said third power terminal.

6. The semiconductor device according to claim 5 , wherein the second conductive member overlaps the first conductive member when viewed in the second direction.

7. Further comprising an insulating layer; The semiconductor device according to claim 5 , wherein the first conductive layer and the second conductive layer are joined to one side of the insulating layer in the second direction.

8. The semiconductor device according to claim 7 , wherein the third power terminal is located adjacent to the first power terminal in a third direction perpendicular to each of the first direction and the second direction.

9. a third conductive layer located on the same side of the insulating layer as the first conductive layer and the second conductive layer in the second direction; the third conductive layer is bonded to the insulating layer; the third power terminal is conductively bonded to the third conductive layer; The semiconductor device according to claim 8 , wherein the second conductive member is electrically connected to the third conductive layer.

10. the second conductive member is conductively connected to the third power terminal; The semiconductor device according to claim 9 , wherein the second conductive member overlaps with the third conductive layer and the third power terminal when viewed in the second direction.

11. a fourth power terminal connected to the fourth electrode; 10. The semiconductor device according to claim 9, wherein the fourth power terminal is located on an opposite side to the third power terminal with respect to the first power terminal in the third direction.

12. a first signal terminal located between the first power terminal and the second power terminal in the first direction; each of the plurality of first semiconductor elements has a first gate electrode located on the same side as the second electrode in the first direction; 12. The semiconductor device according to claim 8, wherein said first signal terminal is electrically connected to said first gate electrode.

13. a second signal terminal located between the second power terminal and the first signal terminal in the first direction; each of the plurality of second semiconductor elements has a second gate electrode located on the same side as the fourth electrode in the first direction; 13. The semiconductor device according to claim 12, wherein said second signal terminal is electrically connected to said second gate electrode.

14. the plurality of first semiconductor elements include first elements and second elements spaced apart from each other in the third direction; The semiconductor device according to claim 13 , wherein the first signal terminal is located between the first element and the second element in the third direction.

15. the plurality of second semiconductor elements include third elements and fourth elements spaced apart from each other in the third direction; The semiconductor device according to claim 14 , wherein the second signal terminal is located between the third element and the fourth element in the third direction.

16. 16 . The semiconductor device according to claim 15 , wherein the first conductive member and the second conductive member surround the first signal terminal and the second signal terminal when viewed in the first direction.

17. Further comprising a first signal wiring and a second signal wiring, the first signal terminal is electrically connected to the first gate electrode via the first signal wiring; the second signal terminal is electrically connected to the second gate electrode via the second signal wiring, the first signal wiring is located between the first element and the second element in the third direction, 16. The semiconductor device according to claim 15, wherein said second signal wiring is located between said third element and said fourth element in said third direction.

18. further comprising a sealing resin that covers the plurality of first semiconductor elements and the plurality of second semiconductor elements; the sealing resin has a top surface facing a side where the first conductive layer and the second conductive layer are located with respect to the insulating layer in the second direction; 18. The semiconductor device according to claim 17, wherein a portion of each of the first signal terminal and the second signal terminal protrudes from the top surface.

19. a plurality of third semiconductor elements each having a fifth electrode and a sixth electrode; a plurality of fourth semiconductor elements each having a seventh electrode and an eighth electrode; the polarity of the seventh electrode is different from the polarity of the sixth electrode; the fifth electrode is conductively connected to the first conductive layer; the sixth electrode is conductively joined to the first conductive member, the seventh electrode is conductively connected to the second conductive layer; the eighth electrode is conductively joined to the second conductive member, a structure of each of the plurality of third semiconductor elements is different from a structure of each of the plurality of first semiconductor elements; 6. The semiconductor device according to claim 5, wherein a structure of each of said plurality of fourth semiconductor elements is different from a structure of each of said plurality of second semiconductor elements.

20. A driving source; The semiconductor device according to claim 13, The semiconductor device is electrically connected to the drive source.

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