Display device and manufacturing method of them

Abstract

To improve a yield a display device.SOLUTION: According to an embodiment, a display device includes: an organic insulating layer formed of an organic insulating material; a lower electrode disposed above the organic insulating layer; a covering resin layer covering at least a part of an end portion of the lower electrode; a rib layer covering the end portion of the lower electrode and the covering resin layer and having a pixel opening overlapping with the lower electrode; an organic layer covering the lower electrode through the pixel opening and emitting light in response to application of a voltage; and an upper electrode covering the organic layer.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have come into practical use. Technology that enables improvement of yields in this type of display device is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a manufacturing method thereof that can improve yield. [Means for solving the problem]

[0005] Generally, according to an embodiment, the display device comprises an organic insulating layer formed of an organic insulating material, a lower electrode arranged above the organic insulating layer, a coating resin layer covering at least a portion of an end of the lower electrode, a rib layer covering the end of the lower electrode and the coating resin layer and having a pixel opening overlapping the lower electrode, an organic layer covering the lower electrode through the pixel opening and emitting light in response to application of a voltage, and an upper electrode covering the organic layer.

[0006] Furthermore, according to an embodiment, a method for manufacturing a display device includes forming an organic insulating layer made of an organic insulating material, forming a lower electrode and a coating resin layer above the organic insulating layer, the lower electrode and the coating resin layer covering at least a portion of an end of the lower electrode, forming a rib layer that covers the end of the lower electrode and the coating resin layer and has pixel openings that overlap with the lower electrode, forming an organic layer that covers the lower electrode through the pixel openings and emits light in response to application of a voltage, and forming an upper electrode that covers the organic layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels according to the first embodiment. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the display device taken along line IV-IV in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view showing another configuration applicable to the lower electrode and the coating resin layer. [Figure 6] FIG. 6 is a flowchart showing an example of a method for manufacturing the display device according to the first embodiment. [Figure 7A] FIG. 7A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 7B] FIG. 7B is a schematic cross-sectional view showing a step subsequent to FIG. 7A. [Figure 7C]FIG. 7C is a schematic cross-sectional view showing a step subsequent to FIG. 7B. [Figure 7D] FIG. 7D is a schematic cross-sectional view showing a step subsequent to FIG. 7C. [Figure 7E] FIG. 7E is a schematic cross-sectional view showing a step subsequent to FIG. 7D. [Figure 7F] FIG. 7F is a schematic cross-sectional view showing a step subsequent to FIG. 7E. [Figure 7G] FIG. 7G is a schematic cross-sectional view showing a step subsequent to FIG. 7F. [Figure 7H] FIG. 7H is a schematic cross-sectional view showing a step subsequent to FIG. 7G. [Figure 7I] FIG. 7I is a schematic cross-sectional view showing a step subsequent to FIG. 7H. [Figure 7J] FIG. 7J is a schematic cross-sectional view showing a step subsequent to FIG. 7I. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing a step subsequent to FIG. 7J. [Figure 8B] FIG. 8B is a schematic cross-sectional view showing a step subsequent to FIG. 8A. [Figure 8C] FIG. 8C is a schematic cross-sectional view showing a step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a schematic cross-sectional view showing a step subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a schematic cross-sectional view showing a step subsequent to FIG. 8D. [Figure 8F] FIG. 8F is a schematic cross-sectional view showing a step subsequent to FIG. 8E. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a structure near the end of the lower electrode according to a comparative example of this embodiment. [Figure 10] FIG. 10 is a schematic plan view showing an example of a layout of sub-pixels according to the second embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view of the display device taken along line XI-XI in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] [First embodiment] 1 is a diagram showing an example of the configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circular, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1 (first subpixel), a green subpixel SP2 (second subpixel), and a red subpixel SP3 (third subpixel). However, the pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] In the display area DA, there are arranged a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL. In the example of Fig. 1, the scanning lines GL and the power supply lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. The source electrode of the pixel switch 2 is connected to the signal line SL. The drain electrode of the pixel switch 2 is connected to the gate electrode of the drive transistor 3 and the capacitor 4. The source electrode of the drive transistor 3 is connected to the power line PL and the capacitor 4. The drain electrode of the drive transistor 3 is connected to the display element DE.

[0017] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example of Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the X direction. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the Y direction.

[0019] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0020] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio and the subpixel SP3 has the smallest aperture ratio. Note that the sizes of the pixel openings AP1, AP2, and AP3 are not limited to this example. For example, at least two of the pixel openings AP1, AP2, and AP3 may have the same size.

[0021] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0022] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0023] Partition walls 6 are arranged in the display area DA. The partition walls 6 are located above the rib layer 5 and entirely overlap the rib layer 5. In the example of FIG. 2, the partition walls 6 have the same planar shape as the rib layer 5. That is, the partition walls 6 have openings in the subpixels SP1, SP2, and SP3. From another perspective, the rib layer 5 and the partition walls 6 have a lattice shape in a planar view and surround the display elements DE1, DE2, and DE3, respectively. The partition walls 6 serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0024] The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 (more specifically, the drain electrodes of the driving transistors 3 shown in FIG. 1 ) of the subpixels SP1, SP2, and SP3, respectively, through contact holes CH1, CH2, and CH3 provided in the organic insulating layer 12, which will be described later. The contact holes CH1, CH2, and CH3 all overlap the rib layer 5 and the partition wall 6.

[0025] In the example of FIG. 2, the partition wall 6 has a protrusion PT1 that protrudes toward the pixel aperture AP1. The contact hole CH1 overlaps with the protrusion PT1. The lower electrode LE2 has a protrusion PT2 that protrudes toward the lower electrode LE3. The lower electrode LE3 has a protrusion PT3 that protrudes toward the lower electrode LE2. The contact holes CH2 and CH3 overlap with these protrusions PT2 and PT3, respectively.

[0026] The subpixels SP1, SP2, and SP3 are provided with coating resin layers CR1, CR2, and CR3, respectively. In Fig. 2, the coating resin layers CR1, CR2, and CR3 are indicated by hatched patterns.

[0027] The coating resin layer CR1 is disposed along the edge E1 of the lower electrode LE1 and surrounds the lower electrode LE1. The coating resin layer CR2 is disposed along the edge E2 of the lower electrode LE2 and surrounds the lower electrode LE2. The coating resin layer CR3 is disposed along the edge E3 of the lower electrode LE3 and surrounds the lower electrode LE3.

[0028] For example, the ends E1, E2, E3 of the lower electrodes LE1, LE2, LE3 and the coating resin layers CR1, CR2, CR3 entirely overlap with the rib layer 5 and the partition walls 6. However, the ends E1, E2, E3 and the coating resin layers CR1, CR2, CR3 do not necessarily have to partially overlap with the partition walls 6.

[0029] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0030] The lower electrodes LE1, LE2, LE3 and the coating resin layers CR1, CR2, CR3 are each disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, LE3. The ends of the lower electrodes LE1, LE2, LE3 (ends E1, E2, E3 shown in FIG. 2) and the coating resin layers CR1, CR2, CR3 are all covered with the rib layer 5.

[0031] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. In other words, the partition wall 6 has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0032] In the example of Figure 3, the lower portion 61 has a bottom layer 63 and an axial layer 64. The bottom layer 63 is located between the axial layer 64 and the rib layer 5. Furthermore, in the example of Figure 3, the upper portion 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed on the axial layer 64. The second top layer 66 is disposed on the first top layer 65.

[0033] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0034] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0035] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0036] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively, to cover the stacked films FL1, FL2, and FL3. Specifically, the sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0037] 3, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6. In addition, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6.

[0038] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0039] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0040] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0041] The electrodes constituting the touch panel may be disposed on the sealing layer SE2. Also, color filters corresponding to the colors of the subpixels SP1, SP2, SP3 may be disposed above the display elements DE1, DE2, DE3, respectively.

[0042] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0043] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0044] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0045] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0046] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0047] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0048] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0049] The bottom layer 63 and the shaft layer 64 are formed of, for example, a metal material. Examples of the metal material for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), and molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), and aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a multi-layer structure. The shaft layer 64 may also include a layer formed of an insulating material. Furthermore, the lower portion 61 may have a single-layer structure formed of a conductive material.

[0050] For example, the first top layer 65 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. Examples of the metal material for the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide for the second top layer 66 include indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO). The upper portion 62 may have a single-layer structure made of a specific material. Furthermore, the upper portion 62 may include a layer made of an insulating material.

[0051] Figure 4 is a schematic cross-sectional view of the display device DSP taken along line IV-IV in Figure 2. This figure shows the organic insulating layer 12, the rib layer 5, the partition wall 6, the lower electrodes LE1, LE2, and the coating resin layers CR1, CR2, and omits other elements.

[0052] In the example of Fig. 4, the bottom layer 63 protrudes from the side surface of the shaft layer 64. In addition, the width of the second top layer 66 is smaller than the width of the first top layer 65. As a result, the upper surface of the first top layer 65 near both ends is exposed from the second top layer 66. The shaft layer 64 is formed thicker than the bottom layer 63, the first top layer 65, and the second top layer 66.

[0053] As described above, the ends E1 and E2 of the lower electrodes LE1 and LE2 and the coating resin layers CR1 and CR2 are all covered by the rib layer 5. Although not shown in the cross section of FIG. 4, the end E3 of the lower electrode LE3 and the coating resin layer CR3 are also covered by the rib layer 5.

[0054] 4, the ends E1, E2 and the coating resin layers CR1, CR2 are located below the lower portion 61, more specifically, below the bottom layer 63 and the axial layer 64. Although not shown in the cross section of FIG. 4, the end E3 of the lower electrode LE3 and the coating resin layer CR3 are also located below the bottom layer 63 and the axial layer 64. However, each of the ends E1, E2, E3 and the coating resin layers CR1, CR2, CR3 may have a portion that is not located below the bottom layer 63 and the axial layer 64.

[0055] As shown in Fig. 4, a step ST is generated on the upper surface of the rib layer 5 due to the ends E1 and E2. Although not shown in the cross section of Fig. 4, a step ST is also generated on the upper surface of the rib layer 5 due to the end E3 of the lower electrode LE3. In this embodiment, these step ST are covered by the bottom layer 63 and the shaft layer 64. The upper surfaces of the shaft layer 64, the first top layer 65, and the second top layer 66 may be deformed in accordance with the step ST.

[0056] As shown enlarged in FIG. 4, the lower electrode LE1 includes a reflective layer RL, a first covering layer V1, and a second covering layer V2. The reflective layer RL reflects light emitted by the organic layer OR1 in the Z direction. The first covering layer V1 is located between the organic insulating layer 12 and the reflective layer RL and covers the lower surface of the reflective layer RL. The second covering layer V2 covers the upper surface of the reflective layer RL. The first covering layer V1 improves adhesion between the reflective layer RL and the organic insulating layer 12. The second covering layer V2 protects the reflective layer RL from various etching processes that occur during the manufacture of the display device DSP.

[0057] The reflective layer RL can be made of a metal material with excellent light reflectivity, such as silver. Each of the cover layers V1 and V2 can be made of a transparent conductive oxide, such as ITO, IZO, or IGZO.

[0058] In the example of Fig. 4, both the first coating layer V1 and the second coating layer V2 are thinner than the reflective layer RL. Furthermore, the first coating layer V1 is thinner than the second coating layer V2. As an example, the thickness of the reflective layer RL is 40 to 150 nm, and the thicknesses of the first coating layer V1 and the second coating layer V2 are 5 to 50 nm. Furthermore, the thickness of the rib layer 5 is 200 to 600 nm. However, the thicknesses of the reflective layer RL, the first coating layer V1, the second coating layer V2, and the rib layer 5 are not limited to those exemplified here.

[0059] The end E1 of the lower electrode LE1 includes the end Er of the reflective layer RL, the end Ev1 of the first coating layer V1, and the end Ev2 of the second coating layer V2. In the example of Fig. 4, the end Er protrudes more than the ends Ev1 and Ev2.

[0060] The coating resin layers CR1, CR2, and CR3 are made of a resin material, which may be, but is not limited to, a positive photosensitive resin such as photosensitive polyimide or photosensitive acrylic.

[0061] 4, the coating resin layer CR1 covers the entire ends Er, Ev1, and Ev2. The coating resin layer CR1 fills the gap between the organic insulating layer 12 and the end Er. The coating resin layer CR1 also covers the upper surface of the reflective layer RL exposed from the second coating layer V2.

[0062] The coating resin layer CR1 does not cover the upper surface UF of the second coating layer V2. In the example of Fig. 4, the surface SF of the coating resin layer CR1 is a gently curved surface that is flat and connected to the upper surface UF. As another example, a step may be formed between the surface SF and the upper surface UF.

[0063] The width W of the coating resin layer CR1 is, for example, equal to or greater than the thickness of the reflective layer RL. Here, the width W corresponds to the width of the portion of the coating resin layer CR1 that does not overlap with the reflective layer RL. For example, the width W is 0.2 μm or greater, and preferably 0.5 μm to 1.0 μm.

[0064] 5 is a schematic cross-sectional view showing another configuration applicable to the lower electrode LE1 and the coating resin layer CR1. In the example shown in this figure, a part of the end E1 of the lower electrode LE1 is covered with the coating resin layer CR1, and the remaining part of the end E1 is not covered with the coating resin layer CR1.

[0065] 5, the end Ev1 and the lower part of the end Er are covered with the coating resin layer CR1, while the upper part of the end Er and the end Ev2 are not covered with the coating resin layer CR1.

[0066] Like the lower electrode LE1, the lower electrodes LE2 and LE3 include a reflective layer RL, a first covering layer V1, and a second covering layer V2. The thicknesses of the reflective layer RL, the first covering layer V1, and the second covering layer V2 in the lower electrodes LE2 and LE3 are equivalent to the thicknesses of these layers in the lower electrode LE1. The width of the covering resin layers CR2 and CR3 is equivalent to the width W of the covering resin layer CR1. Furthermore, the structure near the end E2 of the lower electrode LE2 and the structure near the end E3 of the lower electrode LE3 are similar to the structure near the end E1 of the lower electrode LE1 shown in FIG. 4 or 5.

[0067] 4, the coating resin layers CR1 and CR2 are spaced apart from each other. In the region Ax between the coating resin layers CR1 and CR2, the organic insulating layer 12 is covered with the rib layer 5. Similar regions Ax are also formed between the coating resin layers CR1 and CR3 and between the coating resin layers CR2 and CR3.

[0068] Next, an example of a manufacturing method of the display device DSP will be described. Fig. 6 is a flowchart showing an example of a manufacturing method of the display device DSP. Figs. 7A to 7J and 8A to 8F are schematic cross-sectional views showing the manufacturing process of the display device DSP. In these figures, the substrate 10 and the circuit layer 11 are not shown.

[0069] In manufacturing the display device DSP, first, a circuit layer 11 is formed on a substrate 10 (step PR1 in FIG. 6). Further, an organic insulating layer 12 having contact holes CH1, CH2, and CH3 is formed on the circuit layer 11 (step PR2 in FIG. 6).

[0070] After step PR2, lower electrodes LE1, LE2, LE3 and coating resin layers CR1, CR2, CR3 are formed on the organic insulating layer 12 (step PR3 in FIG. 6). For example, if the coating resin layers CR1, CR3, CR3 are formed of a positive photosensitive resin, the procedure shown in FIGS. 7A to 7J can be applied to step PR3. Note that FIGS. 7A to 7J show the process of forming the lower electrode LE1 and the coating resin layer CR1. The lower electrodes LE2, LE3 and the coating resin layers CR2, CR3 are also formed simultaneously with the lower electrode LE1 and the coating resin layer CR1.

[0071] In step PR3, as shown in FIG. 7A, a first layer L1 made of the material of the lower electrodes LE1, LE2, and LE3 is first formed on the organic insulating layer 12 (step PR3a in FIG. 6). The first layer L1 includes a first covering layer V1a made of the material of the first covering layer V1, a reflective layer RLa made of the material of the reflective layer RL, and a second covering layer V2a made of the material of the second covering layer V2. These layers can be formed by, for example, sputtering.

[0072] Next, a second layer L2 is formed on the first layer L1 (step PR3b in FIG. 6). The second layer L2 may be made of various metal materials or insulating materials that are light-blocking against exposure in step PR3i, which will be described later. In this embodiment, the second layer L2 is made of titanium. In this case, sputtering may be used to form the second layer L2.

[0073] The second layer L2 is thinner than the reflective layer RLa, for example. In one example, the reflective layer RLa is 100 nm, the first cladding layer V1a and the second cladding layer V2a are 25 nm, and the second layer L2 is 30 nm.

[0074] After step PR3b, as shown in FIG. 7B, a resist R0 having a shape corresponding to the lower electrodes LE1, LE2, and LE3 is disposed on the second layer L2 (step PR3c in FIG. 6). Furthermore, a first etching is performed on the second layer L2 (step PR3d in FIG. 6). The first etching is, for example, dry etching. The first etching removes the portions of the second layer L2 that are not covered by the resist R0. As a result, a mask layer MK having a shape similar to that of the resist R0 is formed, as shown in FIG. 7C.

[0075] After step PR3c, a second etching is performed on the first layer L1 (step PR3e in FIG. 6). For example, the first etching includes wet etching that is performed sequentially on the second coating layer V2a, the reflective layer RLa, and the first coating layer V1a.

[0076] In the wet etching of the second coating layer V2a, the portion of the second coating layer V2a exposed from the resist R0 is removed. As a result, the second coating layer V2 is formed as shown in FIG. 7D. In this wet etching, the width of the second coating layer V2 is slightly reduced compared to the width of the mask layer MK.

[0077] In the wet etching of the reflective layer RLa, the portion of the reflective layer RLa exposed from the resist R0 is removed. As a result, the reflective layer RL is formed as shown in FIG. 7E. In addition, in the wet etching, the width of the reflective layer RL is slightly reduced compared to the mask layer MK and the second coating layer V2.

[0078] In the wet etching of the first coating layer V1a, the portion of the first coating layer V1a exposed from the resist R0 is removed. As a result, the first coating layer V1 is formed as shown in FIG. 7F. In this wet etching, the width of the first coating layer V1 is slightly reduced compared to the width of the reflective layer RL. In addition, in this wet etching, the second coating layer V2 may also be eroded. As a result, in the example of FIG. 7F, the width of the second coating layer V2 is slightly reduced compared to the width of the reflective layer RL.

[0079] After step PR3e, the resist R0 is removed (stripped) (step PR3f in FIG. 6). Furthermore, the first coating layer V1 and the second coating layer V2 formed of conductive oxide are subjected to an annealing treatment (step PR3g in FIG. 6). In this annealing treatment, the first coating layer V1 and the second coating layer V2 are crystallized by heating.

[0080] Through the above steps, the lower electrodes LE1, LE2, and LE3 are completed. The ends of the mask layer MK located on the lower electrodes LE1, LE2, and LE3 respectively protrude beyond the ends of the lower electrodes LE1, LE2, and LE3.

[0081] Next, as shown in FIG. 7G, a third layer L3 is formed to cover the lower electrodes LE1, LE2, and LE3 and the mask layer MK (step PR3h in FIG. 6). The third layer L3 is a layer to be processed into the coating resin layers CR1, CR2, and CR3, and is formed of a positive photosensitive resin. The third layer L3 also fills the space below the mask layer MK that protrudes beyond the first coating layer V1, the reflective layer RL, and the second coating layer V2.

[0082] After step PR3h, the third layer L3 is exposed (step PR3i in FIG. 6). Then, the exposed third layer L3 is developed (step PR3j in FIG. 6). The portion of the third layer L3 located below the mask layer MK is not exposed to light. Therefore, as shown in FIG. 7H, a portion of the third layer L3 remains near the edge of the mask layer MK even after development.

[0083] After step PR3j, a third etching is performed on the mask layer MK (step PR3k in FIG. 6). As a result, the mask layer MK is removed as shown in FIG. 7I. The third etching is, for example, wet etching. Hydrofluoric acid or buffered hydrofluoric acid (BHF) can be used as an etchant for this wet etching.

[0084] After step PR3k, the third layer L3 remaining below the mask layer MK is fired (step PR3l in FIG. 6). As a result, a coating resin layer CR1 is formed that covers the end of the lower electrode LE1, as shown in FIG. 7J. Coating resin layers CR2 and CR3 are formed in a similar manner. Note that firing causes the surfaces of the coating resin layers CR1, CR2, and CR3 to become gently curved.

[0085] In Fig. 7J, the coating resin layer CR1 covers the entire end of the lower electrode LE1, as in the example of Fig. 4. As another example, the thickness of the coating resin layer CR1 may be reduced by firing. In this case, the coating resin layer CR1 may have a shape that covers part of the end of the lower electrode LE1, as in the example of Fig. 5.

[0086] After the above step PR3, as shown in FIG. 8A, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed (step PR4 in FIG. 6). Furthermore, partition walls 6 having lower portions 61 and upper portions 62 are formed on the rib layer 5 (step PR5 in FIG. 6). The lower portions 61 include a bottom layer 63 and an axis layer 64 as shown in FIG. 3. The upper portions 62 include a first top layer 65 and a second top layer 66 as shown in FIG. 3. Note that FIG. 8A illustrates a simplified structure of the lower electrodes LE1, LE2, and LE3.

[0087] After the partition walls 6 are formed, pixel openings AP1, AP2, and AP3 are formed in the rib layer 5 as shown in Fig. 8B (step PR6 in Fig. 6). As another example, the pixel openings AP1, AP2, and AP3 may be formed before the partition walls 6 are formed.

[0088] Next, steps for forming display elements DE1, DE2, and DE3 are performed (steps PR7, PR8, and PR9 in FIG. 6). In this embodiment, it is assumed that display element DE1 is formed first, display element DE2 is formed next, and display element DE3 is formed last. However, the order in which display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0089] 8C, the display element DE1 is formed by first forming a laminated film FL1 and a sealing layer SE11 over the entire display area DA and the peripheral area SA. As shown in FIG. 3, the laminated film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1.

[0090] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed by vapor deposition. The sealing layer SE11 is formed by CVD (Chemical Vapor Deposition). The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0091] After the stacked film FL1 and the sealing layer SE11 are formed, a resist R1 is disposed on the sealing layer SE11 as shown in Fig. 8C. The resist R1 covers the subpixel SP1 and part of the partition wall 6 around it.

[0092] Then, as shown in FIG. 8D, etching is performed using the resist R1 as a mask to remove the stacked film FL1 and the portions of the sealing layer SE11 that are not covered by the resist R1. This results in the formation of a display element DE1 in the subpixel SP1. For example, the etching may include wet etching or dry etching, which is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching steps, the resist R1 is removed.

[0093] Display elements DE2 and DE3 are formed in the same manner as display element DE1. That is, when display element DE2 is formed, a laminated film FL2 and a sealing layer SE12 are formed over the entire display area DA and peripheral area SA. As shown in FIG. 3, the laminated film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2. By patterning such laminated film FL2 and sealing layer SE12, a display element DE2 is formed in subpixel SP2, as shown in FIG. 8E.

[0094] In forming the display element DE3, a laminated film FL3 and a sealing layer SE13 are formed over the entire display area DA and peripheral area SA. As shown in Fig. 3, the laminated film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3. By patterning the laminated film FL3 and the sealing layer SE13, the display element DE3 is formed in the subpixel SP3, as shown in Fig. 8F.

[0095] After the display elements DE1, DE2, and DE3 are formed, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in Fig. 3 are formed in this order (step PR10 in Fig. 6). Through these steps, the display device DSP is completed.

[0096] In the present embodiment described above, it is possible to obtain a display device DSP that includes display elements DE1, DE2, DE3 that are separated into subpixels SP1, SP2, SP3 by the overhanging partition walls 6 and individually sealed.

[0097] Furthermore, with the configuration of the lower electrodes LE1, LE2, LE3 and the coating resin layers CR1, CR2, CR3 according to this embodiment, it is possible to improve the yield and reliability of the display device DSP. This effect will be explained below.

[0098] 9 is a schematic cross-sectional view showing a structure in the vicinity of the end E1 of the lower electrode LE1 according to a comparative example of the present embodiment, in which the coating resin layer CR1 covering the end E1 is not arranged.

[0099] In order to increase the reflectivity of the lower electrode LE1, the reflective layer RL needs to be formed thick. Furthermore, it is difficult to form the end portion Er of the reflective layer RL, which is made of a metal material such as silver and processed by wet etching, into a tapered shape with a gradually decreasing thickness. Therefore, the end portion Er may be formed into a steep shape approximately parallel to the Z direction as shown in FIG. 4, or into an overhanging shape with a protruding upper end as shown in FIG. 9.

[0100] In this way, when the reflective layer RL is thick, the shape of the end portion Er is steep, and the rib layer 5 is made of an inorganic insulating material, cracks CK may occur that extend from the vicinity of the end portion Er to the step portion ST on the upper surface of the rib layer 5. When cracks CK occur, a moisture path may be formed from the organic insulating layer 12 to the upper surface of the rib layer 5. If moisture from the organic insulating layer 12 reaches the upper surface of the rib layer 5 through this moisture path, the organic layer OR1 and other layers disposed thereon may corrode, potentially causing display defects.

[0101] In contrast, in this embodiment, a coating resin layer CR1 is disposed to cover at least a portion of the end E1, thereby flattening the vicinity of the end E1 and suppressing the occurrence of cracks CK in the rib layer 5. As a result, it is possible to suppress the penetration of moisture from the organic insulating layer 12 into elements disposed above the rib layer 5.

[0102] Furthermore, since the occurrence of cracks CK is suppressed in this way, the reflectance can be increased by increasing the thickness of the reflective layer RL. Furthermore, it is also possible to further improve water resistance by increasing the thickness of the first coating layer V1 or by adding an inorganic film under the first coating layer V1.

[0103] 4, in this embodiment, the step ST on the upper surface of the rib layer 5 caused by the lower electrode LE1 is covered by the lower part 61. In this case, even if a crack CK occurs, the lower part 61 can block the moisture path through the crack CK.

[0104] Furthermore, when a mask layer MK for the coating resin layer CR1 is formed using a resist R0 for the lower electrode LE1, as in the manufacturing process shown in Figures 7A to 7J, misalignment of the coating resin layer CR1 with respect to the lower electrode LE1 can be suppressed.

[0105] In this manufacturing process, if the first etching performed on the second layer L2 (step PR3d, FIG. 7C) is dry etching, erosion of the edges of the mask layer MK is suppressed, and a mask layer MK with a shape similar to that of the resist R0 can be obtained. Furthermore, if the second etching performed on the first layer L1 (step PR3e, FIGS. 7D-7F) is wet etching, the edges of the first coating layer V1, reflective layer RL, and second coating layer V2 are more likely to erode and recede than the edges of the mask layer MK. This allows for a good space to be formed below the mask layer MK for forming the coating resin layer CR1. Furthermore, if the third etching performed on the mask layer MK (step PR3k, FIG. 7I) is wet etching using hydrofluoric acid or buffered hydrofluoric acid, damage to the second coating layer V2 and the organic insulating layer 12, both of which are made of conductive oxide, can be suppressed.

[0106] Here, the effects of this embodiment have been described focusing on the lower electrode LE1 and the coating resin layer CR1, but the same effects are also achieved by the lower electrodes LE2, LE3 and the coating resin layers CR2, CR3.

[0107] [Second embodiment] A second embodiment will be described below. In this embodiment, the configuration that is not particularly mentioned is the same as that of the first embodiment.

[0108] 10 is a schematic plan view showing an example of the layout of the subpixels SP1, SP2, and SP3 according to this embodiment. As shown in FIG. 10, the lower electrode LE1 has ends E1a, E1b, E1c, and E1d. The lower electrode LE2 has ends E2a, E2b, E2c, and E2d. The lower electrode LE3 has ends E3a, E3b, E3c, and E3d. The ends E1a, E1b, E2a, E2b, E3a, and E3b extend parallel to the Y direction. The ends E1c, E1d, E2c, E2d, E3c, and E3d extend parallel to the X direction. Each end is covered with a rib layer 5.

[0109] 10 corresponds to the shape of the lower portion 61, more specifically, the shape of the axial layer 64. In this embodiment, a portion (first end) of each end of the lower electrodes LE1, LE2, and LE3 overlaps with the axial layer 64, and the remaining portion (second end) does not overlap with the axial layer 64. Here, the overlapping of the ends of the lower electrodes LE1, LE2, and LE3 with the lower portion 61 means that these ends are located below the lower portion 61.

[0110] Specifically, ends E1a and E1c of the lower electrode LE1 overlap with the lower portion 61, but ends E1b and E1d do not overlap with the lower portion 61. Furthermore, ends E2a, E2c, and E2d of the lower electrode LE2 overlap with the lower portion 61, but end E2b does not overlap with the lower portion 61. Furthermore, ends E3a and E3c of the lower electrode LE3 overlap with the lower portion 61, but ends E3b and E3d do not overlap with the lower portion 61.

[0111] For example, when focusing on the lower electrodes LE1 and LE2 and the lower portion 61 therebetween, one end of each of the lower electrodes LE1 and LE2 overlaps with the lower portion 61, while the other does not. In this manner, the relationship in which the lower portion 61 overlaps with one end of the adjacent lower electrode but does not overlap with the other end of the adjacent lower electrode holds true for most of the lower portion 61. However, a portion 61X of the lower portion 61 located between the pixel openings AP2 and AP3 overlaps with both the end E2d of the lower electrode LE2 and the end E3c of the lower electrode LE3. Contact holes CH2 and CH3 are provided below the portion 61X.

[0112] Figure 11 is a schematic cross-sectional view of the display device DSP taken along line XI-XI in Figure 10. In this figure, similar to Figure 4, the organic insulating layer 12, the rib layer 5, the partition wall 6, the lower electrodes LE1, LE2, and the coating resin layers CR1, CR2 are shown, and other elements are omitted.

[0113] 4, a region Ax is formed between the coating resin layers CR1 and CR2, where the organic insulating layer 12 is covered with the rib layer 5. In the example of FIG. 11, a part of the region Ax overlaps with the partition wall 6, and another part does not overlap with the partition wall 6.

[0114] The step ST generated on the upper surface of the rib layer 5 by an end located below the partition wall 6, such as the end E1a, is covered by the bottom layer 63 and the shaft layer 64. On the other hand, the step ST generated by an end not located below the partition wall 6, such as the end E2b, is not covered by the bottom layer 63 and the shaft layer 64.

[0115] In this configuration, even if a crack occurs in the rib layer 5 at a step ST that is not covered by the partition wall 6, such as the step ST caused by the end E2b of the lower electrode LE2, the partition wall 6 cannot block the moisture path caused by the crack. However, in this embodiment, as in the first embodiment, the coating resin layers CR1, CR2, and CR3 are arranged along the ends E1, E2, and E3 of the lower electrodes LE1, LE2, and LE3. Therefore, it is possible to suppress cracks in the rib layer 5 caused by the ends E1, E2, and E3.

[0116] All display devices and manufacturing methods thereof that can be implemented by a person skilled in the art by making appropriate design modifications based on the display devices and manufacturing methods thereof disclosed in the above embodiments also fall within the scope of the present invention as long as they include the gist of the present invention.

[0117] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0118] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0119] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE2...sealing layer, RS1, RS2...resin layer, 5...rib layer, 6...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer, 12...organic insulating layer, RL...reflective layer, V1...first coating layer, V2...second coating layer, CR1, CR2, CR3...coating resin layer.

Claims

1. an organic insulating layer formed of an organic insulating material; a lower electrode disposed above the organic insulating layer; a coating resin layer that covers at least a part of an end portion of the lower electrode; a rib layer that covers an end portion of the lower electrode and the coating resin layer and has a pixel opening that overlaps the lower electrode; an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer; A display device comprising:

2. the coating resin layer surrounds the lower electrode in a plan view; The display device according to claim 1 .

3. the lower electrode includes a reflective layer that reflects light emitted from the organic layer; the coating resin layer covers at least a part of an edge of the reflective layer; The display device according to claim 1 .

4. the lower electrode further comprises a first covering layer located between the organic insulating layer and the reflective layer and formed of a transparent conductive oxide; an end of the reflective layer protrudes beyond an end of the first coating layer; the coating resin layer fills a gap between an end of the organic insulating layer and an end of the reflective layer; The display device according to claim 3 .

5. the lower electrode further includes a second covering layer covering an upper surface of the reflective layer; the coating resin layer does not cover the upper surface of the second coating layer; The display device according to claim 3 .

6. a plurality of sub-pixels each including the lower electrode, the pixel opening, the organic layer, the upper electrode, and the coating resin layer; the coating resin layers of the adjacent sub-pixels are spaced apart; The display device according to claim 1 .

7. the organic insulating layer is covered with the rib layer in a region between adjacent coating resin layers; The display device according to claim 6.

8. a partition wall including a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion; The display device according to claim 7 .

9. the plurality of subpixels include a first subpixel and a second subpixel adjacent to each other with the partition wall interposed therebetween, an end of the lower electrode of the first subpixel and an end of the lower electrode of the second subpixel overlap with the partition wall in a plan view; The display device according to claim 8 .

10. the plurality of subpixels include a first subpixel and a second subpixel adjacent to each other with the partition wall interposed therebetween, In a plan view, one of an end portion of the lower electrode of the first subpixel and an end portion of the lower electrode of the second subpixel overlaps with the partition wall, and the other does not overlap with the partition wall. The display device according to claim 8 .

11. The width of the coating resin layer is 0.2 μm or more. The display device according to any one of claims 1 to 10.

12. The coating resin layer is formed of a positive photosensitive resin. The display device according to any one of claims 1 to 10.

13. forming an organic insulating layer made of an organic insulating material; a lower electrode and a coating resin layer covering at least a portion of an end of the lower electrode are formed above the organic insulating layer; forming a rib layer that covers the end portion of the lower electrode and the coating resin layer and has a pixel opening that overlaps the lower electrode; forming an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage; forming an upper electrode covering the organic layer; A method for manufacturing a display device, comprising:

14. The lower electrode and the coating resin layer are formed by forming a first layer of material for the bottom electrode over the organic insulating layer; forming a second layer having a light-blocking property above the first layer; disposing a resist on the second layer; a mask layer is formed by removing a portion of the second layer exposed from the resist by a first etching; removing a portion of the first layer exposed from the resist by a second etching process to form the lower electrode having a width smaller than that of the mask layer; removing the resist; forming a third layer made of a positive photosensitive resin that covers the lower electrode and the mask layer; exposing the third layer to light; developing the exposed third layer; removing the mask layer by a third etching; This includes: the third layer remaining below an end of the mask layer protruding from an end of the lower electrode during the development forms the coating resin layer; The method for manufacturing a display device according to claim 13 .

15. The first etching is a dry etching. The method for manufacturing a display device according to claim 14 .

16. The third etching is a wet etching. The method for manufacturing a display device according to claim 15.

17. the second layer is formed of titanium; the etching solution in the third etching contains hydrofluoric acid or buffered hydrofluoric acid; The method for manufacturing a display device according to claim 16.

18. The second etching is a wet etching. The method for manufacturing a display device according to claim 14 .

19. forming a partition wall including a lower portion disposed above the rib layer and an upper portion having an end portion protruding from a side surface of the lower portion before forming the organic layer and the upper electrode; The method for manufacturing a display device according to claim 13 , further comprising:

20. the partition wall is formed so as to overlap at least a part of an end portion of the lower electrode in a plan view. The method for manufacturing a display device according to claim 19.

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