Memory device using semiconductor element and method for manufacturing the same

Abstract

To provide a memory device using semiconductor elements and a method for manufacturing the same.SOLUTION: In planar viewing, it has a gate insulating layer contacting both sides of each of parallel channel semiconductor layers 10a1 and 10a2, drive gate conductor layers (WL1 to WL4, PL1, PL2) arranged adjacent to this gate insulating layer, and electrostatic shielding conductor layers (SG1 to SG3, SG1a, SG3a), and N+ regions 11aa and 11ab are at both ends of the channel semiconductor layer 10a1 and N+ regions 11ba and 11bb are at both ends of the channel semiconductor layer 10a2.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a memory device using semiconductor elements and a manufacturing method thereof. [Background technology]

[0002] In recent years, in the development of LSI (Large Scale Integration) technology, there has been a demand for higher integration and higher performance of memory elements.

[0003] Conventional technologies include a DRAM (Dynamic Random Access Memory; see, for example, Non-Patent Document 2) in which a capacitor is connected to an SGT (Surrounding Gate Transistor; see, for example, Patent Document 1 and Non-Patent Document 1) used as a selection transistor, a PCM (Phase Change Memory; see, for example, Non-Patent Document 3) in which a resistance change element is connected, a RRAM (Resistive Random Access Memory; see, for example, Non-Patent Document 4), and an MRAM (Magneto-resistive Random Access Memory; see, for example, Non-Patent Document 5) in which the resistance is changed by changing the direction of magnetic spin using a current.

[0004] There are also DRAM memory cells (see Patent Document 2, Non-Patent Documents 6 to 10) that do not have a capacitor and are composed of a single MOS transistor. In such DRAM memory cells, for example, a source-drain current of an N-channel MOS transistor generates holes and electrons in the channel by impact ionization. Some or all of the holes are retained in the channel to write logical data "1." Then, the holes are removed from the channel to write logical data "0." In this memory cell, memory cells with "1" writes and memory cells with "0" writes randomly exist for a common selected word line. When an on-voltage is applied to the selected word line, the floating body channel voltage of the selected memory cell connected to this selected word line fluctuates significantly due to capacitive coupling between the gate electrode and the channel. The challenges for this memory cell are to improve the operating margin reduction caused by the floating body channel voltage fluctuation and the degradation of data retention characteristics caused by the removal of some of the holes, which are signal charges accumulated in the channel.

[0005] There is also a Twin-Transistor MOS transistor memory element in which one memory cell is formed using two MOS transistors in an SOI (Silicon On Insulator) layer (see, for example, Patent Documents 3 and 4, and Non-Patent Document 11). In these elements, the floating body channels of the two MOS transistors are separated by an N + The layer is formed in contact with the insulating layer on the substrate side. +The floating body channels of the two MOS transistors are electrically isolated by this layer. The signal charge, or holes, is stored in only the floating body channel of one of the MOS transistors. The other MOS transistor acts as a switch to read out the signal holes stored in the other MOS transistor. In this memory cell, the signal charge, or holes, is stored in the channel of one MOS transistor, so just like the memory cell consisting of one MOS transistor mentioned above, there are issues to be addressed: improving the reduced operating margin, or improving the reduced data retention characteristics caused by the removal of some of the signal charge, or holes, stored in the channel.

[0006] Also, there is a dynamic flash memory cell 111 shown in FIG. 6, which does not have a capacitor and is composed of a MOS transistor (see Patent Documents 5 and 6, and Non-Patent Document 12). As shown in FIG. 6(a), a floating body semiconductor body 102 is provided on an SiO2 layer 101 of an SOI substrate. N terminals connected to source lines SL are provided at both ends of the floating body semiconductor body 102. + N connected to layer 103 and bit line BL + There is a layer 104. And N + a first gate insulating layer 109a connected to the layer 103 and covering the floating body semiconductor body 102; + The floating body semiconductor substrate 102 includes a layer 104 and a second gate insulating layer 109b connected to the first gate insulating layer 109a via a slit insulating film 110 and covering the floating body semiconductor substrate 102. A first gate conductor layer 105a covers the first gate insulating layer 109a and is connected to the plate line PL, and a second gate conductor layer 105b covers the second gate insulating layer 109b and is connected to the word line WL. A slit insulating layer 110 is provided between the first gate conductor layer 105a and the second gate conductor layer 105b. This forms a memory cell 111 of a DFM (Dynamic Flash Memory). Note that the source line SL is connected to the N + layer 104, and the bit line BL is connected to + It may be configured to connect to layer 103.

[0007] As shown in FIG. 6(a), for example, N + Zero voltage on layer 103, N + A positive voltage is applied to the layer 104, causing the first N-channel MOS transistor region, consisting of the floating body semiconductor body 102 covered with the first gate conductor layer 105a, to operate in the saturation region, and the second N-channel MOS transistor region, consisting of the floating body semiconductor body 102 covered with the second gate conductor layer 105b, to operate in the linear region. As a result, no pinch-off point exists in the second N-channel MOS transistor region, and an inversion layer 107b is formed over the entire surface. This inversion layer 107b formed below the second gate conductor layer 105b connected to the word line WL essentially functions as the drain of the first N-channel MOS transistor region. As a result, the electric field is maximized in the boundary region of the channel region between the first N-channel MOS transistor region and the second N-channel MOS transistor region, causing impact ionization in this region. 6(b), the memory write operation is performed by removing the electrons from the electron-hole group generated by impact ionization from the floating body semiconductor body 102 and retaining some or all of the hole group 106 in the floating body semiconductor body 102. This state represents logical storage data "1."

[0008] As shown in FIG. 6(c), a positive voltage is applied to the plate line PL, zero voltage is applied to the word line WL and bit line BL, and a negative voltage is applied to the source line SL to remove the hole group 106 from the floating body semiconductor matrix 102, thereby performing an erase operation. This state results in logical data "0." Then, in a data read operation, the voltage applied to the first gate conductor layer 105a connected to the plate line PL is set higher than the threshold voltage for logical data "1" and lower than the threshold voltage for logical data "0." This characteristic, as shown in FIG. 6(d), prevents current from flowing even when the voltage on the word line WL is increased when reading logical data "0." This characteristic significantly expands the operating margin compared to memory cells. In this memory cell, the channels of the first and second N-channel MOS transistor regions, each gated by a first gate conductor layer 105a connected to the plate line PL and a second gate conductor layer 105b connected to the word line WL, are connected by the floating body semiconductor body 102. This significantly suppresses voltage fluctuations in the floating body semiconductor body 102 when a selection pulse voltage is applied to the word line WL. This significantly improves the problems of the memory cell described above, such as a reduction in operating margin and a degradation in data retention characteristics due to the removal of a portion of the hole group (signal charge accumulated in the channel). High integration can be achieved by forming multiple dynamic flash memory cells perpendicular to the substrate (Patent Document 6). Because such dynamic flash memories are configured with adjacent memory cells in the vertical and horizontal directions, reducing interference between adjacent memory cells and facilitating fabrication are required. Further performance improvements and higher integration are also required.

[0009] In addition, in writing "1", electron-hole pairs may be generated using a gate-induced drain leakage (GIDL) current described in Non-Patent Document 10, and the floating body FB may be filled with the generated holes. [Prior art documents] [Patent documents]

[0010] [License 1] Special Announcement No. 2-188966 [License 2] Special Announcement No. 3-171768 [License 3] US2008 / 0137394 A1 [License 4] US2003 / 0111681 A1 [Patent Document 5] Patent No. 7057032 [License 6] US2022 / 0208254 A1 [Non-licensed literature]

[0011] [Non-licensed Document 1] Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573-578 (1991) [Non-licensed Document 2] H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. Dong, J. Kim, YC Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung: “4F2 DRAM Cell with Vertical Pillar Transistor(VPT),” 2011 Proceeding of the European Solid-State Device Research Conference, (2011) [Non-licensed Document 3] HS Philip Wong, S. Raoux, S. Kim, Jiale Liang, JR Reifenberg, B. Rajendran, M. Asheghi and KE Goodson: “Phase Change Memory,” Proceeding of IEEE, Vol.

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[0012] One aspect of the present invention is a semiconductor device comprising: a first channel semiconductor layer and a second channel semiconductor layer separated from a substrate in a vertical direction and extending in parallel in a horizontal direction; a first impurity region in contact with both ends of the first channel semiconductor layer; a second impurity region; a third impurity region in contact with both ends of the second channel semiconductor layer; a fourth impurity region; a first gate insulating layer in contact with a vertical side surface of the first channel semiconductor layer on a side not facing the second channel semiconductor layer; a second gate insulating layer in contact with the vertical side surface of the first channel semiconductor layer facing the second channel semiconductor layer; a third gate insulating layer in contact with the vertical side surface of the second channel semiconductor layer facing the first channel semiconductor layer; a fourth gate insulating layer in contact with the vertical side surface of the second channel semiconductor layer on a side not facing the first channel semiconductor layer; a first gate conductor layer arranged in such a direction, a second gate conductor layer, a third gate conductor layer in contact with the second gate insulating layer and arranged along a side surface of the first channel semiconductor layer and in a direction from an end of the first channel semiconductor layer toward the center, a fourth gate conductor layer, a fifth gate conductor layer, a sixth gate conductor layer in contact with the fourth gate insulating layer and arranged along a side surface of the second channel semiconductor layer in a direction from an end of the second channel semiconductor layer toward the center, and a seventh gate conductor layer, wherein the fourth gate conductive layer and the fifth gate conductive layer are in contact with the third gate insulating layer and arranged along a side surface of the second channel semiconductor layer and in a direction from the end of the second channel semiconductor layer toward the center, the fourth gate conductor layer is an electrostatic shield conductor layer, and the second gate conductor layer and the seventh gate conductor layer are memory drive conductor layers.

[0013] A memory device using the semiconductor element may include an eighth gate conductor layer in contact with the first gate insulating layer and aligned with the second gate conductor layer along a side surface of the first channel semiconductor layer and on the opposite side to the first gate conductor layer, a ninth gate conductor layer in contact with the second gate insulating layer and aligned with the fourth gate conductor layer along a side surface of the first channel semiconductor layer and on the opposite side to the third gate conductor layer, a tenth gate conductor layer in contact with the third gate insulating layer and aligned with the fourth gate conductor layer along a side surface of the second channel semiconductor layer and on the opposite side to the fifth gate conductor layer, and an eleventh gate conductor layer in contact with the fourth gate insulating layer and aligned with the seventh gate conductor layer along a side surface of the second channel semiconductor layer and on the opposite side to the sixth gate conductor layer, and the eighth and eleventh gate conductor layers may be memory driving conductor layers.

[0014] In a plan view, the first gate insulating layer includes a first gate insulating layer portion in contact with the first gate conductor layer and a second gate insulating layer portion in contact with the second gate conductor layer; in a plan view, the second gate insulating layer includes a third gate insulating layer portion in contact with the third gate conductor layer and a fourth gate insulating layer portion in contact with the fourth gate conductor layer; in a plan view, the third gate insulating layer includes a fifth gate insulating layer portion in contact with the fifth gate conductor layer and a sixth gate insulating layer portion in contact with the fourth gate conductor layer; in a plan view, the fourth gate insulating layer includes a seventh gate insulating layer portion in contact with the sixth gate conductor layer and an eighth gate insulating layer portion in contact with the seventh gate conductor layer; and the fourth gate insulating layer portion and the sixth gate insulating layer portion are connected to surround the fourth gate conductor layer.

[0015] The thickness of the fourth gate insulating layer portion and the sixth gate insulating layer portion, which are connected to surround the fourth gate conductor layer, can be greater than the thickness of the first to third gate insulating layer portions, the fifth gate insulating layer portion, the seventh gate insulating layer portion, and the eighth gate insulating layer portion.

[0016] The capacitance per unit area of ​​the fourth gate insulating layer portion and the sixth gate insulating layer portion, which are connected to surround the fourth gate conductor layer, can be smaller than the capacitance per unit area of ​​the first to third gate insulating layer portions, the fifth gate insulating layer portion, the seventh gate insulating layer portion, and the eighth gate insulating layer portion.

[0017] The first and sixth gate conductor layers may be word line conductor layers, and the third and fifth gate conductor layers may be electrostatic shield conductor layers.

[0018] The first gate conductor layer and the third gate conductor layer may be connected, and the connected first gate conductor layer and the third gate conductor layer may be word line conductor layers, and the fifth gate conductor layer and the sixth gate conductor layer may be connected, and the connected fifth gate conductor layer and the sixth gate conductor layer may be word line conductor layers.

[0019] During the signal charge retention period, a voltage may be applied to the electrostatic shield layer to cause a group of holes or electrons, which are the signal, to accumulate on the electrostatic shield layer side of the first channel semiconductor layer and the second channel semiconductor layer.

[0020] One aspect of the present invention includes the steps of forming a first semiconductor layer and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer being spaced apart from a substrate in a vertical direction, extending horizontally in parallel to a first direction in a plan view, and each having a first insulating layer above and below the first semiconductor layer in the vertical direction; forming a first gate insulating layer in contact with each of the side surfaces of the first semiconductor layer and the first insulating layer on the same side, and each of the side surfaces of the second semiconductor layer and the first insulating layer on the same side; forming a first gate conductor layer in contact with the first gate insulating layer; forming a second insulating layer by filling the space between the first gate conductor layers facing each other; and etching the first gate insulating layer, the first gate conductor layer, and the second insulating layer using a first mask material layer as a mask, the first mask material layer extending in a second direction orthogonal to the first direction in a plan view, to form the first gate insulating layer. forming a first space on one end side of the first semiconductor layer and the second semiconductor layer of the mask material layer, and forming a second space on the other end side of the first semiconductor layer and the second semiconductor layer of the first mask material layer; forming a second gate insulating layer in contact with an inner side surface of the second space, and a second gate conductor layer filling the entire third space surrounded by the second gate insulating layer; etching the first semiconductor layer and the second semiconductor layer on the end side of the first gate conductor layer and the second gate conductor layer in a plan view, to form a first channel semiconductor layer and a second channel semiconductor layer; and forming impurity regions containing a large amount of donor or acceptor impurities at both ends of the first channel semiconductor layer and the second channel semiconductor layer, The present invention provides a method for manufacturing a memory device using a semiconductor element, characterized in that, in a plan view, when the second gate conductor layer sandwiched between the first channel semiconductor layer and the second channel semiconductor layer is an electrostatic shield conductor layer, the second gate conductor layer on the end side of the first channel semiconductor layer and the second semiconductor layer is a driving conductor layer, and when the second gate conductor layer sandwiched between the first channel semiconductor layer and the second semiconductor layer is a driving conductor layer, the second gate conductor layer on the end side of the first channel semiconductor layer and the second semiconductor layer is an electrostatic shield conductor layer.

[0021] A fifth gate insulating layer may be formed simultaneously with the first gate insulating layer on each of the side surfaces of the first semiconductor layer and the first insulating layer on the same side, and on each of the side surfaces of the second semiconductor layer and the first insulating layer on the same side, on which the first gate insulating layer is not formed, and a third gate conductor layer may be formed simultaneously with the first gate conductor layer in contact with the third gate insulating layer.

[0022] A second mask material layer is formed so as to overlap at least a portion of the first mask material layer and extend in the second direction, and a third mask material layer of equal width is formed on the side surfaces of the first and second mask material layers opposite to the second mask material layer, and the first insulating layer and the first and second semiconductor layers are etched using the first to third mask material layers as etching masks.

[0023] The first insulating layer and the first and second semiconductor layers are etched using the first to third mask material layers as etching masks, and a third insulating layer can be formed below the third mask material layer in a plan view and between the first channel semiconductor layer and the second channel semiconductor layer. [Brief explanation of the drawings]

[0024] [Figure 1A] 1 is a structural diagram of a two-stage dynamic flash memory cell according to a first embodiment; [Figure 1B] 1 is a structural diagram of a two-stage dynamic flash memory cell according to a first embodiment; [Figure 2] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a second embodiment. [Figure 3] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a third embodiment. [Figure 4A] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a fourth embodiment. [Figure 4B] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a fourth embodiment. [Figure 4C] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a fourth embodiment. [Figure 4D] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a fourth embodiment. [Figure 4E] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a fourth embodiment. [Figure 4F] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a fourth embodiment. [Figure 4G] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a fourth embodiment. [Figure 4H] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a fourth embodiment. [Figure 4I] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a fourth embodiment. [Figure 4J] FIG. 10 is a structural diagram of a two-stage dynamic flash memory cell according to a fourth embodiment. [Figure 5A] FIG. 10 is a structural diagram of a four-stage dynamic flash memory cell according to a fifth embodiment. [Figure 5B] FIG. 10 is a structural diagram of a four-stage dynamic flash memory cell according to a fifth embodiment. [Figure 5C] FIG. 10 is a structural diagram of a four-stage dynamic flash memory cell according to a fifth embodiment. [Figure 6] FIG. 1 is a diagram illustrating a conventional dynamic flash memory. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, a memory device using a semiconductor element (hereinafter referred to as a dynamic flash memory) according to an embodiment of the present invention will be described with reference to the drawings.

[0026] (First embodiment) 1A and 1B, a structure in which dynamic flash memory cells are formed in two columns and two rows in the horizontal and vertical directions according to a first embodiment of the present invention will be described. FIG. 1A is a schematic three-dimensional diagram of a two-row dynamic flash memory cell. FIG. 1B shows a plan view and a cross section of the schematic three-dimensional diagram of FIG. 1A. In an actual dynamic flash memory, memory cells are arranged in large numbers in the horizontal and vertical directions.

[0027] As shown in FIG. 1A, there are two channel semiconductor layers 10a1 (an example of a "first channel semiconductor layer" in the claims) and 10a2 (an example of a "second channel semiconductor layer" in the claims) that are separated vertically from a substrate 1 (an example of a "substrate" in the claims) and extend in parallel in the horizontal direction. Two channel semiconductor layers 10b1 (not shown) and 10b2 are arranged in parallel vertically below the channel semiconductor layers 10a1 and 10a2. When viewed from above, the channel semiconductor layer 10a1 and the channel semiconductor layer 10b1 overlap, and similarly the channel semiconductor layer 10a2 and the channel semiconductor layer 10b2 overlap. N-type semiconductor layers containing a large amount of donor impurities are formed on both ends of the channel semiconductor layer 10a1. + The channel semiconductor layer 10a2 has a first impurity region 11aa (an example of the "first impurity region" in the claims) and a second impurity region 11ab (an example of the "second impurity region" in the claims). + The channel semiconductor layer 10b1 has a N-type impurity region 11ba (an example of the "third impurity region" in the claims) and a N-type impurity region 11bb (an example of the "third impurity region" in the claims) at both ends. + The channel semiconductor layer 10b2 has N-type layers 11ca (not shown) and 11cb. +The channel semiconductor layers 10a1 and 10a2 are connected to the gate insulating layer 10b1 and 10b2 via a gate insulating layer 11da and 11db. The channel semiconductor layers 10a1 and 10a2 and the channel semiconductor layers 10b1 and 10b2 are connected to the gate insulating layer 10b1 and 10b2 via a word line conductor layer WL1 (an example of the "first gate conductor layer" in the claims), a plate line conductor layer PL1 (an example of the "second gate conductor layer" in the claims), and a word line conductor layer WL2 (an example of the "eighth gate conductor layer" in the claims). Shield line conductor layer SG1 (an example of the "third gate conductor layer" in the claims), shield line conductor layer SG2 (an example of the "fourth gate conductor layer" in the claims), and shield line conductor layer SG3 (an example of the "ninth gate conductor layer" in the claims) are in contact with the gate insulating layer on the other side surface of channel semiconductor layers 10a1 and 10b1 and are connected in the vertical direction. Word line conductor layer WL3 (an example of the "sixth gate conductor layer" in the claims), plate line conductor layer PL2 (an example of the "seventh gate conductor layer" in the claims), and word line conductor layer WL4 (an example of the "eleventh gate conductor layer" in the claims) are in contact with the gate insulating layer on the other side surface of channel semiconductor layers 10a2 and 10b2 and are connected in the vertical direction.

[0028] And N + Layer 11aa, N + The layer 11ca is connected to the first source line SL1 that is connected in the vertical direction. + Layer 11ba, N + The layer 11da is connected to the second source line SL2 which is connected in the vertical direction. + Layer 11ab, N + The layer 11bb is connected to the first horizontal bit line BL1. + Layer 11cb, N + The layer 11db is connected to the second horizontally connected bit line BL2.

[0029] As shown in FIG. 1A, the conductor layers for driving the memory of the channel semiconductor layers 10a1 and 10b1 are the word line conductor layer WL1, the plate conductor layer PL1, and the word line conductor layer WL2. The conductor layers for driving the memory of the channel semiconductor layers 10a2 and 10b2 are the word line conductor layer WL3, the plate conductor layer PL2, and the word line conductor layer WL4. When viewed from a horizontal cross section, shield line conductor layers SG1 and SG1a are located between the word line conductor layer WL1 and the word line WL3. The shield line conductor layer SG2 is located between the plate line conductor layer PL1 and the plate line conductor layer PL2.

[0030] Figure 1B(a) shows a plan view of the schematic three-dimensional diagram of the two-stage dynamic flash memory cell of Figure 1A. Figure 1B(b) shows a vertical cross-sectional view along line X-X' in Figure 1B(a) (an example of the "first direction" in the claims). Figure 1B(c) shows a vertical cross-sectional view along line Y-Y' in Figure 1B(a) (an example of the "second direction" in the claims).

[0031] There are two channel semiconductor layers 10a1 and 10a2 that are separated vertically from the substrate 1 and extend in parallel in the horizontal direction. There are two channel semiconductor layers 10b1 and 10b2 that are arranged in parallel below the channel semiconductor layers 10a1 and 10a2 in the vertical direction. When viewed from above, the channel semiconductor layer 10a1 and the channel semiconductor layer 10b1 overlap, and similarly the channel semiconductor layer 10a2 and the channel semiconductor layer 10b2 overlap. N-type semiconductor layers containing a large amount of donor impurities are formed on both ends of the channel semiconductor layer 10a1. + The channel semiconductor layer 10a2 has N-type layers 11aa and 11ab, which are formed at both ends of the channel semiconductor layer 10a2 and contain a large amount of donor impurities. + The channel semiconductor layer 10b1 has N layers 11ba and 11bb, which are doped with a large amount of donor impurities at both ends. + The channel semiconductor layer 10b2 has N layers 11ca and 11cb at both ends. +Layers 11da (not shown, see FIG. 1A) and 11db (not shown, see FIG. 1A) are provided. Insulating layers 12a1, 12a2, and 12a3 are provided between channel semiconductor layers 10a1 and 10b1 and above and below. Insulating layers 12b1, 12b2, and 12b3 are provided between channel semiconductor layers 10a2 and 10b2 and above and below. Gate insulating layers 13aa (an example of the "first gate insulating layer" in the claims) and 13ab (an example of the "second gate insulating layer" in the claims) are provided on both side surfaces of channel semiconductor layers 10a1 and 10b1 and insulating layers 12a1, 12a2, and 12a3. Gate insulating layers 13ba (an example of a "third gate insulating layer" in the claims) and 13bb (an example of a "fourth gate insulating layer" in the claims) are provided on both side surfaces of the channel semiconductor layers 10a2 and 10b2 and the insulating layers 12b1, 12b2, and 12b3. That is, the gate insulating layer 13aa is on the side not facing the channel semiconductor layer 10a2 and is in contact with the vertical side surface of the channel semiconductor layer 10a1, the gate insulating layer 13ab is in contact with the vertical side surface of the first channel semiconductor layer 10a1 that faces the channel semiconductor layer 10a2, the gate insulating layer 13ba is in contact with the vertical side surface of the channel semiconductor layer 10a2 that faces the channel semiconductor layer 10a1, and the gate insulating layer 13bb is in contact with the vertical side surface of the channel semiconductor layer 10a2 that is on the side not facing the channel semiconductor layer 10a1.

[0032] Word line conductor layers WL1, plate line conductor layers PL1, and word line conductor layers WL2 are in contact with the gate insulating layer 13aa on one side surface of the channel semiconductor layers 10a1 and 10b1 and are connected in the vertical direction. Shield line conductor layers SG1, SG2, and SG3 are in contact with the gate insulating layer 13ab on the other side surface of the channel semiconductor layers 10a1 and 10b1 and are connected in the vertical direction. Shield line conductor layers SG1a (an example of a "fifth gate conductor layer" in the claims), SG2, and SG3a (an example of a "tenth gate conductor layer" in the claims) are in contact with the gate insulating layer 13ba on one side surface of the channel semiconductor layers 10a2 and 10b2 and are connected in the vertical direction. The word line conductor layer WL3, plate line conductor layer PL2, and word line conductor layer WL4 are in contact with the gate insulating layer 13bb on the other side surface of the channel semiconductor layers 10a2 and 10b2 and are connected in the vertical direction. That is, the word line conductor layer WL1 and the plate line conductor layer PL1 are in contact with the gate insulating layer 13aa and are aligned along the side surface of the channel semiconductor layer 10a1 in a direction from the edge toward the center of the channel semiconductor layer 10a1. The shield line conductor layer SG1 and the shield line conductor layer SG2 are in contact with the gate insulating layer 13ab and are aligned along the side surface of the channel semiconductor layer 10a1 in a direction from the edge toward the center of the channel semiconductor layer 10a1. The shield line conductor layer SG2 and the shield line conductor layer SG1a, the fifth gate conductive layer, are in contact with the gate insulating layer 13ba and are aligned along the side surface of the channel semiconductor layer 10a2 in a direction from the edge toward the center of the channel semiconductor layer 10a2. The word line conductor layer WL3 and the plate line conductor layer PL2 are in contact with the gate insulating layer 13bb and are aligned along the side surface of the channel semiconductor layer 10a2 in a direction from the end toward the center of the channel semiconductor layer 10a2. The word line conductor layer WL2 is in contact with the gate insulating layer 13aa and is aligned with the plate line conductor layer PL1 along the side surface of the channel semiconductor layer 10a1 and on the opposite side from the word line conductor layer WL1. The shield line conductor layer SG3 is in contact with the gate insulating layer 13ab and is aligned with the shield line conductor layer SG2 along the side surface of the channel semiconductor layer 10a1 and on the opposite side from the shield line conductor layer SG1.The shield line conductor layer SG3a (10th gate conductor layer) is in contact with the gate insulating layer 13ba and is aligned with the shield line conductor layer SG2 along the side surface of the channel semiconductor layer 10a2 and on the opposite side from the shield line conductor layer SG1a. The word line conductor layer WL4 and the plate line conductor layer PL2 are in contact with the gate insulating layer 13bb and are aligned with the plate line conductor layer PL2 along the side surface of the channel semiconductor layer 10a2 and on the opposite side from the word line conductor layer WL3. In plan view, the gate insulating layer 13aa includes a gate insulating layer portion 13aa1 (an example of a "first gate insulating layer portion" in the claims) in contact with the word line conductor layer WL1 and a gate insulating layer portion 13aa2 (an example of a "second gate insulating layer portion" in the claims) in contact with the plate line conductor layer PL1. In plan view, the gate insulating layer 13ab includes a gate insulating layer portion 13ab1 (an example of a "third gate insulating layer portion" in the claims) in contact with the shield line conductor layer SG1 and a gate insulating layer portion 13ab2 (an example of a "fourth gate insulating layer portion" in the claims) in contact with the shield line conductor layer SG2. In plan view, the gate insulating layer 13ba includes a gate insulating layer portion 13ba1 (an example of a "fifth gate insulating layer portion" in the claims) in contact with the shield line conductor layer SG1a and a gate insulating layer portion 13ba2 (an example of a "sixth gate insulating layer portion" in the claims) in contact with the plate line conductor layer SG2. In addition, in plan view, the gate insulating layer 13bb includes a gate insulating layer portion 13bb1 (an example of a "seventh gate insulating layer portion" in the claims) in contact with the word line conductive layer WL3 and a gate insulating layer portion 13bb2 (an example of an "eighth gate insulating layer portion" in the claims) in contact with the shield line conductive layer PL2. The fourth gate insulating layer portion 13ab2 and the gate insulating layer portion 13ba2 are connected to surround the shield line conductive layer SG2. + The layers 11aa and 11db are connected to the first source line SL1, and + The layers 11ba and 11da are connected to the second source line SL2. + The layers 11ab and 11bb are connected to the first bit line BL1, and + The layers 11cb and 11db are connected to the second bit line BL2.

[0033] The gate insulating layers in contact with the word line conductive layers WL1-WL4 and electrostatic shield conductive layers SG1-SG3, SG1a, and SG3a may be made of different materials and have different thicknesses from the gate insulating layers in contact with the plate line conductive layers PL1 and PL2 and shield line conductive layer SG2. Furthermore, each may be formed from multiple conductive material layers. This also applies to other embodiments.

[0034] 1B , the gate insulating layers 13aa, 13ab, 13ba, and 13bb in contact with the plate line conductive layers PL1 and PL2 and the shield line conductive layer SG2 may be removed, and gate insulating layers surrounding the plate line conductive layers PL1 and PL2 and the shield line conductive layer SG2 may be formed. To improve insulation between adjacent conductive layers, the thickness of this gate insulating layer may be greater than that of the gate insulating layers 13aa, 13ab, 13ba, and 13bb. For example, the thickness of the gate insulating layer portions 13ab2 and 13bb2 surrounding and connected to the shield line conductive layer SG2 may be greater than that of the gate insulating layer portions 13aa1, 13aa2, 13ab1, 13ba1, and 13bb1. Furthermore, the material of this gate insulating layer may be different from that of the gate insulating layers 13aa, 13ab, 13ba, and 13bb. In this way, for example, the capacitance per unit area of ​​the gate insulating layer portions 13ab2 and 13bb2 that surround and are connected to the shield conductor layer SG2 may be made smaller than the capacitance per unit area of ​​the gate insulating layer portions 13aa1, 13aa2, 13ab1, 13ba1, and 13bb1, as in the other embodiments.

[0035] Alternatively, the plate line conductive layers PL1, PL2 and the shield line conductive layer SG2 may be surrounded by a gate insulating material layer of the same thickness. This thickness may be made larger than the thickness of the gate insulating layer in contact with the word line conductive layers WL1-WL4 and the electrostatic shield conductive layers SG1-SG3, SG1a, and SG3a to increase the insulation between the word line conductive layers WL1-WL4 and the electrostatic shield conductive layers SG1-SG3, SG1a, and SG3a and the plate line conductive layers PL1, PL2 and the shield line conductive layer SG2.

[0036] The first embodiment has the following features. (1) As shown in Figures 1A and 1B, shield line conductor layers SG1, SG2, SG3, SG1a, and SG3a are located between the word line conductor layer WL1, plate conductor layer PL1, and word line conductor layer WL2, which are the driving conductor layers for the memory cells in the channel semiconductor layers 10a1 and 10b1, and the word line conductor layer WL3, plate conductor layer PL2, and word line conductor layer WL4, which are the driving conductor layers for the memory cells in the channel semiconductor layers 10a2 and 10b2. For example, when a pulse voltage is applied to the word line conductor layers WL1 and WL2 and the plate line conductor layer PL1 to perform a pulse driving operation such as memory write or read in the channel semiconductor layers 10a1 and 10b1, the electrostatic shielding effect of the shield line conductor layers SG1, SG1a, SG2, SG3, and SG3a suppresses voltage fluctuations in the adjacent channel semiconductor layers 10b1 and 10b2. This ensures stable memory operation and improves the characteristics of this memory device. (2) In this embodiment, a three-gate dynamic flash memory cell has been described, which is configured with three rows of gate conductor layers, namely, gate conductor layers WL1, SG1, and SG1a, gate conductor layers PL1, PL2, and PL3, and gate conductor layers WL2, SG3, SG3a, and WL4, on both sides of the channel semiconductor layers 10a1, 10a2, 10b1, and 10b2. In contrast, the present invention can also be applied to a two-gate dynamic flash memory cell, which does not have gate conductor layers WL2, SG3, SG3a, and WL4, and is configured with two rows of gate conductor layers, namely, gate conductor layers WL1, SG1, and SG1a, and gate conductor layers PL1, PL2, and PL3, on both sides of the channel semiconductor layers 10a1, 10a2, 10b1, and 10b2. When pulse drive operations such as memory write and read are performed, voltage fluctuations in the adjacent channel semiconductor layers 10b1 and 10b2 are suppressed due to the electrostatic shielding effect of the shield conductor layers SG1, SG1a, SG2, SG3, and SG3a. This allows stable memory operation and leads to improved characteristics of the memory element (details will be explained using FIG. 3). (3) A voltage may be applied to the shield conductor layers SG1-SG3, SG1a, and SG3a to cause the signal holes or electrons in the channel semiconductor layers 10a1, 10a2, 10b1, and 10b2 to accumulate on the shield conductor layers SG1-SG3, SG1a, and SG3a. This allows the shield conductor layers SG1-SG3, SG1a, and SG3a to function as both the electrostatic shielding effect described above and the backgate effect of accumulating the signal holes or electrons on the shield conductor layers SG1-SG3, SG1a, and SG3a during the signal charge retention period. This also applies to other embodiments. This ensures stable memory operation and improves the characteristics of the memory element.

[0037] (Second embodiment) 2 shows a schematic three-dimensional diagram of a second embodiment of the present invention in which dynamic flash memory cells are arranged in two columns and two rows in the horizontal and vertical directions. In an actual dynamic flash memory, many memory cells are arranged in the horizontal and vertical directions.

[0038] 2, the shield line conductive layer SG1 in FIG. 1 becomes the word line conductive layer WL1A, the shield line conductive layer SG3 becomes the word line conductive layer WL1A, the shield line conductive layer SG1a becomes the word line conductive layer WL3A, and the shield line conductive layer SG3 becomes the word line conductive layer WL4A. The two word line conductive layers WL1 and WL1A are connected, the two word line conductive layers WL2 and WL2A are connected, the word line conductive layers WL3A and WL3a are connected, and the word line conductive layers WL4A and WL4a are connected.

[0039] The second embodiment has the following features. (1) In this structure, a group of holes, which are signals, is mainly accumulated in the channel semiconductor layers 10a1, 10a2, 10b1, and 10b2 covered by the plate line conductor layers PL1 and PL2. The electrostatic shield conductor layer SG2 serves as an electrostatic shield layer between the plate line conductor layers PL1 and PL2. As a result, when a pulse voltage is applied to one of the plate line conductor layers PL1 or PL2 during a memory write or read operation, fluctuations in the channel voltage of the channel semiconductor layers 10a1 and 10b1 or the channel semiconductor layers 10a2 and 10b2 covered by the other plate line conductor layer PL1 or PL2 are suppressed. As a result, stable memory operation is achieved, and the characteristics of this memory element are improved. (2) In this structure, word line conductor layers WL1 and WL1A and word line conductor layers WL2 and WL2A are connected to both sides of the channel semiconductor layers 10a1 and 10b1. Similarly, word line conductor layers WL3A and WL3a and word line conductor layers WL4A and WL4a are connected to both sides of the channel semiconductor layers 10a2 and 10b2. A drive voltage is simultaneously applied to the word line conductor layers WL1 and WL1A and word line conductor layers WL2 and WL2A on both sides of the channel semiconductor layers 10a1 and 10b1, thereby controlling the channel voltage of the channel semiconductor layers 10a2 and 10b2. This allows for a larger read current when logical storage data is "1," which leads to faster memory operation.

[0040] (Third embodiment) 3 shows a schematic three-dimensional diagram of a three-gate dynamic flash memory cell according to a third embodiment of the present invention, in which two columns and two rows of two-gate dynamic flash memory cells are formed in the horizontal and vertical directions. In an actual dynamic flash memory, memory cells are arranged in large numbers in the horizontal plane and vertical direction.

[0041] As shown in FIG. 3, the dynamic flash memory cell structure of this embodiment does not include the word line conductor layers WL2 and WL4 and the shield line conductor layers SG3 and SG3a shown in FIG. 1A. The shield line conductor layers SG1, SG2, and SG1a are located between the word line conductor layer WL1 and plate conductor layer PL1, which are the driving conductor layers for the memory cells in the channel semiconductor layers 10a1 and 10b1, and the word line conductor layer WL3 and plate conductor layer PL2, which are the driving conductor layers for the memory cells in the channel semiconductor layers 10a2 and 10b2. When pulse voltages are applied to the word line conductor layers WL1 and WL3 and the plate line conductor layers PL1 and PL2 to perform memory write and read operations in the channel semiconductor layers 10a1 and 10b1, the electrostatic shielding effect of the shield line conductor layers SG1, SG1a, and SG2 suppresses voltage fluctuations in the adjacent channel semiconductor layers 10b1 and 10b2. This, like the structure shown in FIG. 1, ensures stable memory operation and improves the characteristics of this memory device.

[0042] This embodiment is also applicable to the embodiment of FIG. 2, just like the embodiment of FIG.

[0043] (Fourth embodiment) 4A to 4J show a method for manufacturing the three-gate dynamic flash memory shown in FIGS. 1A and 1B. (a) shows a plan view. (b) shows a vertical cross-sectional view taken along line X-X' in (a) (an example of the "first direction" in the claims). (c) shows a vertical cross-sectional view taken along line Y-Y' in (a) (an example of the "second direction" in the claims). This manufacturing method can also be applied to the manufacturing methods for the three-gate dynamic flash memory in FIG. 2 and the two-gate dynamic flash memory in FIG. 3.

[0044] As shown in FIG. 4A, semiconductor layers 21a, 21b, and 21c of, for example, SiGe and semiconductor layers 22a and 22b of, for example, Si are alternately formed from below away from a substrate 20 (an example of the "substrate" in the claims) in the vertical direction.

[0045] Next, as shown in FIG. 4B, after removing the semiconductor layers 21a, 21b, and 21c, insulating layers 24a, 24b, and 24c are embedded in the resulting spaces.

[0046] Next, as shown in FIG. 4C , a mask material layer (not shown) is formed on the upper surface in the vertical direction, and the insulating layers 24a, 24b, 24c and the semiconductor layers 25a, 25b are etched using this mask material layer as a mask to form insulating layers 29aa, 29ab (an example of the “first insulating layer” in the claims), 29ac (an example of the “first insulating layer” in the claims), semiconductor layers 28aa, 28ab (an example of the “first semiconductor layer” in the claims), and insulating layer 29aa. 9ba, 29bb (an example of a "first insulating layer" in the claims), 29bc (an example of a "first insulating layer" in the claims), and semiconductor layers 28ba, 28bb (an example of a "second semiconductor layer" in the claims), are formed, and semiconductor layers 28aa, 28ab and semiconductor layers 28ba, 28bb are formed, which are separated vertically from substrate 20, extend horizontally parallel to the X-X' line direction in a planar view, and have insulating layers 29aa, 29ab, 29ac above and below each in the vertical direction.

[0047] Next, as shown in FIG. 4D , gate insulating layers 30aa, 30ab, 30ba, and 30bb (an example of the “first gate insulating layer” in the claims) are formed in contact with the insulating layers 29aa, 29ab, and 29ac and the side surfaces of the semiconductor layers 28aa and 28ab, and with the insulating layers 29ba, 29bb, and 29bc and the side surfaces of the semiconductor layers 28ba and 28bb. Gate conductor layers 31aa, 31ab, 31ba, and 31bb (an example of the “first gate conductor layer” in the claims) are formed in contact with the gate insulating layers 30aa, 30ab, 30ba, and 30bb. Then, spaces formed on the outer side surfaces of the gate conductor layers 31aa, 31ab, 31ba, and 31bb are filled with insulating layer 33 (an example of the “second insulating layer” in the claims). As a result, the insulating layer 33 is formed by filling the gap between the gate conductive layer 31ab and the gate conductive layer 31ba that face each other.

[0048] Next, as shown in FIG. 4E, strip-shaped mask material layers 32a and 32b (an example of a "first mask material layer" in the claims) extending in the Y-Y' direction perpendicular to the X-X' direction are used as an etching mask to etch the insulating layer 33, the gate conductor layers 31aa, 31ab, 31ba, and 31bb, and the gate insulating layers 30aa, 30ab, 30ba, and 30bb, thereby forming vertically connected spaces 34a1, 34b1, and 34c1 (an example of a "first space" in the claims), spaces 34a2, 34b2, and 34c2 (an example of a "second space" in the claims), and spaces 34a3, 34b3, and 34c3. As a result, spaces 34a1, 34b1, 34c1 are formed at one end of the semiconductor layers 28aa, 28ab, and 28ba, 28bb of the strip-shaped mask material layer 32a, spaces 34a2, 34b2, 34c2 are formed at the other end of the semiconductor layers 28aa, 28ab, and 28ba, 28bb of the strip-shaped mask material layer 32a, spaces 34a2, 34b2, 34c2 are formed at one end of the semiconductor layers 28aa, 28ab, and 28ba, 28bb of the strip-shaped mask material layer 32b, and spaces 34a3, 34b3, 34c3 are formed at the other end of the semiconductor layers 28aa, 28ab, and 28ba, 28bb of the strip-shaped mask material layer 32a, 32b.

[0049] 4F, gate insulating layers 35a1-35a3, 35b1-35b3, and 35c1-35c3 (each an example of a "second gate insulating layer" in the claims) are formed on the inner side surfaces of spaces 34a1-34a3, 34b1-34b2, and 34c1-34c3 using, for example, ALD (Atomic Layered Deposition). Gate conductor layers 36a1-36a3, 36b1-36b3 (each an example of a "second gate conductor layer" in the claims) and 36c1-36c3 are then formed throughout the spaces surrounded by gate insulating layers 35a1-35a3, 35b1-35b3, and 35c1-35c3 (each an example of a "third space" in the claims).

[0050] Next, as shown in FIG. 4G, using a strip-shaped mask material layer (not shown) extending in the Y-Y' direction as an etching mask, the gate conductor layers 36a1-35a3, 36c1-36c3, gate insulating layers 35a1-35a3, 35c1-35c3, and semiconductor layers 28aa, 28ab, 28ba, and 28bb are etched to form conductor layers 36A1-36A3, 36C1-36C3, insulating layers 35A1-35A3, 35C1-35C3, and semiconductor layers 28Aa, 28Ab (an example of a "first channel semiconductor layer" in the claims), and 28Ba, 28Bb (an example of a "second channel semiconductor layer" in the claims). As a result, the semiconductor layers 28aa, 28ab and semiconductor layers 28ba, 28bb on the outer end sides of the gate conductor layers 36a1 to 35a3 and 36c1 to 36c3 in plan view are etched, and semiconductor layers 28Aa, 28Ab and semiconductor layers 28Ba, 28Bb are formed.

[0051] Next, as shown in FIG. 4H, the conductor layers 36A1 to 36A3 and 36C1 to 36C3 are removed.

[0052] Next, as shown in FIG. 4I, N is formed on both ends of the semiconductor layer 28Aa by, for example, selective epitaxial crystal growth. + The layers 37aa2 and 37ba2 are connected to both ends of the semiconductor layer 28Ab. + The layers 37ba2 and 37bb2 (which are examples of "impurity regions" in the claims) are formed on both ends of the semiconductor layer 28Ba by + The layers 37aa1 (not shown) and 37ab1 (not shown) are provided on both ends of the semiconductor layer 28Bb. + Then, layers 37ba1 and 37bb1 (which are examples of "impurity regions" in the claims) are formed. Then, N + The metal layer 38aa covering and connecting the layers 37aa1 and 37aa2 is formed by N + The metal layer 38ab covering and connected to the layers 37ba1 and 37ba2 is formed by N + A metal layer 38bb is formed to cover and connect the layers 37bb1 and 37bb2.

[0053] Next, an insulating layer (not shown) is formed to cover the metal layers 38aa, 38ab, 38ba, and 38bb. As shown in FIG. 4J, the insulating layer covering the metal layers 38aa and 38ab is removed, leaving the insulating layer 40 covering the metal layers 38ba and 38bb. A metal layer (not shown) is then filled in the vacant space. Then, metal layers 38A and 41a and metal layers 38B and 41b are formed, extending vertically and separated from each other.

[0054] 1A, metal layer 41b connects to source line SL1, metal layer 41a connects to source line SL2, metal layer 38ba connects to bit line BL2, metal layer 38bb connects to bit line BL1, gate conductor layers 31aba, 36b1, 31abb, 31abb, 31baa, and 31bab are shield line conductor layers SG1, SG2, SG1a, and SG3a, gate conductor layers 31aaa, 31aab, 31bab, and 31bbb are word line conductor layers WL1, WL2, WL3, and WL4, and gate conductor layers 36b1 and 36b3 are plate conductor layers PL1 and PL2.

[0055] The manufacturing method of the three-gate dynamic flash memory shown in this embodiment can also be applied to the manufacturing of a two-gate dynamic flash memory structure in which one of the two conductor layers 31aaa-31bab and conductor layers 31aab-30bbb on both sides of the conductor layers 36b1-36b3 is missing, as in Fig. 3. This is the same as in the other manufacturing method embodiments.

[0056] The manufacturing method of this embodiment has the following features. (1) In this dynamic flash memory, gate conductor layers 31aaa, 36b1, and 31aab aligned in the X-X' direction must be insulated from one another. This also applies to gate conductor layers 31aaa, 36b2, and 31abb, gate conductor layers 31baa, 36b2, and 31bab, and gate conductor layers 30bba, 36b3, and 30bbb. In this embodiment, as shown in FIG. 4F, gate insulating layers 35a1-35a3, 35b1-35b3, and 35c1-35c3 formed in contact with the inner side surfaces of spaces 34a1-34a3, 34b1-34b2, and 34c1-34c3 simultaneously function as gate insulating layers and as insulating layers between the gate conductor layers. 4E and 4F, since the large spaces 34a2, 34b2, and 34c2 are formed in a plan view, the plate line conductor layers 36b1 and 36b3 and the shield line conductor layer 36b2 can be formed using, for example, an ALD method, which has good manufacturing controllability, making it easier to manufacture the plate line conductor layers 36b1 and 36b3 and the shield line conductor layer 36b2 that are long in the vertical direction.

[0057] (2) As shown in FIGS. 4G and 4H, both ends of gate conductor layers 36b1-36b3 were etched to remove gate conductor layers 36a1-36a3 and 35c1-35c3. Then, as shown in FIG. 4I, N+ layers 37aa1, 37aa2, 37ab1, 37ab2, 37ba1, 37ba2, 37bb1, and 37bb2 and metal layers 38aa, 38ab, 38ba, and 38bb were formed on both ends of semiconductor layers 28Aa, 28Ab, 28Ba, and 28Bb. As a result, the remaining insulating layers 35A1-35A3 became insulating layers between N+ layers 37aa1, 37aa2, 37ab1, 37ab2, 37ba1, 37ba2, 37bb1, and 37bb2 and gate conductor layers 31aaa-31bbb. This eliminates the need to form a new insulating layer for insulating between the N+ layers 37aa1, 37aa2, 37ab1, 37ab2, 37ba1, 37ba2, 37bb1, 37bb2 and the gate conductor layers 31aaa to 31bbb.

[0058] (Fifth embodiment) 5A to 5D show a manufacturing method of the dynamic flash memory shown in FIGS. 1A and 1B. (a) shows a plan view. (b) is a vertical cross-sectional view taken along line X-X' in (a). (c) is a vertical cross-sectional view taken along line Y-Y' in (a).

[0059] 5A, mask material layers 45a and 45b are formed on the vertical top surfaces to form spaces 34a1-34a3, 34b1-34b3, and 34c1-34c3 in FIG. 4E. In plan view, mask material layers 45a and 45b extend in the direction of line YY'.

[0060] 5B, a mask material layer 46 (an example of a "second mask material layer" in the claims) is formed to cover the gap between the mask material layers 45a and 45b, at least partially overlap with the mask material layers 45a and 45b, and extend in the Y-Y' direction. Using the mask material layers 45a, 45b, and 46 as an etching mask, the metal layers 36a1-36a3 and 36c1-36c3 are removed. Then, insulating layers 47a1-47a3 and 47b1-47b3 are embedded in the resulting spaces.

[0061] Next, an insulating film (not shown) is deposited on the front surface, and then, as shown in Fig. 5C, the deposited insulating film is etched by, for example, RIE (Reactive Ion Etching) to form insulating layers 48a and 48b (an example of a "third mask material layer" in the claims) of equal width on the side surfaces of the mask material layers 45a and 45b opposite to the mask material layer 46. Then, using the mask material layers 45a, 45b, 46 and the insulating layers 48a, 48b as etching masks, the insulating layers 29aa-29ac, 29ba-29bc, 47a1-47a3, 47b1-47b3 and the semiconductor layers 28aa, 28ab, 28ba, 28bb are etched to form insulating layers 50a1-50a3, 50b1-50b3, 29Aa-29Ac, insulating layers 35A1-35A3, 35C1-35C3 (an example of the "third insulating layer" in the claims), and semiconductor layers 28Aa, 28Ab, 28Bb, 28Bb.

[0062] Next, the steps shown in FIGS. 4I and 4J are carried out to form two columns and two stages of dynamic flash memory cells.

[0063] The manufacturing method of this embodiment has the following features. The mask material layers 48a and 48b are formed in a self-aligned manner with respect to the mask material layers 45a and 45b. Forming in a self-aligned manner means that a predetermined structure does not have positional variations relative to a reference structure, such as those caused by mask misalignment during the photolithography process. This allows the gate conductor layers 31aaa-31bbb, 35b1-36b3, channel semiconductor layers 28Aa-28Bb, and insulating layers 50a1-50b3 to be formed in a self-aligned manner. This allows for high reproducibility in the manufacture of dynamic flash memories.

[0064] (Other embodiments) 1, the semiconductor layers 10a1, 10a2, 10b1, and 10b2 may be made of silicon (Si) or other semiconductor materials, which also applies to other embodiments of the present invention.

[0065] 1, the word line conductive layers WL1, WL2, WL3, and WL4 and the shield line conductive layers SG1 and SG3 may be formed from different material layers, and the plate line conductive layers PL1 and PL2 and the shield line conductive layer SG2 may be formed from different material layers. This is the same in other embodiments.

[0066] Also, in Figure 1, N + Dynamic flash memory operation is also possible in a structure in which the polarity of the conductivity types of layers 11aa-11db and P-type semiconductor layers 10a1-10b2 is reversed. In this case, the majority carriers are electrons. Therefore, electrons generated by impact ionization become signal charges in memory operation. This also applies to other embodiments of the present invention.

[0067] Furthermore, the present invention allows for various embodiments and modifications without departing from the broad spirit and scope of the present invention. Furthermore, each of the above-described embodiments is intended to illustrate one example of the present invention and does not limit the scope of the present invention. The above-described embodiments and modifications can be combined arbitrarily. Furthermore, even if some of the constituent elements of the above-described embodiments are omitted as necessary, they will still fall within the scope of the technical concept of the present invention. [Industrial Applicability]

[0068] According to the memory device using semiconductor elements and the manufacturing method thereof of the present invention, a dynamic flash memory, which is a high-density and high-performance memory device, can be obtained. [Explanation of symbols]

[0069] 1, 20 board 10a1, 10a2, 10b1, 10b2 channel semiconductor layer 11aa, 11ab, 11ba, 11bb, 11ca, 11cb, 37aa2, 37ab2, 37ba2, 37bb2 N + layer WL1, WL2, WL3, WL4, WL3a, WL4a, SL1WL1A, WL2A, WL3A, WL3A, WL4A Word line conductor layer PL1, PL2 Plate line conductor layers SG1, SG2, SG3 shielded wire conductor layers 13aa, 13ab, 13ba, 13bb, 31aa, 30ab, 30ba, 30bb, 30aaa, 30aab, 30aba, 30abb, 30baa, 30bab, 30baa, 30bab, 30bba, 30bbb, 35a1, 35a2, 35a3, 35b1, 35b2, 35b3, 35c1, 35c2, 35c3 Gate insulating layer 31aa, 31ba, 31ba, 31bb, 31aaa, 31aab, 31aba, 31aab, 31baa, 31bab, 31bba, 31bbb, 36a1, 36a2, 36a3, 36b1, 36b2, 36b3, 36c1, 36c2, 36c3 Gate conductor layer 12a1, 12a2, 12a3, 12b1, 12b2, 12b3, 24a, 24b, 24c, 29aa, 29ab, 29ac, 29ba, 29bb, 29Aa, 29Ab, 29Ac, 29Ba, 29Bb, 29Bc, 33, 35A1, 35A2, 35A3, 35C1, 35C2, 35C3, 40, 47a1, 47a2, 47a3, 47b1, 47b2, 47b3, 48a, 48b, 29Aa, 29Ab, 29Ac, 29Ba, 29Ab, 29Ac Insulating layer SL1 First source line SL2 Second source line BL1 First bit line BL2 Second bit line 21a, 21a, 21c, 22a, 22b, 25a, 25b, 28aa, 28ab, 28ba, 28bb, 28Aa, 38Ab, 38Ba, 38Bb semiconductor layers 32a, 32b Strip-shaped mask material layers 34a1, 34a2, 34a3, 34b1, 34b2, 34b3, 34c1, 34c2,34c3 space 36A1, 36A2, 36A3, 36C1, 36C2, 36C3 Conductor layers 38aa, 38ab, 38ba, 38bb, 38A, 38B, 41a, 41b metal layer 45a, 45b, 46 mask material layers

Claims

1. a first channel semiconductor layer and a second channel semiconductor layer extending in parallel in a horizontal direction and separated from the substrate in a vertical direction; a first impurity region and a second impurity region in contact with both ends of the first channel semiconductor layer; a third impurity region and a fourth impurity region in contact with both ends of the second channel semiconductor layer; a first gate insulating layer in contact with a vertical side surface of the first channel semiconductor layer on a side not facing the second channel semiconductor layer; a second gate insulating layer in contact with a vertical side surface of the first channel semiconductor layer facing the second channel semiconductor layer; a third gate insulating layer in contact with a vertical side surface of the second channel semiconductor layer facing the first channel semiconductor layer; a fourth gate insulating layer in contact with a vertical side surface of the second channel semiconductor layer on a side not facing the first channel semiconductor layer; a first gate conductor layer and a second gate conductor layer that are in contact with the first gate insulating layer and that are arranged along a side surface of the first channel semiconductor layer and in a direction from an end portion of the first channel semiconductor layer toward a center thereof; a third gate conductor layer and a fourth gate conductor layer that are in contact with the second gate insulating layer and that are arranged along a side surface of the first channel semiconductor layer and in a direction from an end portion of the first channel semiconductor layer toward a center thereof; a fifth gate conductor layer; and a sixth gate conductor layer and a seventh gate conductor layer that are in contact with the fourth gate insulating layer and are arranged along a side surface of the second channel semiconductor layer in a direction from an end of the second channel semiconductor layer toward a center thereof; the fourth gate conductive layer and the fifth gate conductive layer are in contact with the third gate insulating layer, and are aligned along a side surface of the second channel semiconductor layer and in a direction from an end portion of the second channel semiconductor layer toward a center thereof, the fourth gate conductor layer is an electrostatic shield conductor layer, and the second gate conductor layer and the seventh gate conductor layer are memory drive conductor layers; A memory device using a semiconductor element characterized by:

2. an eighth gate conductor layer in contact with the first gate insulating layer, along a side surface of the first channel semiconductor layer, and on the opposite side to the first gate conductor layer, and aligned with the second gate conductor layer; a ninth gate conductor layer in contact with the second gate insulating layer, along a side surface of the first channel semiconductor layer, and on the opposite side to the third gate conductor layer, and aligned with the fourth gate conductor layer; a tenth gate conductor layer in contact with the third gate insulating layer, along a side surface of the second channel semiconductor layer, and on the opposite side to the fifth gate conductor layer, and aligned with the fourth gate conductor layer; an eleventh gate conductor layer in contact with the fourth gate insulating layer, along a side surface of the second channel semiconductor layer, and on the opposite side to the sixth gate conductor layer, and aligned with the seventh gate conductor layer; the eighth and eleventh gate conductor layers are memory driving conductor layers; 2. A memory device using the semiconductor element according to claim 1.

3. In a plan view, the first gate insulating layer includes a first gate insulating layer portion in contact with the first gate conductor layer and a second gate insulating layer portion in contact with the second gate conductor layer; the second gate insulating layer includes, in a plan view, a third gate insulating layer portion in contact with the third gate conductor layer and a fourth gate insulating layer portion in contact with the fourth gate conductor layer; the third gate insulating layer includes, in a plan view, a fifth gate insulating layer portion in contact with the fifth gate conductor layer and a sixth gate insulating layer portion in contact with the fourth gate conductor layer; in a plan view, the fourth gate insulating layer includes a seventh gate insulating layer portion in contact with the sixth gate conductor layer and an eighth gate insulating layer portion in contact with the seventh gate conductor layer; the fourth gate insulating layer portion and the sixth gate insulating layer portion are connected to each other while surrounding the fourth gate conductor layer; 2. A memory device using the semiconductor element according to claim 1.

4. the thickness of the fourth gate insulating layer portion and the sixth gate insulating layer portion, which are connected to surround the fourth gate conductor layer, is greater than the thicknesses of the first to third gate insulating layer portions, the fifth gate insulating layer portion, the seventh gate insulating layer portion, and the eighth gate insulating layer portion; 4. A memory device using the semiconductor element according to claim 3.

5. a capacitance per unit area of ​​the fourth gate insulating layer portion and the sixth gate insulating layer portion, which are connected to surround the fourth gate conductor layer, is smaller than a capacitance per unit area of ​​the first to third gate insulating layer portions, the fifth gate insulating layer portion, the seventh gate insulating layer portion, and the eighth gate insulating layer portion; 4. A memory device using the semiconductor element according to claim 3.

6. the first and sixth gate conductor layers are word line conductor layers; The third and fifth gate conductor layers are electrostatic shield conductor layers.

2. A memory device using the semiconductor element according to claim 1.

7. the first gate conductor layer and the third gate conductor layer are connected, and the connected first gate conductor layer and the third gate conductor layer are word line conductor layers; the fifth gate conductor layer and the sixth gate conductor layer are connected, and the connected fifth gate conductor layer and the sixth gate conductor layer are word line conductor layers; 2. A memory device using the semiconductor element according to claim 1.

8. a voltage is applied to the electrostatic shield layer during a signal charge holding period, the voltage causing a group of holes or a group of electrons, which are signals, to accumulate on the electrostatic shield layer side of the first channel semiconductor layer and the second channel semiconductor layer; 2. A memory device using the semiconductor element according to claim 1.

9. forming a first semiconductor layer and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer being separated from the substrate in a vertical direction, extending horizontally in parallel to a first direction in a plan view, and each having a first insulating layer above and below the first semiconductor layer in the vertical direction; forming a first gate insulating layer in contact with each of the side surfaces of the first semiconductor layer and the first insulating layer on the same side, and each of the side surfaces of the second semiconductor layer and the first insulating layer on the same side; forming a first gate conductor layer in contact with the first gate insulating layer; forming a second insulating layer between the opposing first gate conductor layers; a step of etching the first gate insulating layer, the first gate conductor layer, and the second insulating layer using a first mask material layer as a mask, the first mask material layer extending in a second direction perpendicular to the first direction in a plan view, to form a first space on one end side of the first semiconductor layer and the second semiconductor layer of the first mask material layer, and a second space on the other end side of the first semiconductor layer and the second semiconductor layer of the first mask material layer; forming a second gate insulating layer in contact with an inner side surface of the second space and a second gate conductor layer filling the entire third space surrounded by the second gate insulating layer; a step of etching the first semiconductor layer and the second semiconductor layer located on end sides of the first gate conductor layer and the second gate conductor layer in a plan view to form a first channel semiconductor layer and a second channel semiconductor layer; forming impurity regions containing a large amount of donor or acceptor impurities at both ends of the first channel semiconductor layer and the second channel semiconductor layer, When the second gate conductor layer sandwiched between the first channel semiconductor layer and the second channel semiconductor layer is an electrostatic shield conductor layer, the second gate conductor layer on the end side of the first channel semiconductor layer and the second semiconductor layer is a driving conductor layer, and when the second gate conductor layer sandwiched between the first channel semiconductor layer and the second semiconductor layer is a driving conductor layer, the second gate conductor layer on the end side of the first channel semiconductor layer and the second semiconductor layer is an electrostatic shield conductor layer.

2. A method for manufacturing a memory device using a semiconductor element, comprising:

10. forming a fifth gate insulating layer simultaneously with the first gate insulating layer on each of the side surfaces of the first semiconductor layer and the first insulating layer on the same side and on each of the side surfaces of the second semiconductor layer and the first insulating layer on the same side where the first gate insulating layer is not formed; forming a third gate conductor layer in contact with the third gate insulating layer at the same time as forming the first gate conductor layer; 9. A method for manufacturing a memory device using the semiconductor element according to claim 8.

11. forming a second mask material layer at least partially overlapping the first mask material layer and extending in the second direction; forming a third mask material layer having an equal width on a side surface of the first and second mask material layers opposite to the second mask material layer; etching the first insulating layer and the first and second semiconductor layers using the first to third mask material layers as etching masks; 9. A method for manufacturing a memory device using the semiconductor element according to claim 8.

12. etching the first insulating layer and the first and second semiconductor layers using the first to third mask material layers as etching masks; a third insulating layer is formed below the third mask material layer in a plan view and between the first channel semiconductor layer and the second channel semiconductor layer; 11. A method for manufacturing a memory device using the semiconductor element according to claim 10.

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