Semiconductor device

Abstract

To provide a semiconductor device capable of improving trade-off of "recovery dV / dt max" and turn-on loss and reducing a gate total load amount Qg in a compatible manner.SOLUTION: A semiconductor device comprises: a semiconductor substrate; an emitter electrode which is formed on the semiconductor substrate; a drift layer of a first conductivity type which is formed in the semiconductor substrate; a base layer of a second conductivity type which is formed on the side of a top face of the semiconductor substrate; a collector electrode which is formed under the semiconductor substrate; and a double-stage dummy active trench including on an upper stage an upper-stage dummy part which is not connected to a gate electrode and is covered by an upper-stage insulator film and on a lower stage a lower-stage electrode which is connected to the gate electrode and covered by a lower-stage insulator film inside of a trench of the semiconductor substrate. A film thickness of the lower-stage insulator film in a lateral direction is larger than a film thickness of the upper-stage insulator film in the lateral direction, and a ratio of an area of the lower-stage insulator film with respect to an area of the lower-stage electrode in a cross-sectional view is 0.7 or more.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device whose conduction is controlled by a gate signal. [Background technology]

[0002] Conventionally, a semiconductor device has been disclosed that includes a gate electrode formed in an upper stage inside a trench and a shield electrode formed in a lower stage, with the gate electrode and the shield electrode separated by an insulating film (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2016 / 132552 Summary of the Invention [Problem to be solved by the invention]

[0004] The emitter of a p-side semiconductor device, whose collector is connected to the high-potential side (p-side) of the power supply, may be connected to the collector of an n-side semiconductor device, whose emitter is connected to the low-potential side (n-side) of the power supply. A load is connected to the connection point between the p-side and n-side semiconductor devices. One freewheeling diode is connected to each of the p-side and n-side semiconductor devices. The freewheeling diode connected in anti-parallel to the p-side semiconductor device is called the p-side diode, and the freewheeling diode connected in anti-parallel to the n-side semiconductor device is called the n-side diode.

[0005] When the p-side semiconductor device is turned on while a reflux current is flowing through the n-side diode, a recovery current flows through the n-side diode. For example, the recovery dV / dt of the n-side diode changes depending on the collector current of the p-side semiconductor device. Specifically, the recovery dV / dt of the n-side diode during turn-on loss at a low current of the p-side IGBT (Insulated Gate Bipolar Transistor) is larger than the recovery dV / dt at the rated current of the p-side IGBT. Here, "low current side" means that the collector current of the p-side semiconductor device is small, and "rated current side" means that the collector current of the p-side semiconductor device is large. When the collector current of the p-side semiconductor device is small, the recovery dV / dt of the n-side diode is large, whereas when the collector current of the p-side semiconductor device is large, the recovery dV / dt of the n-side diode is small.

[0006] Thus, when the recovery dV / dt of a diode has current dependency, the following problem occurs. That is, the gate resistance of a semiconductor device may be set so that a large recovery dV / dt is a predetermined value. For example, if the gate resistance is set so that the recovery dV / dt on the low current side is 20 kV / μs, the recovery dV / dt on the rated current side (for evaluating turn-on loss) will be about 10 kV / μs. As a result, the switching time of the semiconductor device becomes longer, and turn-on loss at turn-on increases. That is, when the recovery dV / dt of a diode has current dependency, turn-on loss increases.

[0007] Furthermore, recovery dV / dt becomes noise, but the noise is at its maximum (recovery dV / dt is at its maximum) during low-current switching. Here, the maximum value of recovery dV / dt is also called "recovery dV / dt max." When designing a semiconductor device, it is necessary to keep "recovery dV / dt max" below a certain level, and a common method for controlling this is to add gate resistance. However, increasing the gate resistance worsens turn-on loss. In this way, there is a trade-off between "recovery dV / dt max" and turn-on loss.

[0008] The present inventors have discovered that increasing the value (Cgc / Cge) obtained by dividing the gate electrode-collector capacitance (Cgc) of a semiconductor device by the gate electrode-emitter capacitance (Cge) of the semiconductor device is effective in suppressing the dependence of the recovery dV / dt of a freewheeling diode on the collector current of the semiconductor device. More specifically, increasing the Cgc of the semiconductor device can suppress the increase in recovery dV / dt at low currents. Furthermore, decreasing the Cge of the semiconductor device can increase the recovery dV / dt at high currents (rated currents). In this way, increasing the value of Cgc / Cge improves the current dependence of the recovery dV / dt, shortening the switching time and reducing turn-on loss. Furthermore, suppressing the increase in recovery dV / dt at low currents eliminates the need for a large gate resistor, improving the trade-off between "recovery dV / dt max" and turn-on loss.

[0009] In Patent Document 1, since the parasitic capacitance cannot be adjusted, there is a trade-off between the "recovery dV / dt max" and the turn-on loss. Therefore, there is a problem of increased turn-on loss as described above. Furthermore, Patent Document 1 does not mention anything about reducing the total gate charge Qg.

[0010] The present disclosure has been made to solve such problems, and aims to provide a semiconductor device that can achieve both an improvement in the trade-off between "recovery dV / dt max" and turn-on loss and a reduction in the total gate charge Qg. [Means for solving the problem]

[0011] In order to solve the above problems, the semiconductor device according to the present disclosure includes a semiconductor substrate, an emitter electrode formed on the semiconductor substrate, a drift layer of a first conductivity type formed in the semiconductor substrate, a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate, a collector electrode formed below the semiconductor substrate, and a two-stage dummy active trench inside the trench in the semiconductor substrate, the upper stage having an upper dummy portion not connected to a gate electrode and covered by an upper stage insulating film, and a lower stage electrode connected to the gate electrode and covered by a lower stage insulating film, the left-right thickness of the lower stage insulating film being thicker than the left-right thickness of the upper stage insulating film, and the ratio of the area of ​​the lower stage insulating film to the area of ​​the lower stage electrode in a cross-sectional view is 0.7 or more. [Effects of the Invention]

[0012] According to the present disclosure, it is possible to achieve both an improvement in the trade-off between "recovery dV / dt max" and turn-on loss and a reduction in the total gate charge Qg. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a graph showing the relationship between the area ratio of the lower insulating film and the lower electrode and the capacitance according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment. [Figure 5] FIG. 5 is a graph showing the relationship between the length from the upper end of the lower electrode to the lower end of the lower insulating film and Cge according to the third modification of the first embodiment. [Figure 6] FIG. 6 is a graph showing the relationship between the length from the upper end of the lower electrode to the lower end of the lower insulating film and Cgc / Cge according to the third modification of the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view of a semiconductor device according to a fifth modification of the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view of a semiconductor device according to a sixth modification of the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor device according to Modification 8 of the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view of a semiconductor device according to a ninth modification of the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view of a semiconductor device according to a ninth modification of the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to a tenth modification of the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view of a semiconductor device according to an eleventh modification of the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a cross-sectional view of a semiconductor device according to a first modification of the second embodiment. [Figure 17] FIG. 17 is a cross-sectional view of a semiconductor device according to the third embodiment. [Figure 18] FIG. 18 is a cross-sectional view of a semiconductor device according to a first modification of the third embodiment. [Figure 19] FIG. 19 is a cross-sectional view of a semiconductor device according to Modification 2 of Embodiment 3. In FIG. [Figure 20] FIG. 20 is a cross-sectional view of a semiconductor device according to Modification 3 of Embodiment 3. In FIG. [Figure 21] FIG. 21 is a cross-sectional view of a semiconductor device according to a fourth modification of the third embodiment. [Figure 22] FIG. 22 is a cross-sectional view of a semiconductor device according to a fifth modification of the third embodiment. [Figure 23] FIG. 23 is a cross-sectional view of a semiconductor device according to a sixth modification of the third embodiment. [Figure 24] FIG. 24 is a cross-sectional view of a semiconductor device according to a seventh modification of the third embodiment. [Figure 25]FIG. 25 is a cross-sectional view of a semiconductor device according to Modification 8 of Embodiment 3. In FIG. [Figure 26] FIG. 26 is a cross-sectional view of a semiconductor device according to Modification 1 of Modification 9 of Embodiment 3. In FIG. [Figure 27] FIG. 27 is a cross-sectional view of a semiconductor device according to a tenth modification of the third embodiment. [Figure 28] FIG. 28 is a cross-sectional view of a semiconductor device according to Modification 11 of Embodiment 3. In FIG. [Figure 29] FIG. 29 is a cross-sectional view of a semiconductor device according to the fourth embodiment. [Figure 30] FIG. 30 is a cross-sectional view of a semiconductor device according to a first modification of the fourth embodiment. [Figure 31] FIG. 31 is a cross-sectional view of a semiconductor device according to another example of the first modification of the fourth embodiment. [Figure 32] FIG. 32 is a plan view of a contact pull-up portion of a semiconductor device according to a fifth embodiment. [Figure 33] FIG. 33 is a cross-sectional view taken along line AA in FIG. [Figure 34] FIG. 34 is a cross-sectional view taken along line AA in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, semiconductor devices according to embodiments will be described with reference to the drawings. Note that the same or corresponding components will be denoted by the same reference numerals, and repeated description may be omitted. In the following description, n and p indicate the conductivity type of a semiconductor, and in this disclosure, the first conductivity type will be referred to as n-type and the second conductivity type will be referred to as p-type. These conductivity types may be reversed.

[0015] <First Embodiment> Fig. 1 is a cross-sectional view of a semiconductor device according to embodiment 1. The semiconductor device shown in Fig. 1 constitutes an insulated gate bipolar transistor (IGBT).

[0016] As shown in FIG. 1, a two-stage dummy active trench D / A is provided in a semiconductor substrate. Inside the trench of the semiconductor substrate, the two-stage dummy active trench D / A has, at its upper stage, an upper dummy portion 6 that is not connected to a gate electrode (not shown), and at its lower stage, a lower electrode 7 that is connected to the gate electrode. The upper dummy portion 6 is covered with an upper insulating film 8, and the lower electrode 7 is covered with a lower insulating film 10. The two-stage dummy active trench D / A has a boundary insulating film 9 between the upper dummy portion 6 and the lower electrode 7, and the upper dummy portion 6 and the lower electrode 7 are electrically isolated from each other via the boundary insulating film 9. The boundary insulating film 9 faces a drift layer 11. Note that the term "trench" refers to a hole provided in a semiconductor substrate or a structure formed in the hole.

[0017] In FIG. 1, the semiconductor substrate extends from the contact layer 3 to the collector layer 13. In FIG. 1, the upper end of the contact layer 3 on the paper surface is called the first main surface of the semiconductor substrate, and the lower end of the collector layer 13 on the paper surface is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device. The first and second main surfaces are opposed to each other. The semiconductor device has an n-type drift layer 11 between the first and second main surfaces.

[0018] An n-type carrier accumulation layer 5 having a higher n-type impurity concentration than the drift layer 11 is provided on the first main surface side of the drift layer 11. The carrier accumulation layer 5 is provided between the base layer 4 and the drift layer 11. The carrier accumulation layer 5 and the drift layer 11 may be collectively referred to as the drift layer. Alternatively, the semiconductor device may be configured without the carrier accumulation layer 5 and with the drift layer 11 also provided in the region of the carrier accumulation layer 5 shown in FIG. 1 .

[0019] A p-type base layer 4 is provided on the first main surface side of the carrier accumulation layer 5. The base layer 4 is in contact with an upper insulating film 8 of the two-stage dummy active trench D / A.

[0020] A p-type contact layer 3 is provided on the first main surface side of the base layer 4. The contact layer 3 is a region with a higher p-type impurity concentration than the base layer 4, and when it is necessary to distinguish between the contact layer 3 and the base layer 4, they may be referred to individually. Furthermore, the contact layer 3 and the base layer 4 may collectively be referred to as a p-type base layer.

[0021] An interlayer insulating film 2 is provided on the upper dummy portion 6 of the two-stage dummy active trench D / A. An emitter electrode 1 is provided on the region of the first main surface of the semiconductor device where the interlayer insulating film 2 is not provided, and on the interlayer insulating film 2. Note that in FIG. 1, the emitter electrode 1 may be provided directly on the upper dummy portion 6 without providing the interlayer insulating film 2. When the interlayer insulating film 2 is provided on the upper dummy portion 6 as shown in FIG. 1, the emitter electrode 1 and the upper dummy portion 6 may be electrically connected in another cross section.

[0022] An n-type buffer layer 12 having a higher n-type impurity concentration than the drift layer 11 is provided on the second main surface side of the drift layer 11. The buffer layer 12 is provided to prevent a depletion layer extending from the base layer 4 toward the second main surface from punching through when the semiconductor device is in an off state. Note that the semiconductor device may be configured without the buffer layer 12, and with the drift layer 11 also provided in the buffer layer 12 shown in FIG. 1 . The buffer layer 12 and the drift layer 11 may be collectively referred to as the drift layer.

[0023] A p-type collector layer 13 is provided on the second major surface side of the buffer layer 12. That is, the collector layer 13 is provided between the drift layer 11 and the second major surface.

[0024] A collector electrode 14 is provided on the second main surface side of the collector layer 13. The collector electrode 14 is provided under the semiconductor substrate. The collector electrode 14 is in ohmic contact with the collector layer 13 and is electrically connected to the collector layer 13.

[0025] In the two-stage dummy active trench D / A, the film thickness in the left-right direction of the lower insulating film 10 is thicker than the film thickness in the left-right direction of the upper insulating film 8. In addition, in a cross-sectional view, the ratio of the area of ​​the lower insulating film 10 to the area of ​​the lower electrode 7 is 0.7 or more. Here, the left-right direction is the direction perpendicular to the depth direction of the two-stage dummy active trench D / A (the width direction of the two-stage dummy active trench D / A).

[0026] In the two-stage dummy active trench D / A, the thickness of the lower insulating film 10 in the vertical direction is preferably thicker than the thickness of the upper insulating film 8 in the horizontal direction, thereby efficiently reducing Qg. Furthermore, the thickness of the lower insulating film 10 in the vertical direction may be formed thicker than the thickness of the lower insulating film 10 in the horizontal direction.

[0027] 2 is a graph showing the relationship between the area ratio of the lower insulating film 10 and the lower electrode 7 and the capacitance. In FIG. 2, the vertical axis represents the reciprocal (capacitance) of the lower insulating film 10. The horizontal axis represents the area ratio of the lower insulating film 10 and the lower electrode 7. Furthermore, "0G" is the length from the upper end (end on the first main surface side) of the lower electrode 7 and the lower insulating film 10 to the lower end (end on the second main surface side) of the lower insulating film 10.

[0028] 2, it can be seen that the larger the area of ​​the lower insulating film 10 relative to the area of ​​the lower electrode 7 (the thicker the film thickness of the lower insulating film 10), the smaller the capacitance. In other words, the capacitance can be adjusted by changing the film thickness of the lower insulating film 10. In particular, when the area ratio of the lower insulating film 10 to the lower electrode 7 is 0.7 or more, the capacitance becomes smaller.

[0029] According to the first embodiment, the two-stage dummy active trench D / A has an upper dummy portion 6 and a lower electrode 7. Therefore, by increasing the value of Cgc / Cge, the current dependency of the recovery dV / dt is improved, the switching time is shortened, and the turn-on loss can be reduced. Furthermore, since the increase in the recovery dV / dt at low currents can be suppressed, a large gate resistor is not required, and the trade-off between the "recovery dV / dt max" and the turn-on loss can be improved. Furthermore, by setting the ratio of the area of ​​the lower insulating film 10 to the area of ​​the lower electrode 7 to be 0.7 or more in a cross-sectional view, the total gate charge Qg can be efficiently reduced.

[0030] <Variation 1> 1, the area of ​​the lower electrode 7 may be smaller than the area of ​​the upper dummy portion 6. With this configuration, Cgc becomes smaller, but the total gate charge Qg can be reduced more than in the first embodiment.

[0031] <Variation 2> FIG. 3 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment.

[0032] 3, in the semiconductor device according to the second modification, the area of ​​the lower electrode 7 is larger than the area of ​​the upper dummy portion 6 in a cross-sectional view. With this configuration, Cgc becomes larger, and the "recovery dV / dt max" can be reduced more than in the first embodiment.

[0033] <Variation 3> FIG. 4 is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment.

[0034] 4, in the semiconductor device according to the third modification, the vertical length 21 of the lower electrode 7 is longer than the vertical length 20 of the upper dummy portion 6. Here, the vertical direction refers to the depth direction of the two-stage dummy active trench D / A.

[0035] Figure 5 is a graph showing the relationship between the length from the top end of the lower electrode to the bottom end of the lower insulating film (0G length) and Cge. Figure 6 is a graph showing the relationship between the length from the top end of the lower electrode to the bottom end of the lower insulating film and Cgc / Cge. As shown in Figures 5 and 6, as the 0G length increases, Cge decreases and Cgc / Cge increases. Furthermore, as the 0G length increases, Cgc increases.

[0036] With this configuration, Cgc becomes larger, and the "recovery dV / dt max" can be reduced more than in the first embodiment.

[0037] <Variation 4> FIG. 7 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment.

[0038] 7, in the semiconductor device according to the fourth modification, the vertical length 21 of the lower electrode 7 is shorter than the vertical length 20 of the upper dummy portion 6. With this configuration, Cgc is reduced, but the total gate charge Qg can be reduced more than in the first embodiment.

[0039] <Variation 5> FIG. 8 is a cross-sectional view of a semiconductor device according to a fifth modification of the first embodiment.

[0040] 8, in the semiconductor device according to the fifth modification, the thickness 23 in the vertical direction of the boundary insulating film 9 is thicker than the thickness 22 in the horizontal direction of the upper insulating film 8. This configuration improves the insulation between the upper dummy portion 6 and the lower electrode 7, thereby contributing to improving the reliability of the semiconductor device.

[0041] <Variation 6> 9 is a cross-sectional view of a semiconductor device according to Modification 6 of Embodiment 1. In the semiconductor device according to Modification 6, the upper dummy portion is made of metal 30.

[0042] The metal 30 may be made of, for example, the same material as the emitter electrode 1. In this case, the metal 30 is provided as part of the emitter electrode 1. As shown in FIG. 9, a trench having the metal 30, which is an upper dummy portion, and the lower electrode 7 is called a two-stage metal active trench M / A.

[0043] The hole extraction property can be improved by forming the upper dummy portion from the metal 30. Therefore, the reverse bias safe operating area (RBSOA) can be improved.

[0044] <Variation 7> 1, the upper dummy section 6 may have a higher resistivity than the lower electrode 7. Alternatively, the upper dummy section 6 may have a lower resistivity than the lower electrode 7.

[0045] <Variation 8> 10 is a cross-sectional view of a semiconductor device according to Modification 8 of Embodiment 1. In the semiconductor device according to Modification 8, the upper dummy portion 31 is at a floating potential. As shown in FIG. 10, a trench having the upper dummy portion 31 at a floating potential and the lower electrode 7 is referred to as a two-stage floating active trench F / A.

[0046] By providing the upper dummy portion 31 at a floating potential, it is possible to reduce Cge generated between the active trench A (see FIG. 15) and the upper dummy portion 31 of the two-stage dummy active trench D / A. Therefore, it is possible to further increase the value of Cgc / Cge.

[0047] <Variation 9> 11 and 12 are cross-sectional views of a semiconductor device according to Modification 9 of Embodiment 1. As shown in Figs. 11 and 12, in the semiconductor device according to Modification 9, the metal 30 that is the upper dummy portion is in partial contact with the base layer 4. As shown in Fig. 12, the upper insulating film 8 may have a concave shape in cross-sectional view.

[0048] In the semiconductor device, holes are discharged from the second main surface through the collector layer 13, the drift layer 11, the carrier accumulation layer 5, the base layer 4, and the contact layer 3, and then discharged from the first main surface. By providing the metal 30 as shown in Figures 11 and 12, holes are discharged via the metal 30, which has low electrical resistance, and therefore hole extraction properties can be improved.

[0049] 12, by forming the upper insulating film 8 in a concave shape, it is possible to prevent the metal 30 from contacting the carrier accumulation layer 5. This allows the metal 30 to be provided at a deep position, which makes it possible to reduce the area of ​​the lower electrode 7 and enhance the effect of reducing the total gate charge Qg.

[0050] <Modification 10> 13 is a cross-sectional view of a semiconductor device according to Modification 10 of Embodiment 1. As shown in FIG. 13, in the semiconductor device according to Modification 10, boundary insulating film 9 faces base layer 4. The upper end of lower electrode 7 is located above the lower end of base layer 4.

[0051] 1, when the upper end position of the lower electrode 7 is lower than the lower end position of the base layer 4, a region where the lower electrode 7 and the drift layer 11 or the carrier accumulation layer 5 do not face each other in the left-right direction is formed above the lower electrode 7, and Cgc is not generated in that region. On the other hand, as shown in FIG. 13, by preventing the formation of a region where the lower electrode 7 and the drift layer 11 or the carrier accumulation layer 5 do not face each other in the left-right direction above the lower electrode 7, Cgc can be increased.

[0052] <Variation 11> 14 is a cross-sectional view of a semiconductor device according to Modification 11 of Embodiment 1. As shown in Fig. 14, the lower electrode 7 faces only the drift layer 11 in the left-right direction, with the lower insulating film 10 interposed therebetween. The upper end of the lower electrode 7 is located below the lower end of the carrier accumulation layer 5.

[0053] When holes injected from the second principal surface change the potential of the base layer 4 during turn-on, a displacement current flows from the base layer 4 to the lower electrode 7, causing oscillation of the gate potential and deteriorating the controllability of dV / dt. This phenomenon is particularly noticeable when the base layer 4 is floating and when the lower electrode 7 and the base layer 4 are close to each other. As shown in FIG. 14 , by separating the lower electrode 7 from the base layer 4, adverse effects such as gate oscillation can be suppressed.

[0054] The length of the lower electrode 7 in the vertical direction may be shorter than the length of the lower electrode 7 in the horizontal direction.

[0055] <Embodiment 2> In the second embodiment, a semiconductor device in which a two-stage dummy active trench D / A and an active trench A are provided adjacent to each other will be described.

[0056] Fig. 15 is a cross-sectional view of a semiconductor device according to embodiment 2. As shown in Fig. 15, the semiconductor device according to embodiment 2 includes a two-stage dummy active trench D / A and an active trench A. The two-stage dummy active trench D / A corresponds to the two-stage dummy active trench D / A shown in Fig. 1.

[0057] The active trench A has a gate insulating film 41 provided along the trench in the semiconductor substrate, and an active portion 40 provided in contact with the gate insulating film 41 and connected to the gate electrode.

[0058] The n-type source layers 15 are provided on both left and right sides of the active trench A in contact with the gate insulating films 41. The carrier accumulation layers 5 have a lower n-type impurity concentration than the source layers 15 and a higher n-type impurity concentration than the drift layer 11. Providing the carrier accumulation layers 5 can reduce current loss when a current flows.

[0059] <Variation 1> Fig. 16 is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 2. As shown in Fig. 16, the semiconductor device according to Modification 1 includes two-stage dummy active trenches D / A and two-stage active trenches A / A.

[0060] The two-stage active trench A / A has, inside a trench in a semiconductor substrate, an upper stage active portion 50 connected to a gate electrode at its upper stage, and a lower stage active portion 51 connected to the gate electrode at its lower stage. The upper stage active portion 50 is covered with an upper stage insulating film 52, and the lower stage active portion 51 is covered with a lower stage insulating film 54. A boundary insulating film 53 is provided between the upper stage active portion 50 and the lower stage active portion 51, and the upper stage active portion 50 and the lower stage active portion 51 are electrically isolated from each other via the boundary insulating film 53.

[0061] <Third Embodiment> 15, in the case of a trench arrangement in which an active trench A and an upper dummy portion 6 of a two-stage dummy active trench D / A are adjacent to each other, the upper dummy portion 6, which is at, for example, an emitter potential (not a gate potential), is arranged adjacent to the active trench A, which is at a gate potential, and therefore a coupling capacitance Cge occurs between the active trench A and the upper dummy portion 6. In the third embodiment, a description will be given of a reduction in the coupling capacitance Cge.

[0062] FIG. 17 is a cross-sectional view of a semiconductor device according to a third embodiment. As shown in FIG. 17, in the semiconductor device according to the third embodiment, two active trenches A are provided side by side, and two two-stage dummy active trenches D / As are provided side by side. The set of two active trenches A and the set of two two-stage dummy active trenches D / As are provided alternately. By bundling and arranging the active trenches A and the two-stage dummy active trenches D / As, the density at which the active trenches A and the two-stage dummy active trench D / A are adjacent to each other is reduced compared to when one active trench A and one two-stage dummy active trench D / A are provided alternately. Therefore, the coupling capacitance Cge between the active trench A and the two-stage dummy active trench D / A can be reduced while maintaining Cgc.

[0063] In the example of FIG. 17, two active trenches A and two two-stage dummy active trenches D / A are provided, but it is sufficient that at least two or more of at least one of the active trenches A and the two-stage dummy active trenches D / A are provided side by side.

[0064] <Variation 1> 18 is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 3. As shown in Fig. 18, the number of two-stage dummy active trenches D / A is greater than the number of active trenches A. The greater the number of two-stage dummy active trenches D / A, the greater the effect of reducing the coupling capacitance Cge.

[0065] <Variation 2> 19 is a cross-sectional view of a semiconductor device according to Modification 2 of Embodiment 3. As shown in FIG.

[0066] <Variation 3> 20 is a cross-sectional view of a semiconductor device according to Modification 3 of Embodiment 3. The semiconductor device according to Modification 3 includes two-stage dummy active trenches D / A, active trenches A, and dummy trenches D.

[0067] The dummy trench D has an insulating film 61 provided along the trench in the semiconductor substrate, and a dummy portion 60 that is provided in contact with the insulating film 61 and is not connected to the gate electrode. The dummy portion 60 is electrically connected to the emitter electrode 1, for example.

[0068] By changing the proportion of the dummy trenches D in the total trenches of the semiconductor device, it becomes possible to adjust the gate capacitance.

[0069] <Variation 4> 21 is a cross-sectional view of a semiconductor device according to Modification 4 of Embodiment 3. In the semiconductor device according to Modification 4, two two-stage dummy active trenches D / As are provided side by side. Note that two or more two-stage dummy active trenches D / As may be provided side by side.

[0070] By providing two or more two-stage dummy active trenches D / A side by side, it is possible to reduce Cge occurring between the lower electrode 7 and the dummy trench D. Therefore, it is possible to increase the value of Cgc / Cge.

[0071] <Variation 5> 22 is a cross-sectional view of a semiconductor device according to Modification 5 of Embodiment 3. In the semiconductor device according to Modification 5, two or more dummy trenches D are provided side by side. In addition, the two-stage dummy active trenches D / A and the active trenches A are provided side by side.

[0072] By arranging the two-stage dummy active trench D / A and the active trench A side by side and arranging the dummy trenches D side by side, it is possible to reduce Cge generated between the lower electrode 7 and the dummy trench D and Cge generated between the active trench A and the dummy trench D. Therefore, it is possible to increase the value of Cgc / Cge.

[0073] <Variation 6> 23 is a cross-sectional view of a semiconductor device according to Modification 6 of Embodiment 3. The semiconductor device according to Modification 6 includes a two-stage dummy active trench D / A, an active trench A, and a two-stage floating active trench F / A.

[0074] The two-stage floating active trench F / A has, inside a trench of a semiconductor substrate, an upper stage dummy portion 31 that is at a floating potential and covered with an upper stage insulating film 8, and a lower stage electrode 7 that is connected to a gate electrode and covered with a lower stage insulating film 10, in the lower stage.

[0075] With this configuration, it is possible to reduce the coupling capacitance Cge generated between the active trench A and the upper dummy portion 6 of the two-stage dummy active trench D / A. Therefore, it is possible to increase the value of Cgc / Cge.

[0076] <Variation 7> 24 is a cross-sectional view of a semiconductor device according to Modification 7 of Embodiment 3. In the semiconductor device according to Modification 7, the distance (Lpad / a) between two or more adjacent two-stage dummy active trenches D / A and two or more adjacent active trenches A is larger than the distance (Lpd / a) between two adjacent two-stage dummy active trenches D / A and is also larger than the distance (Lpa) between two adjacent active trenches A.

[0077] By increasing the distance (Lpad / a) between two or more adjacent two-stage dummy active trenches D / A and two or more adjacent active trenches A, it is possible to reduce the coupling capacitance Cge generated between the active trench A and the upper dummy portion 6 of the two-stage dummy active trench D / A. Therefore, it is possible to increase the value of Cgc / Cge.

[0078] <Variation 8> FIG. 25 is a cross-sectional view of a semiconductor device according to Modification 8 of Embodiment 3. As shown in FIG. 25, in the semiconductor device according to Modification 8, two two-step active trenches A / A are provided side by side, and two two-step dummy active trenches D / A are provided side by side. The set of two two-step active trenches A / A and the set of two two-step dummy active trenches D / A are provided alternately. By bundling and arranging the two-step active trenches A / A and the two-step dummy active trenches D / A, the density at which the two-step active trenches A / A and the two-step dummy active trench D / A are adjacent to each other is reduced compared to the case where one two-step active trench A / A and one two-step dummy active trench D / A are provided alternately. Therefore, the coupling capacitance Cge between the two-step active trench A / A and the two-step dummy active trench D / A can be reduced while maintaining Cgc.

[0079] In the example of FIG. 25, two two-stage active trenches A / A and two two-stage dummy active trenches D / A are provided, but it is sufficient if two or more of at least one of the two-stage active trenches A / A and the two-stage dummy active trenches D / A are provided side by side.

[0080] <Variation 9> 26 is a cross-sectional view of a semiconductor device according to Modification 9 of Embodiment 3. As shown in Fig. 26, the number of two-stage dummy active trenches D / A is greater than the number of two-stage active trenches A / A. The greater the number of two-stage dummy active trenches D / A, the greater the effect of reducing the coupling capacitance Cge.

[0081] <Modification 10> Fig. 27 is a cross-sectional view of a semiconductor device according to Modification 10 of Embodiment 3. As shown in Fig. 27, the number of two-stage dummy active trenches D / A may be less than the number of two-stage active trenches A / A.

[0082] <Variation 11> 28 is a cross-sectional view of a semiconductor device according to Modification 11 of Embodiment 3. In the semiconductor device according to Modification 11, the interval (Lpad / a) between two or more adjacent two-step dummy active trenches D / A and two or more adjacent two-step active trenches A / A is larger than the interval (Lpd / a) between two adjacent two-step dummy active trenches D / A and is also larger than the interval (Lpa) between two adjacent two-step active trenches A / A.

[0083] By increasing the interval (Lpad / a) between two or more two-stage dummy active trenches D / A arranged side by side and two or more two-stage active trenches A / A arranged side by side, it is possible to reduce the coupling capacitance Cge generated between the two-stage active trenches A / A and the upper dummy portion 6 of the two-stage dummy active trench D / A. Therefore, it is possible to increase the value of Cgc / Cge.

[0084] <Fourth Embodiment> Double gate drive has been proposed as a method for achieving both reduced on-resistance and reduced switching losses. Double gate drive is a technology that shortens the IGBT switching time and reduces switching losses by dividing the gate drive system into two systems and changing the drive timing of the two gates. Specifically, by turning off the gate of the first system before turning it off and closing the channel, the carriers in the drift layer are reduced before being cut off. This makes it possible to achieve both reduced on-resistance and reduced switching losses.

[0085] 29 is a cross-sectional view of a semiconductor device according to embodiment 4. The gate electrode includes a first gate electrode G and a second gate electrode 2G that is separate from the first gate electrode G. The active portion 40 of the active trench A is connected to the first gate electrode G, and the lower electrode 7 of the two-stage dummy active trench D / A is connected to the second gate electrode 2G.

[0086] <Variation 1> 30 is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 4. The gate electrodes include a first gate electrode G and a second gate electrode 2G that is separate from the first gate electrode G. The first gate electrode G and the second gate electrode 2G are connected to a gate drive circuit 70. The active trench A includes a first active trench A1 and a second active trench A2. The active portion 40 of the first active trench A1 is connected to the first gate electrode G. The active portion 40 of the second active trench A2 and the lower electrode 7 of the two-stage dummy active trench D / A are connected to the second gate electrode 2G.

[0087] 31 is a cross-sectional view of a semiconductor device according to another example of Modification 1 of Embodiment 4. The two-stage active trench A / A includes a two-stage active trench A1 / A1 and a two-stage active trench A2 / A2. The upper active portion 50 of the two-stage active trench A1 / A1 is connected to a first gate electrode G. The lower active portion 51 of the two-stage active trench A1 / A1, the upper active portion 50 of the two-stage active trench A2 / A2, the lower active portion 51 of the two-stage active trench A2 / A2, and the lower electrode 7 of the two-stage dummy active trench D / A are connected to a second gate electrode 2G.

[0088] By turning off the second gate electrode 2G before turning off the semiconductor device, it is possible to reduce Cgc in the lower active portions 51 of the two-step active trenches A1 / A1 and A2 / A2 and the lower electrode 7 of the two-step dummy active trench D / A. Furthermore, by connecting the upper active portion 50 and lower active portion 51 of the two-step active trench A2 / A2 to the second gate electrode 2G, it is possible to close the lower active portion 51 of the two-step active trench A1 / A1, the upper active portion 50 of the two-step active trench A2 / A2, the lower active portion 51 of the two-step active trench A2 / A2, and the lower electrode 7 of the two-step dummy active trench D / A, which are connected to the second gate electrode 2G, before turning off the channel of the upper active portion 50 of the two-step active trench A1 / A1 connected to the first gate electrode G. This makes it possible to reduce carriers in the drift layer 11 and turn-off loss.

[0089] <Fifth Embodiment> FIG. 32 is a plan view of the contact pull-up portion, showing an end structure provided to connect the lower electrode 7 in the two-stage dummy active trench D / A to the gate liner 72 (see FIGS. 33 and 34) and to connect the upper dummy portion 6 to the emitter electrode 1. In FIG. 32, a p-type well layer 71 is provided to cover the trench end. By providing the well layer 71, the electric field can be alleviated, and deterioration of the oxide film can be further suppressed. Note that the well layer 71 does not necessarily have to be provided.

[0090] Fig. 33 is a cross-sectional view taken along line AA in Fig. 32, showing the end structure of the two-stage dummy active trench D / A. In Fig. 33, as an example, the film thickness of lower insulating film 10 that covers lower electrode 7 and separates lower electrode 7 from drift layer 11 and well layer 71 may be thicker than the film thickness of boundary insulating film 9 that separates upper dummy portion 6 and lower electrode 7. Such a configuration improves the insulation between lower electrode 7 and drift layer 11 and well layer 71, thereby contributing to improving the reliability of the semiconductor device.

[0091] 33, as another example, the thickness of boundary insulating film 9 separating upper dummy portion 6 and lower electrode 7 may be made thicker than the thickness of lower insulating film 10 separating lower electrode 7 from drift layer 11 and well layer 71. Such a configuration improves the insulation between upper dummy portion 6 and lower electrode 7, thereby contributing to improving the reliability of the semiconductor device.

[0092] Fig. 34 is a cross-sectional view taken along line AA in Fig. 32, showing the end structure of the two-stage dummy active trench D / A. In Fig. 34, as an example, the horizontal width 7X at the location where the lower electrode 7 and the upper dummy portion 6 are aligned in the horizontal direction (left-right direction) may be longer than the vertical height 7Y of the lower electrode 7 below the upper dummy portion 6. With this configuration, a large contact connection portion can be ensured, thereby relaxing the dimensional tolerance of the contact.

[0093] 34, as another example, the horizontal width 7X at the location where the lower electrode 7 and the upper dummy portion 6 are aligned in the horizontal direction (left-right direction) may be shorter than the vertical height 7Y of the lower electrode 7 located below the upper dummy portion 6. With this configuration, the contact connection portion shrinks and the proportion of the contact connection portion in the chip surface area decreases, thereby increasing the effective area of ​​the cell.

[0094] <Variation 1> In FIG. 33, the thickness of the lower insulating film 10 separating the lower electrode 7 from the drift layer 11 and well layer 71 is such that the thickness 10b in the left-right direction is greater than the thickness 10a in the up-down direction.

[0095] Due to the shape of the trench, the electric field tends to concentrate at the trench edge. The electric field is particularly strong at the trench sidewalls adjacent to the semiconductor layer, compared to the trench bottom. This is because there are no adjacent trenches at the trench edge, preventing the trench from providing an electric field shielding effect. The electric field concentration causes avalanche, which generates holes that are injected into the oxide film, resulting in oxide film degradation. As in this first modification, by making the horizontal film thickness 10b of the lower insulating film 10 thicker than the vertical film thickness 10a, it is possible to suppress oxide film degradation at the trench side where the electric field concentrates. The horizontal film thickness 10b should be at least 1.1 times, preferably 1.2 times, and more preferably 1.5 times, the vertical film thickness 10a. This configuration further suppresses oxide film degradation.

[0096] Within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate.

[0097] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0098] (Appendix 1) a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a second conductivity type base layer formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; a two-stage dummy active trench inside the trench of the semiconductor substrate, the two-stage dummy trench having an upper stage dummy portion not connected to a gate electrode and covered with an upper stage insulating film, and a lower stage electrode connected to the gate electrode and covered with a lower stage insulating film; Equipped with the thickness of the lower insulating film in the left-right direction is thicker than the thickness of the upper insulating film in the left-right direction, A semiconductor device, wherein in a cross-sectional view, the ratio of the area of ​​the lower insulating film to the area of ​​the lower electrode is 0.7 or more. (Appendix 2) 2. The semiconductor device according to claim 1, wherein the lower insulating film has a thickness in the vertical direction that is greater than the thickness of the upper insulating film in the horizontal direction. (Appendix 3) 3. The semiconductor device according to claim 2, wherein the lower insulating film has a thickness in a vertical direction that is greater than a thickness in a horizontal direction of the lower insulating film. (Appendix 4) 2. The semiconductor device according to claim 1, wherein, in a cross-sectional view, an area of ​​the lower electrode is smaller than an area of ​​the upper dummy portion. (Appendix 5) 2. The semiconductor device according to claim 1, wherein, in a cross-sectional view, the area of ​​the lower electrode is larger than the area of ​​the upper dummy portion. (Appendix 6) 6. The semiconductor device according to claim 1, wherein the lower electrode has a vertical length longer than the upper dummy portion. (Appendix 7) 6. The semiconductor device according to claim 1, wherein the lower electrode has a vertical length shorter than the vertical length of the upper dummy portion. (Appendix 8) the two-stage dummy active trench has a boundary insulating film between the upper stage dummy portion and the lower stage electrode, 8. The semiconductor device according to claim 1, wherein the boundary insulating film has a thickness in the vertical direction that is greater than the thickness of the upper insulating film in the horizontal direction. (Appendix 9) 9. The semiconductor device according to claim 1, wherein the upper dummy portion is made of metal. (Appendix 10) 10. The semiconductor device according to claim 1, wherein the upper dummy portion has a higher resistivity than the lower electrode. (Appendix 11) 10. The semiconductor device according to claim 1, wherein the upper dummy portion has a lower resistivity than the lower electrode. (Appendix 12) 9. The semiconductor device according to claim 1, wherein the upper dummy section is at a floating potential. (Appendix 13) 10. The semiconductor device according to claim 9, wherein the upper dummy portion is in contact with the base layer. (Appendix 14) 14. The semiconductor device according to claim 13, wherein the upper insulating film has a concave shape in cross section. (Appendix 15) 15. The semiconductor device according to claim 1, wherein the lower electrode faces the base layer and the drift layer in the left-right direction with the lower insulating film interposed therebetween. (Appendix 16) 15. The semiconductor device according to claim 1, wherein the lower electrode faces only the drift layer in the left-right direction, with the lower insulating film interposed therebetween. (Appendix 17) 17. The semiconductor device according to any one of claims 1 to 16, wherein the length of the lower electrode in the up-down direction is shorter than the length of the lower electrode in the left-right direction. (Appendix 18) 18. The semiconductor device according to any one of claims 1 to 17, further comprising a carrier accumulation layer of the first conductivity type between the base layer and the drift layer. (Appendix 19) 19. The semiconductor device according to any one of appendices 1 to 18, further comprising an active trench having a gate insulating film provided along the trench in the semiconductor substrate and an active portion provided in contact with the gate insulating film and connected to the gate electrode. (Appendix 20) 20. The semiconductor device according to any one of appendices 1 to 19, further comprising a two-stage active trench having a gate insulating film provided along the trench in the semiconductor substrate, and an upper active portion and a lower active portion provided in contact with the gate insulating film, connected to the gate electrode, and separated by a boundary insulating film. (Appendix 21) 20. The semiconductor device according to claim 19, wherein at least two of the two-stage dummy active trenches and the active trenches are provided side by side. (Appendix 22) 22. The semiconductor device according to claim 21, wherein the number of the two-stage dummy active trenches is greater than the number of the active trenches. (Appendix 23) 22. The semiconductor device according to claim 21, wherein the number of the two-stage dummy active trenches is smaller than the number of the active trenches. (Appendix 24) 20. The semiconductor device of claim 19, further comprising a dummy trench. (Appendix 25) 25. The semiconductor device according to claim 24, wherein two or more of the two-stage dummy active trenches are provided side by side. (Appendix 26) 25. The semiconductor device according to claim 24, wherein two or more of the dummy trenches are provided side by side. (Appendix 27) 27. The semiconductor device according to any one of appendices 1 to 26, further comprising a two-stage floating active trench inside the trench of the semiconductor substrate, the two-stage active trench having, in an upper stage, an upper dummy portion that is at a floating potential and covered with an upper stage insulating film, and in a lower stage, a lower stage electrode that is connected to the gate electrode and covered with a lower stage insulating film. (Appendix 28) 22. The semiconductor device according to claim 21, wherein the distance between the two-stage dummy active trench and the active trench is greater than the distance between two adjacent two-stage dummy active trenches and the distance between two adjacent active trenches. (Appendix 29) 21. The semiconductor device according to claim 20, wherein at least two of the two-stage dummy active trenches and the two-stage active trenches are provided side by side. (Appendix 30) 30. The semiconductor device according to claim 29, wherein the number of the two-stage dummy active trenches is greater than the number of the two-stage active trenches. (Appendix 31) 30. The semiconductor device according to claim 29, wherein the number of the two-stage dummy active trenches is smaller than the number of the two-stage active trenches. (Appendix 32) 30. The semiconductor device according to claim 29, wherein the distance between the two-step dummy active trench and the two-step active trench is greater than the distance between two adjacent two-step dummy active trenches and the distance between two adjacent two-step active trenches. (Appendix 33) the gate electrodes include a first gate electrode and a second gate electrode of a different system from the first gate electrode, 20. The semiconductor device of claim 19, wherein the active portion is connected to the first gate electrode, and the lower electrode is connected to the second gate electrode. (Appendix 34) the gate electrodes include a first gate electrode and a second gate electrode of a different system from the first gate electrode, the active trenches include a first active trench and a second active trench; 20. The semiconductor device of claim 19, wherein the active portion of the first active trench is connected to the first gate electrode, and the active portion of the second active trench and the lower electrode are connected to the second gate electrode. (Appendix 35) the gate electrodes include a first gate electrode and a second gate electrode of a different system from the first gate electrode, 21. The semiconductor device of claim 20, wherein the upper active section is connected to the first gate electrode, and the lower active section and the lower electrode are connected to the second gate electrode. (Appendix 36) 2. The semiconductor device according to claim 1, wherein in the contact pull-up portion of the two-stage dummy active trench, the thickness of the lower insulating film is thicker than the thickness of a boundary insulating film separating the upper dummy portion and the lower electrode. (Appendix 37) 2. The semiconductor device according to claim 1, wherein in the contact pull-up portion of the two-stage dummy active trench, the thickness of the lower insulating film is thinner than the thickness of a boundary insulating film separating the upper dummy portion and the lower electrode. (Appendix 38) The semiconductor device described in Appendix 1, wherein, in the contact pull-up portion of the two-stage dummy active trench, the left-right width of the lower electrode at the point where the lower electrode and the upper dummy portion are aligned in the left-right direction is longer than the up-down length of the lower electrode at the point where the lower electrode and the upper dummy portion are aligned in the up-down direction. (Appendix 39) The semiconductor device described in Appendix 1, wherein, in the contact pull-up portion of the two-stage dummy active trench, the left-right width of the lower electrode at a point where the lower electrode and the upper dummy portion are aligned in the left-right direction is shorter than the up-down length of the lower electrode at a point where the lower electrode and the upper dummy portion are aligned in the up-down direction. (Appendix 40) 2. The semiconductor device according to claim 1, wherein in the contact pull-up portion of the two-stage dummy active trench, the horizontal thickness of the lower insulating film at a location where the lower electrode and the upper dummy portion are aligned in the horizontal direction is thicker than the vertical thickness of the lower insulating film at a location where the lower electrode and the upper dummy portion are aligned in the vertical direction. [Explanation of symbols]

[0099] 1 emitter electrode, 2 interlayer insulating film, 3 contact layer, 4 base layer, 5 carrier accumulation layer, 6 upper dummy section, 7 lower electrode, 8 upper insulating film, 9 boundary insulating film, 10 lower insulating film, 11 drift layer, 12 buffer layer, 13 collector layer, 14 collector electrode, 15 source layer, 20 length, 21 length, 22 film thickness, 23 film thickness, 30 metal, 31 upper dummy section, 40 active section, 41 gate insulating film, 50 upper active section, 51 lower active section, 52 upper insulating film, 53 boundary insulating film, 54 lower insulating film, 60 dummy section, 61 insulating film, 70 gate drive circuit.

Claims

1. a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a second conductivity type base layer formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; a two-stage dummy active trench inside the trench of the semiconductor substrate, the two-stage dummy trench having an upper stage dummy portion not connected to a gate electrode and covered with an upper stage insulating film, and a lower stage electrode connected to the gate electrode and covered with a lower stage insulating film; Equipped with the thickness of the lower insulating film in the left-right direction is thicker than the thickness of the upper insulating film in the left-right direction, In a cross-sectional view, a ratio of an area of ​​the lower insulating film to an area of ​​the lower electrode is 0.7 or more.

2. 2. The semiconductor device according to claim 1, wherein the thickness of said lower insulating film in the vertical direction is greater than the thickness of said upper insulating film in the horizontal direction.

3. 3. The semiconductor device according to claim 2, wherein the thickness of said lower insulating film in the vertical direction is greater than the thickness of said lower insulating film in the horizontal direction.

4. 2. The semiconductor device according to claim 1, wherein an area of ​​said lower electrode is smaller than an area of ​​said upper dummy portion in a cross-sectional view.

5. The semiconductor device according to claim 1 , wherein an area of ​​said lower electrode is larger than an area of ​​said upper dummy portion in a cross-sectional view.

6. 2. The semiconductor device according to claim 1, wherein the lower electrode has a vertical length longer than the upper dummy portion.

7. 2. The semiconductor device according to claim 1, wherein the vertical length of said lower electrode is shorter than the vertical length of said upper dummy portion.

8. the two-stage dummy active trench has a boundary insulating film between the upper stage dummy portion and the lower stage electrode, 2. The semiconductor device according to claim 1, wherein the thickness of said boundary insulating film in the vertical direction is greater than the thickness of said upper insulating film in the horizontal direction.

9. 2. The semiconductor device according to claim 1, wherein said upper dummy portion is made of metal.

10. The semiconductor device according to claim 1 , wherein the upper dummy portion has a higher resistivity than the lower electrode.

11. The semiconductor device according to claim 1 , wherein the upper dummy portion has a lower resistivity than the lower electrode.

12. 2. The semiconductor device according to claim 1, wherein said upper dummy portion is at a floating potential.

13. The semiconductor device according to claim 9 , wherein the upper dummy portion is in contact with the base layer.

14. The semiconductor device according to claim 13 , wherein the upper insulating film has a concave shape in cross section.

15. The semiconductor device according to claim 1 , wherein the lower electrode faces the base layer and the drift layer in the left-right direction with the lower insulating film interposed therebetween.

16. The semiconductor device according to claim 1 , wherein the lower electrode faces only the drift layer in the left-right direction, with the lower insulating film interposed therebetween.

17. 2. The semiconductor device according to claim 1, wherein a vertical length of said lower electrode is shorter than a horizontal length of said lower electrode.

18. The semiconductor device according to claim 1 , further comprising a carrier accumulation layer of the first conductivity type between said base layer and said drift layer.

19. 2. The semiconductor device according to claim 1, further comprising an active trench having a gate insulating film provided along the trench in said semiconductor substrate, and an active portion provided in contact with said gate insulating film and connected to said gate electrode.

20. 2. The semiconductor device according to claim 1, further comprising: a gate insulating film provided along the trench in the semiconductor substrate; and a two-stage active trench having an upper stage active portion and a lower stage active portion provided in contact with the gate insulating film, connected to the gate electrode, and separated from each other by a boundary insulating film.

21. 20. The semiconductor device according to claim 19, wherein at least two of the two-stage dummy active trenches and the active trenches are provided side by side.

22. 22. The semiconductor device according to claim 21, wherein the number of the two-stage dummy active trenches is greater than the number of the active trenches.

23. 22. The semiconductor device according to claim 21, wherein the number of the two-stage dummy active trenches is smaller than the number of the active trenches.

24. The semiconductor device of claim 19 , further comprising a dummy trench.

25. The semiconductor device according to claim 24 , wherein two or more of the two-stage dummy active trenches are provided side by side.

26. 25. The semiconductor device according to claim 24, wherein two or more of the dummy trenches are provided side by side.

27. 2. The semiconductor device according to claim 1, further comprising, inside the trench of the semiconductor substrate, a two-stage floating active trench having, in an upper stage, an upper stage dummy portion at a floating potential and covered with an upper stage insulating film, and in a lower stage, a lower stage electrode connected to the gate electrode and covered with a lower stage insulating film.

28. 22. The semiconductor device according to claim 21, wherein the distance between the two-stage dummy active trench and the active trench is larger than the distance between two adjacent two-stage dummy active trenches and the distance between two adjacent two active trenches.

29. The semiconductor device according to claim 20 , wherein at least two of the two-stage dummy active trenches and the two-stage active trenches are provided side by side.

30. 30. The semiconductor device according to claim 29, wherein the number of said two-stage dummy active trenches is greater than the number of said two-stage active trenches.

31. 30. The semiconductor device according to claim 29, wherein the number of the two-stage dummy active trenches is smaller than the number of the two-stage active trenches.

32. 30. The semiconductor device according to claim 29, wherein a distance between the two-step dummy active trench and the two-step active trench is larger than a distance between two adjacent two two-step dummy active trenches and a distance between two adjacent two two-step active trenches.

33. the gate electrodes include a first gate electrode and a second gate electrode of a different system from the first gate electrode, 20. The semiconductor device according to claim 19, wherein said active section is connected to said first gate electrode, and said lower electrode is connected to said second gate electrode.

34. the gate electrodes include a first gate electrode and a second gate electrode of a different system from the first gate electrode, the active trenches include a first active trench and a second active trench; 20. The semiconductor device of claim 19, wherein the active portion of the first active trench is connected to the first gate electrode, and the active portion of the second active trench and the lower electrode are connected to the second gate electrode.

35. the gate electrodes include a first gate electrode and a second gate electrode of a different system from the first gate electrode, 21. The semiconductor device according to claim 20, wherein the upper active section is connected to the first gate electrode, and the lower active section and the lower electrode are connected to the second gate electrode.

36. 2. The semiconductor device according to claim 1, wherein in the contact pull-up portion of the two-stage dummy active trench, the film thickness of the lower insulating film is thicker than the film thickness of a boundary insulating film separating the upper dummy portion and the lower electrode.

37. 2. The semiconductor device according to claim 1, wherein in the contact pull-up portion of the two-stage dummy active trench, the film thickness of the lower insulating film is thinner than the film thickness of a boundary insulating film separating the upper dummy portion and the lower electrode.

38. 2. The semiconductor device according to claim 1, wherein in the contact pull-up portion of the two-stage dummy active trench, the horizontal width of the lower electrode at a point where the lower electrode and the upper dummy portion are aligned in the horizontal direction is longer than the vertical length of the lower electrode at a point where the lower electrode and the upper dummy portion are aligned in the vertical direction.

39. 2. The semiconductor device according to claim 1, wherein in the contact pull-up portion of the two-stage dummy active trench, the horizontal width of the lower electrode at a point where the lower electrode and the upper dummy portion are aligned in the horizontal direction is shorter than the vertical length of the lower electrode at a point where the lower electrode and the upper dummy portion are aligned in the vertical direction.

40. 2. The semiconductor device according to claim 1, wherein in the contact pull-up portion of the two-stage dummy active trench, the horizontal thickness of the lower insulating film at a location where the lower electrode and the upper dummy portion are aligned in the horizontal direction is thicker than the vertical thickness of the lower insulating film at a location where the lower electrode and the upper dummy portion are aligned in the vertical direction.

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