Imaging apparatus

Abstract

To provide an imaging apparatus that can be manufactured at a low cost with high imaging quality.SOLUTION: An imaging device includes a first transistor, a second transistor, a third transistor, a fourth transistor, a photodiode, and a capacitor. Each of the first to the fourth transistors includes a first gate electrode and a second gate electrode. The second gate electrode of each of the first to the fourth transistors and one of electrodes of the capacitor are electrically connected to an anode electrode of the photodiode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, Examples include devices, driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductors are widely used in transistors. However, oxide semiconductors are attracting attention as other materials.

[0005] For example, zinc oxide or In-Ga-Zn oxide is used as the oxide semiconductor. Techniques for producing a transistor have been disclosed (see Patent Documents 1 and 2).

[0006] In addition, Patent Document 3 discloses a pixel transistor using an oxide semiconductor transistor with extremely low off-state current. Used as part of the circuit, CMOS (Complementary Metal Oxide Semiconductor (Semiconductor) circuits can be fabricated using silicon-based transistors. An imaging device configured for road use is disclosed. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119711 Summary of the Invention [Problem to be solved by the invention]

[0008] Imaging devices are expected to be used in a variety of environments, so they are required to be used in low-light environments and in dynamic environments. Even when the subject is a human body, high image quality is required. There is a demand for an imaging device that can be manufactured at lower cost and is highly reliable while satisfying the above requirements. There are.

[0009] For example, in an imaging device that captures radiation images, transistors with less characteristic fluctuation due to radiation are used. It is hoped that it will be used.

[0010] Furthermore, the physical properties of the oxide semiconductor described above change when impurities such as hydrogen are mixed in. Therefore, a transistor using an oxide semiconductor and its surroundings are susceptible to hydrogen and other It is desirable to have a structure that is less susceptible to the inclusion of impurities.

[0011] Therefore, an object of one embodiment of the present invention is to provide an imaging device with high reliability. Another object is to provide a low-cost imaging device. Another object of the present invention is to provide an imaging device that can capture images under low illumination. One of the objectives is to provide an imaging device that can capture images with a wide dynamic range. One of the objects of the present invention is to provide an imaging device with high resolution. Another object is to provide an imaging device with a high degree of integration. Another object is to provide an imaging device that can be used in a wide temperature range. Another object is to provide an imaging device with low power consumption. It is an object of the present invention to provide a semiconductor device having a semiconductor device.

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0013] One embodiment of the present invention is a transistor formed using an oxide semiconductor and a photodiode. The present invention relates to an imaging device having a hologram.

[0014] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. an imaging device including a fourth transistor, a photodiode, and a capacitor, The first to fourth transistors each have a first gate electrode and a second gate electrode. The source electrode or the drain electrode of the first transistor is connected to the photodiode. the source electrode or the drain electrode of the first transistor. The other is electrically connected to the first gate electrode of the second transistor. One of the source electrode or drain electrode of the first transistor is connected to the source electrode or drain electrode of the third transistor. the source electrode or the drain electrode of the fourth transistor. One of the electrodes is electrically connected to the other of the source electrode or the drain electrode of the first transistor. One electrode of the capacitor is connected to the other of the source electrode and the drain electrode of the first transistor. The second gate electrodes of the first to fourth transistors are electrically connected to each other. The other electrode of the capacitance element is electrically connected to the anode electrode of the photodiode. The imaging device is characterized in that the anode electrode of the diode is electrically connected to the anode electrode of the diode.

[0015] The first to fourth transistors each include an oxide semiconductor layer containing In and Zn. and M (M is Al, Ti, Sn, Ga, Y, Zr, La, Ce, Nd or Hf). It is preferable that

[0016] Another embodiment of the present invention is an imaging device including a transistor, a photodiode, and a capacitor. The transistor includes a first electrode, a first insulating film in contact with the first electrode, and a first a first semiconductor layer in contact with the insulating film, a second electrode in contact with the first semiconductor layer, and a third electrode The photodiode has a fourth electrode, a fifth electrode, and a fourth electrode and a fifth electrode. a second semiconductor layer between the first and second insulating layers, the first semiconductor layer having a region in contact with the second insulating layer, The first electrode has a region in contact with the second insulating layer, and the third electrode has a region in contact with the second insulating layer. The second insulating layer has a region in contact with the third insulating layer, and the third insulating layer has a region in contact with the fourth insulating layer. the fourth insulating layer has a region in contact with the fourth electrode and a region overlapping with the first electrode; In the region, the third insulating layer has a region in contact with the fourth electrode, and the fifth electrode has a region in contact with the second electrode. The capacitor element is electrically connected to the third electrode, the second insulating layer, and the third The imaging device is characterized by including an insulating layer and a fourth electrode.

[0017] The photodiode includes a third semiconductor layer in contact with the fourth electrode and a second semiconductor layer in contact with the fifth electrode. The second semiconductor layer is in contact with the third semiconductor layer and the fourth semiconductor layer. The third semiconductor layer has a p-type conductivity, the fourth semiconductor layer has an n-type conductivity, and the fourth semiconductor layer has an n-type conductivity. The conductivity type of the semiconductor layer 2 can be i-type.

[0018] In the region where the photodiode overlaps with the first electrode layer, the fourth semiconductor layer is missing. The configuration may have an area where the

[0019] In addition, in the region overlapping with the first electrode layer, the photodiode is The fourth semiconductor layer may have a missing region.

[0020] In addition, in the region overlapping with the first electrode layer, the photodiode includes a second semiconductor layer, a first The third semiconductor layer and the fourth semiconductor layer may have a missing region. .

[0021] The first semiconductor layer has an oxide semiconductor layer, and the oxide semiconductor is In, Zn, and M (M is A It is preferred that the material contains at least one of the following elements: I, Ti, Sn, Ga, Y, Zr, La, Ce, Nd or Hf stomach. [Effects of the Invention]

[0022] According to one embodiment of the present invention, a highly reliable imaging device can be provided. Alternatively, an imaging device with a high aperture ratio can be provided. Alternatively, an imaging device capable of capturing images under low illumination can be provided. It is possible to provide an imaging device with a wide dynamic range. It is possible to provide an imaging device. Alternatively, it is possible to provide an imaging device with a high degree of integration. Alternatively, it is possible to provide an imaging device that can be used over a wide temperature range. It is possible to provide a low power consumption imaging device. A body device can be provided.

[0023] Note that the effects of one embodiment of the present invention are not limited to these. Depending on the circumstances, the effect may be different from those mentioned above. Alternatively, for example, one aspect of the present invention may be In some cases, these effects may not be present. [Brief explanation of the drawings]

[0024] [Figure 1] 1A and 1B are a cross-sectional view and a circuit diagram of a pixel of an imaging device. [Figure 2] FIG. 2 is a cross-sectional view of a pixel of the imaging device. [Figure 3] FIG. 2 is a cross-sectional view of a pixel of the imaging device. [Figure 4] FIG. 2 is a circuit diagram of a pixel of the imaging device. [Figure 5] FIG. 2 is a circuit diagram of a pixel of the imaging device. [Figure 6] FIG. 2 is a top view of a pixel of the imaging device. [Figure 7] FIG. 1 is a diagram illustrating an imaging apparatus. [Figure 8] FIG. 1 is a diagram illustrating a configuration of an imaging apparatus. [Figure 9] FIG. 2 is a diagram illustrating a drive circuit of the imaging device. [Figure 10] 1A and 1B are cross-sectional views of a pixel and an end portion of a photodiode of an imaging device. [Figure 11] 4 is a timing chart illustrating the operation of the pixel circuit. [Figure 12] FIG. 2 is a circuit diagram of a pixel of the imaging device. [Figure 13] FIG. 10 is a diagram for explaining an integrating circuit. [Figure 14] 4 is a timing chart illustrating the operations of the global shutter system and the rolling shutter system. [Figure 15] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 16] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 17] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 18] FIG. 1 is a top view illustrating a transistor. [Figure 19] 1A and 1B are cross-sectional views illustrating a transistor. [Figure 20] 1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0026] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0027] Here, X and Y represent, for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc. be.

[0028] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0029] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0030] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0031] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0032] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0033] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0034] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , and the second connection path is a transistor through a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. the third connection path does not have the second connection path, and the third connection path The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path; The second connection path has a connection path through a transistor, and (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third connection path is electrically connected to Y via Z2 by an electrical path of The fourth electrical path does not include the fourth connection path, and the fourth electrical path is a drain of a transistor. (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0035] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, and Z2 are devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, and the like.

[0036] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0037] (Embodiment 1) In this embodiment, a structure of an imaging device according to one embodiment of the present invention will be described with reference to drawings. FIG. 1A is a cross-sectional view of a pixel of an imaging device according to one embodiment of the present invention. ) illustrates a pixel circuit of an imaging device according to one embodiment of the present invention.

[0038] The pixel of the imaging device is made up of a transistor 301 and a transistor 302 provided on a substrate 300. 02, transistor 303 (not shown in FIG. 1A), transistor 304 (not shown in FIG. 1A) The transistor has a first gate electrode layer, a first gate insulating film, A bottom-gate transistor having a basic structure of a semiconductor layer, a source electrode layer, and a drain electrode layer. It is a pedestrian.

[0039] In addition, insulating layers 335, 336, and 337 are sandwiched on the transistor. A photodiode 320 is provided.

[0040] Photodiode 320 has a semiconductor layer sandwiched between conductive layers 325 and 326. The semiconductor layer includes a p-type semiconductor layer 321 in contact with the conductive layer 325 and a p-type semiconductor layer 322 in contact with the conductive layer 326. an n-type semiconductor layer 323 sandwiched between the p-type semiconductor layer 321 and the n-type semiconductor layer 323; The photodiode 320 includes a semiconductor layer 322. The conductive layer 325 is an anode electrode of the photodiode 320. The conductive layer 326 can function as a cathode electrode. do.

[0041] An insulating layer 338 is provided on the end of the photodiode 320 as a planarizing film, and a protective layer is provided on the top. An insulating layer 339 is provided as a protective film. 340 will be provided.

[0042] In FIG. 1, the conductive layer 326 and the source electrode layer or the drain electrode layer of the transistor 301 Although an example in which one of the layers is electrically connected via a conductive layer 334 is shown, this configuration is not For example, the conductive layer 326 and one of the source electrode layer and the drain electrode layer may be directly connected to each other. Alternatively, the conductive layer 326 and the source electrode may be electrically connected in a contacting manner. The drain electrode layer is electrically connected to the drain electrode layer through multiple conductive layers including the conductive layer 334. It may be done.

[0043] Note that the pixel of the imaging device of one embodiment of the present invention may include a part of each of the conductive layers, a part of the insulating layer, or A configuration may be adopted in which some elements such as transistors and capacitors are not provided. Other conductive layers, insulating layers, transistors, capacitive elements, etc. may also be provided. .

[0044] Here, the first gate electrode layer or semiconductor layer of the transistor and the photodiode 32 In the overlapping region, the insulating layer 336 contacts the conductive layer 325. By this, the insulating layer 335 and the insulating layer 336 are formed on the semiconductor layer of the transistor from the conductive layer 325. An electric field can be applied via 336, i.e., the conductive layer 325 is connected to the second gate electrode. The insulating layer 335 and the insulating layer 336 function as a second gate insulating film. can be done.

[0045] This can be achieved by partially removing the insulating layer 337 .

[0046] As shown in FIG. 10(A), the insulating layer 337 is formed thinly, that is, the insulating layer 336 When the insulating layer 337 is formed so that a part of the insulating layer 337 is exposed, the part of the insulating layer 337 is removed. There's no need.

[0047] In addition, in the imaging device of one embodiment of the present invention, a source electrode layer or a drain electrode layer of a transistor A part of the region where one of the insulating layers 335 and 336 extends is used as one electrode, and the insulating layer 335 and the insulating layer 336 are dielectric. The capacitor 306 has a body and a part of the conductive layer 325 as the other electrode. In order to use a part of the second electrode as the other electrode, the method for forming the second gate electrode layer of the transistor Similarly, the insulating layer 337 may be partially removed.

[0048] The semiconductor layers of the transistors 301, 302, 303, and 304 are formed of oxide semiconductors. A transistor including an oxide semiconductor has extremely low off-state current. This allows for a wider dynamic range of imaging. In the circuit configuration shown in FIG. 1(B), when the intensity of light incident on the photodiode 320 is high, The potential of the charge storage portion 305 (FD) is reduced when the gate potential is increased. Since the off-state current is extremely low, even when the gate potential is extremely low, Therefore, the current that can be detected is This allows for a wider range, i.e., a wider dynamic range.

[0049] Furthermore, the transistors 301 and 304 have low off-state current. The period during which the charge can be held in the storage section 305 (FD) can be made extremely long. Without complicating the circuit configuration or operation method, the GLORI device performs charge accumulation operation simultaneously in all pixels. Therefore, even if the subject is moving, the image is captured without distortion. Small images can be easily obtained. In addition, the global shutter method allows for a short exposure time ( The period during which the charge is accumulated can be extended, which makes it possible to capture images in low-light environments. Also suitable for.

[0050] Note that an oxide semiconductor is used for the semiconductor layers of the transistors 301, 302, 303, and 304. The above structure is an example, and the semiconductor layer may be made of silicon or the like. A configuration in which transistors using compound semiconductors and transistors using silicon are mixed. For example, the semiconductor layers of the transistors 301 and 304 may be formed of an oxide semiconductor. The semiconductor layers of the transistors 302 and 303 are made of silicon. It can be configured as follows.

[0051] The insulating layer 335 functions as a second gate insulating film and is connected to the semiconductor layer of the transistor. It is preferable that the insulating layer 335 is a film that is unlikely to generate defects at the interface. A silicon nitride film, a silicon oxynitride film, or the like can be used.

[0052] The insulating layers 337, 338, and 340 function as planarizing films. For example, in addition to inorganic films such as silicon oxide films, acrylic resins and polyimide resins are also available. The resins listed below can be used.

[0053] As for the semiconductor layers of the photodiode 320, the i-type semiconductor layer 322 is an amorphous It is preferable to use high-quality silicon. 3 is made of amorphous silicon or microcrystalline silicon containing dopants that impart the respective conductivity types. Photodiodes that use amorphous silicon as a photoelectric conversion layer are It has high sensitivity in the visible light region and is easy to detect weak visible light. The second layer 2 may be made of microcrystalline silicon or polycrystalline silicon.

[0054] The end of the photodiode 320 is connected to the n-type semiconductor layer 32 as shown in FIG. It is preferable that the shape has a step between the first insulating layer 3 and the p-type semiconductor layer 321. At least one of the side surfaces of the n-type semiconductor layer 323, the i-type semiconductor layer 322, and the p-type semiconductor layer 321 It is preferable that one of them is on a different plane. The resistance between the p-type semiconductor layer 323 and the p-type semiconductor layer 321 can be increased, and This can reduce the leakage current between the anode electrode and the cathode electrode of the electrode 320.

[0055] The end of the photodiode 320 is as shown in FIGS. 10(C1) to 10(C3). Although not shown, the above effect can be obtained even with a shape of the n-type semiconductor layer 3. 23, the end faces of the i-type semiconductor layer 322 and the p-type semiconductor layer 321 are gently tapered It may also be configured to have a shape and be continuous.

[0056] In addition, a light-transmitting conductive film may be used for the conductive layer 326 in contact with the photodiode 320. That is, the surface of the photodiode 320 facing the conductive layer 326 is the light receiving surface. Examples of the conductive film include indium tin oxide, silicon-containing indium tin oxide, Indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, and aluminum oxide zinc oxide, tin oxide, fluorine-containing tin oxide, antimony-containing tin oxide, or graphene, etc. The conductive layer 326 is not limited to a single layer, and may be a stack of the above-described light-transmitting conductive films. It's okay to have it.

[0057] In the cross-sectional view of FIG. 1A, the n-type semiconductor layer 323 is entirely covered with the conductive layer 326. 10B, a part of the n-type semiconductor layer 323 is conductive. In this case, the conductive layer 326 may be covered with a non-transparent layer. A thin metal film or the like may also be used.

[0058] Here, in the pixel configuration of the imaging device of one embodiment of the present invention, the transistor and the photo The diode 320 is configured to be stacked.

[0059] The hydrogen contained in the semiconductor layer of the photodiode 320 binds the dangling bonds of silicon. Therefore, the hydrogen improves the electrical properties and reliability of the photodiode 320. On the other hand, when an oxide semiconductor is used for the semiconductor layer of the transistor, In this case, hydrogen in an insulating layer provided near the semiconductor layer is transferred to the semiconductor layer as a carrier. Therefore, hydrogen reduces the reliability of transistors. Therefore, photodiodes using silicon-based semiconductor materials In the case where transistors using oxide semiconductors are stacked, hydrogen diffusion between the transistors is prevented. It is preferable to provide a hydrogen barrier film having the function of

[0060] The hydrogen barrier film may be, for example, silicon nitride, aluminum oxide, aluminum nitride, or oxide. Aluminum nitride, aluminum oxide nitride, gallium oxide, gallium oxide nitride, gallium oxide Thorium, yttrium oxide nitride, hafnium oxide, hafnium oxide nitride, yttria YSZ, etc. can be used.

[0061] In the structure shown in FIG. 1(A), the above-mentioned hydrogen barrier film can be applied to the insulating layer 336. Therefore, it is possible to prevent the diffusion of hydrogen from the photodiode 320 to the transistor side. This can improve the reliability of the transistor. The film 9 can also be made of a material that can be used as the hydrogen barrier film.

[0062] The conductive layer 325 in contact with the photodiode 320 is typically made of titanium, aluminum, Metals such as tungsten, molybdenum, tantalum, or the like may be used for the conductive layer 326. The conductive layer 325 can also be formed using a light-transmitting conductive film having a hydrogen barrier property. The conductive layer prevents hydrogen from diffusing from the photodiode 320 to the transistor side. The effect can be further enhanced.

[0063] Examples of conductive layers having hydrogen barrier properties include titanium nitride, tantalum nitride, and aluminum nitride. Therefore, the conductive layer 325 can be made of a metal nitride such as titanium dioxide. A single layer of the nitride, a laminate of the metal and the nitride, or a laminate of the transparent conductive film and the nitride A laminate of these may also be used.

[0064] The amount of hydrogen diffused from the photodiode 320 to the transistor is It is greatly affected by the absolute amount of hydrogen contained in 320. Therefore, it is necessary to reduce the amount of hydrogen diffusion. In this case, it is also effective to adjust the hydrogen concentration in the i-type semiconductor layer 322, which has a particularly large volume. For example, when amorphous silicon is used for the i-type semiconductor layer 322, the hydrogen concentration in the film is set to 5% or less. It is desirable to make the thickness of the i-type semiconductor layer 322 400 nm or less, preferably 300 nm or less. The thickness of the i-type semiconductor layer 322 is preferably 00 nm or less, and more preferably 200 nm or less. Microcrystalline silicon and polycrystalline silicon, which have lower hydrogen concentrations than amorphous silicon, can also be used. It is valid.

[0065] In addition, the photodiode 320 is partially missing in the area near the transistor. This also contributes to reducing the amount of hydrogen diffusion.

[0066] Specifically, the conductive layer 326 and the n-type photodiode 320 are formed on the transistor. The n-type semiconductor layer 323 can be removed (see FIG. 2(A)). Alternatively, the i-type semiconductor layer 323 and the i-type semiconductor layer 322 can be removed (see FIG. 2(B)). In addition, the conductive layer 326, the n-type semiconductor layer 323, the i-type semiconductor layer 322, and the p-type semiconductor layer 3 21 can be removed (see FIG. 2(C)). This can further reduce the amount of hydrogen diffusion from the node 320 to the transistor.

[0067] It should be noted that the conductive layer 326 and the semiconductor layer in FIGS. 2(A), (B), and (C) are removed. The length of the region is an example. In the cross section, the length is preferably a channel-shaped region. It is more preferably longer than the length of the semiconductor layer, and even more preferably longer than the length of the first gate electrode. The length of the electrode layer should be longer than that of the

[0068] As shown in FIGS. 3A, 3B, and 3C, the same phenomenon occurs on the capacitor element 306. Alternatively, a configuration may be adopted in which a part of the photodiode 320 is missing. This makes it possible to reduce the leakage current between the anode electrode and the cathode electrode.

[0069] The connection of elements included in the pixel of the above-mentioned imaging device will be explained using the circuit diagram shown in FIG. do.

[0070] One of the source electrode and the drain electrode of the transistor 301 is connected to the photodiode 320 The source electrode or the drain electrode of the transistor 301 is connected to the cathode electrode of the transistor 301. The other pole is connected to the first gate electrode of the transistor 302. One of the source electrode or drain electrode of the transistor 302 is connected to the source electrode or drain electrode of the transistor 303. is connected to one of the drain electrodes of the transistor 304. One of the input electrodes is connected to the other of the source electrode or the drain electrode of the transistor 301. One electrode of the capacitor 306 is connected to the source electrode or drain electrode of the transistor 301. The transistors 301, 302, 303, and 304 are connected to the other of the drain electrodes. The second gate electrodes of the photodiodes 320 are connected to the anode electrodes of the photodiodes 320. The other electrode of the capacitor 306 is connected to the anode electrode of the photodiode 320. All of the above connections are electrical connections.

[0071] With the above structure, the pixel circuit of the imaging device of one embodiment of the present invention can a signal line for supplying a signal to the gate electrode layer of the capacitor element; The capacitance lines can be reduced.

[0072] Note that the structure of a pixel circuit of an imaging device of one embodiment of the present invention is shown in FIGS. 4A, the other electrode of the capacitor is connected to the source electrode of the transistor 302. The other of the two electrodes is electrically connected to the drain electrode. 4C to 4F show the first embodiment of the present invention. 4(A) to 4(F) are not provided with the gate electrode 2. can also be combined in any way.

[0073] Here, the transistor 301 controls the charge accumulation section 30 in response to the output of the photodiode 320. It can function as a transfer transistor to control the potential of 5(FD). The transistor 302 is an amplifier transistor that outputs an output according to the potential of the charge storage section 305 (FD). The transistor 303 can function as a transistor. When the transistor is used as a pixel, it can function as a selection transistor for selecting a pixel. The transistor 304 is a reset transistor that initializes the potential of the charge storage section 305 (FD). It can function as a starter.

[0074] FIG. 5 is a diagram illustrating a configuration in which signal lines are connected to the circuit shown in FIG. 1(B). The anode of the photodiode 320 can be connected to the wiring 316. The gate electrode of the transistor 301 can be connected to the wiring 312 (TX). The other of the source electrode and the drain electrode of the transistor 302 is connected to the wiring 314 (GND). The other of the source electrode and the drain electrode of the transistor 304 can be The gate electrode can be connected to the wiring 311 (RS). The other of the source electrode and the drain electrode of the transistor 303 is connected to a wiring 315 (OU The gate electrode can be connected to the wiring 313 (SE). All of the above connections are electrical connections.

[0075] The wiring 311 (RS) functions as a signal line for controlling the transistor 304. The wiring 312 (TX) is a signal line for controlling the transistor 301. The wiring 313 (SE) can function as a The wiring 314 (GND) can function as a signal line for controlling the It can function as a signal line to set a quasi-potential (for example, GND). 15 (OUT) is a signal line for reading out a signal output from the transistor 302. The wiring 316 is connected from the charge storage section 305 (FD) to the photodiode. 5. The circuit configuration shown in FIG. In this configuration, the wiring 317 is a low potential (VSS) line. In the circuit configuration of Figure 5, it functions as a signal line to reset the DD) line.

[0076] The wiring 314 may be supplied with a potential such as GND, VSS, or VDD. Therefore, the potential and voltage are relative. Therefore, the magnitude of the GND potential is not necessarily , is not necessarily 0 volts.

[0077] The operation method of the pixel circuit having the configuration of FIG. 5 will be described later in detail. In other words, the anode electrode of the photodiode 320 is reverse biased. A potential lower than the source potential of each transistor can be applied. The potential is applied to the second gate electrode of the transistor, and the threshold voltage of the transistor is The lower voltage can be shifted in the positive direction.

[0078] 6A is a top view of a pixel of an imaging device having the circuit configuration shown in FIG. The cross section of 1-A2 corresponds to FIG. 1(A). Also, FIG. 6(B) corresponds to FIG. 2(A), (B), (C 6(A) and (B) correspond to the top view of the pixel of the imaging device shown in FIG. For clarity, some elements are omitted from the illustration.

[0079] In this way, the pixel density is increased by stacking the transistors and photodiodes. This allows for the production of high-definition images. Although the characteristics of photodiodes can be deteriorated by exposure to light, this configuration The semiconductor layer of the glass substrate 320 and / or the conductive layer 325 act as a light-shielding film. Deterioration of the transistor can be suppressed.

[0080] 7A, 7B, 7C, and 7D show the configuration of an imaging device that can use the above-described pixels. In Figure 7(A), (B), (C), and (D), three adjacent pixels are shown. The pixels are illustrated as pixel 350a, pixel 350b, and pixel 350c.

[0081] The imaging device in FIG. 7A is an example in which an optical conversion layer 1550 is provided on each pixel. For example, if a filter that blocks light shorter than the wavelength of visible light is used in the optical conversion layer 1550, infrared photography becomes possible. In addition, the optical conversion layer 1550 can be made to block light having wavelengths shorter than near-infrared. If a filter is used, it can be used as a far-infrared imaging device. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. This configuration can be used not only as an imaging device but also as a detector for estimating the light intensity of a specific wavelength. Good too.

[0082] Furthermore, if a scintillator is used for the optical conversion layer 1550, it is possible to use a radiation detector such as that used in an X-ray imaging device. It can be used as an imaging device to obtain an image that visualizes the strength of rays. When radiation strikes a scintillator, it emits light through a phenomenon called photoluminescence. The light is converted into visible light, ultraviolet light, or other light (fluorescence). The image data is acquired by detecting the object with a flat panel detector. This configuration may also be used in a radiation detector or the like.

[0083] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy. These include materials that emit visible and ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C Materials in which eF3, LiF, LiI, and ZnO are dispersed in resin or ceramics are known.

[0084] The imaging device in FIG. 7B is an example in which a color filter 1530 is provided on each pixel. Color filters 1530a, 1530b, and 1530c , R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta) and other colors By allocating, a color image can be obtained.

[0085] The image pickup device of FIG. 7C has pixels 351a and 351b of the display device adjacent to the image pickup device pixels. , 351c. The pixels of the display device include a liquid crystal display element or an EL display element. It includes elements and transistors connected to them. For example, as shown in Figure 7(C), By providing a color filter 1530 on the pixels of the imaging device and the pixels of the display device, A display panel with an image sensor that can display a color image is formed. It is possible.

[0086] The imaging device of FIG. 7(D) has a microlens array 1540 provided on each pixel of the imaging device. The above-mentioned optical conversion layer 1550 and the microlens array are provided between the pixels and the microlens array. A microlens array 1540 can be used to This allows the photodiode 320 to be efficiently irradiated with light.

[0087] In addition, each pixel of the imaging device, the optical conversion layer 1550, the color filter 1530, or Between the microlens array 1540 and the insulating film that serves as a protection layer, A light-shielding layer for preventing penetration, an anti-reflection film, a flattening film, etc. may be provided. On the substrate, an optical conversion layer 1550, a color filter 1530 or a microlens array 15 40 may not be provided.

[0088] FIG. 8 is a conceptual diagram showing the configuration of an imaging device. The imaging device has the circuit shown in FIG. 1(B). a pixel array 1700 in which a plurality of pixels 350 are arranged in a plane; 1730, circuit 1740, and circuit 1750.

[0089] The pixel array 1700 is connected to a circuit 1730 and a circuit 1740. The circuit 1730 For example, it can function as a drive circuit for a reset transistor. The circuit 1730 is electrically connected to the transistor 304 in FIG. 740 can function as, for example, a drive circuit for a transfer transistor. In this case, the circuit 1740 and the transistor 301 in FIG. Although FIG. 8 shows a configuration in which the circuit 1730 and the circuit 1740 are arranged separately, Alternatively, the circuit 1730 and the circuit 1740 may be arranged together in one region. .

[0090] In addition, a circuit 1750 is connected to the pixel array 1700. The circuit 1750 is, for example, It functions as a driver circuit for selecting a vertical output line electrically connected to the transistor 302. It is possible.

[0091] The circuit 1730 and the circuit 1740 are drive circuits for binary output of "Low" or "High." Therefore, as shown in FIG. 9(A), a shift register 1800 and a buffer circuit 1801 are connected. It can be driven in a combination of 900.

[0092] The circuit 1750 also includes a shift register 1810 and a buffer circuit as shown in FIG. Each vertical output line 21 can be configured by a signal line 1910 and an analog switch 2100. 10 is selected by the analog switch 2100 and outputs an output signal to the output line 2200. The analog switch 2100 is sequentially connected to the shift register 1810 and the buffer circuit 1910. It shall be selected.

[0093] The circuit 1730, the circuit 1740, and the circuit 1750 are formed on a substrate in the same manner as the pixel circuit. It may be implemented as a separate IC chip or may be included in an external IC chip.

[0094] In this embodiment, an example in which the present invention is applied to an imaging device has been described. However, one embodiment of the present invention is not limited thereto. For example, one embodiment of the present invention may be directed to a device having another function. The present invention may be applied to a semiconductor device.

[0095] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0096] (Embodiment 2) In this embodiment, the pixel circuit shown in FIG. 5 of the first embodiment will be described in detail.

[0097] In the pixel circuit shown in FIG. 5, the photodiode 320 is a light-receiving element. The transistor 301 has a function of generating a current according to incident light. It has a function of controlling charge accumulation from the transistor 320 to the charge accumulation unit 305 (FD). The resistor 302 has a function of outputting a signal according to the potential of the charge storage section 305 (FD). The transistor 304 has a function of resetting the potential of the charge storage section 305 (FD). The transistor 303 has a function of controlling selection of a pixel circuit during reading.

[0098] The charge accumulation unit 305 (FD) changes depending on the amount of light received by the photodiode 320. It holds the charge that converts into electricity.

[0099] The transistor 302 and the transistor 303 are connected between the wiring 315 and the wiring 314. , and are connected in series. Alternatively, the wiring 314, the transistor 303, and the wiring 315 may be arranged in this order. The transistor 302 and the wiring 315 may be arranged in this order.

[0100] An example of the operation of the circuit shown in FIG. 5 will be described with reference to the timing chart shown in FIG. do.

[0101] For ease of explanation, in FIG. 11, the potential of each wiring is given as a signal that changes between two values. However, since each potential is an analog signal, various values ​​can be taken depending on the situation, not just binary. In the figure, the signal 701 is the potential of the wiring 311 (RS), and the signal 702 is the potential of the wiring 31 2 (TX), signal 703 is the potential of the wiring 313 (SE), and signal 704 is the potential of the charge storage unit 3 The potential of the signal 705 (FD) corresponds to the potential of the wiring 315 (OUT). The potential of the wiring 316 is always "Low", and the potential of the wiring 317 is always "High".

[0102] At time A, the potential (signal 701) of the wiring 311 (RS) is set to “High” and the potential (signal 701) of the wiring 312 When the potential (signal 702) of the charge storage unit 305 (FD) is set to "High", The potential (signal 704) is initialized to the potential ("High") of the wiring 317, and the reset operation begins. The potential (signal 705) of the wiring 315 (OUT) is set to "High". Keep it in the jersey.

[0103] At time B, when the potential (signal 701) of the wiring 311 (RS) is set to “Low”, the reset The charge transfer operation ends and the accumulation operation starts. As a bias is applied, a reverse current flows through the charge storage unit 305 (FD) (signal 704). When light is irradiated, the reverse current of the photodiode 320 increases. The rate at which the potential (signal 704) of the charge storage section 305 (FD) decreases depends on the amount of light irradiated. That is, the transistor changes in response to the amount of light incident on the photodiode 320. The channel resistance between the source and drain of the transistor 302 changes.

[0104] At time C, when the potential (signal 702) of the wiring 312 (TX) is set to "Low", the accumulation operation The operation ends, and the potential (signal 704) of the charge storage unit 305 (FD) becomes constant. The potential is determined by the amount of charge generated by the photodiode 320 during the accumulation operation. That is, it changes according to the amount of light irradiated onto the photodiode 320. The transistor 301 and the transistor 304 are formed as an oxide semiconductor layer having a channel forming region. By forming the transistor with an extremely low current, the charge is held until the next reset operation is performed. It becomes possible to keep the potential of the storage section 305 (FD) constant.

[0105] When the potential (signal 702) of the wiring 312 (TX) is set to "Low", The parasitic capacitance between the charge storage unit 305 (TX) and the charge storage unit (FD) If the change in the potential is large, the photodiode may be damaged during the accumulation operation. Therefore, the amount of charge generated by the diode 320 cannot be accurately obtained. To reduce the amount of The capacitance between the gate and the charge storage portion 305 (F In this embodiment, it is effective to provide a storage capacitor at the potential The explanation will be given ignoring the changes in

[0106] At time D, when the potential (signal 703) of the wiring 313 (SE) is set to "High", the transistor The selector 303 becomes conductive, and the selection operation starts. The wiring 314 (GND) and the wiring 315 (OUT ) is electrically connected via the transistor 302 and the transistor 303. Since the precharge of the wiring 315 (OUT) is completed before time D, the potential ( Here, the potential (signal 705) of the wiring 315 (OUT) is low. The rate at which it drops depends on the current between the source and drain of transistor 302. That is, It changes depending on the amount of light that is irradiated onto the photodiode 320 during the accumulation operation.

[0107] At time E, when the potential (signal 703) of the wiring 313 (SE) is set to "Low", The transistor 303 is cut off, the selection operation is completed, and the potential of the wiring 315 (SE) (signal 705 ) is a constant value. Here, the constant value is determined by the amount of light irradiated onto the photodiode 320. Therefore, by obtaining the potential of the wiring 315 (SE), the accumulated The amount of light that is incident on the photodiode 320 during operation can be known.

[0108] More specifically, when the light irradiating the photodiode 320 is strong, the charge accumulation unit 30 The potential of the transistor 5 (FD), i.e., the gate voltage of the transistor 302, drops. The current flowing between the source and drain of the transistor 302 becomes smaller, and the wiring 315 (OUT ) (signal 705) slowly decreases. can read out a relatively high potential.

[0109] Conversely, when the light irradiating the photodiode 320 is weak, the charge accumulation unit 305 (FD) The potential of the transistor 302, i.e., the gate voltage of the transistor 302, becomes high. The current flowing between the source and drain of the capacitor 302 increases, and the potential of the wiring 315 (OUT) (signal 705) falls quickly. Therefore, a relatively low voltage is output from wire 315 (OUT). The position can be read out.

[0110] In addition, by supplying a potential of, for example, about −1 V to −10 V to the wiring 316, each transistor The threshold voltage of the transistor can be shifted in the positive direction. The threshold voltage has shifted in the negative direction due to aging caused by stress or other factors. The threshold voltage of the transistor can be corrected.

[0111] Although FIG. 5 shows an example in which the transistor 301 is provided, The embodiment is not limited to this. As shown in FIG. 12, the transistor 301 may be omitted. It is Noh.

[0112] In the above-described circuit example, the wiring 315 (OUT) has the same configuration as that shown in FIGS. An integrating circuit as shown in C) may be connected. This increases the S / N ratio and makes it possible to detect weaker light. This can increase the sensitivity of the device.

[0113] FIG. 13(A) shows an integrator circuit using an operational amplifier circuit (also called an OP amplifier). The inverting input terminal of the amplitude circuit is connected to the wiring 315 (OUT) via a resistor element R. The non-inverting input terminal of the amplifier circuit is connected to the ground potential. The output terminal of the operational amplifier circuit is connected to the capacitance It is connected to the inverting input terminal of the operational amplifier circuit via element C.

[0114] FIG. 13(B) shows an integrating circuit using an operational amplifier circuit with a different configuration from that shown in FIG. 13(A). The inverting input terminal of the operational amplifier circuit is connected to the wiring 315 (OUT The non-inverting input terminal of the operational amplifier circuit is connected to the ground potential. The output terminal of the path is connected to the inverting input terminal of the operational amplifier circuit via a capacitive element C2.

[0115] FIG. 13(C) shows an example in which an operational amplifier circuit with a different configuration from those in FIGS. 13(A) and 13(B) is used. The output terminal of the operational amplifier circuit is connected to the wiring 315 (OUT The inverting input terminal of the operational amplifier circuit is connected to the inverting input terminal of the operational amplifier circuit. The resistor R and the capacitor C form a CR integrator circuit. constitutes a unity gain buffer.

[0116] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0117] (Embodiment 3) In this embodiment, an example of a method for driving a pixel circuit will be described.

[0118] As described in the second embodiment, the operation of the pixel circuit is a reset operation, a storage operation, and a selection operation. The global imaging method is used to control the entire pixel matrix. The shutter system and the rolling shutter system are known.

[0119] FIG. 14A is a timing chart for the global shutter system. 14(A) has a plurality of pixel circuits arranged in a matrix, and the pixel circuits have the circuit shown in FIG. As an example of an imaging device, the operation of the pixel circuits from the first row to the nth row (n is a natural number of 3 or more) This explains the following.

[0120] In FIG. 14A, signals 501, 502, and 503 are in the first row, the second row, This is a signal input to the wiring 311 (RS) connected to each pixel circuit in the nth row. Signals 504, 505, and 506 are supplied to the pixel circuits in the first, second, and n-th rows. The signals 507 and 508 are input to the connected wiring 312 (TX). The signal 509 is transmitted to the wiring 313 ( This is the signal input to the SE.

[0121] A period 510 is a period required for one image capture. A period 511 is a period required for the pixels in each row. The period 520 is a period in which the circuits are simultaneously performing reset operations. The selection operation is performed sequentially in the pixel circuits of each row. As an example, the period 531 is a period during which the pixel circuits in the first row are performing a selection operation. In this way, in the global shutter system, the reset operation is performed almost simultaneously in all pixel circuits. After this, accumulation operations are performed in all pixel circuits almost simultaneously, and readout operations are performed sequentially for each row. can be.

[0122] In other words, in the global shutter system, accumulation operations are performed in all pixel circuits almost simultaneously. Therefore, the image pickup is performed simultaneously in the pixel circuits of each row. Even if the object is moving, it is possible to obtain images with little distortion.

[0123] On the other hand, FIG. 14(B) is a timing chart when the rolling shutter method is used. For signals 501 to 509, please refer to the explanation in FIG. 14(A). 10 is the period required for one image capture. Furthermore, periods 611, 612, and 613 are These are the reset periods for the first row, the second row, and the n-th row, respectively. Periods 622 and 623 are accumulation operation periods for the first row, second row, and nth row, respectively. Furthermore, a period 631 is a period during which the pixel circuits in the first row are performing a selection operation. In the rolling shutter method, the accumulation operation is not performed simultaneously in all pixel circuits, but for each row. Since the imaging is performed sequentially, the simultaneity of imaging in the pixel circuits of each row cannot be ensured. The timing of the image capture differs between the first and last lines, so there is a large amount of distortion when the subject is moving. This results in a large image.

[0124] To realize the global shutter system, the signal readout from each pixel must be completed sequentially. The potential of the charge storage section (FD) must be maintained until the The retention of the period is achieved by forming a channel formation region of the transistor 301 or the like using an oxide semiconductor. This can be achieved by using a transistor with low off-state current. When a transistor in which the channel formation region is formed of silicon or the like is used, the off-state current The current is so high that the potential of the charge storage section (FD) cannot be maintained for a long time, and the global shutter method It becomes difficult to use

[0125] As described above, a transistor in which a channel formation region is formed using an oxide semiconductor is used in a pixel circuit. This makes it easy to realize the global shutter method.

[0126] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0127] (Fourth embodiment) In this embodiment, a transistor and a semiconductor device that can be used in an imaging device of one embodiment of the present invention will be described. The materials constituting the transistor will be described. 1, some elements may be enlarged, reduced, or omitted for clarity.

[0128] 15A and 15B illustrate transistors that can be used in an imaging device of one embodiment of the present invention. 15(A) is a top view and a cross-sectional view of the same. The cross section along the line C1-C2 corresponds to FIG. 15(B). The channel length direction and the direction perpendicular to the channel length direction are called the channel width direction.

[0129] The transistor includes an insulating layer 915 formed on a substrate 900, a gate electrode layer 920, and a , a gate insulating film 930 formed in the order of an insulating layer 931 and an insulating layer 932, and an oxide semiconductor a source electrode layer 950 and a drain electrode layer 960 in contact with a part of the oxide semiconductor layer 940; The electrode layer 960 is formed on the above structure. In addition, an insulating layer 980 and an insulating layer 990 are formed on the above structure. That's fine.

[0130] In the above configuration, the gate insulating film 930 has two layers. However, the gate insulating film 930 may have a single layer. good.

[0131] In one embodiment of the present invention, the insulating layer 980 and the insulating layer 990 are used as a second gate insulating film. The insulating layer 990 can function as the hydrogen barrier film described in Embodiment Mode 1. The material can be formed from a material that functions as a

[0132] Further, a transistor that can be used in the imaging device of one embodiment of the present invention has a structure shown in FIG. It may also be a channel-protected bottom gate structure as shown in (B). 16(A) is a top view, and the cross section taken along the dashed line D1-D2 in FIG. 16(A) corresponds to FIG. 16(B). The direction of the dashed dotted line D1-D2 is the channel length direction, and the direction perpendicular to the channel length direction is The direction is called the channel width direction.

[0133] Here, the insulating layer 933 has a function of protecting the channel region. 33 may be disposed only in the region overlapping with the channel region, or ) they may also be arranged in other areas.

[0134] Further, a transistor that can be used in the imaging device of one embodiment of the present invention has a structure shown in FIG. A bottom-contact bottom-gate structure as shown in FIG. 17(A) may also be used. 17(A) is a cross section taken along the dashed line E1-E2 in FIG. 17(B). The direction of the dashed dotted line E1-E2 corresponds to the channel length direction, and the direction perpendicular to the channel length direction corresponds to the The intersecting direction is called the channel width direction.

[0135] In a transistor that can be used in an imaging device according to one embodiment of the present invention, an oxide semiconductor The oxide semiconductor layer can be used as an active layer. Since the mobility is higher than that of the conventional transistor, it is easy to make the transistor smaller. This allows the pixel to be smaller, however, one embodiment of the present invention is not limited thereto. In some cases or depending on the situation, the active layer may include a semiconductor other than an oxide semiconductor. It's fine.

[0136] In the transistors shown in FIGS. 15(A), (B) and 16(A), (B), The length of the oxide electrode layer 920 in the channel length direction is set to be larger than the length of the oxide semiconductor layer 940. For example, when the imaging device of one embodiment of the present invention is combined with a display device or the like, In a display device having a backlight, the gate electrode layer serves as a light-shielding layer, and the oxide This can prevent the deterioration of electrical characteristics caused by light irradiation of the semiconductor layer 940.

[0137] The source electrode layer 950 and the drain electrode layer 960 in the transistor are The structure shown in the top view of FIG. 18(A) and FIG. 18(B) can be used. , (B) shows an oxide semiconductor layer 940, a source electrode layer 950, and a drain electrode layer 960. As shown in FIG. 18(A), only the source electrode layer 950 and the drain electrode Width of pole layer 960 (W SD ) is the width (W OS ) is formed longer than Also, as shown in FIG. SD is WOS It is formed shorter than It's okay. W OS ≧W SD (W SD is W OS (below) so that the gate electric field is This makes it easier to apply the metal to the entire semiconductor layer 940, thereby improving the electrical characteristics of the transistor. Cut.

[0138] Components of a transistor according to one embodiment of the present invention will be described in detail below.

[0139] The substrate 900 may be a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like. In addition, it is possible to use a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, substrate, a compound semiconductor substrate made of silicon germanium, SOI (Silicon On Insulator) Insulator substrates or the like can be used.

[0140] The insulating layer 915 may be, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or A single layer of a silicon nitride oxide film or a laminate of these can be used. 5 may not be provided and the gate electrode layer may be in direct contact with the substrate.

[0141] The gate electrode layer 920 may include chromium (Cr), copper (Cu), aluminum (Al), and gold (A). u), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (T i), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt or an alloy containing the above-mentioned metal element or The gate electrode layer 9 can be formed using an alloy or the like in which different metal elements are combined. The film 20 may have a single layer structure or a laminated structure of two or more layers.

[0142] The gate electrode layer 920 may be formed of indium tin oxide or indium oxide containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium titanium oxide oxide, indium tin oxide, indium zinc oxide, silicon oxide Applying conductive materials with translucency, such as doped indium tin oxide and graphene In addition, a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element can be used. It is also possible.

[0143] In addition, an In—Ga—Zn-based oxynitride semiconductor is formed between the gate electrode layer 920 and the insulating layer 931. film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn-based oxynitride nitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN , ZnN, etc.) may be provided.

[0144] The insulating layers 931 and 932 are formed by plasma enhanced chemical vapor deposition (PECVD). Enhanced Chemical Vapor Deposition (ECV) method, spa Silicon oxide film, silicon oxynitride film, silicon nitride oxide film, silicon nitride film, etc. aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film aluminum film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, ceramic oxide film For example, an insulating layer containing at least one of a lithium oxide film and a neodymium oxide film can be used. The gate insulating film 930 does not have a laminated structure of insulating layers 931 and 932, but is made of the above-mentioned materials. A single layer insulating film selected from the above may be used, or three or more layers of insulating films may be used. 0 can also be formed using the above materials.

[0145] Note that the insulating layer in contact with the oxide semiconductor layer 940 which functions as a channel formation region of the transistor The edge layer 932 is preferably an oxide insulating film, and contains oxygen in excess of the stoichiometric composition. In other words, the insulating layer 932 has a region containing oxygen (an oxygen-excess region). The insulating layer 932 is an insulating film capable of releasing oxygen. To prevent this, the insulating layer 932 may be formed in an oxygen atmosphere, for example. Oxygen may be introduced into the insulating layer 932 to form an oxygen-excess region. ion implantation, ion doping, plasma immersion ion implantation, plasma Treatment etc. can be used.

[0146] Furthermore, when hafnium oxide is used for the insulating layers 931 and 932, the following effects are achieved. Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Therefore, the film thickness can be made larger than when silicon oxide is used, and the tunnel current The leakage current can be reduced.

[0147] In this embodiment, a silicon nitride film is formed as the insulating layer 931, and a silicon nitride film is formed as the insulating layer 932. The silicon nitride film has a lower dielectric constant than the silicon oxide film. The thickness required to obtain the same capacitance as a silicon oxide film is large, so The gate insulating film 930 of the gate electrode is made thicker by including a silicon nitride film. Therefore, the dielectric strength of the transistor can be improved, and the static electricity of the transistor can be reduced. Destruction can be suppressed.

[0148] The oxide semiconductor layer 940 is typically an In-Ga oxide, an In-Zn oxide, an In-Mn oxide, or an In-GaAs oxide. -Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn or Hf) In particular, it is preferable to use In-M-Zn oxide.

[0149] When the oxide semiconductor layer 940 is an In-M-Zn oxide, the In-M-Zn oxide is deposited. The atomic ratio of the metal elements in the sputtering target used for this purpose does not necessarily depend on the oxide film to be formed. The atomic ratio is not the same as that of the compound semiconductor layer 940, but has a difference of about ±40%. For example, a film was formed using a sputtering target with In:M:Zn=4:2:4.1. In this case, the atomic ratio of the deposited film is approximately In:M:Zn=4:2:3.

[0150] The oxide semiconductor layer 940 has an energy gap of 2 eV or more, preferably 2.5 e V or more, more preferably 3 eV or more. By using a compound semiconductor, the off-state current of a transistor can be reduced.

[0151] The thickness of the oxide semiconductor layer 940 is 3 nm to 200 nm, preferably 3 nm or more. The thickness is set to at most 100 nm, and more preferably at least 3 nm and at most 50 nm.

[0152] In addition, an oxide semiconductor layer with low carrier density is used as the oxide semiconductor layer 940. For example, the oxide semiconductor layer 940 has a carrier density of 1×10 17 pieces / cm 3 The following is preferably is 1 x 10 15 pieces / cm 3 or less, more preferably 1 × 10 13 pieces / cm 3 Below, more preferred Preferably 1 x 1011 pieces / cm 3 The following applies.

[0153] In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component are For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Moreover, silicon forms impurity levels in the oxide semiconductor layer. The impurity levels become traps and degrade the electrical characteristics of the transistor. It is preferable to reduce the impurity concentration at the interface with other layers.

[0154] In order to provide stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, In order to achieve this, the impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is But 1×10 17 / cm 3 preferably less than 1 x 10 15 / cm 3 is less than More preferably, 1×10 13 / cm 3 It means that it is less than.

[0155] To make the oxide semiconductor layer intrinsic or substantially intrinsic, a part or the entire layer must be made of silicon. Concentration 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 It is sufficient to set it to less than. , hydrogen concentration is 2×10 20 atoms / cm 3 Less than or equal to 5 x 1019 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 More preferably, 5×10 18 atoms / cm 3 The nitrogen concentration should be 5×10 19 a toms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is more preferable: is 1 x 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / c m 3 The impurity concentrations are determined by SIMS (Secondary I It can be obtained by Mass Spectrometry (MSM) analysis.

[0156] Furthermore, if the oxide semiconductor layer contains silicon or carbon at a high concentration, the crystallinity may be reduced. In order to prevent the crystallinity of the oxide semiconductor layer from being reduced, it is necessary to Or the silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than and In addition, the carbon concentration is 1×10 19 atoms / cm 3 Less than 5x1 0 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than This can be done as follows.

[0157] A transistor using a highly purified oxide semiconductor layer for a channel formation region has a low off-state current. For example, when the channel width is 1×10 6 μm In a transistor with a channel length of 10 μm, the voltage between the source and drain electrodes (drain When the on-voltage is in the range of 1V to 10V, the off-state current is Below the detection limit, i.e., 1×10 -13 In this case, the off-peak per channel width is The current is less than 100 zA / μm. In the case of V, an extremely low off-state current of several tens of yA / μm is obtained. The off-state current of a transistor using a highly purified oxide semiconductor layer for a channel formation region is This is significantly lower than that of a transistor using crystalline silicon.

[0158] When the oxide semiconductor layer 940 has a single layer structure of In-M-Zn oxide, the The atomic ratio of In to M is higher than 25 atomic % for In and 75 atomic % for M. %, or In is higher than 34 atomic % and M is less than 66 atomic %. It is preferable to do so.

[0159] Required semiconductor and electrical characteristics of the transistor (field-effect mobility, threshold voltage, etc.) The composition, carrier density, impurity concentration, defect density, etc. of the oxide semiconductor layer 940 are appropriately determined depending on the It is best to control it properly.

[0160] The oxide semiconductor layer 940 may have a structure in which a plurality of oxide semiconductor layers are stacked. 19(A), the oxide semiconductor layer 940 is replaced with the oxide semiconductor layer 941. It can be a stack of a and the oxide semiconductor layer 941b. The oxide semiconductor layer 941a and the oxide semiconductor layer 941b can have different compositions. For example, for one of the oxide semiconductor layers, one of an oxide containing two types of metals, an oxide containing three types of metals, and an oxide containing four types of metals is used, and for the other oxide semiconductor layer, an oxide containing two types of metals different from those in one of the oxide semiconductor layers, an oxide containing three types of metals, and an oxide containing four types of metals may be used.

[0161] Also, the constituent elements of the oxide semiconductor layer 941a and the oxide semiconductor layer 941b may be the same, and the atomic ratios of both may be different. For example, for one of the oxide semiconductor layers, the atomic ratio In:M:Zn =1:1:1, 5:5:6, 3:1:2, 2:1:3, or 4:2:4.1 targets are used for formation, and for the other oxide semiconductor layer, the atomic ratio In:M:Zn = 1:3:2, 1: 3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6 targets are used for formation.

[0162] At this time, among one of the oxide semiconductor layers and the other oxide semiconductor layer, for the oxide semiconductor layer on the side closer to the gate electrode ( channel side), the atomic ratio of In and M in the oxide semiconductor layer is set such that In≥M, and for the oxide semiconductor layer on the side farther from the gate electrode (back channel side), the atomic ratio of In and M in the oxide semiconductor layer is set such that In<M, and a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic ratio of In and M in the oxide semiconductor layer on the channel side such that In<M, and the atomic ratio of In and M in the oxide semiconductor layer on the back channel side such that In≥M, the variation amount of the threshold voltage of the transistor can be reduced.

[0163] The oxide semiconductor layer of the transistor may have a three-layer structure. The constituent elements of the oxide layers may be the same, but the atomic ratio of each may be different. The structure of a transistor having a three-layer structure will be described with reference to FIG. The structure in which the oxide semiconductor layer has a multilayer structure can be applied to the other transistors described in this embodiment. You can also do this.

[0164] In the transistor shown in FIG. 19B, the oxide semiconductor layer 942a and the oxide semiconductor layer 94 2b and an oxide semiconductor layer 942c are stacked in this order from the gate insulating film side.

[0165] The oxide semiconductor layer 942a and the oxide semiconductor layer 942c are made of InM 1x Z n y O z Use materials that can be expressed as (x≧1, y>1, z>0, M1=Ga, Hf, etc.) The oxide semiconductor layer 942b can be formed from InM 2x Zn y O z ( Materials that can be expressed as x≧1, y≧x, z>0, M2=Ga, Sn, etc. can be used. .

[0166] By selecting the composition ratio in this manner, the conduction band minimum of the oxide semiconductor layer 942a and the oxide The lower end of the conduction band of the oxide semiconductor layer 942b is closer to the vacuum level than the lower end of the conduction band of the semiconductor layer 942c. This allows the transistor to have a well structure with the deepest point. It is possible to increase the field effect mobility of the semiconductor and reduce the amount of variation in threshold voltage. This can be done.

[0167] For example, the oxide semiconductor layer 942a and the oxide semiconductor layer 942c may be formed by using an oxide semiconductor layer having an atomic ratio of In:G a:Zn=1:1:1, 1:3:2, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1:9:6, and the atomic ratio of the oxide semiconductor layer 942b is In:Ga:Zn=1: The ratio may be 1:1, 5:5:6, 3:1:2, 2:1:3 or 4:2:4.1.

[0168] The oxide semiconductor layer 942a, the oxide semiconductor layer 942b, and the oxide semiconductor layer 942c Since the oxide semiconductor layer 942b has the same constituent elements, the oxide semiconductor layer 942b has a In detail, the defect level is small in the gate insulating film. The number of defect states at the interface between the oxide semiconductor layer 942a and the oxide semiconductor layer 942b is smaller than that at the interface between the oxide semiconductor layer 942a and the oxide semiconductor layer 942b. By stacking oxide semiconductor layers as shown above, the amount of fluctuation in the threshold voltage of the transistor can be reduced. It can be reduced.

[0169] In addition, the oxide semiconductor layer 942a, the oxide semiconductor layer 942b, and the oxide semiconductor layer 942 An oxide semiconductor having a different crystallinity may be used for the oxide layer c. The compound semiconductor layer 942b is preferably a film having crystallinity, and has a crystallinity in a direction substantially perpendicular to the surface. It is more preferable that the film is c-axis oriented.

[0170] The source electrode layer 950 and the drain electrode layer 960 are formed of a material that extracts oxygen from the oxide semiconductor layer. It is preferable to use a conductive film with good electrical properties. For example, Al, Cr, Cu, Ta, Ti, M O, W, Ni, Mn, Nd, Sc, etc. can be used. In addition, alloys and the like of the above materials can be used. Conductive nitrides of the above materials may also be used. The material may be a laminate of a plurality of materials selected from the group consisting of conductive nitrides of materials. The high melting point of Ti is a key factor in the process, as it can be easily bonded to other metals and the subsequent process temperature can be relatively high. It is more preferable to use W. Also, low-resistivity Cu or Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) or the above materials with Cu or Cu-X alloys A layered structure with gold may also be used.

[0171] Note that the Cu-X alloy is formed by heat treatment in a region in contact with the oxide semiconductor layer or in contact with the insulating film. A coating film may be formed on the area where the coating film is applied. The coating film is formed from a compound containing X. X Examples of compounds containing X include oxides of X, In-X oxides, Ga-X oxides, and In-G aX oxide, In-Ga-Zn-X oxide, etc. Coating film Coating film is a blocking film. As a result, it is possible to prevent Cu in the Cu-X alloy film from penetrating into the oxide semiconductor layer. do.

[0172] The conductive film has a property of extracting oxygen from the oxide semiconductor layer. The oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed in the oxide semiconductor layer. The region becomes significantly n-type when oxygen enters the oxygen vacancy. acts as the source or drain of the transistor.

[0173] The metal film, semiconductor film, inorganic insulating film, and the like described in this embodiment are typically formed by sputtering. It can be formed by a thermal CVD method or a plasma CVD method, but other methods, such as a thermal CVD method, are also possible. Examples of thermal CVD methods include MOCVD (Metal Organometallic Chemical Vapor Deposition). Chemical Vapor Deposition (ALD) and Atomic c Layer Deposition method.

[0174] The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0175] In the thermal CVD method, the source gas and oxidant are simultaneously fed into the chamber. By reacting the material near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0176] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0177] (Embodiment 5) A structure of an oxide semiconductor film that can be used in one embodiment of the present invention will be described below. .

[0178] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°.

[0179] Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. The single-crystal oxide semiconductor film is called CAAC-OS (C Axis Aligned Crystal Polycrystalline oxide semiconductor film The oxide semiconductor film includes a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

[0180] First, the CAAC-OS film will be described.

[0181] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0182] Transmission Electron Microscope (TEM) A bright-field image and a combined analysis image of the diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be identified. On the other hand, high-resolution TEM images also reveal clear boundaries between crystalline parts, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0183] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction roughly parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystal part. The CAAC-OS film is formed on a surface (also called a surface on which the film is formed) or on the upper surface. The CAAC-OS film has a shape similar to that of the crystalline silicon film, and is arranged parallel to the surface on which the CAAC-OS film is formed or the upper surface thereof.

[0184] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction roughly perpendicular to the sample surface. They then confirmed that the metal atoms in the crystals were arranged in triangular or hexagonal shapes. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0185] Using an X-ray diffraction (XRD) device, for example, InG Analysis of CAAC-OS films with ZnO4 crystals by out-of-plane method When this is done, a peak appears at a diffraction angle (2θ) of 31°. This peak is due to the The crystals of the CAAC-OS film have a c-axis orientation. It can be seen that the c-axis is oriented in a direction substantially perpendicular to the surface on which the film is formed or the upper surface.

[0186] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ 31°, a peak also appears at 2θ 36°. The peak at 2θ of 36° is due to the presence of crystals in the CAAC-OS film that do not have a c-axis orientation. The CAAC-OS film shows a peak at 2θ of 31°, and It is preferable that θ does not show a peak at 36°.

[0187] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The elements that bond more strongly with oxygen than the metal elements that make up the semiconductor film are transferred from the oxide semiconductor film to the oxygen. The loss of atoms disrupts the atomic arrangement of the oxide semiconductor film, which causes a decrease in crystallinity. Heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius (or molecular radius ) is large, which causes the atomic arrangement of the oxide semiconductor film to become disordered and reduces the crystallinity. Impurities contained in the oxide semiconductor film serve as carrier traps or carrier generation sources.

[0188] The CAAC-OS film is an oxide semiconductor film with a low density of defect states.

[0189] Low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "substantially highly purified intrinsic" refers to a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics ( It is also called normally-on.) It is rare for it to become a high-purity intrinsic or substantially high-purity The intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The impurity concentration is high and the charge is stable for a long time, so the charge may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. become.

[0190] In addition, transistors using CAAC-OS films show improved electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0191] Next, a microcrystalline oxide semiconductor film will be described.

[0192] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a crystal region and a crystal region where no clear crystal part can be identified. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fine particles are often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In addition, the nc-OS film has clearly defined grain boundaries in high-resolution TEM images. It may not be possible to recognize it.

[0193] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, an XRD device using X-rays with a diameter larger than that of the crystal part is used for the nc-OS film. When structural analysis is performed using the out-of-plane method, peaks indicating crystal planes are observed. In addition, the probe diameter (e.g., When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a diameter of 50 nm or more, On the other hand, the diffraction pattern of the nc-OS film is similar to that of the crystalline part. Nanobeam electron diffraction is performed using an electron beam with a probe diameter close to the size of the crystal or smaller than the crystal part. When nanobeam electron diffraction is performed on the nc-OS film, a spot is observed. Distributed multiple spots are observed.

[0194] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher defect state density than the CAAC-OS film.

[0195] Next, the amorphous oxide semiconductor film will be described.

[0196] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline portion. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0197] In the amorphous oxide semiconductor film, no crystalline portion can be confirmed in a high-resolution TEM image.

[0198] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the analysis by the Lane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. Observed.

[0199] The oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may be used, particularly, for amorphous-like oxidation. Amorphous-like Oxide Semiconductor (a-like OS) The membrane is called a conductor membrane.

[0200] In the a-like OS film, voids are observed in high-resolution TEM images. In addition, crystals can be clearly seen in high-resolution TEM images. The a-like OS film has a region where the crystal part is not observed and a region where the crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed with a TEM, and the growth of the crystals can be seen. On the other hand, in the case of nc-OS films, crystallization does not occur due to the small amount of electron irradiation observed by TEM. It is rarely seen.

[0201] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a finely crystalline oxide semiconductor film. The film may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0202] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0203] (Sixth embodiment) An imaging device according to one embodiment of the present invention and a semiconductor device including the imaging device are used in a display device, a personal computer ... personal computers, image playback devices equipped with recording media (typically DVDs: Digital l Versatile Disc and other recording media can be played and images can be displayed on the disc. In addition, the imaging device according to one embodiment of the present invention can be used in a device having a display. Examples of electronic devices that can use the semiconductor device including the imaging device include a mobile phone, Game consoles including portable ones, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras, goggle-type displays (head-mounted displays), navigation audio systems, audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multi-function printers, automated teller machines (ATMs) , vending machines, medical testing equipment, etc. Specific examples of these electronic devices are shown in Figure 20. .

[0204] FIG. 20A shows a video camera, which includes a first housing 841, a second housing 842, a display unit 843, The operation key 844, the lens 845, the connection part 846, etc. 845 is provided in the first housing 841, and the display unit 843 is provided in the second housing 842. The first housing 841 and the second housing 842 are connected by a connecting portion 846. The angle between the first housing 841 and the second housing 842 can be changed by the connecting portion 846. The image on the display unit 843 is transmitted between the first housing 841 and the second housing 84 at the connection unit 846. 2. The focal point of the lens 845 is can be equipped with the imaging device according to one aspect of the present invention.

[0205] FIG. 20B shows a digital camera, which includes a housing 831, a shutter button 832, and a microphone 8 33, a light emitting part 837, a lens 835, etc. The imaging device may include an imaging device according to one embodiment of the present invention.

[0206] FIG. 20C shows a wristwatch-type information terminal, which includes a housing 821, a display unit 822, a wristband 8 The display unit 822 may be a touch panel. The imaging device of one embodiment of the present invention can be used for the laser 829.

[0207] FIG. 20(D) shows a radiation imaging system including a radiation source 805, a stand 803, a flat panel The detector 801 is provided. The radiation 807 emitted from the radiation source passes through the object 809. The light is then detected by a flat panel detector mounted on the mount 803, and an image can be obtained. The imaging device of one embodiment of the present invention can be used for the flat panel detector 801. do.

[0208] FIG. 20E shows a portable data terminal, which includes a first housing 811, a display unit 812, a camera 819, etc. The display unit 812 has a touch panel through which information can be input. The display unit has an image sensor function. The imaging device according to the embodiment can be used.

[0209] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can. [Explanation of symbols]

[0210] 300 boards 301 Transistor 302 Transistor 303 Transistor 304 Transistor 305 Charge storage section 306 Capacitor 311 Wiring 312 Wiring 313 Wiring 314 Wiring 315 Wiring 316 Wiring 317 Wiring 320 Photodiode 321 p-type semiconductor layer 322 i-type semiconductor layer 323 n-type semiconductor layer 325 Conductive Layer 326 Conductive Layer 334 Conductive Layer 335 Insulation Layer 336 Insulating Layer 337 Insulating Layer 338 Insulating Layer 339 Insulating Layer 340 Insulating Layer 350 pixels 350a pixels 350b pixels 350c pixels 351a pixels 351b pixels 351c pixels 501 signal 502 signal 503 signal 504 signal 505 signal 506 signal 507 signal 508 signal 509 signal 510 period 511 period 520 period 531 period 610 period 611 period 612 period 621 period 622 period 623 period 631 period 701 signal 702 signal 703 Signal 704 signal 705 signal 801 Flat Panel Detector 803 Mounting stand 805 Radiation source 807 Radiation 809 Subject 811 Case 812 Display section 819 Camera 821 Case 822 Display section 823 Wristband 825 Lens 829 Camera 831 Case 832 shutter button 833 Mike 835 Lens 837 Light-emitting part 841 Case 842 Case 843 Display section 844 Operation Key 845 Lens 846 Connection 900 boards 915 Insulation layer 920 gate electrode layer 930 Gate insulating film 931 Insulation Layer 932 Insulation layer 933 Insulation Layer 940 Oxide semiconductor layer 941a Oxide semiconductor layer 941b Oxide semiconductor layer 942a Oxide semiconductor layer 942b Oxide semiconductor layer 942c Oxide semiconductor layer 950 Source electrode layer 960 Drain electrode layer 980 Insulation Layer 990 Insulation layer 1530 Color Filter 1530a Color Filter 1530b color filter 1530c color filter 1540 Microlens Array 1550 Optical conversion layer 1700 pixel array 1730 circuits 1740 circuits 1750 circuits 1800 shift registers 1810 Shift Register 1900 Buffer Circuit 1910 Buffer circuit 2100 Analog Switch 2110 vertical output line 2200 output line

Claims

[Claim 1] An imaging device having a transistor, a photodiode, and a capacitance element, the transistor has a first electrode, a first insulating film in contact with the first electrode, a first semiconductor layer in contact with the first insulating film, and a second electrode and a third electrode in contact with the first semiconductor layer; the photodiode has a fourth electrode, a fifth electrode, and a second semiconductor layer between the fourth electrode and the fifth electrode; the first semiconductor layer has a region in contact with the second insulating layer; the second electrode has a region in contact with the second insulating layer, the third electrode has a region in contact with the second insulating layer, the second insulating layer has a region in contact with the third insulating layer; the third insulating layer has a region in contact with the fourth insulating layer, the fourth insulating layer has a region in contact with the fourth electrode, In a region overlapping with the first electrode, the third insulating layer has a region in contact with the fourth electrode, the fifth electrode is electrically connected to the second electrode; an imaging device, wherein the capacitive element has a region to which the third electrode extends, the second insulating layer, the third insulating layer, and the fourth electrode;

Images