Semiconductor device

Abstract

To provide a transistor which uses an oxide semiconductor having high electron field-effect mobility and less variation in threshold voltage and high reliability; and provide a semiconductor device which uses the transistor and achieves high performance difficult to achieve until now.SOLUTION: In a semiconductor device, an oxide semiconductor film containing two or more, favorably three or more elements selected from indium, tin, zinc and aluminum is used for a transistor. The oxide semiconductor film is deposited while hating a substrate. Further, in a making process of the transistor, oxygen is supplied to the oxide semiconductor film by a neighboring insulation film and / or ion implantation and oxygen deficiency which becomes a carrier generation source is reduced without limit. In addition, in the making process of the transistor, by highly purifying the oxide semiconductor film, a hydrogen concentration is extremely decreased.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a semiconductor element such as a transistor using an oxide semiconductor, The present invention relates to a method for producing the same.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, light-emitting display devices, and electronic devices are all semiconductor devices. [Background technology]

[0003] As typified by liquid crystal display devices, many of the transistors formed on glass substrates are non-transistors. It is made of amorphous silicon, polycrystalline silicon, etc. Although the field-effect mobility of the transistor is low, it can be used on large glass substrates. In addition, although the field effect mobility of transistors using polycrystalline silicon is high, the size of the glass substrate is large. It has the drawback that it is not suitable for area reduction.

[0004] In addition to transistors using silicon, transistors have recently been made using oxide semiconductors. The technology of fabricating oxide semiconductors and applying them to electronic and optical devices is attracting attention. The transistor was fabricated using zinc oxide and In-Ga-Zn-O oxide as the substrate. The technology used for switching elements of display pixels is disclosed in Patent Documents 1 and 2. It has been done.

[0005] A transistor using an oxide semiconductor film has a higher thermal conductivity than a transistor using amorphous silicon. When the organic compound is used, it has a high field-effect mobility, and therefore the performance of the display device can be significantly improved. It is expected to be.

[0006] On the other hand, for semiconductor devices that require high field-effect mobility in transistors, polycrystalline silicon Transistors using silicon or single crystal silicon are often used. When the transistor is used in a semiconductor device other than a display device, polycrystalline silicon or single crystal There is a demand for high field effect mobility comparable to that of silicon-based transistors.

[0007] A transistor using an In-Sn-Zn-O oxide with high field-effect mobility has been disclosed. (See Non-Patent Document 1). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Non-patent literature]

[0009] [Non-Patent Document 1] Eri Fukumoto, Toshiaki Arai, Narihiro Morosawa, Kazuhiko Tokunaga, Yasuhiro Terai, Takashige Fujimori and Tatsuya Sasaoka, "High Mobility Oxide Semiconductor TFT for Circuit Integration of AM-OLED", IDW'10 p631-p634 Summary of the Invention [Problem to be solved by the invention]

[0010] Even in semiconductor devices that require high field-effect mobility in transistors, transistors using oxide semiconductors are There is a possibility that a transistor can be applied.

[0011] However, transistors using oxide semiconductors have been difficult to pass through thermal bias tests (BT tests) and photo-induced degradation tests. Electrical characteristics may fluctuate due to bias testing, etc., making it difficult to say that the reliability is sufficient. stomach.

[0012] Therefore, we have developed a semiconductor device with high field-effect mobility, small variations in threshold voltage, and high reliability. An object of the present invention is to provide a transistor including an oxide semiconductor having a structure similar to that of the first embodiment.

[0013] In addition, it has high field-effect mobility, small variations in threshold voltage, and high reliability. By using a transistor having such a structure, a high-performance semiconductor device that has been difficult to realize until now is provided. This is one of the challenges. [Means for solving the problem]

[0014] The oxide semiconductor used in the transistor of one embodiment of the present invention contains indium, tin, zinc, and and aluminum.

[0015] In addition, in the manufacturing process of a transistor, the insulating film adjacent to the transistor and / or the ion implantation Oxygen is supplied to the oxide semiconductor, and oxygen vacancies that serve as carrier generation sources are reduced.

[0016] In addition, in the manufacturing process of a transistor, the oxide semiconductor is highly purified and used as a carrier generation source. The hydrogen concentration is made extremely low.

[0017] A method for manufacturing a transistor according to one embodiment of the present invention will be described below.

[0018] First, a process is carried out to reduce impurities such as hydrogen adsorbed on the substrate surface, and then an underlying insulating film is formed. Then, an oxide semiconductor film is formed, and then a first heat treatment is performed. The film is an insulating film that releases oxygen when heated. In this case, it is not necessary to carry out a process for reducing impurities adsorbed on the substrate surface.

[0019] The treatment for reducing impurities adsorbed on the substrate surface may be, for example, a plasma treatment, a heat treatment, or A chemical treatment is carried out. Preferably, a plasma treatment is carried out. Specifically, the plasma treatment is carried out using a rare gas ( Helium, neon, argon, krypton, xenon, etc.), atmosphere containing oxygen or nitrogen Plasma is generated in the atmosphere, and a bias voltage is applied to the substrate to treat the substrate surface. By reducing the impurities on the substrate surface, the interface between the substrate and the underlying insulating film can be improved. The interface state density can be reduced. The interface state can cause fluctuations in the threshold voltage of a transistor. Therefore, by reducing the interface state density, the transistor density within the substrate surface can be reduced. This can prevent variations in threshold voltage and a decrease in reliability.

[0020] After processing to reduce impurities adsorbed on the substrate surface, an insulating film is formed on the substrate without exposure to the atmosphere. This is preferable because it prevents impurities from being re-adsorbed onto the substrate surface due to exposure to the atmosphere. It can be prevented.

[0021] By providing an insulating film that releases oxygen by heat treatment as a base insulating film, Oxygen deficiency occurring in the conductor film can be compensated for by a subsequent heat treatment. Oxygen vacancies in the semiconductor film act as a carrier generation source, and the threshold voltage of the resulting transistor This can be a factor in fluctuating pressure.

[0022] In addition, by providing a base insulating film that releases oxygen by heat treatment, the base insulating film and the oxide film The interface state density with the semiconductor film can be reduced. This can trap charges associated with transistor operation, reducing transistor reliability. This can cause a decrease in

[0023] It is preferable that the base insulating film has flatness. Specifically, the average surface roughness (Ra) is The thickness is 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. Chemical Mechanical Polishing (CMP) is used for the insulating film. A planarization treatment such as polishing may be performed. As a result, the interface between the base insulating film and the oxide semiconductor film is in a good condition, and therefore, the transistor to be obtained can be This improves the field effect mobility of the transistor and reduces the fluctuation in threshold voltage.

[0024] The oxide semiconductor film may be an In-Al-Sn-Zn-O based material, an In-Sn-Zn-O based material, In-Al-Zn-O based materials, Zn-Sn-O based materials, etc. are used. In particular, In-Sn- Zn-O based materials can be used to develop transistors with high field-effect mobility and high reliability. This is preferable because

[0025] Note that when an oxide semiconductor film is formed while heating the substrate, the field-effect transition of the obtained transistor is improved. The substrate heating temperature during the formation of the oxide semiconductor film is preferably 100 ° C. or higher and 600 ° C. or lower, preferably 150 ° C. or higher and 550 ° C. or lower, more preferably 200 ° C. The oxide semiconductor film is preferably formed by a sputtering method. stomach.

[0026] Note that the oxide semiconductor film has a conductivity of 2.5 eV or more, preferably 2.8 eV or more, and more preferably The oxide semiconductor film has a band gap of 3.0 eV or more. By providing the step, a transistor with extremely low off-state current can be obtained.

[0027] The oxide semiconductor film may be in a single-crystal, polycrystalline (also referred to as polycrystalline), amorphous, or other state. Take a stance.

[0028] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0029] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor film with a crystalline-amorphous mixed phase structure in which the amorphous phase contains crystalline and amorphous parts. The crystal part must be small enough to fit inside a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the amorphous part contained in the CAAC-OS film were The boundary between the crystal and the CAAC-OS film is not clear. Therefore, the CAAC-OS film has no grain boundary. The resulting decrease in electron mobility is suppressed.

[0030] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the sphere or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. The range of 5° to 95° is also included. This also includes the range of 10° to 5°.

[0031] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0032] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0033] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0034] After the oxide semiconductor film is formed, first heat treatment is preferably performed. Atmospheric atmosphere (10 Pa or less), inert atmosphere (atmosphere consisting of inert gases such as nitrogen and rare gases) Or an oxidizing atmosphere (containing oxidizing gases such as oxygen, ozone, or nitrous oxide at 10 ppm or more) In the atmosphere), the temperature is 250°C or higher and 650°C or lower, preferably 300°C or higher and 600°C or lower. It is done by temperature.

[0035] The first heat treatment can reduce the concentration of impurities such as hydrogen in the oxide semiconductor film. Alternatively, the interface between the base insulating film and the oxide semiconductor film can be in a good state. Since the first heat treatment is performed after the semiconductor film is formed, oxygen released from the base insulating film is It is possible to prevent the diffusion of the metal in the direction of the arrow. After that, the atmosphere may be changed without lowering the temperature, and heat treatment may be carried out in an oxidizing atmosphere. By carrying out the heat treatment in this manner, oxide semiconductors can be formed in an inert atmosphere or a reduced pressure atmosphere. The impurities are reduced from the film, and then oxygen vacancies that occurred during the impurity removal are filled in an oxidizing atmosphere. can be reduced.

[0036] For the heat treatment and film formation, gases containing few impurities, especially gases containing little moisture, are used. Specifically, a gas with a dew point of −70° C. or less may be used.

[0037] After the first heat treatment, the oxide semiconductor film is processed into an island shape. The process involves forming a resist mask using a photomask, and then etching the resist using a dry etching method or a wet etching method. The area other than the area where the resist mask is formed may be etched by etching. The processing step is called a photolithography step.

[0038] Next, a conductive film is formed and processed by a photolithography process or the like to form an oxide semiconductor film. A source electrode and a drain electrode are formed so that at least a portion of the electrodes contact each other.

[0039] Next, a gate insulating film and a conductive film are formed in this order, and the conductive film is then formed by a photolithography process or the like. The gate insulating film is processed to form a gate electrode overlapping with the oxide semiconductor film. It is preferable to use an insulating film that releases oxygen by heat treatment.

[0040] Next, a second heat treatment is performed. The second heat treatment may be performed under the same conditions as the first heat treatment. By performing the second heat treatment, oxygen is released from the base insulating film and the gate insulating film, The oxygen vacancies in the oxide semiconductor film can be reduced. The density of states and the density of interface states between the oxide semiconductor film and the gate insulating film can be reduced. , increasing the field effect mobility of the resulting transistor and reducing the variation in threshold voltage; Furthermore, reliability can be improved.

[0041] By the above method, it is possible to obtain a semiconductor device with high field-effect mobility, small variations in threshold voltage, and high reliability. Therefore, a transistor including an oxide semiconductor having high conductivity can be manufactured.

[0042] It is preferable to provide an interlayer insulating film covering the transistor. As a result, oxygen released from the underlying insulating film and gate insulating film diffuses outward from the transistor. When an interlayer insulating film is provided, the second heat treatment is performed after the interlayer insulating film is formed. A heat treatment may be carried out.

[0043] The transistor preferably has a top-gate structure. It is preferable to use a structure in which the gate electrode is formed later. A gate electrode having a channel region, a source region, and a drain region is formed in a self-aligned manner with a mask. The oxide semiconductor film can be formed by forming a gate electrode, a source region, and a drain region. Since there is almost no overlap between the transistors, the parasitic capacitance can be reduced. In addition, by using the gate electrode as a mask, the channel region can be No photomask is required to form the silicon dioxide, source and drain regions. However, this does not exclude a bottom gate structure.

[0044] The transistor thus obtained has a high field-effect mobility (e.g., Mobility is 31cm 2 / Vs or more), the variation in threshold voltage is small and it has high reliability. (For example, the fluctuation range of the threshold voltage in the negative BT test is 1V or less), and the off-current is It can be made extremely small (for example, when the channel length is 3 μm and the substrate temperature is 85°C, The off-state current per 1 μm of channel width is 10 μA or less, which has been difficult to achieve until now. Therefore, it becomes possible to manufacture a semiconductor device with high performance. [Effects of the Invention]

[0045] According to one embodiment of the present invention, a semiconductor device having high field-effect mobility and small variation in threshold voltage can be obtained. It is possible to provide a highly reliable transistor including an oxide semiconductor.

[0046] Furthermore, by using the transistors obtained in this way, high performance transistors that have been difficult to achieve until now can be realized. Therefore, a semiconductor device having high performance can be provided. [Brief explanation of the drawings]

[0047] [Figure 1] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 2] 1A to 1C illustrate a method for manufacturing the transistor shown in FIG. [Figure 3] 1A to 1C illustrate a method for manufacturing the transistor shown in FIG. [Figure 4] 1A to 1C illustrate a method for manufacturing the transistor shown in FIG. [Figure 5] 1A and 1B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 6] 6A to 6C illustrate a method for manufacturing the transistor shown in FIGS. [Figure 7] 6A to 6C illustrate a method for manufacturing the transistor shown in FIGS. [Figure 8] 1A to 1C are cross-sectional views illustrating a manufacturing method of a semiconductor device according to one embodiment of the present invention, a circuit diagram, and a diagram illustrating electrical characteristics. [Figure 9] 1A to 1C are cross-sectional views illustrating a manufacturing method of a semiconductor device according to one embodiment of the present invention, a circuit diagram, and a diagram illustrating electrical characteristics. [Figure 10] 1A and 1B are a block diagram and a partial circuit diagram illustrating a specific example of a CPU including a transistor according to one embodiment of the present invention. [Figure 11] FIG. 10 is a perspective view illustrating an example of an electronic device according to one embodiment of the present invention. [Figure 12] 1A and 1B are a top view and a cross-sectional view illustrating a structure of a transistor. [Figure 13] 10 shows the Vgs-Ids characteristics and field-effect mobility of the transistors of Sample 1 and Sample 2. FIG. [Figure 14] 10 shows the Vgs-Ids characteristics and field-effect mobility of the transistors of Sample 3 and Sample 4. FIG. [Figure 15] 10 is a graph showing Vgs-Ids characteristics of a transistor of Sample 1 before and after a BT test. [Figure 16] FIG. 10 is a graph showing Vgs-Ids characteristics of a transistor of Sample 4 before and after a BT test. [Figure 17] 10A and 10B are graphs showing changes in Vgs-Ids characteristics and field-effect mobility depending on the measurement temperature of the transistor of Sample 4. [Figure 18] 10 shows the relationship between the threshold voltage and the field-effect mobility of the transistor in Sample 4 and the substrate temperature. [Figure 19] FIG. 1 shows an XRD spectrum of an In—Sn—Zn—O film. [Figure 20] TEM cross-sectional image of an In-Sn-Zn-O film. [Figure 21] TEM cross-sectional image of an In-Sn-Zn-O film. [Figure 22] FIG. 10 shows the off-state current of a transistor including an In-Sn-Zn-O film. [Figure 23] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 24] 1A and 1B are diagrams illustrating a crystal structure of an oxide semiconductor according to one embodiment of the present invention. [Figure 25] FIG. 10 is a graph illustrating the Vgs dependence of the field-effect mobility obtained by calculation. [Figure 26] FIG. 10 is a graph illustrating the Vgs dependence of Ids and field-effect mobility obtained by calculation. [Figure 27] FIG. 10 is a graph illustrating the Vgs dependence of Ids and field-effect mobility obtained by calculation. [Figure 28] FIG. 10 is a graph illustrating the Vgs dependence of Ids and field-effect mobility obtained by calculation. DETAILED DESCRIPTION OF THE INVENTION

[0048] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using drawings, The symbols are used in common between different drawings. When referring to the same thing, the hatch pattern is used. In some cases, the same symbol is not attached.

[0049] The terms used in this specification will be briefly explained below.

[0050] Regarding the source and drain of a transistor, when one is called the drain, the other is called the source. In other words, they are not distinguished by whether the potential is high or low. The part referred to as a source may be read as a drain.

[0051] Voltage often refers to the potential difference from a reference potential (for example, ground potential (GND)). Therefore, the terms voltage and potential may be interchanged.

[0052] Although it is expressed as "connecting," there is no physical connection in the actual circuit, and it is just wiring. may be extended.

[0053] The ordinal numbers such as 1st and 2nd are used for convenience and indicate the order of processes or stacking. It is not intended to indicate a specific name for identifying the invention.

[0054] (Embodiment 1) In this embodiment, examples of transistors according to one embodiment of the present invention will be described with reference to FIGS. We will explain using the following terms.

[0055] Figure 1 shows a top view and a cross-sectional view of a transistor with a top-gate / top-contact structure. Figure 1(A) shows a top view of the transistor. Figure 1(B) shows the dot-chain structure of Figure 1(A). A cross section AB corresponding to the line AB is shown.

[0056] The transistor shown in FIG. 1B includes a base insulating film 102 provided over a substrate 100 and a base insulating film 103 provided over a substrate 100. A protective insulating film 104 is provided around the insulating film 102, and the base insulating film 102 and the protective insulating film An oxide semiconductor having a high resistance region 106a and a low resistance region 106b formed on the film 104. A conductive film 106, a gate insulating film 108 provided on the oxide semiconductor film 106, and a gate insulating film a gate electrode 110 overlapping with the oxide semiconductor film 106 with an insulating film 108 interposed therebetween; A sidewall insulating film 112 is provided in contact with the side surface of the gate electrode 110, and at least an oxide semiconductor A pair of electrodes 114 provided in contact with the oxide semiconductor film 106, and a gate insulating film 116 An interlayer insulating film 116 is provided to cover the port electrode 110 and the pair of electrodes 114, and an interlayer insulating film The insulating film 116 is connected to at least one of the pair of electrodes 114 through an opening formed therein. and a wiring 118.

[0057] Although not shown, a protective film is provided to cover the interlayer insulating film 116 and the wiring 118. By providing the protective film, the surface conduction of the interlayer insulating film 116 can be prevented. This can reduce the minute leakage current that occurs, and the off-state current of the transistor can be reduced. The protective film can be made of acrylic resin, polyimide resin, epoxy resin, and silicone. The resin may be selected from the group consisting of polyethylene terephthalate resins and polyethylene terephthalate resins.

[0058] In a broad sense, the off-state current refers to the drain current that flows when a transistor is in the off state. The off state of an n-channel transistor is when the gate voltage is below the threshold voltage. In p-channel transistors, the gate voltage is lower than the threshold voltage. The drain current is the current between the source and drain of a transistor. The gate voltage is the potential difference between the gate potential and the source potential. It means difference.

[0059] In a normally-off transistor, the off-state current flows when the gate voltage is 0V. Normally-off transistors are n-channel transistors. In the case of a p-channel transistor, the threshold voltage is greater than 0V. A gate-type transistor with a threshold voltage of less than 0V.

[0060] The thickness of the oxide semiconductor film 106 is greater than or equal to 1 nm and less than or equal to 40 nm. nm or more and 20 nm or less. In particular, for transistors with a channel length of 30 nm or less In other words, the short channel effect can be suppressed by setting the thickness of the oxide semiconductor film 106 to about 5 nm. As a result, stable electrical characteristics can be obtained.

[0061] The oxide semiconductor film 106 may be made of, for example, an In—Al—Sn—Zn—O-based material, In—Sn -Zn-O based materials, In-Al-Zn-O based materials, Zn-Sn-O based materials, etc. Here, for example, an In-Sn-Zn-O based material contains indium, tin, and zinc. The composition ratio of the oxide semiconductor film is not particularly limited. By using this for 106, a transistor with high field effect mobility can be obtained.

[0062] The oxide semiconductor film 106 has a band gap of 2 A material having a refractive index of 0.5 eV or more, preferably 2.8 eV or more, and more preferably 3.0 eV or more is selected. By using the oxide semiconductor film 106 whose band gap is in the above range, The off-state current of the transistor can be reduced.

[0063] Note that the oxide semiconductor film 106 contains reduced amounts of hydrogen, alkali metals, alkaline earth metals, and the like. The oxide semiconductor film 106 preferably has an extremely low impurity concentration. When 106 contains the above-mentioned impurities, the recombination in the band gap occurs due to the level formed by the impurities. This causes an increase in the off-state current of the transistor.

[0064] The hydrogen concentration in the oxide semiconductor film 106 was measured by secondary ion mass spectrometry (SIMS). ry Ion Mass Spectrometry) is 5 × 10 19 cm -3 Less than 5 x 10 18 cm -3 Less than or equal to 1×10 18 cm -3 below , and more preferably 5 × 10 17 cm -3 The following applies.

[0065] The alkali metal concentration in the oxide semiconductor film 106 was measured by SIMS. Degrees are 5 x 10 16 cm -3 Less than 1 × 10 16 cm -3 The following is more preferably is 1 x 10 15 cm -3 Similarly, the lithium concentration is 5×10 15 cm -3 Below Below, preferably 1 x 10 15 cm -3 Similarly, the potassium concentration is 5 x 10 1 5 cm -3 Less than 1 × 10 15 cm-3 The following applies.

[0066] The above-described transistor including the oxide semiconductor film 106 has high field-effect mobility and The field effect mobility of the transistor is 31 cm 2 / Vs or higher, or 40cm 2 / Vs or more, 60cm 2 / Vs or more, 80cm 2 / Vs or more or 10 0cm 2 / Vs or more, for example, the channel length is 3 μm and the channel width is 1 μm The off-state current at -18 Below A, 1×10 -21 A or less or 1 x 10 -24 It can be A or less.

[0067] The oxide semiconductor film 106 is preferably non-single-crystal. When oxygen vacancies occur in the oxide semiconductor film 106 due to the influence of heat or the like, If the material is a perfect single crystal, there is no interstitial oxygen to compensate for the oxygen vacancies, so the oxide Carriers are generated in the semiconductor film 106 due to the oxygen vacancies. The threshold voltage of the transistor may shift in the negative direction.

[0068] The oxide semiconductor film 106 preferably has crystallinity. For example, it is a polycrystalline film or a CAAC film. -OS membrane is used.

[0069] An example of the crystal structure contained in the CAAC-OS film is shown in detail in Figs. 23 and 24. 23 and 24, the upward direction is the c-axis direction, and the c The plane perpendicular to the axial direction is the ab plane. When simply referring to the upper half and the lower half, the ab plane is used as the boundary. In Figure 23, the circled O is a tetrahedron. O, and a double circled O indicates a three-coordinate O.

[0070] Figure 23(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms (hereafter referred to as 4) adjacent to the In atom. The structure has a metal atom with a coordinated oxygen atom. The structure shown here is called a small group. The structure in Figure 23(A) is an octahedral structure. However, for simplicity, the structure is shown as a plane. Each of the groups has three tetracoordinated O atoms. The small group shown in Figure 23(A) has a charge of 0. .

[0071] Figure 23(C) shows a structure with one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 23(C) contains one tetracoordinate O atom, and the lower half contains three tetracoordinate O atoms. Or, in Figure 23(C), there are three 4-coordinate O atoms in the upper half and one 4-coordinate O atom in the lower half. There may be a coordinated O. The small group shown in Figure 23(C) has a charge of 0.

[0072] FIG. 23(B) shows a structure having one hexacoordinated Sn atom and six tetracoordinated O atoms adjacent to the Sn atom. The upper half of Figure 23(B) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 23(B) has a charge of +1.

[0073] Figure 23(D) shows a small group containing two Zn atoms. The upper half of Figure 23(D) shows one Zn atom. The small group shown in Figure 23(D) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. The charge is -1. Figure 23(E) shows one pentacoordinate In atom and three tricoordinate In atoms adjacent to the In atom. The structure shows a tetracoordinated O atom and two tetracoordinated O atoms adjacent to In. The upper and lower halves of Figure 23(E) each contain one tetrahedral valence atom. The small group shown in Figure 23(E) has a charge of 0.

[0074] Here, we refer to a collection of small groups as a medium group, and a collection of multiple medium groups as a The body is called a large group (also called a unit cell).

[0075] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the hexacoordinated In atom have three neighboring In atoms in the downward direction, and the lower half Each of the three O atoms has three adjacent In atoms in the upward direction. One O in the upper half of n has one neighboring Zn in the downward direction, and the three O in the lower half have There are three adjacent Zn atoms above the metal atom. The number of neighboring metal atoms below the O is equal, and similarly, the number of four-coordinated O atoms below the metal atom is The number of O atoms is equal to the number of neighboring metal atoms above the O atom. The sum of the number of neighboring metal atoms and the number of neighboring metal atoms above is 4. Therefore, The number of tetrahedral O atoms above a metal atom and the number of tetrahedral O atoms below another metal atom When the sum of these is four, two small groups containing metal atoms can bond together. For example, when a hexacoordinated metal atom (In or Sn) is bonded via a tetracoordinated O atom in the lower half, In this case, there are three tetracoordinated O atoms, so there are five-coordinated metal atoms (In) or four-coordinated metal atoms ( Zn).

[0076] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinated oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0077] Figure 24(A) shows an example of a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 24(B) shows a large group consisting of three medium groups. 4(C) shows the atomic arrangement when the layer structure of FIG. 24(B) is observed from the c-axis direction.

[0078] In FIG. 24(A), for simplicity, the tricoordinate O atoms are omitted, and only the number of the tetracoordinate O atoms is shown. For example, the circle indicates that there are three tetrahedral O atoms in the upper and lower halves of Sn. Similarly, in FIG. 24(A), the upper and lower halves of In are There is one tetracoordinate O in each of them, which is shown as a circled 1. Similarly, in Figure 24 In (A), there is one tetracoordinate O in the bottom half and three tetracoordinate O in the top half. Zn with one tetrahedral O atom in the top half and three tetrahedral O atoms in the bottom half. This shows that:

[0079] In FIG. 24(A), the middle group, which is composed of an In-Sn-Zn-O system layer structure, is Sn has three tetrahedral O atoms in the upper half and three in the lower half, and one tetrahedral O atom in the upper half. In is bonded to the In in the upper and lower halves, and the In is bonded to the Z n, and three tetracoordinate O atoms bond to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. and In in the lower half, which is bonded to Zn2 with one tetrahedral O in the upper half. It bonds to a small group consisting of 4, 4, and 4 through one 4-coordinate O in the lower half of this small group. Three O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple loops are connected to form a large group. The medium groups that make up the large group are However, not all of the groups have the same composition.

[0080] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6 67, -0.5. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, the layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. The structure that takes on a charge of -1 is as follows: As shown in Figure 23(D), there is a small group containing two Zn atoms. For example, Sn If there is one small group containing two Zn atoms for every one containing one Zn atom, the charges will cancel out. Therefore, the total charge of the layer structure can be set to zero.

[0081] Specifically, the large group shown in FIG. 24(B) is repeated to form In-Sn-Zn -O system crystal (In2SnZn3O8) can be obtained. -Zn-O system layer structure is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be expressed by the composition formula:

[0082] In addition to these, In-Al-Sn-Zn-O based materials, In-Al-Zn-O based materials The same applies to the case where an Sn-Zn-O based material is used.

[0083] The CAAC-OS film is easily formed when the underlying film is flat. Roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. The Ra is defined in JIS B0601. It is a three-dimensional extension of the centerline average roughness that is currently used, so that it can be applied to surfaces. It can be expressed as "the average of the absolute values ​​of the deviations from the specified surface to the target surface" and is defined by formula (1).

[0084]

number

[0085] In the formula (1), S0 is the measurement plane (coordinates (x1, y1) (x1, y2) (x2 ,y1) (the rectangular region bounded by the four points represented by (x2,y2)), Z0 refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0086] The transistor shown in FIG. 1B is formed by self-aligning oxide film using the gate electrode 110 as a mask. The low-resistance regions 106b of the nitride semiconductor film 106 (which are the source and drain regions of the transistor, respectively) The high-resistance region 106a (which functions as a drain region of the transistor) Therefore, it is possible to obtain a fine transistor. In addition, a photoresist for forming the low resistance region 106b and the high resistance region 106a can be used. The lithography process can be omitted, reducing the costs associated with the photolithography process. Furthermore, the low resistance region 106b and the gate electrode 110 are almost completely separated. Since there is almost no overlap, the parasitic capacitance formed by the low resistance region 106b and the gate electrode 110 This prevents the transistor from operating at high speed.

[0087] The transistor shown in FIG. 1B has the sidewall insulating film 112, and therefore, the transistor is turned on. In this state, a current flows from the pair of electrodes 114 to the high resistance region 106 via the low resistance region 106b. The current flows through the low resistance region 106b, which reduces the electric field concentration. Even in fine transistors with short channel lengths, degradation such as hot carrier degradation can be suppressed. This can control the load and improve reliability.

[0088] Note that in the transistor illustrated in FIG. 1, the oxide semiconductor film 106 overlaps with the sidewall insulating film 112. The low resistance region 106b includes, but is not limited to, the region where the oxide The region of the semiconductor film 106 that overlaps with the sidewall insulating film 112 is included in the high resistance region 106a. Such a structure also reduces the above-mentioned hot carrier degradation and other degradation. It can be reduced.

[0089] The base insulating film 102 is preferably an insulating film that releases oxygen by heat treatment.

[0090] The base insulating film 102 is required to have a sufficiently flat surface so that the crystals of the oxide semiconductor film 106 can be easily grown. It is preferable that the polymer has a flat property.

[0091] The base insulating film 102 is made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or silicon oxide. Aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, iridium oxide tritium oxide, lanthanum oxide, cesium oxide, tantalum oxide, and magnesium oxide The above may be selected and used as a single layer or a laminate.

[0092] Silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen. For example, oxygen is 50 atomic % or more and 70 atomic % or less, and nitrogen is 0.5 atomic % or more and 15 atomic % or less , silicon is in the range of 25 atomic % to 35 atomic % and hydrogen is in the range of 0 atomic % to 10 atomic % Silicon nitride oxide refers to a material containing more nitrogen than oxygen in its composition. For example, oxygen is 5 atomic % or more and 30 atomic % or less, and nitrogen is 20 % or more and 55 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen is 10 atomic % or more and 25 atomic % or less. However, the above range is based on the Rutherford method. Rutherford Backscattering Spectroscopy (RBS) rometry) and Hydrogen Forward Scattering (HFS) This is measured using Scattering Spectrometry (SCST). The composition of the constituent elements has a value in which the total does not exceed 100 atomic %.

[0093] "Oxygen is released by heat treatment" refers to TDS (Thermal Desorption / Stimulation Spectroscopy (thermal desorption spectroscopy) analysis, converted to oxygen atoms The amount of oxygen released is 1.0×10 18 atoms / cm 3 Above, especially 3.0 x 10 20 ato ms / cm 3 This means that the above is the case.

[0094] Here, a method for measuring the amount of released oxygen using TDS analysis will be described below.

[0095] The total amount of released gas during TDS analysis is proportional to the integral value of the ion intensity of the released gas. The total amount of released gas can then be calculated by comparing this integral value with that of a standard sample.

[0096] For example, the TDS analysis results of a silicon wafer containing a specified density of hydrogen as a standard sample, and From the results of TDS analysis of the insulating film, the amount of oxygen molecules released from the insulating film (N O2 ) is expressed in equation (2). Here, all the gases detected at mass number 32 obtained by TDS analysis can be calculated. It is assumed that the mass number is derived from oxygen molecules. There is also CH3OH, which has a mass number of 32. It is unlikely that this will occur, so it will not be considered here. The oxygen atom with mass number 7 and the oxygen molecule with mass number 18 also exist in nature. The proportion of this product is extremely small and therefore not taken into consideration.

[0097]

number

[0098] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the insulating film is analyzed by TDS. α is a coefficient that affects the ion intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. The amount of oxygen released from the insulating film is Using a thermal desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Corporation, 1×10 16atoms / cm 3 measured using a silicon wafer containing hydrogen atoms .

[0099] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen atoms is included in the calculation, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0100] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount released.

[0101] In the above structure, the film that releases oxygen by heat treatment is silicon oxide (S iO X (X>2)) or silicon oxide (SiO X (X>2) It means that the number of oxygen atoms per unit volume is more than twice the number of silicon atoms. The number of silicon atoms and oxygen atoms per volume was measured by Rutherford backscattering spectroscopy. This is the value.

[0102] Oxygen is supplied from the base insulating film 102 to the oxide semiconductor film 106, The interface state density between the insulating film 106 and the underlying insulating film 102 can be reduced. Due to the action of the oxide semiconductor film 106, carriers are trapped at the interface between the oxide semiconductor film 106 and the base insulating film 102. This makes it possible to suppress the deterioration of the electrical characteristics of a transistor. can.

[0103] Furthermore, charge may be generated due to oxygen vacancies in the oxide semiconductor film 106. The oxygen vacancies in the compound semiconductor film act as donors and emit electrons, which are carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. The oxide semiconductor film 106 is preferably supplied with oxygen from the film 102. The excess oxygen in 106 causes the threshold voltage to shift in the negative direction. This can reduce oxygen vacancies in the oxide semiconductor film 106, which is a cause of the problem.

[0104] The protective insulating film 104 is heated to a temperature of 250° C. or higher and 450° C. or lower, preferably 150° C. or higher and 800° C. or lower. It has the property of not allowing oxygen to pass through even after heat treatment for one hour in the temperature range of This is preferable.

[0105] Due to the above-mentioned properties, the protective insulating film 104 is provided around the base insulating film 102. When the heat treatment is performed, oxygen released from the base insulating film 102 by the heat treatment flows outside the transistor. In this way, oxygen is held in the base insulating film 102. Therefore, it is possible to prevent a decrease in the field effect mobility of the transistor and reduce the variation in the threshold voltage. This can improve reliability.

[0106] However, a structure in which the protective insulating film 104 is not provided can also be adopted.

[0107] The protective insulating film 104 is made of silicon oxynitride, silicon nitride, aluminum oxide, or aluminum nitride. nium, hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, cerium oxide Select one or more of sodium oxide, tantalum oxide and magnesium oxide and form a single layer or multilayer. Just use it.

[0108] A flexible substrate may also be used as the substrate 100. The method of providing a transistor is to fabricate a transistor on a non-flexible substrate and then Alternatively, the resistor may be peeled off and transferred to the flexible substrate 100. A release layer may be provided between the non-flexible substrate and the transistor.

[0109] The gate electrode 110 is made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, T and W, and their nitrides, oxides and alloys, in a single layer or laminated form. Alternatively, an oxide or oxynitride containing at least In and Zn may be used. For example, an In-Ga-Zn-ON material may be used.

[0110] The gate insulating film 108 is formed by the same method and with the same material as the base insulating film 102. That's fine.

[0111] The pair of electrodes 114 may be formed by the same method and with the same material as the gate electrode 110. That's fine.

[0112] The interlayer insulating film 116 may be formed by the same method and with the same material as the base insulating film 102. The interlayer insulating film 116 may be made of a resin material (polyimide resin, acrylic resin, etc.). ) may be laminated. It is relatively easy to form a thick film of a resin material, and Photosensitive resin is a suitable material for the interlayer insulating film 116 because it is easy to process.

[0113] The wiring 118 may be formed by the same method and using the same material as the gate electrode 110. .

[0114] The field-effect mobility of a transistor will be described below with reference to FIGS.

[0115] The field-effect mobility of transistors, not limited to oxide semiconductors, is often lower than originally intended for various reasons. The measured field-effect mobility is lower than the expected field-effect mobility. These include defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Using the Vinson model, the field effect mobility assuming there are no defects inside the semiconductor is calculated as follows: Derived theoretically.

[0116] Let μ0 be the field-effect mobility of the original transistor, and let us consider the existence of some potential barrier in the semiconductor. The field-effect mobility μ measured when it is assumed that there are grain boundaries (grain boundaries, etc.) is expressed by the formula (3): can be.

[0117]

number

[0118] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. In the Levinson model, it is assumed that the height E of the potential barrier comes from defects. is determined and expressed by equation (4).

[0119]

number

[0120] where e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the The dielectric constant, n, is the carrier density per unit area of ​​the channel, C ox is the gate per unit area Insulating film capacitance, V gs is the gate voltage, and t is the channel thickness. In the case of the following semiconductor layers, the thickness of the channel may be the same as the thickness of the semiconductor layer.

[0121] Drain current I in the linear region ds is expressed by Equation (5).

[0122]

number

[0123] Here, L is the channel length and W is the channel width, and here, L and W are set to 10 μm. Also, V ds is the drain voltage.

[0124] Taking the logarithm of both sides of equation (5) gives equation (6).

[0125]

number

[0126] The right side of equation (6) is V gs Since it is a function of ds / V gs ), the horizontal axis is 1 / V gs The defect density N can be calculated from the slope of the line gs - I ds The characteristic gives the defect density N in the semiconductor.

[0127] The defect density N in a semiconductor depends on the substrate temperature during semiconductor deposition. In-Sn-Zn with a ratio of n and Zn of In:Sn:Zn=1:1:1 [atomic ratio] When an oxide semiconductor film is formed using an -O target, the defect density in the oxide semiconductor N is 1 × 10 12 / cm 2 It will be about that amount.

[0128] Based on the defect density N in the oxide semiconductor described above, it is calculated using formulas (3) and (4). By calculation, the field effect mobility μ of the original transistor is 120 cm 2 / Vs. Therefore, there are no defects in the oxide semiconductor and at the interface between the oxide semiconductor and the gate insulating film. , the field effect mobility μ of an ideal transistor is 120 cm 2 / Vs. In oxide semiconductors with many defects, the field-effect mobility μ of transistors is 30 cm 2 / Vs degree degrees.

[0129] Even if there are no defects inside the semiconductor, the transistors may be scattered by the interface between the channel and the gate insulating film. The transport properties of the transistor are affected. The current at a distance x from the gate insulating film interface is The field effect mobility μ1 is expressed by the following equation (7).

[0130]

number

[0131] where D is the electric field strength due to the gate electrode, B is a constant, and l is the depth at which the effect of interface scattering occurs. B and l can be obtained by measuring the electrical characteristics of the transistor. From actual measurements of the electrical characteristics of transistors using compound semiconductors, B = 4.75 × 10 7 cm / s, l=10nm. When D increases, that is, V gs When becomes higher, Eq. (7) It can be seen that the field-effect mobility μ1 decreases as the second term increases.

[0132] An ideal oxide semiconductor with no defects in the oxide semiconductor and at the interface with the gate insulating film The results of calculating the field-effect mobility μ2 of such a transistor are shown in Figure 25. Using the Sentaurus Device manufactured by Nopsys, the band gap of oxide semiconductors The dielectric constant was set to 15, the electron affinity to 4.7 eV, the dielectric constant to 15, and the thickness to 15 nm. Furthermore, the work function of the gate is set to 5.5 eV, and the work functions of the source and drain are set to 4.6 eV. The thickness of the gate insulating film was set to 100 nm and the relative dielectric constant was set to 4.1. The length and width of the channel are both 10 μm. ds was set to 0.1V.

[0133] As shown in Figure 25, V gs is around 1V, the field effect mobility μ2 is 100cm 2 / Vs Although it has more than one peak, V gs As the temperature increases, the effect of interface scattering increases and the It can be seen that the field effect mobility μ2 decreases.

[0134] When such an ideal transistor is miniaturized, the calculation results are shown in Figs. This is shown in Figure 28. Note that the calculation is based on the assumption that the transistor has the structure shown in Figure 1(B). Here, the resistivity of the low resistance region 106b is set to 2×10 -3 Ωcm, and the width of the gate electrode 110 is set to 3 The width of the sidewall insulating film 112 is 5 nm, and the channel width is 40 nm. For convenience, the region is referred to as a high resistance region 106a. It is assumed to be an intrinsic semiconductor.

[0135] The calculation was performed using the Sentaurus Device manufactured by Synopsys. (B) I ds (solid line) and field-effect mobility μ (dotted line) Vgs It is a dependency. ds is V ds is set to 1V, and the field-effect mobility μ is V ds of The calculation is based on a voltage of 0.1 V. Here, the gate insulating film is assumed to be 15 nm thick. 6(A), 10nm is shown in Fig. 26(B), and 5nm is shown in Fig. 26(C). Each is shown.

[0136] From Figure 26, the thinner the gate insulating film, the lower the OFF state (here, V gs is -3V to 0V The drain current I ds On the other hand, the peak of the field-effect mobility μ value and ON state (here V gs indicates the range from 0V to 3V.) ds There is no noticeable change in V gs is around 1V and I ds is a semiconductor device This exceeds the 10 μA required for devices such as mori.

[0137] Similarly, the transistor shown in FIG. 1B is a transistor in which an oxide semiconductor layer overlaps with the sidewall insulating film 112. Regarding a transistor having a different structure in that the region of the semiconductor film 106 is included in the high resistance region 106a, In other words, the transistor is offset by the width of the sidewall insulating film 112. The width of the offset region is called the offset length (Lo Also called ff).

[0138] The region of the oxide semiconductor film 106 overlapping with the sidewall insulating film 112 is included in the high-resistance region 106a. In the case of a transistor with Loff set to 5 nm, the drain current I ds (Solid line) and field-effect mobility μ (dotted line) V gsThe dependency is shown in Figure 27. ds is V ds is set to 1V, and the field-effect mobility μ is V ds is calculated as 0.1V. The case where the thickness of the insulating film is 15 nm is shown in FIG. 27(A), and the case where the thickness is 10 nm is shown in FIG. 27(B). ) and 5 nm are shown in FIG. 27(C).

[0139] 28 shows the structure shown in FIG. 1(B) in which the oxide semiconductor layer overlapping the sidewall insulating film 112 is removed. In a transistor in which the region of the conductor film 106 is the high resistance region 106a, Loff is 15n m, the drain current I ds (solid line) and field-effect mobility μ (dotted line) gs Depends It is dependent. ds is V ds is set to 1V, and the field-effect mobility μ is V ds to 0.1V Here, when the thickness of the gate insulating film is 15 nm, the The case where the thickness is 10 nm is shown in FIG. 28(B), and the case where the thickness is 5 nm is shown in FIG. 28(C). show.

[0140] From the calculation results shown in Figures 27 and 28, similar to Figure 26, it can be seen that the gate insulating film is thin. The lower the voltage, the more the off-state (V gs The drain voltage at Flow I ds On the other hand, the peak value of the field-effect mobility μ and the on-state (here, V gs but The drain current I ds It can be seen that there is no noticeable change in .

[0141] The peak of the field-effect mobility μ is 80 cm in FIG. 2 / Vs, but Fig. 27 So 60cm 2 / Vs, 40cm in Figure 28 2 / Vs, as Loff increases It can be seen that the I ds It can be seen that the same tendency is observed. On the other hand, in the on state, ds decreases with increasing offset length Loff, but I ds The decrease in V is much slower than that in V. gs is 1 In the vicinity of V, I ds It can be seen that this exceeds the 10 μA required for memory, etc.

[0142] An example of a method for manufacturing the transistor illustrated in FIG. 1B is described below.

[0143] All of the films contain impurities such as hydrogen, which adversely affect the characteristics of transistors. It is preferable to form the film so that it is not broken.

[0144] For example, impurities adhering to the surface of the substrate 100 may be incorporated into the film. In order to prevent this, it is necessary to reduce impurities on the surface of the substrate 100 before forming the insulating base film 102. As the treatment for reducing impurities, a plasma treatment, a heat treatment or the like may be performed. or chemical treatment.

[0145] In addition, impurities originating from inside the film-forming equipment (film-forming chamber, etc.) can also be a problem, so It is preferable to remove impurities by baking the film forming chamber. Just leave it there.

[0146] In addition, the deposition chamber was previously used for dummy deposition for about 5 minutes on about 100 dummy substrates. It is more preferable to evacuate the film forming chamber after each dummy film formation. Dummy film formation is the process of forming a film on a dummy substrate by a method such as sputtering. A film is deposited on the dummy substrate and the inner wall of the film formation chamber, and the impurities in the film formation chamber and the absorption of the inner wall of the film formation chamber are measured. The dummy substrate is preferably made of a material that releases little gas. For example, the same material as the substrate 100 may be used. This can reduce the impurity concentration in the film.

[0147] Note that baking and dummy film formation in the film formation chamber are performed in the transistor manufacturing process. It is better to do this at a higher temperature than the temperature at which the material is heated. This can reduce the amount of impurities released during the heating process.

[0148] The purity of the gas used for film formation also affects the impurity concentration in the film, so it is recommended to use gas with as high purity as possible. It is especially preferable to use gas with a low moisture content. Gases with a temperature of 0°C or lower may be used. More preferably, for example, argon with a purity of 9N may be used. Gas (dew point -121℃, water 0.1ppb, hydrogen 0.5ppb) and oxygen gas with a purity of 8N A gas (dew point -112°C, water 1 ppb, hydrogen 1 ppb) is used.

[0149] First, a process for reducing impurities on the surface of the substrate 100 is performed. , without air exposure, sputtering method, evaporation method, plasma chemical vapor deposition (PCVD method) , pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy A base insulating film 152 is formed by using the CIE method (MBE method) or the like (see FIG. 2(A)).

[0150] The base insulating film 152 is preferably formed by sputtering at a substrate heating temperature of 20°C above room temperature. The temperature is set to 0°C or lower, preferably 50°C to 150°C, and the film is formed in an oxygen gas atmosphere. A rare gas may be added to oxygen gas, in which case the ratio of oxygen gas must be 30% by volume or more. The content is preferably 50% by volume or more, and more preferably 80% by volume or more. The thickness of the film is 100 nm or more and 1000 nm or less, preferably 200 nm or more and 700 nm or less. The lower the substrate heating temperature during film formation and the higher the oxygen gas ratio in the film formation atmosphere, the thicker the film. The thicker the base insulating film 152, the greater the amount of oxygen released when the base insulating film 152 is subjected to a heat treatment. The sputtering method can reduce the hydrogen concentration in the film compared to the PCVD method. The base insulating film 152 may be formed to a thickness exceeding 1000 nm, but this may reduce productivity. The thickness should be such that it does not interfere with the

[0151] Next, the base insulating film 152 is processed by a photolithography process or the like, and the base insulating film 10 2 is formed (see Figure 2(B)).

[0152] Next, sputtering, evaporation, PCVD, PLD, ALD, MBE, etc. A protective insulating film 154 is formed using the above (see FIG. 2(C)).

[0153] Next, a protective insulating film 104 having a surface level aligned with the base insulating film 102 is formed by CMP processing. The base insulating film 102 and the protective insulating film 104 are formed as follows (see FIG. 2(D)). At this time, the above-mentioned CMP process is performed to flatten the base insulating film 102. In addition to the planarization process by CMP, plasma processing may also be used. A planarization process using a polishing agent may be performed.

[0154] Next, sputtering, evaporation, PCVD, PLD, ALD, MBE, etc. The oxide semiconductor film 156 is formed using the above-mentioned method (see FIG. 2E).

[0155] The oxide semiconductor film 156 is preferably formed by a sputtering method at a substrate heating temperature of 100° C. or higher than 600°C, preferably higher than 150°C and lower than 550°C, and more preferably higher than 200°C The oxide semiconductor film 156 is formed in an oxygen gas atmosphere at a temperature of 500° C. or lower. The thickness is set to 100 nm or more and 40 nm or less, preferably 3 nm or more and 20 nm or less. The higher the concentration of impurities in the oxide semiconductor film 156, the lower the impurity concentration in the oxide semiconductor film 156. The atomic arrangement in the film 156 is aligned and densified, forming a polycrystalline film or CAAC-OS film. Furthermore, forming the film in an oxygen gas atmosphere also reduces the amount of excess atoms such as rare gases. However, since it does not contain any acid, it is easy to form a polycrystalline film or a CAAC-OS film. The atmosphere may be a mixture of oxygen and rare gases, in which case the proportion of oxygen gas must be 30% by volume or more. The content is preferably 50% by volume or more, and more preferably 80% by volume or more. The thinner the conductive film 156, the more the short channel effect of the transistor is reduced. If it is too high, the influence of interface scattering becomes strong, which may result in a decrease in field effect mobility.

[0156] The oxide semiconductor film 156 is formed by sputtering an In-Sn-Zn-O based material. In this case, the atomic ratio is preferably In:Sn:Zn=2:1:3, In:Sn:Zn=1: 2:2, In:Sn:Zn=1:1:1 or In:Sn:Zn=20:45:35 The In-Sn-Zn-O target is used, which has an atomic ratio close to that mentioned above. By depositing the oxide semiconductor film 156 using a Zn—O target, a polycrystalline film or CAAC-OS film is easily formed.

[0157] Next, a first heat treatment is performed. The first heat treatment is performed in a reduced pressure atmosphere, an inert atmosphere, or an oxidizing atmosphere. The first heat treatment is performed in a hydrogen atmosphere. It is possible.

[0158] The first heat treatment is performed in a reduced pressure atmosphere or an inert atmosphere, and then the temperature is maintained. It is preferable to switch to an oxidizing atmosphere and then further heat treatment. When heat treatment is performed in an inert atmosphere, the impurity concentration in the oxide semiconductor film 156 can be effectively reduced. However, oxygen deficiency occurs at the same time. Oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere.

[0159] The oxide semiconductor film 156 is formed by first heat treatment in addition to heating the substrate during film formation. As a result, the electric field of the transistor It is possible to increase the field effect mobility to a level close to the ideal field effect mobility described later.

[0160] Note that oxygen ions are implanted into the oxide semiconductor film 156, and the oxide semiconductor film 15 6, impurities such as hydrogen contained therein are released, and the heat treatment is carried out simultaneously with the heat treatment or after the heat treatment. The oxide semiconductor film 156 may be crystallized by a process (such as first heat treatment).

[0161] In the present invention, instead of the first heat treatment, a laser beam is irradiated to selectively oxidize the surface. Alternatively, the compound semiconductor film 156 may be crystallized by laser beam irradiation while the first heat treatment is being performed. The oxide semiconductor film 156 may be selectively crystallized by laser beam irradiation. In the case of laser beam irradiation, the irradiation is carried out in an inert atmosphere, an oxidizing atmosphere, or a reduced pressure atmosphere. , continuous wave laser beam (CW laser beam) or pulsed laser beam ( For example, an Ar laser, a Kr laser, or an electron beam can be used. Gas lasers such as ximer lasers, or single or polycrystalline YAG, YVO4, Rusterite (Mg2SiO4), YAlO3 or GdVO4 with N as dopant Doped with one or more of d, Yb, Cr, Ti, Ho, Er, Tm and Ta Lasers using a medium, or glass lasers, ruby ​​lasers, alexandrite lasers, Solid-state lasers such as Ti:sapphire lasers, or one or more of copper vapor or gold vapor lasers A vapor laser that oscillates can be used. The fundamental wave of such a laser beam, or By irradiating a laser beam of any one of the second harmonic to the fifth harmonic of the fundamental wave, oxide The semiconductor film 156 can be crystallized. It is preferable to use a material having a larger energy than the band gap of the body film 156. For example, Laser emitted from an excimer laser oscillator of KrF, ArF, XeCl, or XeF The laser beam may be linear.

[0162] It is also possible to perform laser beam irradiation multiple times under different conditions. For example, The first laser beam irradiation is performed in a rare gas atmosphere or a reduced pressure atmosphere, and the second laser beam When the irradiation of oxygen is performed in an oxidizing atmosphere, oxygen vacancies in the oxide semiconductor film 156 are reduced and high crystallinity is achieved. This is preferable because it provides good performance.

[0163] Next, the oxide semiconductor film 156 is processed by a photolithography process or the like to form an oxide semiconductor film. A membrane 166 is formed (see FIG. 2(F)).

[0164] Next, a gate insulating film 158 and a conductive film 160 are formed in this order (see FIG. 3(A)). The film formation method is either sputtering, evaporation, PCVD, PLD, ALD or The MBE method or the like can be used.

[0165] The gate insulating film 158 is preferably formed by the same method as the base insulating film 152 .

[0166] Next, the conductive film 160 is processed by a photolithography process or the like to form the gate electrode 110. (See FIG. 3(B)).

[0167] Next, using the gate electrode 110 as a mask, the oxide semiconductor film 1 The impurity 120 having the function of reducing the resistance value of the high resistance region 106a and The oxide semiconductor film 106 having the low-resistance region 106b is formed (see FIG. 3C). The impurity 120 may be phosphorus, nitrogen, boron, or the like. Then, a heat treatment is performed at a temperature of 250° C. to 650° C. The impurity 120 is an ion When doped using the implantation method, the oxide semiconductor is more dense than when doped using the ion doping method. This is preferable because it reduces the amount of hydrogen mixed into the conductive film 106. However, the ion doping method This does not exclude the following.

[0168] Note that the impurity 120 is added through the gate insulating film 158, so that the oxide semiconductor film Damage caused when doping the impurity 120 into the silicon substrate 106 can be reduced.

[0169] Next, the insulating film 162 is formed by a sputtering method, a vapor deposition method, a PCVD method, a PLD method, an ALD method, or The insulating film 162 is formed by using the MBE method or the like (see FIG. 3(D)). The film may be formed in the same manner as in 52.

[0170] Next, the insulating film 162 is etched to form the sidewall insulating film 112. The sidewall insulating film 112 is formed by etching the insulating film 162 with high anisotropy. By performing a highly efficient etching process, it is possible to form the film in a self-aligned manner. It is preferable to use an etching method. The etching gas used in the dry etching method is For example, trifluoromethane, octafluorocyclobutane, tetrafluoromethane, etc. Examples of fluorine-containing gases include etching gases containing rare gases or hydrogen. Dry etching is also suitable. It is preferable to use the RIE method.

[0171] After the sidewall insulating film 112 is formed, the gate insulating film 158 is processed to form the gate insulating film 108. (See FIG. 4(A)). Note that the gate insulating film can be formed in the same process as the formation of the sidewall insulating film 112. A gate insulating film 108 may also be formed.

[0172] Instead of the process immediately after the formation of the gate electrode 110, the gate insulating film 112 may be formed after the formation of the sidewall insulating film 112. The electrode 110 and the sidewall insulating film 112 are used as a mask (before the gate insulating film 108 is formed). In this case, the impurity 120 may be added to the oxide semiconductor film 166 (through the gate insulating film 158). In this way, the region of the oxide semiconductor film 106 overlapping with the sidewall insulating film 112 can be It can be included in the high resistance region 106a.

[0173] Next, a conductive film is formed by sputtering, evaporation, PCVD, PLD, ALD or MB. The conductive film is formed by a photolithography process or the like, and a pair of The electrode 114 is formed (see FIG. 4(B)).

[0174] Next, the interlayer insulating film 116 is formed by sputtering, evaporation, PCVD, PLD, or ALD. Alternatively, the film is formed by using an MBE method or the like, and openings are provided to expose the pair of electrodes 114. When a resin material is laminated on the interlayer insulating film 116, the resin material may be further deposited by spin coating or slitting. The resin material may be formed by using a coating method or the like. That's fine.

[0175] Next, a conductive film is formed by sputtering, evaporation, PCVD, PLD, ALD or MB. The conductive film is formed by a photolithography process or the like, and then Wirings 118 are formed in contact with the pair of electrodes 114 (see FIG. 4(C)). The interlayer insulating film 116 has a thickness of 20 nm or more, preferably 50 nm or more, at least in a part thereof. It is more preferable to use an aluminum oxide film having a thickness of 100 nm or more. By using an aluminum oxide film, hydrogen or water can be easily absorbed from the outside of the transistor. It is possible to prevent the intrusion of impurities that adversely affect the electrical characteristics of the transistor. This can prevent oxygen released from the film 102 from diffusing outward from the transistor. The effect depends on the quality of the aluminum oxide film, but a certain thickness is required. However, if the aluminum oxide film is too thick, productivity will decrease. It is preferable to select the thickness. Note that instead of the aluminum oxide film, a silicon nitride film or an oxide nitride film may be used. Silicon dioxide may also be used.

[0176] Here, a second heat treatment is performed. The second heat treatment is performed after the interlayer insulating film 116 is formed. The second heat treatment may be performed after forming the insulating film 18, or after forming the insulating film 18. In an air or oxidizing atmosphere, 150°C or higher and 550°C or lower, preferably 250°C or higher The second heat treatment is performed at a temperature of 400° C. or less. Oxygen is released from the oxide insulating film 108, and oxygen vacancies in the oxide semiconductor film 106 are reduced. In addition, the interface state density between the base insulating film 102 and the oxide semiconductor film 106 and the oxide The interface state density between the compound semiconductor film 106 and the gate insulating film 108 can be reduced. This makes it possible to reduce variations in the threshold voltage of the transistor and improve reliability. The second heat treatment may be replaced with the heat treatment performed after the addition of the impurities 120.

[0177] In addition, when a resin material is used for the interlayer insulating film 116, the resin material is subjected to a heat treatment and a second heat treatment. The heat treatment may be common.

[0178] Through the above steps, the transistor illustrated in FIG. 1B can be manufactured.

[0179] According to this embodiment, the semiconductor device has high field effect mobility, small variations in threshold voltage, and high To provide a transistor including an oxide semiconductor, which has high reliability and an extremely low off-state current. can be done.

[0180] Therefore, the transistor including the oxide semiconductor film described in this embodiment has a low off-state current. It has the property of being highly stable and has high field-effect mobility, so it can be used in transistors with high field-effect The present invention can also be applied to logic circuits that require high mobility.

[0181] This embodiment may be used in combination with other embodiment modes.

[0182] (Embodiment 2) In this embodiment, transistors having a structure different from that of Embodiment 1 will be described with reference to FIGS. We will explain using the following terms.

[0183] Figure 5 shows a top view and a cross-sectional view of a transistor with a top-gate / bottom-contact structure. Figure 5(A) shows a top view of the transistor. Figure 5(B) shows the dot-chain structure of Figure 5(A). A cross section AB corresponding to the line AB is shown.

[0184] The transistor shown in FIG. 5B is a transistor including a substrate 200 and a base insulating film provided on the substrate 200. 202, a pair of electrodes 214 provided in the groove of the base insulating film 202, and and a high resistance region 206a and a low resistance region 206b provided on a pair of electrodes 214. and a gate insulating film 20 provided on the oxide semiconductor film 206. 8 and a gate electrode 208 provided to overlap with the oxide semiconductor film 206 via a gate insulating film 208. an interlayer insulating film provided to cover the electrode 210, the gate insulating film 208, and the gate electrode 210; 216, and a film formed on the interlayer insulating film 216, the gate insulating film 208, and the oxide semiconductor film 206. and wiring 218 that connects to the pair of electrodes 214 through the openings. However, a protective film may be provided to cover the interlayer insulating film 216 and the wiring 218. By providing the protective film, minute cracks caused by surface conduction of the interlayer insulating film 216 are prevented. The peak current can be reduced.

[0185] The substrate 200, the base insulating film 202, the oxide semiconductor film 206, the gate insulating film 208, the gate The port electrode 210, the pair of electrodes 214, the interlayer insulating film 216, and the wiring 218 are each formed on a substrate. A plate 100, an underlying insulating film 102, an oxide semiconductor film 106, a gate insulating film 108, and a gate electrode 110, a pair of electrodes 114, an interlayer insulating film 116, and a wiring 118 are made of the same material and are similar to each other. The method may be as follows.

[0186] In the transistor shown in FIG. 5B, the pair of electrodes 214 are connected to the lower part of the oxide semiconductor film 206. This structure differs from the transistor shown in FIG. When forming the counter electrode 214, a part of the oxide semiconductor film 206 is exposed to plasma, chemicals, etc. Therefore, when the oxide semiconductor film 206 is formed thin (for example, This is a preferable structure when forming the film to a thickness of 5 nm or less.

[0187] An example of a method for manufacturing the transistor illustrated in FIG. 5B is described below.

[0188] First, a base insulating film 252 is formed on the substrate 200 (see FIG. 6(A)).

[0189] Next, the base insulating film 252 is processed to form the base insulating film 202 (see FIG. 6(B)).

[0190] Next, a conductive film 264 is formed (see FIG. 6(C)).

[0191] Next, a CMP process is performed to form a pair of electrodes 214 whose surface is flush with the base insulating film 202. (See Figure 6(D)).

[0192] Next, an oxide semiconductor film 256 is formed (see FIG. 6E).

[0193] Next, first heat treatment is performed. For details of the first heat treatment, refer to the description in Embodiment Mode 1.

[0194] Next, the gate insulating film 208 and the conductive film 260 are formed in this order (see FIG. 6(F)).

[0195] Next, the conductive film 260 is processed to form the gate electrode 210 (see FIG. 7(A)).

[0196] Next, using the gate electrode 210 as a mask, the oxide semiconductor film 2 The impurity 220 having the function of reducing the resistance value of the semiconductor layer 56 is added to form the high resistance region 206a and The oxide semiconductor film 206 having the low-resistance region 206b is formed (see FIG. 7B). Regarding the impurity 220, the material, doping method and the like of the impurity 120 in the first embodiment are the same as those in the first embodiment. See the description of the heat treatment below.

[0197] Next, an interlayer insulating film 216 is formed, and openings are provided to expose the pair of electrodes 214. A conductive film is formed, and the conductive film is processed to form wiring 218 that contacts each of the pair of electrodes 214. (See FIG. 7(C)).

[0198] Here, the second heat treatment is performed. For details of the second heat treatment, refer to the description in Embodiment Mode 1. .

[0199] Through the above steps, the transistor illustrated in FIG. 5B can be manufactured.

[0200] According to this embodiment, the semiconductor device has high field effect mobility, small variations in threshold voltage, and high To provide a transistor including an oxide semiconductor, which has high reliability and an extremely low off-state current. can be done.

[0201] This embodiment may be used in combination with other embodiment modes.

[0202] (Embodiment 3) In this embodiment, a semiconductor device using the transistor described in Embodiment 1 or 2 An example of fabricating a memory, which is a semiconductor device, will be described.

[0203] A typical example of volatile memory is a memory element that selects transistors to form a capacitor. DRAM (Dynamic Random Access Memory) stores information by storing electrical charges in the Access Memory, which uses circuits such as flip-flops to store memory contents. There is SRAM (Static Random Access Memory).

[0204] The transistors shown in the first or second embodiment are used as part of the transistors included in the memory. A register can be applied.

[0205] For example, in the case of a DRAM, which is a semiconductor device to which the transistor described in Embodiment 1 is applied, This will be explained with reference to FIG.

[0206] 8A shows a cross-sectional view of the DRAM. The transistor 340 is formed on the substrate 100. 0 and a protective insulating film provided around the base insulating film 102. 104, and a high resistance region 106a provided on the base insulating film 102 and the protective insulating film 104. and an oxide semiconductor film 106 having a low-resistance region 106b, and The gate insulating film 108 overlaps the high resistance region 106a via the gate insulating film 108. The gate electrode 110 is provided so as to overlap with the sidewall insulating film 11 2, and a pair of electrodes 114 in contact with at least the low resistance region 106b and the sidewall insulating film 112. The high resistance region 106a has a gate electrode 110 and a gate electrode 112 of the transistor 340. When a voltage equal to or greater than the threshold voltage is applied, a channel is formed.

[0207] The transistor 340 is covered with an interlayer insulating film 324 and an electrode 326 provided on the interlayer insulating film 324. One of them, the interlayer insulating film 324, and the electrode 326 form a capacitor 330. Although the figure shows a parallel plate type capacitor, it is also possible to use a stack type or a Alternatively, a trench type capacitor may be used.

[0208] Furthermore, the transistor 340 is provided over the interlayer insulating film 324 and the electrode 326. The interlayer insulating film 116 and the interlayer insulating film 324 are connected via openings formed in the interlayer insulating film 116 and the interlayer insulating film 324. and a wiring 118 that connects to the other of the pair of electrodes 114. However, a protective film may be provided to cover the interlayer insulating film 116 and the wiring 118. By providing the protective film, minute leaks caused by surface conduction of the interlayer insulating film 116 can be prevented. The current can be reduced, and the off-state current of the transistor can be reduced.

[0209] FIG. 8B is a circuit diagram of the DRAM shown in FIG. 8A. The DRAM has a bit line BL and , a word line WL, a sense amplifier SAmp, a transistor Tr, and a capacitor C. The transistor Tr corresponds to the transistor 340, and the capacitor C corresponds to the This corresponds to Capashta 330.

[0210] The time change of the potential held in the capacitor C is shown in Figure 8 by the off-current of the transistor Tr. It is known that the voltage gradually decreases as shown in (C). Initially, the voltage is charged from V0 to V1. As time passes, the potential decreases to VA, which is the limit point at which data1 can be read. This period is called the retention period T_1. In other words, in the case of a binary DRAM, the reset occurs during the retention period T_1. A fresh operation is required.

[0211] Here, by applying the transistor 340 to the transistor Tr, the transistor T Since the off-current of r can be made extremely small, the retention period T_1 can be extended. In other words, it is possible to extend the interval between refresh operations, which reduces DRAM consumption. In addition, the high field effect mobility of the transistor Tr allows for a reduction in D RAM can be operated at high speed.

[0212] For example, if the off-state current is 1×10 -18 Below A, 1×10 -21 A or below, preferred Or 1 x 10 -24 A transistor using an oxide semiconductor film with a temperature of 1000 Å or less is used to develop a DRAM. With this configuration, the interval between refresh operations can be set to several tens of seconds to several decades.

[0213] As described above, by applying a transistor according to one embodiment of the present invention to a DRAM, It is possible to obtain a DRAM that is highly reliable, consumes little power, and is capable of high-speed operation.

[0214] Next, a nonvolatile memory, which is a semiconductor device to which the transistor described in Embodiment 1 is applied, will be described. An example will be described with reference to FIG.

[0215] 9A is a cross-sectional view of a nonvolatile memory. The transistor 350 includes a substrate 100 and A base insulating film 382 is provided on the substrate 100, and a first insulating film is provided on the base insulating film 382. A semiconductor device having a resistive region 384a, a second resistive region 384b, and a third resistive region 384c. A conductor film 384, a gate insulating film 386 provided on the semiconductor film 384, and a gate insulating film 386 A gate electrode 392 is provided so as to overlap the first resistance region 384a via the gate electrode 86. and a sidewall insulating film 394 in contact with the side surface of the electrode 392. The resistance is increased in the order of the first resistance region 384a, the second resistance region 384b, and the third resistance region 384c. The first resistance region 384a is connected to the gate electrode 392 of the transistor 350. When a voltage higher than the threshold voltage is applied, a channel is formed. A pair of electrodes may be provided in contact with resistive region 384c.

[0216] The transistor 350 may be formed using a semiconductor film other than an oxide semiconductor film, such as a polycrystalline silicon film. , single crystal silicon film, polycrystalline germanium film, single crystal germanium film, etc. A transistor having a semiconductor film including the The transistor using an oxide semiconductor film shown in 2 may be used.

[0217] An interlayer insulating film 396 is provided in contact with the transistor 350. Since the film 396 is also the surface on which the transistor 340 is formed, the surface of the interlayer insulating film 396 is preferably Specifically, the surface of the interlayer insulating film 396 has a roughness Ra of 1 nm or less, preferably It is preferably 0.3 nm or less, and more preferably 0.1 nm or less.

[0218] The interlayer insulating film 396 may have a single layer or a stacked layer structure. It is preferable that the layer be an insulating film that releases oxygen by heat treatment.

[0219] The transistor 340 is provided on the interlayer insulating film 396. One of the pair of electrodes 114 is connected to a gate electrode 392 of the transistor 350. In addition, one of the pair of electrodes 114 of the transistor 340 and the interlayer insulating film The insulating film 324 and the electrode 326 form a capacitor 330. This shows a parallel plate capacitor, but it can also be a stacked or trench type to increase capacitance. A capacitor of this type may also be used.

[0220] FIG. 9(B) is a circuit diagram of the nonvolatile memory shown in FIG. 9(A). a transistor Tr_1, a gate line GL_1 connected to the gate of the transistor Tr_1, A source line SL_1 connected to the source of the transistor Tr_1, a transistor Tr_2, and , a source line SL_2 connected to the source of the transistor Tr_2, and a a drain line DL_2 connected to the drain of the capacitor C; The capacitance line CL connected to the other end of the capacitor C, the drain and and a floating gate FG connected to the gate of transistor Tr_2. The transistor Tr_1 corresponds to the transistor 340, and the transistor Tr_2 corresponds to the transistor 340. The resistor 350 corresponds to the capacitor C, and the capacitor C corresponds to the capacitor 330.

[0221] Note that the nonvolatile memory shown in this embodiment mode changes the potential of the floating gate FG according to the potential of the floating gate FG. , which utilizes the fact that the apparent threshold voltage of transistor Tr_2 fluctuates. For example, Figure 9(C) shows the potential V CL and the drain current flowing through transistor Tr_2 In current I ds This is a diagram explaining the relationship with _2.

[0222] Here, the floating gate FG adjusts the potential via the transistor Tr_1. For example, the potential of the source line SL_1 is set to VDD. The potential of L_1 is set to a potential equal to or higher than the threshold voltage Vth of transistor Tr_1 plus VDD. By doing so, the potential of the floating gate FG can be set to HIGH. By setting the potential of the gate line GL_1 to be equal to or lower than the threshold voltage Vth of the transistor Tr_1, The potential of the floating gate FG can be set to LOW.

[0223] Therefore, V shown with FG=LOW CL -I ds _2 curve and FG=HIGH V CL -I ds You can get either of the two curves. That is, when FG=LOW, V CL = 0V, the drain current Ids Since _2 is small, the data is 0. Also, FG=H In IGH, V CL = 0V, the drain current I ds Since _2 is larger, it becomes data 1. In this way, data can be stored.

[0224] Here, by applying the transistor 340 to the transistor Tr_1, Since the off-current of the transistor Tr_1 can be made extremely small, the floating transistor shown in Figure 9(B) The charge stored in the flip gate FG leaks unintentionally through the transistor Tr_1. This allows data to be stored for a long period of time. The high field-effect mobility of the transistor Tr_1 allows the nonvolatile memory to operate at high speed. This can be done.

[0225] As described above, by applying a transistor according to one embodiment of the present invention to a nonvolatile memory, This makes it a non-volatile memory that is highly reliable over a long period of time, consumes little power, and is capable of high-speed operation. can be obtained.

[0226] This embodiment may be used in combination with other embodiment modes.

[0227] (Fourth embodiment) The transistor described in Embodiment 1 or 2 and the semiconductor device described in Embodiment 3 A CPU (Central Processing Unit) is implemented using at least a semiconductor device. nit) can be configured.

[0228] FIG. 10(A) is a block diagram showing a specific configuration of the CPU. The PU is provided on a substrate 1190 with an arithmetic logic unit (ALU). nit) 1191, ALU controller 1192, instruction decoder 1193 , interrupt controller 1194, timing controller 1195, register 11 96, Register Controller 1197, Bus Interface (Bus I / F) 119 8. Rewritable ROM1199 and ROM interface (ROM I / F) The substrate 1190 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. The ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 10(A) is merely an example of a simplified configuration. Actual CPUs have a wide variety of configurations depending on their applications.

[0229] The instructions input to the CPU via the bus interface 1198 are After being input to the decoder 1193 and decoded, the ALU controller 1192 Rupture controller 1194, register controller 1197, timing controller It is entered into 1195.

[0230] ALU controller 1192, interrupt controller 1194, register controller The timing controller 1197 and the timing controller 1195 control various Specifically, the ALU controller 1192 controls the operation of the ALU 1191. The interrupt controller 1194 also generates a signal for the CPU program. During execution, interrupt requests from external I / O devices and peripheral circuits are handled according to their priority and mask status. The register controller 1197 determines the address of the register 1196 and processes it. It generates a process and reads and writes register 1196 depending on the CPU state.

[0231] The timing controller 1195 controls the ALU 1191 and the ALU controller 119 2, an instruction decoder 1193, an interrupt controller 1194, and It generates a signal to control the timing of the operation of the register controller 1197. The timing controller 1195 generates an internal clock signal CLK1 based on the reference clock signal CLK1. The internal clock generator generates the clock signal CLK2. Supply to the circuit.

[0232] In the CPU shown in FIG. 10A, the semiconductor device of the third embodiment is provided in the register 1196. It is being done.

[0233] In the CPU shown in FIG. 10A, the register controller 1197 controls the ALU 1191 The holding operation in register 1196 is selected according to the instruction from register 1196. In the semiconductor device of 196, data is held by a phase inversion element or a capacitor. Select whether to hold data by a phase inversion element. In this case, the power supply voltage is supplied to the semiconductor device in the register 1196. When data is to be held, the data is rewritten to the capacitor and the register 119 is The supply of power supply voltage to the semiconductor device in the power supply circuit 6 can be stopped.

[0234] Regarding the power supply shutdown, as shown in FIG. 10(B) or FIG. 10(C), A switching element is connected between nodes to which the power supply potential VDD or VSS is applied. The circuits shown in FIGS. 10(B) and 10(C) are explained below. Make it clear.

[0235] 10B and 10C show a switch for controlling the supply of a power supply potential to a semiconductor device. 1 is a configuration example of a memory circuit including a transistor using an oxide semiconductor as an active layer in a switching element. Shows.

[0236] The memory device shown in FIG. 10B includes a switching element 1141 and a semiconductor device 1142. Specifically, each semiconductor device 1142 has: The semiconductor device described in Embodiment 3 can be used. The semiconductor device 1142 is supplied with a high-level power supply potential V DD is supplied to each semiconductor device 1142 included in the semiconductor device group 1143. is given the potential of the signal IN and the potential of the low-level power supply potential VSS.

[0237] In FIG. 10B, the switching element 1141 is the one according to the first embodiment or the second embodiment. The transistor can be a transistor shown in The switching is controlled by the signal SigA.

[0238] In FIG. 10B, the switching element 1141 has only one transistor. However, the present invention is not limited to this configuration, and a plurality of transistors may be included. In the case where the switching element 1141 has a plurality of transistors that function as switching elements, In this case, the plurality of transistors may be connected in parallel or in series. Alternatively, a combination of series and parallel connections may be used.

[0239] In addition, in FIG. 10(C), each semiconductor device 1142 included in the semiconductor device group 1143 has a switch. A low-level power supply potential VSS is supplied to the memory device through the switching element 1141. The switching element 1141 controls each semiconductor device included in the semiconductor device group 1143. The supply of a low-level power supply potential VSS to the semiconductor device 1142 can be controlled.

[0240] A switch is provided between a group of semiconductor devices and a node to which a power supply potential VDD or a power supply potential VSS is applied. When a switching element is installed to temporarily stop CPU operation and cut off the supply of power voltage It is possible to retain data even in this state, which reduces power consumption. For example, a user of a personal computer may input information into an input device such as a keyboard. The CPU can be stopped while the It is possible.

[0241] In addition, the transistor described in Embodiment 1 or 2 and the transistor described in Embodiment 3 By using this semiconductor device, a CPU that can operate at high speed with low power consumption can be obtained. do.

[0242] Here, we have taken the CPU as an example, but the same can be said for DSP (Digital Signal Processor) processor), custom LSI, FPGA (Field Programmable Gate Array) It can also be applied to LSIs such as MOS gate arrays.

[0243] This embodiment may be used in combination with other embodiment modes.

[0244] (Embodiment 5) In this embodiment, an example of an electronic device to which the third or fourth embodiment is applied will be described. Reveal.

[0245] 11A shows a portable information terminal. The portable information terminal has a housing 500 and a button 501. , a microphone 502, a display unit 503, a speaker 504, and a camera 505. Although not shown, the memory of the portable information terminal or the semiconductor device shown in the third embodiment or the CPU shown in the fourth embodiment. It can be used.

[0246] FIG. 11B shows a digital still camera. The digital still camera has a housing 520 and , a button 521, a microphone 522, and a display unit 523. However, the semiconductor device described in the third embodiment can be used as a memory of the digital still camera. This can be done.

[0247] By using a transistor or a semiconductor device according to one embodiment of the present invention, high reliability can be achieved. High-performance electronic devices can be obtained.

[0248] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Example]

[0249] In this example, the crystalline state of an In—Sn—Zn—O film will be described.

[0250] First, X-ray diffraction (XRD) of the In-Sn-Zn-O film The XRD analysis was performed using a Bruker AXS X-ray diffractometer D8 A Measurements were taken using the out-of-plane method using DVANCE.

[0251] Samples A and B were prepared for XRD analysis. The method for preparing material B will be explained.

[0252] First, a dehydrogenated quartz substrate was prepared.

[0253] Next, an In-Sn-Zn-O film was formed on the quartz substrate to a thickness of 100 nm.

[0254] The In-Sn-Zn-O film was prepared by sputtering in an oxygen atmosphere at a power of 100 W ( The target was In:Sn:Zn=1:1:1 [atomic ratio]. The n-Sn-Zn-O target was used. The substrate heating temperature during film formation was either room temperature or 20 The temperature was set to 0° C. The sample thus prepared was designated as Sample A.

[0255] Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for 1 hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to a further heat treatment for 1 hour. The sample thus prepared was designated as sample B.

[0256] Figure 19 shows the XRD spectra of sample A and sample B. In sample A, peaks derived from crystals However, in sample B, 2θ was observed around 35 deg and 37 deg to 38 deg. A peak derived from crystals was observed in g.

[0257] Next, a transmission electron microscope (TEM) of sample B was used. Microscope (n) cross-sectional images are shown in Figures 20 and 21.

[0258] Figures 20 and 21 are TEM cross-sectional images at 0.5 million and 4 million magnifications, respectively. The TEM was a Hitachi H-9000NAR, with an acceleration voltage of 300 kV.

[0259] As shown in Figs. 20 and 21, the In-Sn-Zn-O film of sample B has various crystal structures. It is clear that the crystal is oriented polycrystalline. [Example]

[0260] In this example, the electrical characteristics of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film were The characteristics are explained below.

[0261] FIG. 12 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this example. 12(A) is a top view of the transistor. Also, FIG. 12(B) is a dot-and-dash diagram of FIG. 12(A). FIG. 2 is a cross-sectional view corresponding to line AB.

[0262] The transistor shown in FIG. 12B includes a substrate 600 and a base insulating film provided over the substrate 600. a base insulating film 602, an oxide semiconductor film 606 provided over the base insulating film 602, and an oxide semiconductor film A pair of electrodes 614 in contact with the oxide semiconductor film 606 and a pair of electrodes 614 The gate insulating film 608 is provided, and the oxide semiconductor film 606 is provided with the gate insulating film 608 interposed therebetween. The gate electrode 610 is provided so as to overlap with the gate insulating film 608. The interlayer insulating film 616 provided to cover the gate insulating film 608 and the interlayer insulating film 616 The wiring 618 is connected to the pair of electrodes 614 through the openings, and the interlayer insulating film 616 and and a protective film 620 provided to cover the wiring 618.

[0263] The substrate 600 is a glass substrate, the underlying insulating film 602 is a silicon oxide film, and the oxide The semiconductor film 606 is an In—Sn—Zn—O film, and the pair of electrodes 614 is a tungsten film. a silicon oxide film as the gate insulating film 608; and a nitrogen film as the gate electrode 610. The interlayer insulating film 616 is a layered structure of a tantalum nitride film and a tungsten film. The laminated structure is made of a conductor film and a polyimide film, and the wiring 618 is made of a titanium film, an aluminum film, The laminated structure in which the titanium film is formed in this order is a polyimide film as a protective film 620, and Each was used.

[0264] In the transistor having the structure shown in FIG. 12A, the gate electrode 610 and the pair of electrodes The width of the overlap with the oxide semiconductor film 606 is referred to as Lov. The protrusion of pole 614 is called dW.

[0265] A method for manufacturing a transistor having the structure shown in FIG. 12B will be described below.

[0266] First, the surface of the substrate 600 was subjected to plasma treatment in an argon atmosphere. A sputtering device was used, and a bias power of 200 W (RF) was applied to the substrate 600 side. This was done for 3 minutes.

[0267] Next, while maintaining the vacuum state, a silicon oxide film, which is the base insulating film 602, is deposited to a thickness of 300 nm. The film was deposited to a thickness of 1000 nm.

[0268] The silicon oxide film was formed using a sputtering device in an oxygen atmosphere at 1500W (RF) The target used was a quartz target. The substrate heating temperature during film formation was was set to 100°C.

[0269] Next, the surface of the base insulating film 602 was subjected to CMP processing to be flattened to approximately Ra=0.2 nm.

[0270] Next, an In-Sn-Zn-O film, which is an oxide semiconductor film, was formed to a thickness of 15 nm.

[0271] The In-Sn-Zn-O film was prepared using a sputtering system with a volume ratio of argon to oxygen of 2:3. The film was deposited in a mixed atmosphere of In:Sn An In-Sn-Zn-O target with an atomic ratio of Zn = 1:1:1 was used. The substrate heating temperature during film formation was set to 200°C.

[0272] Next, a heat treatment was carried out at a temperature of 250°C, 450°C or 650°C. First, heat treatment was carried out in a nitrogen atmosphere for 1 hour, and then, while maintaining the temperature, heat treatment was carried out in an oxygen atmosphere for 1 hour. Heat treatment was carried out for 1 hour.

[0273] Next, the oxide semiconductor film is processed by a photolithography process to form an oxide semiconductor film 60 6 was formed.

[0274] Next, a tungsten film was formed to a thickness of 50 nm.

[0275] The tungsten film was formed using a sputtering device in an argon atmosphere at a power of 1000W (D The substrate heating temperature during film formation was set to 200°C.

[0276] Next, the tungsten film is processed by a photolithography process to form a pair of electrodes 614. Formed.

[0277] Next, a silicon oxide film serving as a gate insulating film 608 was formed to a thickness of 100 nm. The relative dielectric constant of the silicon oxide film was set to 3.8.

[0278] The silicon oxide film, which is the gate insulating film 608, was formed in the same manner as the base insulating film 602. .

[0279] Next, a tantalum nitride film and a tungsten film were deposited in this order at 15 nm and 13 nm, respectively. The film was deposited to a thickness of 5 nm.

[0280] The tantalum nitride film was formed using a sputtering device in a mixed atmosphere of argon and nitrogen at a ratio of 5:1. The film was deposited at a power of 1000 W (DC). The substrate was not heated during the deposition.

[0281] The tungsten film was formed using a sputtering device in an argon atmosphere with a power of 4000W (D The substrate heating temperature during film formation was set to 200°C.

[0282] Next, the tantalum nitride film and the tungsten film are processed by a photolithography process. Then, a gate electrode 610 was formed.

[0283] Next, a silicon oxynitride film that will become an interlayer insulating film 616 was formed to a thickness of 300 nm.

[0284] The silicon oxynitride film that becomes the interlayer insulating film 616 is formed by using a PCVD apparatus with monosilane: hypochlorous acid. The film was formed in a mixed atmosphere of nitrogen dioxide and silicon dioxide = 1:200 with a power of 35 W (RF). The substrate heating temperature was set to 325°C.

[0285] Next, a silicon oxynitride film that will become the interlayer insulating film 616 is applied by a photolithography process. I worked on it.

[0286] Next, a photosensitive polyimide film that will become the interlayer insulating film 616 is formed to a thickness of 1500 nm.

[0287] Next, the film used in the photolithography process of the silicon oxynitride film that will become the interlayer insulating film 616 is The photosensitive polyimide that will become the interlayer insulating film 616 is exposed to light using a photomask, and then developed. Heat treatment is performed to harden the photosensitive polyimide film, and then the silicon oxynitride film is combined with the An interlayer insulating film 616 was formed. The heat treatment was carried out in a nitrogen atmosphere at a temperature of 300° C. Ta.

[0288] Next, a titanium film, an aluminum film, and a titanium film were deposited in this order at 50 nm and 10 The films were deposited to thicknesses of 0 nm and 5 nm.

[0289] The titanium film was deposited on both layers using a sputtering device in an argon atmosphere at a power of 1000W. The film was deposited as DC. The substrate was not heated during the deposition.

[0290] The aluminum film was formed using a sputtering device in an argon atmosphere at a power of 1000 W (D C) The substrate was not heated during film formation.

[0291] Next, the titanium film, the aluminum film, and the titanium film are processed by a photolithography process. Thus, a wiring 618 was formed.

[0292] Next, a photosensitive polyimide film serving as a protective film 620 was formed to a thickness of 1500 nm.

[0293] Next, a photosensitive polyimide film is formed using the photomask used in the photolithography process for the wiring 618. The film was exposed to light and then developed to form an opening in the protective film 620 that exposed the wiring 618. .

[0294] Next, a heat treatment was carried out to harden the photosensitive polyimide film. The heat treatment was carried out in the same manner as that for the photosensitive polyimide film used in the film 616 .

[0295] Through the above steps, a transistor having the structure shown in FIG. 12B was manufactured.

[0296] Next, the electrical characteristics of the transistor having the structure shown in FIG. 12B were evaluated.

[0297] V in the transistor with the structure shown in this example gs -I ds The characteristics were measured and the results are shown in Figure 13 The transistor used for the measurement has a channel length L of 3 μm and a channel width W is 10 μm, Lov is 3 μm on one side (total 6 μm), dW is 3 μm on one side (total 6 μm) There is. ds was set to 10V.

[0298] Figures 13 and 14 show the I ds (solid line) and field-effect mobility (dotted line) V gs Indicates dependency.

[0299] Here, the samples differ in the conditions of heat treatment performed after the formation of the oxide semiconductor film 606. No heat treatment was performed. Samples 2 to 4 were heated at 250°C, 450°C, and 650°C, respectively. The heat treatment is carried out at a temperature of .

[0300] Here, FIG. 13(A) shows sample 1, FIG. 13(B) shows sample 2, FIG. 14(A) shows sample 3, and FIG. (B) corresponds to sample 4, respectively.

[0301] In Samples 1 to 4, switching characteristics of the transistor were obtained. Furthermore, when Sample 1 is compared with Samples 2 to 4, the formation of the oxide semiconductor film is It can be seen that the field-effect mobility of the transistor increases by performing a heat treatment after the film formation. The authors attribute this to the fact that the impurity concentration in the oxide semiconductor film is reduced by heat treatment. Therefore, it was thought that the oxide semiconductor film was formed by heat treatment. The impurity concentration in the film is reduced, and as a result, the field-effect mobility of the transistor is improved to the ideal field-effect It can be seen that we were able to approach the actual mobility.

[0302] In this way, by performing heat treatment after the oxide semiconductor film is formed, impurities in the oxide semiconductor film can be removed. It was found that the concentration of the semiconductor was reduced, and as a result, the field-effect mobility of the transistor was increased. do. [Example]

[0303] In this example, the transistors of Sample 1 and Sample 4 prepared in Example 2 were subjected to a BT test. was carried out.

[0304] The BT test in this embodiment will be described. The transistors to be subjected to the BT test are the same as those in the second embodiment. The structure is the same as that of the transistor shown in FIG.

[0305] First, the substrate temperature is set to 25°C, and V ds is set to 10V, and the V of the transistor gs -I ds Characteristics Next, the substrate temperature was set to 150°C, and V ds was set to 0.1V. Next, the gate V so that the electric field strength applied to the insulating film 608 becomes 2MV / cm gs Apply 20V to Then, V gs Next, the substrate temperature was set to 25°C, and V ds is set to 10V, and the V of the transistor gs -I dsMeasurement was carried out. This is a plus BT test It is called.

[0306] Similarly, first set the substrate temperature to 25°C, and then V ds is set to 10V, and the V of the transistor gs -I d s Next, the substrate temperature was set to 150°C, and V ds was set to 0.1V. , V so that the electric field strength applied to the gate insulating film 608 becomes −2 MV / cm. gs Ni-2 0 V was applied and held for 1 hour. gs Next, the substrate temperature was set to 2 5℃, V ds is set to 10V, and the V of the transistor gs -I ds Measurements were carried out. It is called the Inas BT test.

[0307] The results of the positive BT test for sample 1 are shown in Figure 15(A), and the results of the negative BT test are shown in Figure 15(B). The results of the positive BT test for sample 4 are shown in Figure 16(A), and the results of the negative BT test for sample 4 are shown in Figure 16(B). The results are shown in Figure 16(B). The figure also shows the V before and after the BT test. gs -I ds Variation in characteristics Arrows are added for clarity.

[0308] The threshold voltage fluctuations of sample 1 due to the positive BT test and the negative BT test are as follows: The positive and negative BT tests for sample 4 were 1.80V and -0.42V. The threshold voltage variations due to the BT test were 0.79 V and 0.76 V, respectively.

[0309] Samples 1 and 4 showed little change in threshold voltage before and after the BT test, indicating high reliability. It can be seen that this is a high-performance transistor. [Example]

[0310] In this example, the relationship between the substrate temperature and the electrical characteristics of the transistor of Sample 4 fabricated in Example 2 was investigated. Sexual relations were assessed.

[0311] The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, and Lov is 3 μm on one side (total 6 μm), and dW is 0 μm. ds was set to 10V. The substrate temperatures were -40°C, -25°C, 25°C, 75°C, 125°C and 150°C.

[0312] In Figure 17, I ds (solid line) and field-effect mobility (dotted line) gs It also indicates dependency. Figure 18(A) shows the relationship between the substrate temperature and the threshold voltage, and Figure 18(B) shows the relationship between the substrate temperature and the field effect transition. The relationship between the mobility is shown.

[0313] From FIG. 18(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was 0.38 V (-40°C) to -1.08 V (150°C).

[0314] Furthermore, it can be seen from FIG. 18(B) that the higher the substrate temperature, the lower the field effect mobility. The range is 37.4cm 2 / Vs(-40℃)~33.4cm 2 / Vs(150℃ ) was.

[0315] It can be seen that sample 4 has small fluctuations in electrical characteristics within the above temperature range. [Example]

[0316] In this example, the channel width of the transistor using the In-Sn-Zn-O film is The off-state current was evaluated.

[0317] The structure of the transistor used in the measurement was the transistor shown in FIG. 12 of Example 2, where L is 3 μm, W is 10 cm, Lov is -2 μm, and dW is 0 μm. μm, the gate electrode 610 and the pair of electrodes 614 do not overlap, and the width is The structure has an offset region (Loff) of 2 μm each (total of 4 μm). structure).

[0318] In this example, the oxide semiconductor film 606 and the gate insulating film 608 were the same as those in Example 2. are provided in different ways.

[0319] A method for forming the oxide semiconductor film 606 in this example will be described below.

[0320] First, an In-Sn-Zn-O film, which is an oxide semiconductor film, is formed to a thickness of 15 nm.

[0321] The In-Sn-Zn-O film was prepared using a sputtering system with a volume ratio of argon to oxygen of 2:3. The film is deposited in a mixed atmosphere of In:Sn An In-Sn-Zn-O target with an atomic ratio of Zn = 1:1:1 is used. The substrate was not heated during film formation or after film formation.

[0322] Next, the oxide semiconductor film is processed by a photolithography process to form an oxide semiconductor film 60 Form 6.

[0323] Similarly, a method for forming the gate insulating film 608 will be described below.

[0324] First, a silicon oxynitride film is formed as a gate insulating film 608 to a thickness of 300 nm.

[0325] The silicon oxynitride film was formed using a PCVD device with a mixture of monosilane and nitrous oxide at a ratio of 1:200. The film is formed in a mixed atmosphere with a power of 150 W (RF). Let's assume it's 0℃.

[0326] In this embodiment, the substrate 600, the underlying insulating film 602, the pair of electrodes 614, the gate electrode 616, the gate electrode 618, the gate electrode 619, the gate electrode 620, the gate electrode 621, the gate electrode 622, the gate electrode 623, the gate electrode 624, the gate electrode 625, the gate electrode 626, the gate electrode 627, the gate electrode 628, the gate The electrode 610, the interlayer insulating film 616, the wiring 618, and the protective film 620 are formed in the same manner as in the second embodiment. and similar materials.

[0327] Figure 22 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. For simplicity, the value obtained by multiplying the reciprocal of the substrate temperature by 1000 (1000 / T) is the horizontal axis.

[0328] The method for measuring the off-state current of a transistor is briefly explained below. The transistor is called the first transistor.

[0329] The drain of the first transistor is connected to the floating gate FG. The gate FG is connected to the gate of the second transistor.

[0330] First, the first transistor is turned off, and then a charge is applied to the floating gate FG. A constant drain voltage is applied to the second transistor.

[0331] At this time, the charge on the floating gate FG gradually leaks through the first transistor. When the charge on the floating gate FG is released, the source potential of the second transistor becomes The amount of change in the source potential over time is used to determine the leakage current from the first transistor. The amount of charge can be estimated and the off-current can be measured.

[0332] As shown in FIG. 22, the transistor shown in this example has an off-state current ( Unit: A / μm) is 2×10 when the substrate temperature during measurement is 85°C. -21 A / μm(2zA / μm).

[0333] As shown in this example, the off-state current of the transistor using the In-Sn-Zn-O film is extremely low. You can see that it is very small. [Explanation of symbols]

[0334] 100 boards 102 Undercoat insulating film 104 Protective insulating film 106 Oxide semiconductor film 106a High resistance area 106b Low resistance region 108 Gate insulating film 110 gate electrode 112 Sidewall insulating film 114 Pair of Electrodes 116 Interlayer insulating film 118 Wiring 120 Impurities 152 Undercoat insulating film 154 Protective insulating film 156 Oxide semiconductor film 158 Gate insulating film 160 Conductive film 162 insulating film 166 Oxide semiconductor film 200 boards 202 Undercoat insulating film 206 Oxide semiconductor film 206a High resistance area 206b Low resistance region 208 Gate insulating film 210 gate electrode 214 Pair of Electrodes 216 Interlayer insulating film 218 Wiring 220 Impurities 252 Undercoat insulating film 256 Oxide semiconductor film 260 Conductive Film 264 Conductive Film 324 Interlayer insulating film 326 Electrode 330 Capacitor 340 transistors 350 transistors 382 Undercoat insulating film 384 Semiconductor Film 384a resistance area 384b resistance area 384c resistance area 386 Gate insulating film 392 gate electrode 394 Sidewall insulating film 396 Interlayer insulating film 500 cabinets 501 Button 502 Microphone 503 Display section 504 Speaker 505 Camera 520 chassis 521 Button 522 Microphone 523 Display section 600 boards 602 Undercoat insulating film 606 Oxide semiconductor film 608 Gate insulating film 610 Gate electrode 614 Pair of electrodes 616 Interlayer insulating film 618 Wiring 620 Protective film 1141 Switching element 1142 Semiconductor devices 1143 Semiconductor Devices 1189 ROM interface 1190 PCB 1191 ALU 1192 ALU controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 registers 1197 Register Controller 1198 Bus Interface 1199 ROM

Claims

1. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; a capacitor; a semiconductor device, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor and one end of the capacitor; each of the first transistor and the second transistor has a gate electrode above a channel formation region; a first insulating film having a region in contact with a side surface of a gate electrode of the first transistor; a second insulating film having a region in contact with the first insulating film; an oxide semiconductor film having a region provided over the second insulating film and including a channel formation region of the second transistor; a third insulating film having a region in contact with a side surface of the gate electrode of the second transistor; a first conductive layer having a region provided over the third insulating film and functioning as one of a source electrode and a drain electrode of the second transistor; a fourth insulating film on the first conductive layer and on the gate electrode of the second transistor; a second conductive layer having a region provided on the fourth insulating film and functioning as one electrode of the capacitor; the oxide semiconductor film contains In, Ga, and Zn, the first conductive layer is electrically connected to a gate electrode of the first transistor; the second conductive layer has a region overlapping with the first conductive layer with the fourth insulating film interposed therebetween and a region overlapping with a channel formation region of the first transistor with the fourth insulating film and the first conductive layer interposed therebetween; a first transistor including a first insulating film and a second insulating film, the first insulating film including a first insulating film and a second insulating film, the first insulating film including a first insulating film and a second insulating film, the second ...

2. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; a capacitor; a semiconductor device, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor and one end of the capacitor; each of the first transistor and the second transistor has a gate electrode above a channel formation region; a first insulating film having a region in contact with a side surface of a gate electrode of the first transistor; a second insulating film having a region in contact with the first insulating film; an oxide semiconductor film having a region provided over the second insulating film and including a channel formation region of the second transistor; a third insulating film having a region in contact with a side surface of the gate electrode of the second transistor; a first conductive layer having a region provided over the third insulating film and functioning as one of a source electrode and a drain electrode of the second transistor; a fourth insulating film on the first conductive layer and on the gate electrode of the second transistor; a second conductive layer having a region provided on the fourth insulating film and functioning as one electrode of the capacitor; the oxide semiconductor film contains In, Ga, and Zn, the oxide semiconductor film has crystallinity, the first conductive layer is electrically connected to a gate electrode of the first transistor; the second conductive layer has a region overlapping with the first conductive layer with the fourth insulating film interposed therebetween and a region overlapping with a channel formation region of the first transistor with the fourth insulating film and the first conductive layer interposed therebetween; a first transistor including a first insulating film and a second insulating film, the first insulating film including a first insulating film and a second insulating film, the first insulating film including a first insulating film and a second insulating film, the second ...

3. a first transistor having silicon in a channel formation region; a second transistor including an oxide semiconductor in a channel formation region; a capacitor; a semiconductor device, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor and one end of the capacitor; each of the first transistor and the second transistor has a gate electrode above a channel formation region; a first insulating film having a region in contact with a side surface of a gate electrode of the first transistor; a second insulating film having a region in contact with the first insulating film; an oxide semiconductor film having a region provided over the second insulating film and including a channel formation region of the second transistor; a third insulating film having a region in contact with a side surface of the gate electrode of the second transistor; a first conductive layer having a region provided over the third insulating film and functioning as one of a source electrode and a drain electrode of the second transistor; a fourth insulating film on the first conductive layer and on the gate electrode of the second transistor; a second conductive layer having a region provided on the fourth insulating film and functioning as one electrode of the capacitor; the oxide semiconductor film contains In, Ga, and Zn, the first conductive layer is electrically connected to a gate electrode of the first transistor; the second conductive layer has a region overlapping with the first conductive layer with the fourth insulating film interposed therebetween and a region overlapping with a channel formation region of the first transistor with the fourth insulating film and the first conductive layer interposed therebetween; the first conductive layer overlaps both ends of a semiconductor film having a channel formation region of the first transistor in a cross-sectional view in a channel length direction of the second transistor; a first transistor including a first insulating film and a second insulating film, the first insulating film including a first insulating film and a second insulating film, the first insulating film including a first insulating film and a second insulating film, the second ...

4. In any one of claims 1 to 3, The second insulating film has a function as an interlayer insulating film, the interlayer insulating film has a laminated structure including a silicon oxide film, The semiconductor device, wherein the silicon oxide film has a region in contact with a lower surface of the oxide semiconductor.

5. In any one of claims 1 to 4, the second transistor has a gate insulating film; when viewed in a cross section of the second transistor in a channel length direction, both ends of the gate insulating film are located on an upper surface of the oxide semiconductor film; The semiconductor device, wherein the gate insulating film comprises silicon oxide.

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