Semiconductor device

Abstract

To provide a semiconductor device having a large storage capacity per unit area.SOLUTION: A semiconductor device includes: a first insulator having a first opening; a first conductor having a second opening on the first insulator; a second insulator having a third opening on the first insulator; and an oxide provided so as to penetrate the first, second, and third openings. The oxide has a first region at least in the first opening, has a second region at least in the second opening, and has a third region at least in the third opening. The first region and the third region are lower in resistance than the second region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to, for example, a memory device and a semiconductor device. The present invention relates to a memory device and a method for manufacturing a semiconductor device. The present invention also relates to a memory transistor and a method for manufacturing the memory transistor, for example, The present invention relates to a processor and an electronic device. Also, the present invention relates to a method for manufacturing a processor and an electronic device. The present invention also relates to a memory device, a processor, and a method for driving an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. One aspect of the invention is a process, machine, manufacture, or composition of matter. It concerns the matter of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, semiconductor circuits, and The electronic equipment may include semiconductor devices. [Background technology]

[0004] In recent years, with the increase in the amount of data handled, there has been a demand for semiconductor devices with larger storage capacities. To increase the storage capacity per unit area, memory cells are stacked. It is effective to form the memory cells in a stacked manner (see Patent Documents 1 and 2). By doing so, the memory capacity per unit area can be increased in accordance with the number of stacked memory cells. can be done. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Publication No. 2011 / 0065270A1 [Patent Document 2] U.S. Patent Publication No. 9634097B2 Summary of the Invention [Problem to be solved by the invention]

[0006] In Patent Document 1 and Patent Document 2, a plurality of memory elements (also called memory cells) are stacked. These are connected in series to form a three-dimensional memory cell array (memory On the other hand, such a three-dimensional memory cell array In this case, the more the number of stacked memory elements, the higher the series resistance between memory cells becomes. The resistance of the memory cell array increases. There were problems such as current loss through the memory cell array and heat generation.

[0007] In addition, in Patent Document 1, a semiconductor pattern provided in a columnar shape has a charge storage layer. In addition, in Patent Document 2, a semiconductor pattern provided in a columnar shape is The semiconductor is in contact with an insulator that acts as a tunnel dielectric. At these interfaces, trap centers may be formed. The trap centers formed at the interface capture electrons and increase the threshold voltage of the transistor. In order to vary the current driving force in the on-state of the transistor, that is, the on-state voltage, This can adversely affect current and field effect mobility, as well as reliability.

[0008] In view of the above problems, one aspect of the present invention is to provide a semiconductor device having good electrical properties and no trap center. An object of the present invention is to provide a semiconductor device in which formation of defects is suppressed.

[0009] Another object of the present invention is to provide a semiconductor device having a large storage capacity per unit area. Another object is to provide a semiconductor device having a novel structure in which memory cells are stacked. Another object is to provide a semiconductor device with high productivity.

[0010] Another object of the present invention is to provide a module including the semiconductor device. An object of the present invention is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. One of the objectives is to provide a novel electronic device. do.

[0011] Another object of the present invention is to provide a semiconductor device with reduced power consumption during circuit operation. Alternatively, a module having a semiconductor device with reduced power consumption during circuit operation may be provided. Alternatively, it is an object of the present invention to provide a device that consumes less power during circuit operation. An object of the present invention is to provide an electronic device having a semiconductor device or a module.

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0013] One aspect of the present invention is a semiconductor device comprising a first insulator having a first opening and a second opening on the first insulator. a first conductor having an opening; a second insulator on the first conductor having a third opening; an oxide provided so as to penetrate the first opening, the second opening, and the third opening; The oxide has a first region in the first opening and a second region in the second opening. a third opening having a third region, the first region and the third region is a semiconductor device having a lower resistance than the second region.

[0014] One aspect of the present invention is a semiconductor device comprising a first insulator having a first opening and a second opening on the first insulator. a first conductor having an opening; a second insulator on the first conductor having a third opening; an oxide provided so as to penetrate the first opening, the second opening, and the third opening; a third insulator in contact with the first conductor, and a second conductor in contact with the third insulator, The third insulator is provided between the first conductor and the third insulator, and the third insulator is an oxide of the second conductor. The oxide has a first region in the first opening and a second region in the second opening. and a third region in the third opening, the first region, and The third region is a semiconductor device having a lower resistance than the second region.

[0015] In the above, the semiconductor device further comprises at least one of silicon and a metal element. The nitride may have a nitride including the first region and the third region. It is preferable that the sensor is provided in the position indicated by the arrows.

[0016] In the above, the semiconductor device further includes a fourth insulator, a fifth insulator, and a sixth insulator. and a fourth insulator is provided between the first conductor and the oxide. The fifth insulator is provided between the fourth insulator and the oxide, and the sixth insulator is provided between the fifth insulator and the oxide. It is preferably provided between the insulator and the oxide.

[0017] In the above, the fourth insulator is any one of silicon, aluminum, and hafnium. It is preferably an oxide containing iodide.

[0018] In the above, the sixth insulator is any one of silicon, aluminum, and hafnium. It is preferably an oxide containing iodide.

[0019] In the above, the nitride is between the sixth insulator and the first region, and between the sixth insulator and It is preferably provided between the third regions.

[0020] In the above, the diameter of the first opening and the diameter of the third opening are larger than the diameter of the second opening. It is preferable.

[0021] One embodiment of the present invention includes forming a first insulating film, forming a first conductive film on the first insulating film, and A second insulating film is formed on the first conductive film, and the second insulating film, the first conductive film, and The first insulating film is processed to form a first insulator having a first opening and a second insulating film on the first insulator. a first conductor having two openings and a second insulator on the first conductor having a third opening; and processing the first insulator and the second insulator to form a first opening having a diameter of The diameter of the third opening is made larger than the diameter of the second opening, and the first opening, In the second opening and the third opening, a first insulator, a first conductor, and a second forming a third insulator in contact with the insulator; and a metal element, and processing the first nitride to form a first nitride. , in the first opening and in the third opening, a side wall surface of the third insulator that is approximately aligned with the inner side wall surface of the third insulator. forming a second nitride having a wall surface within the first opening, the second opening, and the third opening; Method for manufacturing a semiconductor device in which an oxide is formed in contact with a third insulator and a second nitride It is the law.

[0022] In the above, it is preferable to perform a heat treatment after forming the oxide.

[0023] In the above, the third insulator includes a fourth insulator, a fifth insulator, and a sixth insulator. It is preferable that the fourth insulator has a laminated structure including the above-mentioned. The fifth insulator is formed, and the sixth insulator is formed after the fifth insulator is formed. It is preferable to form a third insulator having the following structure.

[0024] One aspect of the present invention is a semiconductor device comprising a first insulator having a first opening and a second opening on the first insulator. a first conductor having an opening; a second insulator on the first conductor having a third opening; an oxide provided inside the first opening, the second opening, and the third opening; and a first insulator; A third insulator is provided between the first conductor, the second insulator, and the oxide. The diameter of the second opening is larger than the diameter of the first opening and the diameter of the third opening, and the oxide is The side and top surfaces of the first insulator, the side surfaces of the first conductor, and the third insulator are connected to each other. The oxide is provided along the bottom surface and side surface of the second insulator, and in the first opening, having a first region and in a second opening; having a second region and in a third opening; The first and third regions are semiconductors having a lower resistance than the second region. It is a body device.

[0025] Another aspect of the present invention is a semiconductor device including a first insulator having a first opening, and a second insulating film on the first insulator. a first conductor having two openings and a second insulator on the first conductor having a third opening; an oxide provided inside the first opening, the second opening, and the third opening; and a first insulating film. a third insulator provided between the insulator, the first conductor, the second insulator, and the oxide; a fourth insulator in contact with the oxide, and a second conductor in contact with the fourth insulator, The diameter of the opening is larger than the diameter of the first opening and the diameter of the third opening, and the oxide is The side and top surfaces of the first insulator, the side surfaces of the first conductor, and the second insulator are connected via the edge. The fourth insulator is disposed along the bottom and side surfaces of the body, and is disposed between the oxide and the second conductor. the oxide has a first region in the first opening and a second region in the second opening. and a second region within the third opening, a third region within the first region, and The third region is a semiconductor device having a lower resistance than the second region.

[0026] In the above, the first conductor functions as a first gate, and the second conductor functions as a second gate. It preferably functions as a gate.

[0027] In the above, the oxide is a compound of In, an element M (M is Al, Ga, Y, or Sn), and Z. n and

[0028] In the above, the oxide is a first layer and a second layer provided in contact with the inside of the first layer. a third layer provided in contact with the inner surface of the second layer, and The energy gap of the first layer is narrower than that of the second layer, and the energy gap of the third layer is narrower than that of the first layer. It is preferable that the energy gap of the first layer is narrower than that of the second layer.

[0029] In the above, the semiconductor device further has a fifth insulator in the second opening, and the oxide is , and is preferably provided between the third insulator and the fifth insulator.

[0030] In the above, the first region and the third region contain more argon than the second region. It is preferable that

[0031] In the above, the first region and the third region contain hydrogen, nitrogen, and It is preferable that the alloy contains at least one of the above metal elements in a large amount.

[0032] In the above, the third insulator includes the sixth insulator, the seventh insulator, the eighth insulator, the sixth insulator is provided between the first conductor and the oxide, and the seventh insulator is The sixth insulator is provided between the oxide, and the eighth insulator is provided between the seventh insulator and the oxide. It is preferable that the ion beam is provided between the ion beam and the ion beam.

[0033] In the above, the sixth insulator is any one of silicon, aluminum, and hafnium. It is preferably an oxide containing iodide.

[0034] In the above, the eighth insulator is any one of silicon, aluminum, and hafnium. It is preferably an oxide containing iodide.

[0035] In one embodiment of the present invention, a first insulating film is formed, and a first conductive film is formed on the first insulating film. forming a second insulating film on the first conductive film; forming a second insulating film on the first conductive film; and a first insulating film is processed to form a first insulator having a first opening and a second insulating film on the first insulator. a first conductor having an opening; and a second insulator on the first conductor having a third opening. , and the first conductor is processed to make the diameter of the second opening equal to the diameter of the first opening. and the third opening have a diameter larger than that of the first opening, the second opening, and the third opening. In the opening, a first insulating material, a first conductor, and a second insulating material are contacted. A third insulator is formed, an oxide is formed, and a third insulator is formed so as to be in contact with the oxide. The third insulating film is formed as shown in FIG. 1, and the third insulating film is processed to form a layer of the oxide layer inside the second opening. A fourth insulator having a sidewall surface substantially coincident with the sidewall surface is formed, and the fourth insulator is used as a mask. The present invention relates to a method for manufacturing a semiconductor device, in which a resistance-lowering treatment is performed on a part of an oxide.

[0036] In the above, the resistance-lowering treatment is preferably a treatment of adding an element to the oxide.

[0037] In the above, the elements are argon, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, Chlorine, helium, neon, krypton, xenon, aluminum, ruthenium, titanium, At least one selected from tantalum, tungsten, chromium, and indium preferable.

[0038] In the above, the resistance reduction treatment may be a plasma treatment, an ion implantation treatment, an ion implantation treatment, or the like. Preferably, the process is either an on-doping process or a reverse sputtering process. [Effects of the Invention]

[0039] According to one aspect of the present invention, the semiconductor device has good electrical properties and suppresses the formation of trap centers. It is possible to provide a semiconductor device.

[0040] Furthermore, a semiconductor device having a large storage capacity per unit area can be provided. We provide a semiconductor device with a new structure in which memory cells (also called memory transistors) are stacked. Alternatively, a semiconductor device with high productivity can be provided.

[0041] Alternatively, a module having the semiconductor device can be provided. It is possible to provide a device or an electronic device having the module. A conductor device may be provided, or a novel module may be provided. Alternatively, a novel electronic device can be provided.

[0042] Furthermore, a semiconductor device with reduced power consumption during circuit operation can be provided. Alternatively, a module having a semiconductor device with reduced power consumption during circuit operation is provided. Alternatively, a semiconductor device with reduced power consumption during circuit operation can be provided. can provide an electronic device having the module.

[0043] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above will be self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0044] [Figure 1] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 3] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 5] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 6] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 18]1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 21] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 22] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 23] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 24] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 25] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 26] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 27] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 28] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 29] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 30] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 31] 1A and 1B are a functional block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention, and a circuit diagram illustrating a configuration example of a memory string. [Figure 32] FIG. 1 is a functional block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 33] FIG. 1 illustrates an example of a three-dimensional structure of a memory cell array according to one embodiment of the present invention. [Figure 34] FIG. 1 illustrates an example of a three-dimensional structure of a memory cell array according to one embodiment of the present invention. [Figure 35] FIG. 1 illustrates an example of a three-dimensional structure of a memory cell array according to one embodiment of the present invention. [Figure 36]FIG. 10 is a circuit diagram illustrating the operation of a memory device according to one embodiment of the present invention. [Figure 37] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 38] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 39] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 40] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 41] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 42] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 43] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 44] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 45] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 46] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 47] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 48] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 49] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 50] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 51] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 52] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 53] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 54] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 55]1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 56] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 57] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 58] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 59] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 60] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 61] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 62] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 63] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 64] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 65] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 66] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 67] 1A to 1C illustrate a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 68] FIG. 1 is a schematic diagram of a memory device according to one embodiment of the present invention. [Figure 69] FIG. 1 is a block diagram showing an example of the configuration of an AI system according to one embodiment of the present invention. [Figure 70] FIG. 1 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention. [Figure 71] 1 is a schematic perspective view showing an example of the configuration of an IC incorporating an AI system according to one embodiment of the present invention. [Figure 72] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 73] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0045] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the invention in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the mode and details of the present invention. The present invention should not be construed as being limited to the description of the following embodiments.

[0046] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown. The drawings are merely schematic illustrations, and are not limited to the shapes or values ​​shown in the drawings. In this case, the same reference numerals are used in common between different drawings to designate the same parts or parts having similar functions. In addition, when referring to the same function, the hatch pattern is used. In some cases, the same symbol is used and no particular symbol is assigned.

[0047] In addition, in this specification and the like, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second" "the" or "third" can be used as appropriate for explanation. The ordinal numbers listed in the specification do not match the ordinal numbers used to identify an aspect of the present invention. There are cases where this happens.

[0048] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used to indicate the position of components. The positional relationship is used for convenience in describing the structure with reference to the drawings. The relationship between the two components changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0049] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "of" is not subject to any particular restrictions as long as it allows the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. It has various functions such as switching elements, resistors, inductors, capacitors, etc. This includes elements such as:

[0050] In this specification, the term "nitride oxide" refers to a compound containing more nitrogen than oxygen. An oxynitride is a compound that contains more oxygen than nitrogen. The content of element can be measured by, for example, Rutherford Backscattering (RBS) spectroscopy. It can be measured using techniques such as backscattering spectrometry. do.

[0051] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "conductive layer" can be changed to the term "conductive film." Alternatively, for example, the term "insulating film" may be changed to "insulating layer" It may be possible to change the term to

[0052] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes cases where the angle is between -5° and 5°. "Almost parallel" means that the two lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. " refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0053] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0054] In this specification, the term "barrier film" refers to a film that prevents impurities such as hydrogen and oxygen from permeating. When the barrier film has conductivity, it is called a conductive barrier film. Sometimes I call.

[0055] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes called oxide semiconductors. In other words, the transistor can be a transistor including a metal oxide or an oxide semiconductor.

[0056] In this specification, the expression "In:Ga:Zn=4:2:3 or its vicinity" refers to the atomic ratio of In:Ga:Zn=4:2:3 or its vicinity. In the total number, when In is 4, Ga is 1 to 3 (1≦Ga≦3), and Zn is 2 or more and 4.1 or less (2≦Zn≦4.1). Also, In:Ga:Zn=5:1:6 Or in its vicinity means that when In is 5, Ga is greater than 0.1 and less than or equal to 2 (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also , when it comes to In:Ga:Zn = 1:1:1 or in its vicinity, for the total number of atoms, when In is 1 , Ga is greater than 0.1 and less than or equal to 2 (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and less than or equal to 2 (0.1 < Zn ≤ 2).

[0057] (Embodiment 1) In this embodiment, the configuration, manufacturing method, circuit configuration , and operation of a semiconductor device according to one aspect of the disclosed invention will be described with reference to FIGS. 1 to 36.

[0058] (Memory Transistor MT, Memory Cell Array 700) First, the configuration of the memory transistor MT and the memory cell array 700 of the semiconductor device will be described with reference to FIGS. 1 to 3. FIG. 1 is a cross-sectional view of the memory cell array 700. FIGURE 2(A) is a top view of the memory cell array 700. Note that FIG. 2(A) is a top view of the plane indicated by the dashed line A5 - A6 in FIG. 1, and some components are omitted and shown. Also, FIG. 1 is a cross-sectional view of the part indicated by the dashed line A|1 - A2 in FIG. 2(A) . Also, FIG. 2(B) is a cross-sectional view of the part indicated by the dashed line A3 - A4 in FIG. 2(A) and is a cross-sectional view for explaining an example of a memory string. Also, FIG. 3(A) is a cross-sectional view of the part enclosed by the dashed line 791 in FIG. 1, enlarged, and is a diagram for explaining an example of a memory transistor MT that functions as a memory cell . Also, FIG. 3(B) is a cross-sectional view of the part enclosed by the dashed line 792 in FIG. 1, enlarged , and is a diagram for explaining an example of a selection transistor that functions as a selection transistor. Also, FIG. 3(B) is a cross-sectional view of the part enclosed by the dashed line 792 in FIG. 1, enlarged 1 and 2 are diagrams illustrating an example of a transistor that functions as a For convenience, an orthogonal coordinate system consisting of x-axis, y-axis, and z-axis will be set up as shown in Figure 2. The x-axis and y-axis are parallel to the upper surface of the substrate 720 on which the memory cell array 700 is provided. The z-axis is taken perpendicular to the upper surface of the substrate 720.

[0059] The memory cell array 700 has an insulator 721 on a base 720. , conductors 701 (conductors 701_1 to conductors 701_m: m is a natural number of 2 or more), and and the insulators 722 (insulators 722_1 to 722_m) are alternately stacked. 702 and an insulator on the laminate. 724, which penetrates the insulator 724, the conductor 702, the stack, and the insulator 721. The insulators 703 (insulators 703_1 to 703_2) are disposed inside the openings formed as shown in FIG. 4), and oxides 704 (oxides 704_1 to 704_4) are formed inside the insulator 703. 4) between the insulator 703 and the oxide 704 so as to be in contact with a part of the oxide 704. The oxide layer 704 has a layer 716 containing at least one of a metal element, hydrogen, and nitrogen. The insulators 711 (insulators 711_1 to 711_4) are provided inside the insulator 711. The conductors 712 (conductors 712_1 to 712_4) are disposed inside the oxide 70. The upper ends of the oxides 704_1 to 704_4 are electrically connected to the conductors 705 (conductive 704_1 to 704_4) The lower ends of the conductors 706 (conductors 706_1 to 706_6) are electrically connected to the conductors 706. _4), and an insulator 717 and an insulator 724 are disposed on the insulator 724 and the conductor 705. 13, and the conductors 712_1 to 712_4 are electrically connected to the conductors 712_1 to 712_4. conductor 714 and conductor 715, and conductors 701_1 to 701_m and The conductors 707 (conductors 707_1 to 707_m) are electrically connected to each other. The conductors 707_1 to 707_m and the conductors 708 (conductors 1 and 2, a plurality of In order to represent the conductor 701, the conductor 701 is shown in four or more stages. The number of stages of the conductor 701 is not limited to one, but may be at least two or more.

[0060] Here, as shown in FIG. 1 and FIG. 2(A), the conductor 701 is provided extending in the x-axis direction. As shown in FIGS. 1 and 2B, the insulator 703 and the oxide 704 The conductor 701, the insulator 703, and the oxide 704 are arranged to extend in the z-axis direction. It is preferable that the conductors 04 and 05 are disposed so as to intersect perpendicularly with each other. The conductor 707 is provided extending in the z-axis direction. The conductor 708 is provided extending in the y-axis direction. In addition, a conductor functioning as the bit line BL connected to the conductor 705 may be provided. It is also possible to provide the conductor 705 extending in the y-axis direction. The conductor 705 may be provided extending in the y-axis direction.

[0061] The conductor 712 is formed in a columnar shape and extends in the z-axis direction. An insulator 711 is provided to surround the body 712, and an oxide film is further provided to surround the insulator 711. 704 are provided, each extending in the z-axis direction. A conductor 712 is provided like a core inside the columnar oxide 704. An insulator 711 is provided between the conductor 704 and the conductor 712. The insulator 703 is The conductor 707 is provided so as to surround the side periphery of the columnar oxide 704. and extends in the z-axis direction.

[0062] The diameter of the openings formed in the insulators 721, 722, and 724 is 701 and the diameter of the opening formed in the conductor 702, and the layer 716 is insulator 721 , insulator 722, and insulator 724 are provided on the sides thereof via insulator 703. 16 contacts a part of the oxide 704, thereby lowering the resistance of the region, and forming a low resistance region. The oxide 704 has a low resistance region, and thus the memory cell stack In a memory cell array, the serial resistance between memory cells can be reduced. can.

[0063] The columnar oxide 704 is electrically connected to the conductor 706 at its lower end in the z-axis direction, and At the end, the conductor 705 is electrically connected. 706 is electrically connected to the bottom ends of two adjacent pillar-shaped oxides 704, and the two pillar-shaped oxides The upper ends of the conductors 704 are electrically connected to the electrically isolated conductors 705, respectively. In this embodiment, a U-shaped oxide film is formed by electrically connecting two pillar-shaped oxides 704 with a conductor 706. Although the present invention will be described with reference to a memory string, the present invention is not limited to this. For example, the conductor 70 6 is one of the bit line BL and the source line SL, and the conductor 705 is one of the bit line BL and the source line SL. In this case, the conductor 706 may be a plurality of columnar oxides 70. 4, or may be electrically connected to one columnar oxide 704. The conductor 705 may be electrically connected to a plurality of pillar-shaped oxides 704, or may be connected to a single pillar-shaped oxide. It may be electrically connected to the oxide 704 .

[0064] The bottom end of the columnar oxide 704 is electrically connected to one of the bit line BL and the source line SL, and the top When the end is electrically connected to the other end, selective transistors are provided near the bottom end and the top end of the columnar oxide 704. For example, the conductor 706 may be a part of the bit line BL, When 705 is a part of the source line SL, a conductor 706 and a memory transistor MT are , the selection transistor SST, the conductor 705 and the memory transistor MT, Provide a resistor SDT.

[0065] Here, the region where the conductor 701 intersects with the insulator 703 and the oxide 704 and The area around the conductor 702 functions as a memory transistor MT. The region where the oxide 704 intersects with the gate electrode 3 and the oxide 704 and its vicinity function as a select transistor. The channel length direction of these memory transistors MT and select transistors is the z-axis. The memory transistor MT and the select transistor are electrically connected in series. These constitute a memory string.

[0066] FIG. 3A is an enlarged cross-sectional view of the portion surrounded by the dashed line 791 in FIG. 1. 1 is a diagram showing a cross section of a memory transistor MT at a k-th stage (k is an integer of 2 or more and m-1 or less). The memory transistor MT includes a conductor 701_k and an insulator 703 (insulator 703a, Insulator 703b and insulator 703c) and oxide 704 (oxide 704a, oxide 7 704b and oxide 704c). 1.

[0067] The conductor 701_k functions as the gate of the memory transistor MT, and the insulator 703a , serves as a gate insulating layer, insulator 703b serves as a charge storage layer, and insulator 70 3c functions as a tunnel insulating layer.

[0068] As will be described in detail later, the oxide 704 is made up of oxide 704a, oxide 704b, and oxide 704b. 704c, and the oxide 704a has a relatively high energy The gap is wide, and the oxide 704c has a relatively high energy gap with respect to the oxide 704b. In other words, the oxide 704b has a wider gap than the oxide 704a and the oxide 704c. Therefore, the energy gap is relatively narrow.

[0069] In addition, a region 734 of the oxide 704 located in the same layer as the conductor 701_k is a channel In addition, the oxide 704 contains a small amount of metal elements, hydrogen, and nitrogen. The region 731 (region 731a, region 731b) in contact with the layer 716 containing at least one of the In addition, the region 732 (region 7) located between the region 734 and the region 731 functions as a Region 732a, region 732b) function as a junction region. Region 732 is thicker than region 734. It is preferable that the region 732 has a low resistance. The region 732 may have a higher resistance than the region 731. The region 731 may function as a channel forming region, or may function as a low resistance region similar to the region 731. You may do so.

[0070] The k-th memory transistor MT is the k-1-th memory transistor MT or the k The +1st stage memory transistor MT shares a low resistance region. The oxide 704 is the low resistance region. By having such a structure, a memory string in which memory cells are stacked or a memory cell array can be In this case, the series resistance between memory cells can be reduced.

[0071] When the conductor 712 is provided, the conductor 701_k functions as a first gate, and the conductor 7 12 functions as the second gate. The first gate is also referred to simply as the gate or The gate is called the back gate, and the second gate is called the oxide 7 An insulator 711 is provided between the gate insulating layer 714 and the conductor 712, and functions as a second gate insulating layer. At this time, the insulator 703a functions as a first gate insulating layer. In the circuit operation of the transistor MT, the potential of the conductor 712 functioning as the second gate is controlled. By controlling the voltage, the power consumption of the memory transistor MT can be reduced.

[0072] FIG. 3B is an enlarged cross-sectional view of the portion surrounded by the dashed line 792 in FIG. 1. Select transistors (bit line side transistor: SDT, and source line side transistor: The select transistor is made up of a conductor 702 and an insulator 703 ( Insulator 703a, insulator 703b, and insulator 703c) and oxide 704 (oxide 7 704a, oxide 704b, and oxide 704c). and an insulator 711 .

[0073] The conductor 702 functions as the gate of the selection transistor, and the insulator 703a functions as the gate insulator. The gate insulating layer may include at least the insulator 703a. The insulators 703b and 703c may not be provided. a, the insulator 703b, and the insulator 703c are provided, and then the insulator 703b and The insulating material 703c may be removed.

[0074] The oxide 704 includes oxide 704a, oxide 704b, and oxide 704c. The oxide 704a has a relatively wide energy gap compared to the oxide 704b. The oxide 704c has a relatively wide energy gap compared to the oxide 704b. As a result, the oxide 704b has relatively high energy density compared to the oxide 704a and the oxide 704c. The energy gap is narrow.

[0075] In addition, a region 734 of the oxide 704 located in the same layer as the conductor 702 is a channel forming region. In addition, at least a metal element, hydrogen, and nitrogen are contained in the oxide 704. The region 731 (region 731a, region 731b) in contact with the layer 716 containing the SiO 2 is a low resistance region. In addition, the region 732 (region 732) located between the region 734 and the region 731 functions as a Region 732a and region 732b function as junction regions. Region 732 has a lower resistance than region 734. It is preferable that the region 732 has a resistance value similar to that of the region 731. The region 732 may have a higher resistance than the region 731. It may function as a channel forming region, or it may function as a low resistance region like the region 731. Good too.

[0076] When the conductor 712 is provided, the conductor 702 functions as a first gate, and the conductor 712 The first gate functions as a second gate. The first gate is sometimes called the first gate, and the second gate is sometimes called the back gate. An insulator 711 is provided between the gate electrodes 712 and functions as a second gate insulating layer. In this case, the insulator 703a functions as a first gate insulating layer. The active conductor 712 allows the threshold of the select transistor to be controlled.

[0077] Note that the structure of the semiconductor device described in this embodiment mode is an example, and the present invention is not limited to this embodiment mode. The number and arrangement of circuit elements, wiring, etc. shown in the drawings are not limited to those shown in the drawings. The number and arrangement of circuit elements, wiring, etc., included in the semiconductor device according to this embodiment etc. can be set appropriately in accordance with the circuit configuration and driving method.

[0078] The base 720 on which the memory cell array 700 is provided preferably has an insulating surface. Substrates having an insulating surface include semiconductor substrates with an insulator formed on the surface, insulating substrates, and A conductive substrate with an insulator formed on its surface may be used. Semiconductor substrates such as silicon and germanium, or silicon carbide and silicon germanium semiconductor substrates such as gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. The insulating substrate may be, for example, a glass substrate, a quartz substrate, or a sapphire substrate. Plates, stabilized zirconia substrates (yttria-stabilized zirconia substrates, etc.), resin substrates, etc. In addition, the semiconductor substrate having an insulator region therein, for example, SO A silicon-on-insulator (I) substrate may also be used. The substrate may be a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like.

[0079] The conductor 701 functions as the gate of the memory transistor MT and is electrically connected to the word line. That is, conductor 701, conductor 707, and conductor 708 are connected to the word line Here, the conductor 701 functions as a part of the underlying conductor 70 as shown in FIG. It is preferable that the conductive layer 1 is provided in a stepped shape extending from the upper conductive layer 701 toward the A2 side. As shown in the figure, by providing the conductor 701, a part of the upper surface of the lower conductor 701 Since the conductor 701 does not overlap with the conductor 701 in the upper layer, the conductor 701 in the corresponding region of each layer and each conductor 7 07 can be connected.

[0080] The conductor 701 can be made of a conductive material such as silicon or metal. When silicon is used as the conductor 701, amorphous silicon or polysilicon may be used. In addition, to make silicon conductive, p-type impurities or n-type impurities can be added. Pure materials may also be added. In addition, conductive materials containing silicon may include titanium, cobalt, or Alternatively, a silicide containing nickel can be used as the conductor 701. When the material is used for the conductor 701, aluminum, chromium, copper, silver, gold, platinum, tantalum, Nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese Choose from cancer, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more of the above metal elements can be used.

[0081] The conductor 702 is provided on the conductor 701. The conductor 702 is a select transistor. (Bit line side select transistor: SDT, and source line side select transistor: SST) and electrically connects to the wiring DGL or wiring SGL. The conductor 702 also functions as a part of the wiring DGL or the wiring SGL. The conductor 702 can be made of the same material as the conductor 701. The same material as the conductor 701 may be used, or a different material may be used. The material of the conductor 702 may be determined depending on the application, taking into consideration the work function and the like.

[0082] The insulating films provided on the upper and lower layers of the conductor 701 and the conductor 702 are Oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, Metal nitride oxides, etc. can be used. Silicon oxide, silicon oxynitride, nitride oxide Silicon, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide Silicon oxide doped with carbon and nitrogen, silicon oxide with pores, or resins are comparatively Because of its low dielectric constant, it is suitable for use in the insulating film.

[0083] On the other hand, the insulating film may be made of aluminum oxide, gallium oxide, hafnium oxide, or zirconium oxide. oxides containing ruthenium, aluminum and hafnium, oxide nitride with silicon and hafnium, oxide with silicon and hafnium, Nitride oxide containing hafnium or nitride containing silicon and hafnium However, since these have a high relative dielectric constant, the conductors 701 may be separated from each other or from each other. Parasitic capacitance may occur between the conductor 702 and the conductor 703. The material to be used for the insulating film can be determined.

[0084] The insulator 703 includes an insulator 703a, an insulator 703b, and an insulator 703c. The insulator 703a is provided on the conductor 701 side, and the insulator 703c is provided on the oxide 704 side. The insulator 703b is provided between the insulators 703a and 703c. 703a serves as a gate insulating layer, and insulator 703b serves as a charge storage layer; The insulator 703c functions as a tunnel insulating layer.

[0085] The select transistor may have the same structure as the memory transistor MT. As shown in (B), the select transistor must be provided with a charge storage layer and a tunnel insulating layer. The bit line side transistor: SDT, and the source line side transistor: SST In this case, the insulators 703b and 703c are removed, and the insulator 703 is replaced by the insulator 7 Alternatively, only the oxide 704 may be provided. The structure has three layers: oxide 704a, oxide 704b, and oxide 704c. The oxide 704 has a two-layer structure of an oxide 704a and an oxide 704b. The second gate electrode may have a laminated structure of four or more layers. In this case, the conductor 702 functions as a first gate electrode and is an insulating The insulator 703a functions as a first gate insulating film, and the insulator 711 functions as a second gate insulating film. The conductor 712 can control the threshold of the selection transistor. do.

[0086] The insulator 703a is preferably made of silicon oxide or silicon oxynitride. Also, aluminum oxide, hafnium oxide, or aluminum and hafnium oxide Alternatively, these oxides may be stacked to form the insulator 703a.

[0087] The insulator 703b is preferably made of a material that functions as a charge storage layer, and silicon nitride is It is preferable to use silicon dioxide or silicon nitride oxide. Oxides containing niobium, or aluminum and hafnium may also be used.

[0088] The insulator 703c is preferably made of silicon oxide or silicon oxynitride. Also, aluminum oxide, hafnium oxide, or aluminum and hafnium oxide Alternatively, an oxide such as SiO 2 may be used. Alternatively, these may be stacked to form the insulator 703c. The insulator 703c is preferably thinner than the insulator 703a. When writing or erasing data to the transistor MT, the insulator 703c passes through the insulator 703c. , charge transfer occurs between the oxide 704 and the insulator 703b. 3c functions as a tunnel insulating layer.

[0089] In particular, the opening formed in the laminated body having the conductor 701, the conductor 702, and the insulating film When forming the insulator 703, the insulator 703 formed at the bottom of the opening is removed by dry etching. It is necessary to remove it by anisotropic etching using a tool such as a grease gun. The side surfaces of the insulator 703c are also exposed to plasma, radicals, gas, chemicals, etc. When the side surface of the insulator 703c is damaged by these, a trap cell is formed in the insulator 703c. This can cause trap centers, which can affect the electrical characteristics of the transistor. To suppress the generation of ions, the side surface of the insulator 703c is made resistant to damage caused by etching. In this case, the insulator 703c is made of aluminum oxide. silicon oxide and aluminum oxide, or silicon oxynitride and aluminum oxide It is preferable to use a stack of silicon dioxide.

[0090] The insulators 703a, 703b, and 703c are formed by ALD (Atomic Deposition). Layer Deposition (CVD) and Chemical Vapor Deposition (CVD) The insulators 703a and 703b can be formed by using a position method. In order to prevent contamination of the interface between the insulator 703b and the insulator 703c, In this method, a multi-chamber film deposition system with multiple chambers is used to expose the film to the atmosphere. It is preferable to form the films continuously without interruption.

[0091] The oxide 704 is a metal oxide that functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor). It is preferable to use oxide semiconductors, which are superior to semiconductors made of silicon and the like. This is preferable because the transistor has good on-state characteristics and high mobility.

[0092] For example, the oxide 704 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, One or more selected from tantalum, tungsten, magnesium, etc.) The oxide 704 may be an In-Ga oxide or an In-Z n-oxides may also be used.

[0093] The oxide 704 is made up of an oxide 704a provided on the insulator 703c side and an oxide 704b on the insulator 703c side. An oxide 704b is provided on the inside, and an oxide 704c is provided on the inside of the oxide 704b. In this case, the oxide 704a preferably has the following relative structure to the oxide 704b: It is preferable to use an oxide with a relatively wide energy gap. c) Use an oxide with a relatively wide energy gap compared to the oxide 704b. Here, oxides with a wide energy gap are referred to as wide gap, energy Oxides with narrow gaps are sometimes called narrow gaps.

[0094] The oxide 704a and the oxide 704c are wide-gap oxides, and the oxide 704b is narrow-gap oxide. When the oxide 704a and the oxide 704c are set to a conduction band gap, the energy It is preferable that the energy of the oxide 704b is higher than the energy of the bottom of the conduction band of the oxide 704b. In other words, the electron affinity of the oxide 704a and the oxide 704c is smaller than that of the oxide 704b. It is preferably smaller than the electron affinity.

[0095] In addition, the oxide 704a, the oxide 704b, and the oxide 704c are formed by adding the atoms of the respective metal atoms. It is preferable to combine oxide 704a and oxide 704b in different numerical ratios. In the metal oxide used for the oxide 704c, the atomic ratio of element M in the constituent elements is The atomic ratio of element M in the constituent elements of the metal oxide used in 04b is larger than that In addition, in the metal oxide used for the oxide 704a and the oxide 704c, The atomic ratio of element M to In in the metal oxide used for oxide 704b is It is preferable that the atomic ratio of the metal to the oxide 704b is larger than that of the element M. In the oxide, the atomic ratio of In to element M is In the metal oxide used in 4c, the atomic ratio of In to element M is preferably larger than that of In. It's nice.

[0096] The oxide 704a and the oxide 704c are made of, for example, In:Ga:Zn=1:3:4, I Compositions of n:Ga:Zn=1:3:2 or In:Ga:Zn=1:1:1 or similar The oxide 704b may be, for example, a metal oxide having a similar composition. In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, or In : Use a metal oxide having a composition of Ga:Zn=5:1:6 or a composition close to that These oxides 704a, 704b, and 704c can be It is preferable to combine them while satisfying the relationship of the number of atoms ratio. For example, oxide 704a and The oxide 704c has a composition of In:Ga:Zn=1:3:4 or a composition close to that. The metal oxide, oxide 704b, is selected from In:Ga:Zn=4:2:3 to 4.1 in composition and It is preferable to use a metal oxide having a composition close to that range. The atomic ratio in the oxide formed or the atomic ratio in the sputtering target is shown.

[0097] The oxide 704a and the oxide 704c are formed using CAAC-OS, which will be described later. It is preferable to use CAC-OS as the oxide 704b. When the oxide 704c is a CAAC-OS, the c-axis is the same as that shown in FIGS. The direction is parallel to the xy plane shown in the figure, i.e. perpendicular to the z axis, and extends from the side of the opening toward the center. It is preferable to orient the particles in this way.

[0098] Here, the junction between oxide 704a and oxide 704b, and the junction between oxide 704c and oxide 704b are At the junction of oxide 704b, the conduction band edge changes gradually. a and oxide 704b, and oxide 704c and oxide 704b. The conduction band edge can be said to change continuously or to be a continuous junction. In order to achieve this, the interface between oxide 704a and oxide 704b and the interface between oxide 704c and oxide 704d must be It is preferable to reduce the defect level density of the mixed layer formed at the interface with 04b.

[0099] Specifically, the oxide 704a, the oxide 704b, and the oxide 704c contain, in addition to oxygen, By having a common element (as the main component), a mixed layer with a low defect level density can be formed. For example, when the oxide 704b is an In-Ga-Zn oxide, the oxide 704a , and oxide 704c includes In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, This allows the interface between the oxide 704a and the oxide 704b and The defect state density at the interface between the oxide 704c and the oxide 704b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the memory transistor MT can obtain a high on-current.

[0100] For a more detailed description of metal oxides that can be used as the oxide 704, see , as will be described later.

[0101] FIG. 3A is an enlarged view of the memory transistor MT enclosed by the dashed line 791 in FIG. As shown in FIG. 3A, the oxide 704b is a mixture of the oxide 704a and the oxide 704 In this configuration, the oxide 704 is sandwiched between the conductors c. The direction from 705 to conductor 706 or from conductor 706 to conductor 705 When carriers flow, they mainly flow in the component with a narrow gap. Therefore, when the above-mentioned configuration is used, the oxide 704b, which is a narrow gap, is replaced with the oxide 704b, which is a wide gap. By sandwiching the oxide 704 between the oxide 704a and oxide 704c, the capacitance flowing through the oxide 704 is reduced. The rear can be confined to the oxide 704b, and a high current can be obtained in the on-state of the transistor. Therefore, a current driving force, that is, a large on-state current and a high field-effect mobility can be obtained.

[0102] Furthermore, by providing the oxide 704a between the oxide 704b and the insulator 703c, The oxide 704b, which serves as a carrier path, does not come into direct contact with the insulator 703c. The formation of a pit center can be suppressed at the interface between the semiconductor (oxide semiconductor) and the insulator. The trap centers formed in the This may adversely affect the reliability and on / off characteristics of the transistor. Therefore, the transistor using this oxide has poor electrical characteristics due to the trap center. Since the device is not affected by the The transistor and the semiconductor device can achieve high current and high field-effect mobility. A semiconductor device including such a transistor can have high reliability.

[0103] In order to provide a low resistance region in the oxide 704, a gold film was formed in contact with a part of the oxide 704. It is preferable to provide a layer 716 containing one of a metal element, hydrogen, and nitrogen. 6 is connected to the sides of the insulators 721, 722, and 724 via the insulator 703. As will be described in detail later, the insulating material 721, the insulating material 722, and the insulating material 724 are formed as insulators. The diameter of the opening formed is larger than the diameter of the opening formed in the conductor 701 and the conductor 702. Layer 716 is only present in the same layer as insulators 721, 722, and 724. Therefore, the oxide 704 is formed in the region in contact with the insulator 703 and the region in contact with the layer 716. It has.

[0104] The layer 716 has the functions of supplying hydrogen to the oxide 704, supplying nitrogen to the oxide 704, and and a function of extracting oxygen from the oxide 704. The layer 716 having such a function contacts the oxide 704, and thereby the oxide 704 is filled with the quenching agent. A carrier is generated.

[0105] Specifically, oxygen is extracted from the oxide 704, and the oxide 704 contains oxygen. A defect occurs. Hydrogen is trapped in this oxygen defect, generating carriers. Alternatively, if nitrogen is trapped in the resulting oxygen vacancy, it will bond with two indium atoms. When nitrogen bonds to these two indium atoms, Nitrogen has an unpaired electron and is thought to function as a carrier.

[0106] As a material that has the function of supplying hydrogen to the oxide 704, silicon nitride containing hydrogen is used. In addition, a material formed using a gas containing hydrogen can be used. It can be formed using monosilane, disilane, ammonia, etc., and is a silicon, silicon oxide Silicon oxide, silicon oxynitride, silicon nitride oxide, etc. can be used. Nitrides containing silicon or metal elements are used as materials with the function of supplying nitrogen. Such materials include silicon nitride, silicon nitride oxide, and silicon oxynitride. , etc. Also, one or more of aluminum, tantalum, and titanium can be used. Specifically, nitrides containing aluminum nitride, tantalum nitride, and nitrides containing tantalum nitride can be used. titanium nitride, nitrides containing aluminum and tantalum, nitrides containing aluminum and titanium, etc. etc. can be used.

[0107] The oxide 704 is in contact with a layer 716 containing any one of a metal element, hydrogen, and nitrogen. After the formation of the layer, it is preferable to perform a heat treatment. By performing the heat treatment, oxygen is extracted and hydrogen is removed. The supply of oxygen or nitrogen is promoted, and the resistance of the oxide 704 is efficiently reduced partially. In this way, by providing a low resistance region in the oxide 704, the memory cell In stacked memory strings or memory cell arrays, the series resistance between memory cells The resistance can be reduced.

[0108] When the conductor 712 is provided, the same material as the conductor 701 may be used for the conductor 712. The conductor 712 is formed inside the opening with a large aspect ratio (in other words, inside the oxide 70 4 and the recess of the insulator 711), so that It is preferable that the insulator 711 is formed by plating. Similar materials can be used.

[0109] In addition, when the insulator 711 is provided inside the oxide 704c, the insulator 711 is 04 is a material that can supply oxygen or impurities such as hydrogen and nitrogen. By using an oxide containing as little hydrogen or nitrogen as possible as the insulator 711, Oxygen can be supplied to the oxide 704. By supplying oxygen to the oxide 704, the oxide Impurities such as hydrogen and water contained in the oxide 704 can be removed. By using an oxide with as few impurities as possible as the oxide 704, The transistor MT and the semiconductor device using the memory transistor MT have high reliability. You can get sexuality.

[0110] In addition, by using an oxide containing hydrogen or nitrogen as the insulator 711, the oxide 704 In some cases, hydrogen or nitrogen can be supplied. By supplying hydrogen or nitrogen to the oxide 704, the oxide The resistance of the oxide 704 may be reduced so that it does not adversely affect the circuit operation. By lowering the voltage to a level that does not exceed the threshold voltage, the memory transistor MT can be operated at a lower drive voltage. In addition, when the memory transistor MT is in the on state, a high current driving force, i.e., A large on-current and a high field effect mobility can be obtained.

[0111] The opening formed in the stacked body in which the memory transistor MT is provided is In the above, the upper surface is circular, but the shape is not limited to this. For example, the upper surface may be elliptical. The shape may be a rectangular shape, or a polygonal shape such as a triangle or a square. In this case, the corners may be rounded. Therefore, the top surface shapes of the insulator 703 and the oxide 704 may also change. The opening has a cross-sectional area of ​​a lower opening (on the conductor 706 side) that is larger than that of an upper opening (on the conductor 705 side). The cross-sectional area of ​​the groove may be narrowed.

[0112] The oxide 704, the insulator 703, and the conductor 701 (conductors 701_1 to 701_2) 1 and 2) constitute a memory transistor MT. shows an example in which memory transistors MT are stacked in m stages (m is a natural number of 2 or more). 1 and 2, the conductors 701 are shown in four rows to represent the plurality of conductors 701. Although more than one stage is shown, this embodiment is not limited to FIG. 1 and includes at least conductors 70 It is sufficient to have two or more stages of 1.

[0113] The conductor 705 is electrically connected to the oxide 704 and is connected to the source line SL or the bit line BL The conductor 705 may be formed of a conductive material containing a metal element. Alternatively, among the materials that can be used for the layer 716 as the conductor 705, In this case, as described above, a part of the oxide 704 In addition, the resistance of the conductor 705 is reduced at the interface between the conductor 705 and the oxide 704. It is preferable that a metal compound layer containing the metal element and the component of the oxide 704 is formed. The formation of the metal compound layer makes contact between the conductor 705 and the oxide 704. Alternatively, the conductor 705 may be formed by absorbing oxygen contained in the oxide 704. The oxide 704 absorbs the conductor 705 and reduces the resistance of the oxide 704 near the interface between the conductor 705 and the oxide 704. Therefore, the contact resistance between the conductor 705 and the oxide 704 can be reduced.

[0114] The conductor 705 may be aluminum, ruthenium, titanium, tantalum, chromium, tungsten, or the like. Use a conductive material containing one or more metal elements selected from stainless steel and copper. is preferred.

[0115] The conductor 706 is a conductor that functions as a part of the bit line BL, as shown in FIG. 705 and an oxide 704 electrically connected to the source line SL. 05 and the oxide 704 electrically connected to the memory string. The area enclosed by the dotted line in Figure 2(A) represents the memory string. That is, FIG. 2A shows a memory cell array 700 having four memory strings. are.

[0116] The conductor 706 can be made of the same material as the conductor 705. As 706, a material having conductivity among the materials that can be used for the layer 716 is used. In this case, as described above, a part of the oxide 704 has a low resistance. The conductor 706 may be made of the same material as the conductor 705 or may be made of a different material.

[0117] In addition, at the interface between the conductor 706 and the oxide 704, a metal element contained in the conductor 706 and an oxide It is preferable that a metal compound layer containing the metal compound 704 is formed. The formation of the layer reduces the contact resistance between the conductor 706 and the oxide 704. Alternatively, the conductor 706 absorbs oxygen contained in the oxide 704, and the oxide 704 is formed. By reducing the resistance near the interface between the conductor 706 and the oxide 704 in 04, the conductor 706 By doing so, the contact resistance with the oxide 704 can be reduced.

[0118] (Memory cell array 700A) FIG. 4 shows a memory cell array 700 having six stages of memory transistors MT. 4 is a top view illustrating a memory cell array 700A. For example, the selection transistor provided on the conductor 701 is omitted. Transistors (bit line side transistor: SDT, and source line side transistor: SST) ) and the conductor 702 which is a component thereof are omitted. A conductor 705 functions as a part of the source line SL, a conductor 706 functions as a part of the word line WL, The wiring BG electrically connects the conductor 708 and the conductor 712 that functions as a second gate. The conductor 715 that functions as part of the conductor 715 is shown in solid lines.

[0119] In the memory cell array 700A, each memory cell array 700 has six stages of memory transistors. The memory cell has four memory strings each having a transistor MT.

[0120] The bit line side ends of the memory strings are connected to different bit lines BL (BL_1 to BL_B L_4), the source line side end of the memory string is electrically connected to the source line S The source line SL is electrically connected to the ground line L and is given a common potential. Alternatively, a constant potential may be applied. The position may be changed.

[0121] The conductors 701_1 to 701_6 are electrically connected to different word lines WL. The conductors 701_1 to 701_6 on the bit line side are connected to WLa_1 to WLa_6, respectively. The conductors 701_1 to 701_6 on the source line side are electrically connected to , are electrically connected to WLb_1 to WLb_6, respectively.

[0122] The conductors 712 are electrically connected to the wiring BG. 712 is electrically connected to the common wiring BG, the present invention is not limited to this. The conductors 712 arranged in the row direction may be electrically connected to a common wiring BG. Alternatively, a different potential may be applied to each wiring BG. In this case, it is preferable that the plurality of wirings BG are electrically connected to each other. The plurality of wirings BG may refer to all of the wirings BG included in the memory cell array 700A. There is a match.

[0123] In addition, in order to apply an arbitrary potential to the wiring BG, the wiring BG must be connected to a power supply that controls the potential of the wiring BG. The circuit that controls the It is sometimes called a driver or driver circuit. The BG driver circuit may be provided for each BG wiring, or one BG driver circuit may be provided for each BG wiring. For example, a plurality of wirings BG may be electrically connected to the memory cell array 700A. has one BG driver circuit and connects all the wiring BGs of the memory cell array 700A. may be electrically connected to the BG driver circuit.

[0124] The bit lines BL (BL_1 to BL_4) and the word lines WL (WLa_1 to WLa WLb_1 to WLb_6) are appropriately selected to form the memory cell array 70 0 can be selected. Data can be written to, read from, erased, etc., from the transistor MT.

[0125] In addition, each memory string is provided with a selection transistor (not shown). Therefore, an arbitrary memory cell array 700 in the memory cell array 700A is selected, and the selected Write and read operations can be performed on any memory transistor MT in the memory cell array 700. You can then erase it, etc.

[0126] (Configuration example of storage device 750) FIG. 5 shows a memory device 75 in which a memory cell array 700A is stacked on a circuit 300. 5, the memory cell array 700A includes a transistor 30 1, a circuit 300 having a transistor 302 and a transistor 303 is formed. The transistors 301 and 302 are stacked in a region where the transistors 301 and 302 are stacked. 2 constitutes a sense amplifier 304, and transistor 303 serves as a column selection switch. Specifically, the bit line BL of the memory cell array 700A is connected to the transistor 30 The gate of the transistor 301 is electrically connected to one of the source and drain of the transistor 302. The transistor 302 is electrically connected to one of the source and drain of the transistor 302. The gate of the transistor 301 is electrically connected to the other of the source and drain of the transistor 301. In addition, one of the source and drain of the transistor 301 and the source of the transistor 302 The other of the drains is the source of a transistor 303, which functions as a column selection switch. and electrically connected to one of the drains. This reduces the layout area of ​​the memory device 750. In FIG. 5, ten stages of memory transistors MT are provided. 1 shows an example in which 20 memory transistors MT are provided per memory string. However, the number of layers in which the memory transistors MT are stacked is not limited to this. For example, The plates may be stacked in 64 or 128 layers, or may be stacked in 200 or more layers.

[0127] The bit lines BL of the memory cell array 700A are embedded in the insulators 726, 722, etc. The sense amplifier 304 and the column selection switch 306 are connected to the conductor 752 formed to be embedded therein. The circuit 300 is electrically connected to a transistor 303 that functions as a switch. The circuits and transistors shown are examples, and are not limited to the circuit configurations and transistor structures. In addition to the above, there are also control circuits, row decoders, row drivers, source line drivers, input / output circuits, Appropriate circuits and transistors are set depending on the configuration of the memory device 750 and its driving method. It can be done.

[0128] The transistor 301, the transistor 302, and the transistor 303 are formed on a substrate 311. conductor 316, insulator 315, and semiconductor made up of a part of substrate 311, respectively. region 313, and a low resistance region 314a that functions as a source or drain region; and low resistance region 314b. As shown in FIG. 5, one low resistance region is The source or drain region of one of the transistors 301 and 302, In some cases, one of the two regions may be shared as the source region or drain region of the other.

[0129] The transistor 301, the transistor 302, and the transistor 303 have a channel formed The semiconductor region 313 (part of the substrate 311) formed thereon has a convex shape. The side and top surfaces of the heat sink 13 are covered with a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. The transistor 301, the transistor 302, and the transistor 303 utilize the protruding portion of the semiconductor substrate. It is also called a FIN type transistor because it uses a The insulating layer may have an insulating material that functions as a mask for forming the semiconductor portion. Although the case where a convex portion is formed by processing a part of a conductor substrate has been shown, it is also possible to process an SOI substrate to form a convex shape. Alternatively, a semiconductor film having the following structure may be formed.

[0130] The transistor 301, the transistor 302, and the transistor 303 are p-channel transistors. The transistor 301 and the transistor 302 may be either a n-channel or n-channel type. The transistors 302 are preferably transistors each having a different polarity.

[0131] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are the drain region, silicon is It preferably contains a semiconductor such as a silicon-based semiconductor, and preferably contains single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gallium It may be formed of a material containing gallium aluminum arsenide (GaAlAs), GaAlAs (Gallium Aluminum Arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, we can control the effective mass of silicon. Alternatively, GaAs and GaAlAs may be used to form a transistor. The transistor 301, the transistor 302, and the transistor 303 are HEMT (High Electrical MEMS) It may also be called a power transistor mobility transistor.

[0132] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the body material, elements that impart n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. The element imparting electrical conductivity is included.

[0133] The insulator 315 separates the transistors 301, 302, and 303. It functions as a gate insulating film.

[0134] The conductor 316 that functions as the gate electrode is made of an element that gives n-type conductivity, such as arsenic or phosphorus. Semiconductor materials such as silicon that contain elements that impart p-type conductivity, such as silicon or boron A conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0135] Since the work function is determined by the conductor material, the threshold can be adjusted by changing the conductor material. Specifically, titanium nitride, tantalum nitride, etc. are used as the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use a material such as It is preferable to use metal materials such as tungsten and aluminum as the lamination material, and particularly tungsten. It is preferable to use tin in terms of heat resistance.

[0136] An insulator 317 is provided above the conductor 316 to function as an etching stopper. In addition, it is preferable that the side of the insulator 315 is provided with an insulating layer that functions as a spacer. It is preferable that an insulator 318 is provided. As a result, the low resistance region 314a and the low resistance region 314b are electrically connected to the conductor 328. Therefore, the low resistance region 314a and the low resistance region 314b can be determined in a self-aligned manner. Misalignment occurred when forming the opening to expose a portion of the resist region 314b. In this way, an opening can be formed to expose the intended area. A conductor 328 is formed in the opening, forming a low resistance region 314a and a low resistance A good contact with reduced contact resistance is obtained between region 314b and conductor 328. The low resistance region 314a and the low resistance region 314b formed in this way are electrically conductive. The contact with the insulator 328 is sometimes called a self-aligned contact. 317, and a conductor electrically connected to the conductor 316 so as to be embedded in the insulator 322. An electrical current 329 may be provided.

[0137] The transistors 301, 302, and 303 are covered with an insulator. 320, insulator 322, insulator 324, insulator 326, and insulator 327 are stacked in this order. It is set up as follows.

[0138] As insulator 320, insulator 322, insulator 324, insulator 326, and insulator 327 For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide Aluminum, aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc. That's good enough.

[0139] The insulator 322 smooths out the steps caused by the transistor 301 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process such as chemical mechanical polishing (CMP). It's fine.

[0140] The insulator 324 also includes a substrate 311, a transistor 301, and the like. The region where the array 700A is provided has a barrier property that prevents hydrogen and impurities from diffusing. It is preferred to use a membrane.

[0141] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, a semiconductor having an oxide semiconductor such as a memory transistor MT can be used. When hydrogen diffuses into the conductive element, the characteristics of the semiconductor element may be deteriorated. , the diffusion of hydrogen is suppressed between the memory transistor MT and the transistor 301, etc. It is preferable to use a film that suppresses the diffusion of hydrogen. Specifically, the film that suppresses the diffusion of hydrogen is a film that suppresses the amount of hydrogen desorption. Use a small film.

[0142] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorption from the insulator 324 can be measured by TDS analysis when the surface temperature of the film is 5 In the range of 0 to 500°C, the amount of desorption converted to hydrogen atoms is Converted to 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 at oms / cm 2 The following is fine.

[0143] It is preferable that the insulators 326 and 327 have a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 and the insulator 327 is preferably less than 4, and more preferably 3. For example, the relative dielectric constant of the insulator 326 and the insulator 327 is preferably less than 1000 kJ / cm. The dielectric constant is preferably 0.7 times or less, more preferably 0.6 times or less, of the dielectric constant of the insulating body 324. By using a material with a low resistance as the interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0144] Also, insulator 320, insulator 322, insulator 324, insulator 326, and insulator 327 conductors 328 and 329, which are electrically connected to the memory cell array 700A, The conductor 330 and the like are embedded. 330 has a function as a plug or wiring. In the case of a conductor having a function, multiple structures may be collectively assigned the same symbol. In the specification and the like, the wiring and the plug electrically connected to the wiring may be integrated into one body. That is, when a part of the conductor functions as a wiring, and when a part of the conductor functions as a plug, Sometimes it works.

[0145] The materials of each plug and wiring (conductor 328, conductor 329, conductor 330, etc.) Examples of the conductive material include metals, alloys, metal nitrides, and metal oxides. Tungsten and other materials that have both heat resistance and electrical conductivity can be used as single layers or laminated layers. It is preferable to use a high melting point material such as molybdenum, and it is more preferable to use tungsten. Alternatively, it is preferable to form the wiring board from a low-resistance conductive material such as aluminum or copper. By using a resistive conductive material, the wiring resistance can be reduced.

[0146] A wiring layer may be provided on the insulator 327 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. , the insulator 350, the insulator 352, and the insulator 354 are formed with a conductor 356. The conductor 356 functions as a plug or wiring. The conductor 328, the conductor 329, and the conductor 330 may be formed using the same materials. do.

[0147] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. In addition, the conductor 356 has a barrier property against hydrogen. It is preferable that the insulating material 350 contains a conductor. In particular, the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 301 and the like can be separated from the memory transistor MT by a barrier layer. Therefore, the diffusion of hydrogen from the transistor 301 to the memory transistor MT can be suppressed. can be done.

[0148] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, It is possible to suppress the diffusion of hydrogen from the transistor 301 and the like while maintaining the conductivity of the transistor. In this case, the tantalum nitride layer, which has a barrier property against hydrogen, acts as a barrier against hydrogen. It is preferable that the insulating material 350 has a structure in which the insulating material 350 is in contact with the insulating material 350.

[0149] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. , an insulator 360, an insulator 362, and an insulator 364 are formed with a conductor 366. The conductor 366 functions as a plug or wiring. The conductor 328, the conductor 329, and the conductor 330 may be formed using the same materials. do.

[0150] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. The conductor 366 has a barrier property against hydrogen. It is preferable that the insulating material 360 contains a conductor. In particular, the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 301 and the like can be separated from the memory transistor MT by a barrier layer. Therefore, the diffusion of hydrogen from the transistor 301 to the memory transistor MT can be suppressed. can be done.

[0151] An insulator 722 is provided on the insulator 364 and the conductor 366. The memory cell array 700A is provided above the insulator 364 and the insulator 722. A barrier film made of a material similar to that of the insulator 324 may be provided between them.

[0152] In FIG. 5, a U-shaped memory cell is shown in which two pillar-shaped oxides 704 are electrically connected by a conductor 706. Although an example of the memory cell array 700A having a string has been shown, the present invention is not limited to this. Figure 6 shows eight stages of memory transistors MT and two select transistors (SDT, SST). In the columnar oxide 704 having the above structure, the bottom end of one columnar oxide 704 is connected to the bit line BL. The upper end is electrically connected to the conductor 705B functioning as the source line SL. In other words, one columnar oxide 704 is electrically connected to the columnar oxide 705S. In FIG. 6, the conductor 705B is made up of four Although the columnar oxide is electrically connected to the bottom end of the columnar oxide, the present invention is not limited to this. One conductor 705B may be electrically connected to the oxide 704, or two or more columnar oxides may be connected to the oxide 704. One conductor 705B may be electrically connected to 704. Also, conductor 705S may be The upper ends of the two pillar-shaped oxides are electrically connected to each other, but the present invention is not limited to this. One conductor 705S may be electrically connected to the columnar oxide 704, or two or more columns may be electrically connected to the columnar oxide 704. One conductor 705S may be electrically connected to the oxide 704.

[0153] A selection transistor SDT is provided between the conductor 705B and the memory transistor MT. A selection transistor SST is provided between the conductor 705S and the memory transistor MT. The conductor 705B, which functions as the bit line BL, is connected to the circuit 30 provided below. 0, and electrically connects the memory cell array 700A and the circuit 300. The number of wirings (routing wirings) and plugs for the storage device 750 can be reduced. This is preferable because it can further reduce the area of ​​the stacked layers. Although the number of memory transistors MT is eight, the present invention is not limited to this. For example, 32, 64, or 128 layers may be stacked. Alternatively, 200 or more layers may be stacked.

[0154] <<Metal oxides>> Metal oxides applicable to the oxide 704 according to the present invention will be described below.

[0155] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, titanium, iron, etc. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or One or more types may be included.

[0156] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, a combination of the aforementioned elements may be used.

[0157] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0158] [Metal oxide composition] Hereinafter, a CAC (C This paper explains the structure of the Cloud-Aligned Composite OS.

[0159] In this specification, CAAC (c-axis aligned crystal) l), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. An example is shown below.

[0160] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconducting properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making these functions work in a complementary manner, the switching function (On / Off) The function of making the CAC-OS or CAC-metal oxide In CAC-OS or CAC-metal oxide, the respective functions By separating the two, the functions of both can be maximized.

[0161] In addition, CAC-OS or CAC-metal oxide is a conductive area and an insulating area. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive and insulating regions in the material are formed by nanoparticles. The conductive region and the insulating region may be separated by different materials. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0162] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0163] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field-effect mobility can be obtained.

[0164] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0165] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor) and non crystalline oxide semiconductors.

[0166] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0167] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is difficult to confirm the lattice distortion. This is because the CAAC-OS crystals are grown in the ab-plane direction. In the case of ZnO, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated due to changes in the distance, etc.

[0168] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). It is noted that indium and element M tend to have a structure (also called a layered structure). When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) ) layer. Also, when indium in the In layer is replaced with element M, it can be expressed as (In, It can also be expressed as the M layer.

[0169] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS should be free from impurities and defects (oxygen vacancies (V O :oxygen v Therefore, CAAC- Metal oxides with OS have stable physical properties. Metal oxides are heat resistant and highly reliable.

[0170] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0171] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low density regions. The ke-OS has lower crystallinity than the nc-OS and CAAC-OS.

[0172] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention may be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more of them.

[0173] [Transistors with metal oxides] Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0174] Note that by using the above metal oxide for the channel formation region of a transistor, a high field efficiency can be achieved. It is possible to realize a transistor with high mobility. It can be realized.

[0175] Here, an example of a hypothesis regarding electrical conduction in metal oxides will be described.

[0176] Electrical conduction in solids is hindered by scattering sources called scattering centers. For example, in single crystals, In the case of silicon, lattice scattering and ionized impurity scattering are known to be the main scattering centers. In other words, when there are few lattice defects or impurities, the electrical conduction in the solid There are no blocking factors and carrier mobility is high.

[0177] The above is also assumed to be true for metal oxides. In metal oxides containing less oxygen than the oxygen that fills the composition, oxygen vacancies V O There are many It is thought that the atoms around this oxygen vacancy are in a distorted position rather than in their essential state. It is possible that the distortion caused by this oxygen vacancy is the scattering center.

[0178] Also, for example, in a metal compound containing more oxygen than the stoichiometric composition, Excess oxygen is present. Excess oxygen, which exists in a free state in the metal compound, accepts electrons. By doing so, O - Ya O 2- It becomes. - Ya O 2- The excess oxygen may become a scattering center. There is.

[0179] From the above, it is clear that metal oxides have an essential state in which oxygen is contained in a stoichiometric composition. In this case, the carrier mobility is considered to be high.

[0180] Indium-, a type of metal oxide containing indium, gallium, and zinc, Gallium zinc oxide (IGZO) tends to have difficulty growing crystals in the atmosphere. Therefore, smaller crystals are more likely to be formed than larger crystals (here, crystals of several mm or several cm). In some cases, crystals (such as the nanocrystals mentioned above) are structurally more stable. The strain energy is relieved more easily when small crystals are connected to each other than when large crystals are formed. This is thought to be because

[0181] In addition, in the region where small crystals are connected to each other, the strain energy of the region is relaxed. Therefore, defects may be formed in the region. By relaxing the strain energy, the mobility of carriers can be increased.

[0182] It is also preferable to use a metal oxide with a low carrier density for the transistor. When the carrier density of the metal oxide film is reduced, the impurity concentration in the metal oxide film is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. For example, metal oxides , the carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all. stomach.

[0183] Furthermore, a highly pure intrinsic or substantially highly pure intrinsic metal oxide film has a low density of defect states. Therefore, the trap level density may also be low.

[0184] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, the trap level density is high. A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. be.

[0185] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide must be kept low. In order to reduce the impurity concentration in the metal oxide, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0186] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0187] When metal oxides contain silicon or carbon, which are elements of Group 14, they become metal oxides. Defect levels are formed in the oxides. This leads to the formation of silicon and carbon concentrations in the metal oxides. The concentration of silicon and carbon near the interface with the metal oxide was measured by secondary ion mass spectrometry (SIM). S: Secondary Ion Mass Spectrometry) concentration) is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0188] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor that uses a metal oxide containing metals in the channel formation region is normally on. Therefore, the concentration of alkali metals or alkaline earth metals in metal oxides It is preferable to reduce the degree of Al in the metal oxide obtained by SIMS. The concentration of potassium metal or alkaline earth metal is 1×10 18 atoms / cm 3 Below, I prefer Or 2 x 10 16 atoms / cm 3 Do the following:

[0189] In addition, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, and the carriers As a result, the density increases and it becomes easier to make the metal oxide containing nitrogen into a channel type. The transistors used in the metal-doped region tend to be normally-on. In the oxide, it is preferable that the nitrogen content in the channel formation region is reduced as much as possible. For example, the nitrogen concentration in metal oxides is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following .

[0190] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, metal oxides containing hydrogen can be used The transistor tends to be normally on. Therefore, hydrogen in the metal oxide is not formed. Specifically, in the case of metal oxides, the The resulting hydrogen concentration is 1×1020 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 Less than.

[0191] Use of metal oxide with sufficiently reduced impurities in the channel formation region of a transistor Therefore, the off-state current of the transistor can be reduced and stable electrical characteristics can be provided.

[0192] (Method of manufacturing memory cells) Next, one embodiment of a method for producing a memory transistor MT that functions as a memory cell of the present invention. This will be described with reference to FIGS. 7 to 11. Note that FIGS. 7 to 11 show the memory transistor M 1A to 1C are cross-sectional views showing the manufacturing process of a T.

[0193] First, as shown in FIG. 7A, conductors 701 and insulators 722 are alternately stacked.

[0194] Next, as shown in FIG. 7B, the conductor 701 and the insulator 722 are processed to form the conductor 7 An opening having a diameter of φ1 is formed in the insulating material 722 and the insulating material 721.

[0195] Next, as shown in FIG. 7C, the insulator 722 is isotropically etched. The opening diameter of 722 is enlarged. The diameter of the opening at this time is φ2 (φ2>φ1). The edge 722 can be said to have a recess on the side of the conductor 701 sandwiched between it and the top and bottom. .

[0196] Next, an insulator 703 is formed inside the opening as shown in FIGS. 8(B) is an enlarged view of the area surrounded by the dashed line in FIG. 8(A), and shows the k-1th stage of the a conductor 701_k-1, an insulator 722_k-1, a conductor 701_k in the kth stage, and Insulator 722_k and conductor 701_k+1 in the (k+1)th stage (k is 2 or more and m-1 or less) The insulator 703 is made up of an insulator 703a, an insulator 703b, and an insulator 703c. The insulator 703 is formed by stacking the insulator 703c in order. , and the insulator 703a is formed with good coating properties, and the insulator 703a is formed on the side surface of the insulator 722, the side surface of the conductor 701, It is formed so as to contact a part of the upper surface and a part of the lower surface.

[0197] Next, as shown in FIG. 9(A), at least a metal element, hydrogen, and nitrogen are introduced into the opening. 9B shows the area surrounded by the dashed line in FIG. As shown in FIG. 9(B), the film 716A has an insulator 703 therebetween. However, the present invention is not limited to this. As shown in FIG. 9(C), the film 716 is formed so as to fill the entire opening, not just the recess. A may be formed.

[0198] Next, the film 716A is processed to form a layer 71 containing at least one of a metal element, hydrogen, and nitrogen. The film 716A is formed by isotropic etching or In forming the film 716A, anisotropic etching can be used. As shown, if film 716A fills the recesses and the openings are not completely filled, film 716 It is preferable to use isotropic etching for processing A. On the other hand, as shown in FIG. If the film 716A is formed to fill the recesses and openings, an anisotropic etch is performed. By the above-described processing, a layer 716 is formed inside the recess. It is possible.

[0199] Next, as shown in FIG. 10(B), an oxide 704 is formed in the opening. The oxide 704 located in the same layer as the insulator 722 is in contact with the insulator 703. Oxide 704 contacts layer 716 .

[0200] Next, an insulator 711 is formed inside the oxide 704, and a conductor 7 is formed inside the insulator 711. The conductor 712 is formed (see FIG. 10B). Instead, the inside of the oxide 704 may be filled with an insulator 711.

[0201] Next, a heat treatment is performed to reduce the resistance of the oxide 704 in contact with the layer 716. The region 731 (region 731a and region 731b) is in contact with the layer 716 and therefore has low resistance. On the other hand, the resistance of the region 734 not in contact with the layer 716 remains high. The area 732 between the area 731 and the area 734 (area 732a and area 732b) ) functions as a junction region. Region 732 preferably has a lower resistance than region 734. The region 732 may have a resistance value similar to that of the region 731. It may have higher resistance than 731.

[0202] The region 734 of the oxide 704 functions as a channel forming region of the memory transistor MT. The region 731a is used as one of the source and drain of the memory transistor MT. The region 731b functions as the other of the source and drain. _k serves as the first gate of the memory transistor MT, and the conductor 712 serves as the second gate of the memory transistor MT. The insulator 703a functions as a gate, and the insulator 70 3b functions as a charge storage layer, and insulator 703c functions as a tunnel insulating layer. The conductor 711 functions as a second gate insulating layer. The source or drain of the memory transistor MT is connected to the transistors located above and below it. For example, the region 731b may function as a drain or a source. When the region 701_k functions as the source of a transistor having the conductor 701_k as the gate, 31b functions as the drain of a transistor whose gate is the conductor 701_k+1. There are cases where this happens.

[0203] Through the above steps, a memory transistor MT that functions as a memory cell can be formed. By the above method, patterns for fabricating memory transistors MT for each layer can be formed. It is possible to fabricate multiple layers of memory transistors MT at once without forming a gate. Furthermore, when a memory cell array is fabricated by the above method, the memory transistor MT Even if the number of layers is increased, the process of pattern formation and etching of the memory transistor MT In this way, the process of manufacturing the memory cell array can be shortened. A semiconductor device with high productivity can be provided.

[0204] (Method of manufacturing a memory cell array) Next, one embodiment of a method for manufacturing a memory cell array of the present invention will be described with reference to FIGS. 12 to 30, (A) is a top view seen from the z-axis direction. (B) is a cross-sectional view of the area indicated by the dashed line A1-A2 in (A). ) is a cross-sectional view of the portion indicated by the dashed line A3-A4 in (A). 26(D) are the dashed lines in FIG. 24(B) and FIG. 26(B), respectively. FIG. 1 is an enlarged cross-sectional view of the area surrounded by the arrow.

[0205] First, a conductor 706 is formed on a substrate 720 having an insulating surface, and a metal film is formed on the substrate 720 so as to cover the conductor 706. Thus, an insulator 721 is formed (see FIG. 12).

[0206] First, a conductive film that will become the conductor 706 is formed, and then processed using lithography. However, the conductor 706 and the insulator 721 can be formed by The present invention is not limited to this. An insulator 721 is formed on a base 720, and unnecessary portions of the insulator 721 are removed. By removing the insulating film, grooves and openings are formed, and the conductor 706 is formed to be embedded in the grooves and openings. Such a method for forming a conductor may be a damascene method (single damascene method, dual damascene method, etc.). The conductor 706 and the insulator 707 formed by the damascene method are sometimes called a damascene method. By further forming an insulating film on 21, the structure shown in FIG. 12 can be obtained.

[0207] The conductor 706 and the insulator 721 can be formed by a sputtering method, a CVD method, a molecular beam epitaxial method, or the like. Molecular Beam Epitaxy (MBE) method, pulsed laser deposition PLD (Pulsed Laser Deposition) method or ALD method, etc. This can be done using

[0208] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0209] The plasma CVD method can produce high-quality films at relatively low temperatures. This film formation method does not use a plasma, so it is possible to reduce plasma damage to the object being treated. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc. included in a semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage occurs. In addition, the thermal CVD method can increase the yield of semiconductor devices. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0210] The ALD method is also a film formation method that can reduce plasma damage to the workpiece. In addition, the ALD method does not cause plasma damage during film formation, so films with few defects can be produced. is obtained.

[0211] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the object to be treated and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0212] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum chamber, the time required for film formation is shorter due to the time required for transport and pressure adjustment. Therefore, the productivity of the semiconductor device can be increased in some cases.

[0213] In the lithography method, first, the resist is exposed to light through a photomask. The exposed areas are then removed or left behind using a developer to form a resist mask. Next, a conductive, semiconductive or insulating layer is formed by etching through the resist mask. For example, KrF excimer laser light, ArF Using excimer laser light, EUV (Extreme Ultraviolet) light, etc. The resist is exposed to light to form a resist mask. A liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the light source and the exposure is performed. Instead of the light, an electron beam or an ion beam may be used. When using a photomask, the photomask is not required. Dry etching such as ashing is performed, wet etching is performed, and dry After the etching process, a wet etching process is performed, or after the wet etching process, A dry etching process can be performed.

[0214] In addition, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When using a hard mask, an insulating film or a conductive film that will be the hard mask material is formed on the conductive film. Then, a resist mask is formed on the hard mask, and the hard mask material is etched to form the desired A hard mask of a desired shape can be formed.

[0215] This processing can be performed by dry etching or wet etching. The etching method is suitable for microfabrication.

[0216] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate type electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching device or the like can be used.

[0217] When a hard mask is used for etching the conductive film, the etching process is performed using the hard mask. This may be done after removing the resist mask used to form the mask, or after leaving the resist mask. In the latter case, the resist mask may disappear during etching. After etching the conductive film, the hard mask may be removed by etching. If the hard mask material does not affect the subsequent process or can be used in the subsequent process, There is no need to remove the hard mask.

[0218] The conductive film to be the conductor 706 is formed by sputtering a conductive film containing a metal element. It is also possible to form it by using a CVD method.

[0219] The surface of the insulator 721 is preferably subjected to planarization treatment as necessary. The planarization process can be performed by chemical mechanical polishing (CMP) or reflow.

[0220] A conductive film 701A and an insulating film 722A are alternately formed on the conductor 706 and the insulator 721. In this embodiment, the conductive film 701A is formed over the insulator 721, and the conductive film 70 1A, the order of formation is not limited to this. An insulating film 722A is formed on the insulating film 722A, and a conductive film 701A is formed on the insulating film 722A. The conductive film 701A and the insulating film 722A can be formed by a CVD method. Alternatively, a sputtering method may be used.

[0221] In this embodiment, the conductive film 701A and the insulating film 722A are each formed into four layers. However, the number of layers is not limited to this. For example, the conductive film 701A and the insulating film 722A may be formed in five or more layers. The number of layers may be 32, 64, 128, or 200 or more.

[0222] A conductive film 702A is formed on the top layer of the insulating film 722A. The conductive film 702A is formed by the same method as the conductive film 701A. The conductive film 702A can be formed using the same material as the conductive film 7 It may be formed by the same method as that of the conductive film 70. 2A may be made of the same material as the conductive film 701A, or may be made of a different material.

[0223] Next, the conductive film 702A, the conductive film 701A, and the insulating film 722A are processed, and the resultant structure shown in FIG. ) Step-like conductive films 701B, 702B, and insulating films 722B are formed. In processing the conductive film 702A, the conductive film 701A, and the insulating film 722A, 702A, the conductive film 701A, and the insulating film 722A are etched, and the mask 723 is slit. By alternately performing etching, the conductive film 701B, the conductive film 702B, and the insulating film 7 22B can be formed. By processing A, the mask 723 is reduced in both width and thickness to become a mask 723A (FIG. 14 reference.).

[0224] Next, the mask 723A is removed and an insulator 724 is formed. The insulator 724 is formed by a CVD method. The insulator 724 can be formed by using a CMP method or a reflow method. A mask 725 is formed on the insulator 724. Planarization By forming a mask 725 on the insulating layer 724, the accuracy of lithography is improved. (See Figure 15.)

[0225] Next, using a mask 725, the insulator 724, the conductive film 702B, the conductive film 701B, and the insulating film 724 are The film 722B and the insulator 721 are processed. A conductor 701 that functions as a gate and is electrically connected to a word line and a gate of a select transistor A conductor 702 that functions as a gate is formed. This forms an insulator 722 (see FIG. 16).

[0226] Next, the mask 725 is removed. Next, the insulator 724, the conductive film 702B, and the conductive film 701 B, the insulating film 722B, and the insulator 721 are filled with the portions removed by the above processing. The insulator 726 is formed as shown in FIG. 7. The insulator 726 is formed by using a CVD method or an ALD method. In particular, the ALD method allows for the formation of grooves and openings with a large aspect ratio. It is preferable to use the ALD method because it is possible to form a film with a uniform thickness. The insulator 726 may be formed by a combination of a VD method. It is preferable that the planarization process is performed using a flow method. When performing the above, the insulator 726 may be polished until the surface of the insulator 724 is exposed. The insulators 724 and 726 may be polished together. In this case, the thickness of the insulator 724 is , become thinner.

[0227] Next, the insulator 724 is processed using a lithography method to expose the conductor 701. The first openings are formed in such a way that the conductors 701 are each formed in a stepped shape. Although not shown, an opening for exposing the conductor 702 may also be formed at the same time. Good (see Figure 17).

[0228] Next, a conductor 707 is formed so as to fill the first opening (see FIG. 18). 707 can be formed by using a CVD method or an ALD method. This makes it possible to form a film of uniform thickness even on grooves and openings with a large aspect ratio. Alternatively, the conductor 707 may be formed by combining the ALD method and the CVD method. The conductor 707 may have a layered structure made up of multiple layers. The conductor 707 is formed by forming a conductive film on the insulator 724 and inside the first opening. The conductive film can be formed by forming a conductive film on the insulating film and then removing unnecessary conductive film by using CMP or the like.

[0229] Next, a mask 729 is formed on the insulator 724 and the insulator 726. The conductor 702, the conductor 701, the insulator 722, and the insulator 721 are formed by a lithography method. 19. Then, a second opening is formed to expose the conductor 706 (see FIG. 19). .

[0230] Next, isotropic etching is performed on the insulators 721, 722, and 724. The diameters of the openings of the insulators 721, 722, and 724 are enlarged (see FIG. 20). By this process, the diameter of the opening of the insulator becomes equal to the diameter of the opening of the conductor 701 and the conductor 702. The insulator is larger than the diameter of the opening. It can be said that the side of the conductive material 701 or conductive material 702 has a recess. The process involves isotropic etching using dry etching with gas, radicals, plasma, etc. For example, isotropic etching such as wet etching using a liquid or the like can be used. The liquid used in wet etching is sometimes called an etchant. When isotropic etching is performed using a gas containing at least one of chlorine, bromine, and fluorine, The isotropic etching can be performed by using a mask 729. It is preferable to do this without removing

[0231] Next, the insulator 703 is placed on the insulator 724 and the conductor 707 and inside the second opening. An insulating film 703A is formed (see FIG. 21). Although not shown, the insulating film 703 A is an insulating film that becomes the insulator 703a, an insulating film that becomes the insulator 703b, and an insulating film that becomes the insulator 703c. The insulating film 703A can be formed by sequentially stacking insulating films such as a CVD method or an ALD method. In particular, the ALD method allows for the formation of grooves with a large aspect ratio. This is preferable because it allows a film of uniform thickness to be formed even in holes or openings. The insulating film 703A may be formed by combining the ALD method and the CVD method. The insulating film to be the insulating film 703b, the insulating film to be the insulator 703c, and the insulating film to be the insulator 703c are the same. The insulator 7 may be formed in the same film forming apparatus or in a different film forming apparatus. The insulating film that becomes the insulator 703c is made thinner than the insulator 703a. It is preferable to form it thinner than the insulating film that will become 703a.

[0232] The insulating film 703A formed by the above method has good coating properties and is insulator 721 and insulator 722. The insulating film 703A can also be formed in the recessed portion of the insulator 724. That is, the side surfaces of the insulators 721, 722, and 724, the conductors 701, and The conductor 701 and the conductor 702 are not only on the side surface thereof but also on a part of the upper surface thereof and the lower surface thereof. The insulating film 703A can be formed so as to contact a part of the surface.

[0233] Next, a film 716A containing at least one of a metal element, hydrogen, and nitrogen is deposited inside the second opening. The film 716A is formed by at least an insulator 721, an insulator 722, The second opening 724 may be formed so as to fill the recess of the insulator 724. It is not necessary to fill the entire interior. The film 716A can be formed using a CVD method or an ALD method. In particular, the ALD method allows for the formation of grooves and openings with a large aspect ratio. The ALD method is also preferable because it can form a film with a uniform thickness. The film 716A may be formed by combining the methods D.

[0234] Next, the film 716A is processed to form a layer 71 containing at least one of a metal element, hydrogen, and nitrogen. The film 716A is formed by isotropic etching or anisotropic etching. In forming the film 716A, as shown in FIG. If the film 716A fills the recesses and does not completely fill the openings, the film 716A may be machined. On the other hand, it is preferable to use isotropic etching to fill the recesses and openings. When the film 716A is formed, it is preferable to use anisotropic etching. By such processing, a layer 716 can be formed inside the recess.

[0235] Next, the insulating film 703A formed on the bottom of the second opening is removed to obtain the insulator 703. It is preferable to use anisotropic etching to remove the insulating film 703A. 724 and the insulating film 703A on the conductor 707 are also removed. The insulating film 703A is formed only on the side wall of the second opening (see FIG. 24). By removing it, the conductor 706 is exposed again.

[0236] Here, as shown in FIG. 24(D), the insulator 703 located above the second opening 24(B) and the insulating layer 703b and the insulating layer 703c may be removed. First, the inside of the second opening is easily opened in a later process. A removable material 727 (also called a sacrificial layer) is formed to fill the second opening. The insulator 7 exposed by the etching is removed to a desired depth. By sequentially removing the conductor 702, the horizontal direction (x-y The insulator 703 located in the direction (the direction of the insulating film 703) can be only the insulator 703a. The gate insulating film of the select transistors SST and SDT is made of an insulator 703a. After removing insulator 703c and insulator 703b, material 727 is removed.

[0237] Next, an oxide film 704A that will become the oxide 704 is formed inside the second opening. 4A is formed on the insulator 724, the conductor 707, the insulator 703, and inside the second opening. The oxide film that becomes oxide 704a, the oxide film that becomes oxide 704b, and the oxide film that becomes oxide 704c. The oxide 704 can be formed by sequentially depositing layers 716 and 718. In addition, part of the oxide 704 is formed so as to be in contact with the conductor 706. .

[0238] The oxide film that becomes oxide 704a, the oxide film that becomes oxide 704b, and the oxide film that becomes oxide 704c. The oxide film can be formed by using a CVD method or an ALD method. In particular, the ALD method This allows for the formation of a film with a uniform thickness even in grooves and openings with a large aspect ratio. Alternatively, the oxide film may be formed by combining the ALD method and the CVD method. Also, different film forming methods and film forming apparatuses may be used for each oxide film.

[0239] Next, an insulating film 711A is formed inside the oxide film 704A, and The insulating film 711A and the conductive film 712A are formed by a CVD method or an ALD method. In particular, the ALD method allows for the formation of grooves with a large aspect ratio. This is preferable because it allows a film of uniform thickness to be formed even in holes or openings. The film may be formed by combining the ALD method and the CVD method (see FIG. 25).

[0240] The insulator 711 is a semiconductor layer including the memory transistor MT and the semiconductor layer including the memory transistor MT. According to the characteristics required for the device, a material that supplies oxygen to the oxide 704 or a material that supplies hydrogen to the oxide 704 is selected. Materials can be used.

[0241] Next, a heat treatment is performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C. Preferably, the heat treatment is carried out at a temperature of 300° C. or higher and 400° C. or lower. The method is not limited to the above, and may be carried out in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere. .

[0242] By performing a heat treatment while the oxide film 704A and the layer 716 are in contact with each other, the oxide film 704A The mechanism by which the oxide film 704A has a low resistance is as described above. This is the same mechanism by which the oxide 704 decreases in resistance as in FIG. 26(D) is an enlarged view of the area surrounded by the dashed line in FIG. Region 734 of oxide film 704A is a low resistance region. The resistance of the non-contact region 731 remains high. The bonding region may be provided in the above-mentioned area.

[0243] In addition, by performing a heat treatment while the oxide film 704A and the conductor 706 are in contact with each other, When the oxide film 704A contacts the conductor 706, At the interface between the conductor 706 and the oxide film 704A, the metal element contained in the conductor 706 and the oxide film 704A are present. In some cases, a metal compound layer containing the component O4A may be formed. This is preferable because the contact resistance between the conductor 706 and the oxide film 704A is reduced. In addition, the conductor 706 may absorb oxygen contained in the region 728 of the oxide film 704A. At this time, the resistance of the oxide film 704A near the interface between the conductor 706 and the oxide film 704A is This reduces the contact resistance between the conductor 706 and the oxide film 704A, which is preferable. By performing a heat treatment while the oxide film 704A and the conductor 706 are in contact with each other, the oxide film 70 4A has a lower resistance, and the contact resistance between the conductor 706 and the oxide film 704A is Reduce.

[0244] Next, the unnecessary conductive film above the portion indicated by the dotted line in FIG. 26(B) and FIG. 26(C) is removed. 712A, insulating film 711A, and oxide film 704A are removed by CMP or the like, and oxide 70 4. An insulator 711 and a conductor 712 are obtained (see FIG. 27). This may be performed after removing unnecessary conductive film 712A, insulating film 711A, and oxide film 704A.

[0245] Next, as shown in FIG. 28, the bit lines BL, the source lines SL, and some of the word lines WL are connected. The conductor 705 is formed by the oxide 704 and the conductor 7 7. A conductor 712 is provided inside the oxide 704. If the conductor 705 is provided with an opening that exposes at least the conductor 712, It is preferable to electrically separate the conductor 705 from the conductor 712. In this case, the opening is The insulator 711 may be exposed. It may be possible.

[0246] 29, an insulator 717 is formed to cover the conductor 705. The oxide 717 has a part of the conductor 705 (a conductor electrically connected to the oxide 704 on the bit line side). An opening is provided to expose the conductive material 712. When forming the opening, the diameter of the opening is set to be larger than the diameter of the opening provided in the conductor 705. Since the opening is provided in the conductor 705, the opening exposing the conductor 712 may be The opening is formed in a self-aligned manner, and the diameter of the bottom of the opening is formed to an unintended size. This is preferable because it can prevent problems such as the opening being misaligned with the conductor 712.

[0247] Next, as shown in FIG. 30, an opening formed in the insulator 717 is provided to expose the conductor 712. In this step, an insulator 713 is formed to cover the conductor 705. By forming an insulating film to be the insulator 713 using the ALD method or the like, and then performing anisotropic etching, The insulating film formed on the bottom of the opening is removed by this. The insulating film is also removed to form an insulator 713. At this time, the formed insulator 713 may also exist on the insulator 717. There is a match.

[0248] Next, the conductors 714 and 715 which function as the bit line BL and the wiring BG are In FIG. 30, the conductor 714 and the conductor 715 are shown as different layers. The conductor 714 and the conductor 715 are connected to one The conductors 714 and 715 may be formed together as a single conductor. In this case, the conductor 71 is formed on the insulator 717 and fills the opening formed in the insulator 717. The conductive film 4 is formed, and unnecessary conductive film is removed by CMP or the like to form a conductive film. Then, the conductor 715 can be formed. The formation of the insulating film may be performed by lithography or by a damascene method. The insulator 713 is provided on the side of the opening formed in the insulator 717 and the conductor 705. Therefore, the conductor 715 electrically connected to the conductor 712 is electrically connected to the conductor 705. When the conductor 714 and the conductor 715 are formed together, the insulating A conductive film is formed on the insulating film 717 so as to fill the opening formed in the insulating film 717. The conductors are processed using a lithography method to form conductors 714 and 715. It is possible.

[0249] By the above steps, a memory cell array can be manufactured. The memory cell array consists of four layers of memory transistors MT and four memory strings. It may include, but is not limited to, five or more layers of memory transistors MT. For example, the memory transistors MT may be arranged as follows: It is possible to manufacture memory cell arrays with 32 layers, 64 layers, and 128 layers. It is possible to fabricate a memory cell array having 0 or more layers of memory transistors MT.

[0250] By fabricating a memory cell array in this manner, memory transistors can be formed in each layer. Multiple layers of memory transistors MT can be fabricated without patterning to fabricate MT. Furthermore, when a memory cell array is fabricated by the above method, Even if the number of layers of the memory transistor MT is increased, the pattern formation of the memory transistor MT In this way, the number of steps for the memory cell array fabrication is reduced. Since the time required for the manufacturing can be shortened, a semiconductor device with high productivity can be provided.

[0251] (3D NAND configuration example) Figure 31(A) shows the configuration of a three-dimensional NAND type nonvolatile memory device (3D NAND). 31A shows an example of a memory device 100 including a control circuit 105, a memory cell array 1 10, having peripheral circuits.

[0252] The control circuit 105 controls the entire storage device 100, and writes data, The control circuit 105 processes external command signals and controls the peripheral circuits. The peripheral circuits include a row decoder 121, a row driver 122, a sense amplifier 123, and a A filter 123, a source line driver 124, and an input / output circuit 125 are provided.

[0253] The memory cell array 110 has a plurality of memory strings 112. 1 shows an example of the circuit configuration of the memory string 112. In the memory string 112, Between the line BL and the source line SL, a selection transistor SST and memory transistors MT1 to M T2k (k is an integer equal to or greater than 1) and the select transistor SDT are electrically connected in series.

[0254] When the memory transistors MT1 to MT2k are not distinguished, This is called MT. The same applies to other elements.

[0255] The select transistors SST, SDT, and the memory transistors MT1 to MT2k are As mentioned above, this is a transistor in which the channel is made of metal oxide. The transistor MT has a charge storage layer and constitutes a nonvolatile memory cell.

[0256] The gates of the select transistors SST and SDT each function as a select gate line. The memory transistors MT1 to MT2k are electrically connected to the wirings SGL and DGL. The gates of the bit lines WL1 to WL2k are electrically connected to the word lines WL1 to WL2k, respectively. The lines BL extend in the column direction, and the wirings SGL, DGL and word lines WL extend in the row direction.

[0257] The select transistors SST and SDT and the memory transistor MT are ) each of the gate electrodes may have a second gate. The second gate is connected to the wiring BG In FIG. 31(B), the select transistor SST and the memory transistor A wiring BG electrically connected to the second gates of the selection transistors MT1 to MTk and a The second gates of the memory transistors MTk+1 to MT2k are electrically connected to the second gates of the memory transistors SDT. The wirings BG are connected to each other. Different potentials may be applied to the wirings BG. Alternatively, the wirings BG may be electrically connected to each other.

[0258] The wiring BG preferably extends in the column direction in parallel with the bit lines BL. The arrangement may be such that

[0259] The wiring BG can control the threshold voltages of the select transistors SST and SDT. The potential of the wiring BG may be controlled in accordance with the circuit operation of the memory cell array.

[0260] The input / output circuit 125 temporarily stores data to be written to the memory cell array 110. It temporarily stores data read from the memory cell array 110.

[0261] The source line driver 124 drives the source line SL.

[0262] The bit line BL is electrically connected to a sense amplifier 123. The sense amplifier 123 When reading data, the voltage read from the memory string 112 to the bit line BL is When writing data, the voltage corresponding to the data to be written is detected and amplified. A voltage is input to the bit line BL.

[0263] The row decoder 121 decodes address data input from the outside and outputs the accessed data. The row driver 122 selects a row to be read according to the result of decoding by the row decoder 121. The voltages required for writing, reading, and erasing data are applied to the lines DGL, SGL, and word line WL. Enter.

[0264] The memory cell array 110 also includes peripherals such as a control circuit 105 and a sense amplifier 123. In particular, the memory cell array 110 may be provided in a layer different from the sense amplifier 123. By stacking them so as to overlap, the memory cell array 110 and the sense amplifier 123 This is preferable because it simplifies the wiring to be routed to the storage device 10 shown in FIG. 0, a control circuit 105, a row decoder 121, a row driver 122, a sense amplifier 12 3. The memory cell array 110 is mounted on the source line driver 124 and the input / output circuit 125. The block diagram shows a three-dimensional storage device 100 that is provided so as to overlap with a scan amplifier 123. It shows.

[0265] 33 to 35 show examples of a three-dimensional stacked structure of the memory cell array 110. 1 is a schematic circuit diagram illustrating an example of a three-dimensional structure of a memory cell array 110. In order to simplify the illustration, some circuits (memory strings) are omitted. 35 is a perspective view showing an example of a three-dimensional structure of the word line WL and the conductor 701. 33 is a perspective view showing an example of a three-dimensional structure of the connection portion of the memory cell array 1. 10 is stacked in the area where the sense amplifier 123 is formed. The layout area of ​​the storage device 100 can be reduced. As shown, even in the conductors 701 of the same stage, the conductor 701a on the bit line BL side is connected to the word line WLa. The conductor 701b on the source line SL side is connected to the word line WLb. The wiring BG electrically connected to the bit line BL is provided in the same layer as the bit line BL. Although an example is shown in which the bit lines extend in the column direction like BL, the present invention is not limited to this. An insulator may be provided on L, and the wiring BG may be provided on the insulator. 33 to 35, the 1 Eight memory transistors MT1 to MT8 are provided for each memory string 112. An example is shown.

[0266] (Explanation of the circuit operation of the memory device) Next, the operation of writing and reading data to the memory string 112 will be described with reference to FIG. The following description will be made using (A) to (C). A group of memory transistors MT that share WL2k is called a page.

[0267] In FIGS. 36A to 36C, as an example, the memory string 112 is Although an example having memory transistors MT1 to MT8 is shown, the number of memory transistors MT is Not limited.

[0268] <Erase operation> When writing data to the memory transistor MT, the data is erased before the write operation. It is preferable to erase the data. The operation of erasing data is sometimes called a reset operation. The erase operation is performed for each memory string 112 (also called a block). A block from which data is to be erased is selected, and word lines WL1 to WL2 are connected as shown in FIG. 36(A). L8 is at a low potential (a potential at which the memory transistors MT1 to MT8 are non-conductive, for example, 0V ) is applied to the source line SL and the bit line BL, and an erase potential VE is applied to the selection transistor. This can be done by turning on the select transistor SDT and the select transistor SST. By this operation, the charge stored in the charge storage layer of each of the memory transistors MT1 to MT8 This allows the memory transistors MT1 to MT8 to The data "1" is held.

[0269] The erase operation can be performed by applying an erase potential to the wiring BG. An erase potential of 15 V is applied, and a low potential (memory transistor A potential (for example, 0V) is applied to make MT1 to MT8 non-conductive, and the select transistor SDT This can be done by making the select transistor SST conductive.

[0270] Alternatively, the selection transistor SDT and the selection transistor SST are made non-conductive, and the memory transistor The oxide including the channel formation region of the transistor MT is made floating and erased to the wiring BG. By applying a positive charge (for example, 15 V) as a potential, the Data can be erased. At this time, the select transistor SDT and the select transistor Since the source line SST is non-conductive, the potentials of the bit line BL and the source line SL can be any. For example, a low potential (memory transistors MT1 to M A potential (for example, 0V) is applied to T8 so that it is non-conductive. Since the oxide containing the wiring is floating, the potential of the oxide increases as the potential of the wiring BG increases. The charge storage layer can be pulled out to the oxide side by increasing the charge storage layer.

[0271] As a further different erase operation, for example, a low potential (memory A potential (for example, 0 V) ​​that makes the transistors MT1 to MT8 non-conductive is applied. The select transistor SDT and the select transistor SST are made conductive, and the bit line B At this time, the potentials of the bit line BL and the source line SL are increased. The potential of the line SL is set lower than the potential of the line BG. For example, the bit line BL and the source line S The potential of L is set to 10 V, and the potential of the wiring BG is set to 12 V. At this time, the potential of the wiring BG This turns on the memory transistor MT, and the oxide of the memory transistor MT also As a result, the electrons stored in the charge storage layer can be extracted to the oxide side.

[0272] The erasing operation is not limited to the above method. For example, the erasing operation may be performed by deleting data from a memory In this case, the erase operation is not necessarily performed by sequentially selecting the write transistors MT. It is not necessary to erase all memory transistors MT. It is also possible to erase data by selecting only the transistor MT. For example, data "0" Alternatively, the erase operation may be performed only on the memory transistor MT in which the data is written.

[0273] The data in the memory transistors MT that are not rewritten is erased when the block is erased. It is preferable to store it in a separate memory area before the delete operation.

[0274] <Write operation> Next, the data write operation will be described with reference to FIG.

[0275] The data write operation can be performed for each page as described above. A write potential (for example, 15 V) is applied to the word line of the page to be written, and a write potential (for example, 15 V) is applied to the word line of the page to be written. A positive potential (a potential at which the transistor is conductive, for example, 3 V) is applied to the word line of the page. As shown in FIG. 36(B), a write potential is first applied to the word line WL1. A positive potential is applied to the lines WL2 to WL8, and the select transistor SST is set to a non-conductive state. Then, a positive potential is applied to the selection transistor SDT to make it conductive. Data corresponding to the potential of the bit line BL is written to the memory transistor MT1. When the potential of the bit line BL is low (for example, 0 V), the voltage applied to the word line WL1 is The potential difference between the applied write potential and the stored write potential increases, causing the charge in the memory transistor MT1 to increase. Electrons are injected into the storage layer. Also, the potential of the select transistor SDT and the bit line BL When both are at a positive potential, the select transistor SDT is non-conductive. Since the transistor MT is electrically floating, the charge storage layer of the memory transistor MT1 In other words, when a low potential is applied to the bit line BL, electrons are not injected into the memory cell. When data "0" is written to transistor MT1 and a positive potential is applied, a memory transaction The data of transistor MT1 remains at "1".

[0276] Here, by applying a different potential to each memory string 112 to the bit line BL, Data can be written page by page.

[0277] It is also possible to write multi-level data to the memory transistor MT. The charge accumulation in the memory transistor MT depends on the potential of the charge line BL and the time for applying the potential. The amount of charge injected into the layer can be controlled.

[0278] <Read operation> Next, the data read operation will be described with reference to FIG.

[0279] Data read operations can also be performed page by page. A low potential (for example, 0V) is applied to the word lines of the pages to be read, and the word lines of the pages to be read are applied to the word lines of the pages to be read. A positive potential (a potential at which the transistor is conductive, for example, 3V) is applied to the As shown in C), a low potential is first applied to the word line WL1, and then the word lines WL2 to WL8 are Then, a positive potential is applied to the select transistor SDT and the select transistor SST. A read potential (for example, 1 V) is applied to the bit line BL, and the source line A low potential (for example, 0 V) ​​is applied to the SL. At this time, the memory transistor MT If a is "1", a current flows through the memory string 112, and the potential of the bit line BL drops. If the data stored in the memory transistor MT1 is "0", the memory string 11 No current flows through the bit line BL2, and the potential of the bit line BL does not change. The potential of BL is detected and amplified. It is possible.

[0280] At this time, by applying a positive potential to the wiring BG, the threshold voltage of the memory transistor MT is The potential applied to the wiring BG may be shifted to the negative side. The memory transistors MT that are not turned on are adjusted to be normally on. This prevents erroneous reading. This is preferable because it is possible to reduce the potential that is applied and reduce the power consumption of the memory device.

[0281] Here, by reading out the data of each memory string 112 to the bit line BL, the page Data can be read in units of 1.

[0282] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0283] (Embodiment 2) In this embodiment, a method according to one aspect of the present invention different from that described in the first embodiment will be described. The structure and manufacturing method of the semiconductor device will be described with reference to FIGS. Note that the explanation of the components that overlap with those in the first embodiment may be omitted. In the semiconductor device shown in FIGS. 37 to 67, the semiconductor device shown in the first embodiment is configured. The structures having the same functions as the structures to be described are given the same reference numerals, and detailed explanations of the structures and the manufacturing methods are given. In the semiconductor device described in this embodiment mode, The indicated metal oxides can be used.

[0284] (Memory transistor MT, memory cell array 700) First, the structure of the memory transistor MT and the memory cell array 700 of the semiconductor device will be described. The structure of the memory cell array 700 will be described with reference to FIGS. 37 to 39. 38A is a cross-sectional view of the memory cell array 700. 8(A) is a top view of the plane indicated by the dashed line A5-A6 in FIG. 37, and shows a part of the structure. 37 is a diagram showing the structure of the device A1-A2 in FIG. 38(A) by a dashed line. 38(B) is a cross-sectional view of the portion shown in FIG. 38(A) along the dashed line A3-A4. 1 is a cross-sectional view of a portion indicated by a cross-sectional view of an example of a memory string. 39(A) is an enlarged cross-sectional view of the portion surrounded by the dashed line 791 in FIG. 1 is a diagram illustrating an example of a memory transistor MT functioning as a memory cell. FIG. 39(B) is an enlarged cross-sectional view of the portion surrounded by the dashed line 792 in FIG. 1 is a diagram illustrating an example of a transistor that functions as a selection transistor. Below, as shown in Figures 37 and 38, a Cartesian coordinate system consisting of x-axis, y-axis, and z-axis is used. Here, the x-axis and y-axis are the time when the memory cell array 700 is provided. The axis is taken parallel to the upper surface of the base 720, and the z axis is taken perpendicular to the upper surface of the base 720.

[0285] The memory cell array 700 has an insulator 721 on a base 720. , conductors 701 (conductors 701_1 to conductors 701_m: m is a natural number of 2 or more), and and the insulators 722 (insulators 722_1 to 722_m) are alternately stacked. 702 and an insulator on the laminate. 724, which penetrates the insulator 724, the conductor 702, the stack, and the insulator 721. The insulators 703 (insulators 703_1 to 703_3) are disposed inside the openings formed so as to _4), and oxide 704 (oxide 704_1 to oxide 704_4) is formed inside the insulator 703. 711_1 to 711_4) inside the oxide 704. _4), and between the oxide 704 and the insulator 711, The insulator 711 has an insulator 719 that functions as a conductors 712_1 to 712_4), upper ends of oxides 704_1 to 704_4, The conductors 705 (conductors 705_1 to 705_4) are electrically connected to each other. The oxides 704_1 to 704_4 are electrically connected to the bottom ends of the oxides 704_1 to 704_4. 706 (conductors 706_1 to 706_4), and conductors 701_m and the conductors 707 (conductors 707_1 to 707_m) electrically connected to each other. 707_m), and are electrically connected to the conductors 707_1 to 707_m, respectively. The conductors 708 (conductors 708_1 to 708_m) are connected to the conductors 702. The conductor 709 is electrically connected to the conductor 709. Then, the insulator 71 is formed on the insulator 724, the conductor 705, the conductor 708, and the conductor 710. 7 and an insulator 713, and the conductors 712_1 to 712_4 are 37 and 38, the conductor 714 and the conductor 715 are electrically connected. In FIG. 8, the conductors 701 are displayed in four or more rows to represent a plurality of conductors 701. The embodiment is not limited to that shown in FIG. 37, and any embodiment may be used as long as it has at least two or more stages of conductors 701. That's fine.

[0286] As shown in FIG. 37 and FIG. 38(A), the conductor 701 extends in the x-axis direction. 37 and 38(B), an insulator 703 and an oxide 704 is provided extending in the z-axis direction. It is preferable that the oxide 704 and the oxide 705 are provided so as to intersect each other perpendicularly. As shown in the figure, the conductor 707 is provided extending in the z-axis direction. In addition, the conductor 705 may be provided so as to extend in the direction of the bit line BL. The conductor 705 may be provided so as to extend in the y-axis direction. The conductor 705 may be provided so as to extend in the y-axis direction.

[0287] The conductor 712 is formed in a columnar shape and extends in the z-axis direction. An insulator 711 is provided to surround the body 712, and an oxide film is further provided to surround the insulator 711. 704 are provided, each extending in the z-axis direction. A conductor 712 is provided like a core inside the columnar oxide 704. An insulator 711 is provided between the conductor 704 and the conductor 712. The insulator 703 is The conductor 707 is provided so as to surround the side periphery of the columnar oxide 704. and extends in the z-axis direction.

[0288] The diameter of the openings formed in the conductors 701 and 702 is 22, and the diameter of the opening formed in the insulator 724, and The conductor can be said to have a recess. The insulator 719 is 2, an insulator 703 and an oxide 704 are provided on the side of the insulator 703. 703 and oxide 704 are formed along the recessed portion, and the insulator 721, conductor 701, and insulator 722, conductor 702, and insulator 724, and insulator 719 is The insulating layer 703 and the oxide layer 704 are provided inside the recess. The insulator 719 has a low resistance region, and the insulator 719 forms a low resistance region in part of the oxide 704. In this case, it can function as a mask covering other portions of oxide 704. 4 has a low resistance region, and thus a memory string in which memory cells are stacked, or a memory In the re-cell array, the series resistance between memory cells can be reduced. In 704, the region whose side surface is covered with the insulator 719 functions as a channel forming region. It is possible.

[0289] The columnar oxide 704 is electrically connected to the conductor 706 at its lower end in the z-axis direction, and At the end, it is electrically connected to the conductor 705. Also, as shown in FIG. The body 706 is electrically connected to the bottom ends of two adjacent pillar-shaped oxides 704, and the two pillars The top ends of the oxides 704 are electrically connected to the electrically isolated conductors 705, respectively. In this embodiment, a U-shaped oxide film is formed by electrically connecting two pillar-shaped oxides 704 with a conductor 706. However, the present invention is not limited to this. 06 is one of the bit line BL and the source line SL, and the conductor 705 is one of the bit line BL and the source line SL. In this case, the conductor 706 may be a plurality of columnar oxides 708. 704, or may be electrically connected to one columnar oxide 704. The conductor 705 may be electrically connected to a plurality of pillar-shaped oxides 704, or may be connected to a single pillar. The silicon dioxide 704 may be electrically connected to the silicon dioxide 704 .

[0290] The bottom end of the columnar oxide 704 is electrically connected to one of the bit line BL and the source line SL, and the top When the end is electrically connected to the other end, selective transistors are provided near the bottom end and the top end of the columnar oxide 704. For example, the conductor 706 may be a part of the bit line BL, When 705 is a part of the source line SL, a conductor 706 and a memory transistor MT are , the selection transistor SST, the conductor 705 and the memory transistor MT, Provide a resistor SDT.

[0291] Here, the region where the conductor 701 intersects with the insulator 703 and the oxide 704 and The area around the conductor 702 functions as a memory transistor MT. The region where the oxide 704 intersects with the gate electrode 3 and the oxide 704 and its vicinity function as a select transistor. The channel forming regions of these memory transistors MT and select transistors are The memory transistor MT and the selection transistor are electrically connected to each other. These are connected in series to form a memory string.

[0292] FIG. 39(A) is an enlarged cross-sectional view of the portion surrounded by the dashed line 791 in FIG. 1 is a diagram showing a cross section of a memory transistor MT at a k-th stage (k is an integer of 2 or more and m-1 or less). The memory transistor MT is made up of a conductor 701_k and an insulator 703 (insulator 703 a, insulator 703b, and insulator 703c), and oxide 704 (oxide 704a, oxide The insulating layer 704 includes a conductor 712 and an insulator 704b. 711.

[0293] The conductor 701_k functions as the gate of the memory transistor MT, and the insulator 703a , serves as a gate insulating layer, insulator 703b serves as a charge storage layer, and insulator 70 3c functions as a tunnel insulating layer.

[0294] As will be described in detail later, the oxide 704 is made up of oxide 704a, oxide 704b, and oxide 704b. 704c, and the oxide 704a has a relatively high energy The gap is wide, and the oxide 704c has a relatively high energy gap with respect to the oxide 704b. In other words, the oxide 704b has a wider gap than the oxide 704a and the oxide 704c. Therefore, the energy gap is relatively narrow.

[0295] In addition, a region 734 of the oxide 704 located in the same layer as the conductor 701_k is a channel The region 73 of the oxide 704 that is not covered with the insulator 719 functions as a formation region. 1 (region 731a, region 731b) function as a low resistance region. The region 732 (region 732a, region 732b) located between the regions 731 is used as a junction region. The region 732 preferably has a lower resistance than the region 734. The region 732 may have a resistance value similar to that of the region 731, or may have a higher resistance than the region 731. The region 732 may function as a channel forming region, similar to the region 734. However, like the region 731, it may function as a low resistance region.

[0296] The k-th memory transistor MT is the k-1-th memory transistor MT or the k The +1st stage memory transistor MT shares a low resistance region. The oxide 704 is the low resistance region. By having such a structure, a memory string in which memory cells are stacked or a memory cell array can be In this case, the series resistance between memory cells can be reduced.

[0297] When the conductor 712 is provided, the conductor 701_k functions as a first gate, and the conductor 7 12 functions as the second gate. The first gate is also referred to simply as the gate or The gate is called the back gate, and the second gate is called the oxide 7 Between the second conductor 712 and the second conductor 711, an insulator 719 is provided. In this case, the insulator 703a functions as a first gate insulating layer. In the circuit operation of the memory transistor MT, a conductive layer that functions as a second gate is The potential of the capacitor 712 is controlled to reduce the power consumption of the memory transistor MT. can be done.

[0298] FIG. 39(B) is an enlarged cross-sectional view of the portion surrounded by the dashed line 792 in FIG. The select transistor (bit line side transistor: SDT and source line side transistor) The select transistor is a cross-sectional view of a conductive material 702 and an insulator 703. 3 (insulator 703a, insulator 703b, and insulator 703c) and oxide 704 (oxide The conductive material 71 has a conductive layer 71a, an oxide 704b, and an oxide 704c. 2, and an insulator 711.

[0299] The conductor 702 functions as the gate of the selection transistor, and the insulator 703a functions as the gate insulator. The gate insulating layer may include at least the insulator 703a. The insulators 703b and 703c may not be provided. a, the insulator 703b, and the insulator 703c are provided, and then the insulator 703b and The insulating material 703c may be removed.

[0300] The oxide 704 includes oxide 704a, oxide 704b, and oxide 704c. The oxide 704a has a relatively wide energy gap compared to the oxide 704b. The oxide 704c has a relatively wide energy gap compared to the oxide 704b. As a result, the oxide 704b has relatively high energy density compared to the oxide 704a and the oxide 704c. The energy gap is narrow.

[0301] In addition, a region 734 of the oxide 704 located in the same layer as the conductor 702 is a channel forming region. In addition, the region 731 ( The regions 731a and 731b function as low resistance regions. The region 732 (region 732a, region 732b) located between 731 functions as a bonding region. It is preferable that the region 732 has a lower resistance than the region 734. 2 may have a resistance value similar to that of the region 731, or may have a higher resistance than the region 731. The region 732 may function as a channel formation region, similar to the region 734. It may function as a low resistance region similar to region 731 .

[0302] When the conductor 712 is provided, the conductor 702 functions as a first gate, and the conductor 712 The first gate functions as a second gate. The first gate is sometimes called the first gate, and the second gate is sometimes called the back gate. Between the gate electrodes 712, an insulator 711 and an insulator 719 are provided, and a second gate insulating film In this case, the insulator 703a functions as a first gate insulating layer. The conductor 712, which functions as a second gate, controls the threshold voltage of the select transistor. It is possible.

[0303] Note that the structure of the semiconductor device described in this embodiment mode is an example, and the present invention is not limited to this embodiment mode. The number and arrangement of circuit elements, wiring, etc. shown in the drawings are not limited to those shown in the drawings. The number and arrangement of circuit elements, wiring, etc., included in the semiconductor device according to this embodiment etc. can be set appropriately in accordance with the circuit configuration and driving method.

[0304] The base 720 on which the memory cell array 700 is provided preferably has an insulating surface. Substrates having an insulating surface include semiconductor substrates with an insulator formed on the surface, insulating substrates, and A conductive substrate with an insulator formed on its surface may be used. Semiconductor substrates such as silicon and germanium, or silicon carbide and silicon germanium semiconductor substrates such as gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. The insulating substrate may be, for example, a glass substrate, a quartz substrate, or a sapphire substrate. Plates, stabilized zirconia substrates (yttria-stabilized zirconia substrates, etc.), resin substrates, etc. In addition, the semiconductor substrate having an insulator region therein, for example, SO A silicon-on-insulator (I) substrate may also be used. The substrate may be a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like.

[0305] The conductor 701 functions as the gate of the memory transistor MT and is electrically connected to the word line. That is, conductor 701, conductor 707, and conductor 708 are connected to the word line Here, the conductor 701 functions as a part of the lower conductor 7 as shown in FIG. It is preferable that O1 is provided in a stepped shape extending from the upper layer conductor 701 toward the A2 side. In this way, by providing the conductor 701, a part of the upper surface of the lower conductor 701 However, since the conductor 701 does not overlap with the conductor 701 in the upper layer, the conductor 701 in the corresponding region of each layer and each conductor 707 can be connected.

[0306] The conductor 701 can be made of a conductive material such as silicon or metal. When silicon is used as the conductor 701, amorphous silicon or polysilicon may be used. In addition, to make silicon conductive, p-type impurities or n-type impurities can be added. Pure materials may also be added. In addition, conductive materials containing silicon may include titanium, cobalt, or Alternatively, a silicide containing nickel can be used as the conductor 701. When the material is used for the conductor 701, aluminum, chromium, copper, silver, gold, platinum, tantalum, Nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese Choose from cancer, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more of the above metal elements can be used.

[0307] The conductor 702 is provided on the conductor 701. The conductor 702 is a select transistor. (Bit line side select transistor: SDT, and source line side select transistor: SST) and electrically connects to the wiring DGL or wiring SGL. The conductor 702, the conductor 709, and the conductor 710 are connected to the wiring DGL or the wiring SGL. The conductor 702 also functions as a part of the conductor 701. The conductor 702 may be made of the same material as the conductor 701, or may be made of a different material. The materials of the conductors 701 and 702 may be selected depending on the application. The number of people can be taken into consideration when making a decision.

[0308] The insulating films provided on the upper and lower layers of the conductor 701 and the conductor 702 are Oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, Metal nitride oxides, etc. can be used. Silicon oxide, silicon oxynitride, nitride oxide Silicon, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide Silicon oxide doped with carbon and nitrogen, silicon oxide with pores, or resins are comparatively Because of its low dielectric constant, it is suitable for use in the insulating film.

[0309] On the other hand, the insulating film may be made of aluminum oxide, gallium oxide, hafnium oxide, or zirconium oxide. oxides containing ruthenium, aluminum and hafnium, oxide nitride with silicon and hafnium, oxide with silicon and hafnium, Nitride oxide containing hafnium or nitride containing silicon and hafnium However, since these have a high relative dielectric constant, the conductors 701 may be separated from each other or from each other. Parasitic capacitance may occur between the conductor 702 and the conductor 703. The material to be used for the insulating film can be determined.

[0310] The insulator 703 includes an insulator 703a, an insulator 703b, and an insulator 703c. The insulator 703a is provided on the conductor 701 side, and the insulator 703c is provided on the oxide 704 side. The insulator 703b is provided between the insulators 703a and 703c. 703a serves as a gate insulating layer, and insulator 703b serves as a charge storage layer; The insulator 703c functions as a tunnel insulating layer.

[0311] The select transistor may have the same structure as the memory transistor MT. As shown in 9(B), the select transistor is provided with a charge storage layer and a tunnel insulating layer. The bit line side transistor: SDT and the source line side transistor: SS At T, the insulators 703b and 703c are removed, and the insulator 703 is replaced by the insulator Alternatively, only the second gate electrode 703a may be provided. A conductor 712 may be provided as a pole. In this case, the conductor 702 is the first gate electrode. The insulator 703a functions as a first gate insulating film, and the insulator 711 functions as a second gate insulating film. The conductor 712 functions as a gate insulating film of the select transistor 2. It can be controlled.

[0312] The insulator 703a is preferably made of silicon oxide or silicon oxynitride. Also, aluminum oxide, hafnium oxide, or aluminum and hafnium oxide Alternatively, these oxides may be stacked to form the insulator 703a.

[0313] The insulator 703b is preferably made of a material that functions as a charge storage layer, and silicon nitride is It is preferable to use silicon dioxide or silicon nitride oxide. Oxides containing niobium, or aluminum and hafnium may also be used.

[0314] The insulator 703c is preferably made of silicon oxide or silicon oxynitride. Also, aluminum oxide, hafnium oxide, or aluminum and hafnium oxide Alternatively, an oxide such as SiO 2 may be used. Alternatively, these may be stacked to form the insulator 703c. The insulator 703c is preferably thinner than the insulator 703a. When writing or erasing data to the transistor MT, the insulator 703c passes through the insulator 703c. , charge transfer occurs between the oxide 704 and the insulator 703b. 3c functions as a tunnel insulating layer.

[0315] In particular, the opening formed in the laminated body having the conductor 701, the conductor 702, and the insulating film When forming the insulator 703, the insulator 703 formed at the bottom of the opening is removed by dry etching. It is necessary to remove it by anisotropic etching using a tool such as a grease gun. The side surfaces of the insulator 703c are also exposed to plasma, radicals, gas, chemicals, etc. When the side surface of the insulator 703c is damaged by these, a trap cell is formed in the insulator 703c. This can cause trap centers, which can affect the electrical characteristics of the transistor. To suppress the generation of ions, the side surface of the insulator 703c is made resistant to damage caused by etching. In this case, the insulator 703c is made of aluminum oxide. silicon oxide and aluminum oxide, or silicon oxynitride and aluminum oxide It is preferable to use a stack of silicon dioxide.

[0316] The insulators 703a, 703b, and 703c are formed by using an ALD method or a CVD method. In addition, the insulator 703a, the insulator 703b, and the insulator 70 To prevent contamination of the interface of 3c, the same chamber or a multi-chamber system Using a multi-chamber film-forming device, films are formed continuously without being exposed to the atmosphere. It is preferable that

[0317] The oxide 704 is a metal oxide that functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor). It is preferable to use oxide semiconductors, which are superior to semiconductors made of silicon and the like. This is preferable because the transistor has good on-state characteristics and high mobility.

[0318] For example, the oxide 704 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, One or more selected from tantalum, tungsten, magnesium, etc.) The oxide 704 may be an In-Ga oxide or an In-Z n-oxides may also be used.

[0319] The oxide 704 is made up of an oxide 704a provided on the insulator 703c side and an oxide 704b provided on the insulator 703c side. An oxide 704b is provided on the side of the oxide 704b, and an oxide 704c is provided inside the oxide 704b. In this case, the oxide 704a has a phase difference with respect to the oxide 704b. It is preferable to use an oxide with a wider energy gap. In this case, an oxide having a relatively wide energy gap can be used for the oxide 704b. Here, an oxide having a wide energy gap is called a wide gap, An oxide with a narrow gap is sometimes called a narrow gap. In 39(B), the oxide 704 is composed of oxide 704a, oxide 704b, and oxide The oxide 704 has a three-layer structure including oxide 704a, oxide 704b, and oxide 704c, but is not limited to this. and oxide 704b, or may have a stacked structure of four or more layers.

[0320] The oxide 704a and the oxide 704c are wide-gap oxides, and the oxide 704b is narrow-gap oxide. When the oxide 704a and the oxide 704c are set to a conduction band gap, the energy It is preferable that the energy of the oxide 704b is higher than the energy of the bottom of the conduction band of the oxide 704b. In other words, the electron affinity of the oxide 704a and the oxide 704c is greater than that of the oxide 704b. It is preferable that it is smaller than the child affinity.

[0321] In addition, the oxide 704a, the oxide 704b, and the oxide 704c are formed by adding the atoms of the respective metal atoms. It is preferable to combine oxide 704a and oxide 704b in different numerical ratios. In the metal oxide used for the oxide 704c, the atomic ratio of element M in the constituent elements is The atomic ratio of element M in the constituent elements of the metal oxide used in 04b is larger than that In addition, in the metal oxide used for the oxide 704a and the oxide 704c, The atomic ratio of element M to In in the metal oxide used for oxide 704b is It is preferable that the atomic ratio of the metal to the oxide 704b is larger than that of the element M. In the oxide, the atomic ratio of In to element M is In the metal oxide used in 4c, the atomic ratio of In to element M is preferably larger than that of In. It's nice.

[0322] The oxide 704a and the oxide 704c are made of, for example, In:Ga:Zn=1:3:4, I Compositions of n:Ga:Zn=1:3:2 or In:Ga:Zn=1:1:1 or similar The oxide 704b may be, for example, a metal oxide having a similar composition. In:Ga:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, or In : Use a metal oxide having a composition of Ga:Zn=5:1:6 or a composition close to that These oxides 704a, 704b, and 704c can be It is preferable to combine them while satisfying the relationship of the number of atoms ratio. For example, oxide 704a and The oxide 704c has a composition of In:Ga:Zn=1:3:4 or a composition close to that. The metal oxide, oxide 704b, is selected from In:Ga:Zn=4:2:3 to 4.1 in composition and It is preferable to use a metal oxide having a composition close to that range. The atomic ratio in the oxide formed or the atomic ratio in the sputtering target is shown.

[0323] The oxide 704a and the oxide 704c are formed using CAAC-OS, which will be described later. It is preferable to use CAC-OS as the oxide 704b. When the oxide 704c is a CAAC-OS, the c-axis is The direction is parallel to the xy plane shown in Fig. 1, i.e. perpendicular to the z-axis, and from the side of the opening toward the center. It is preferable that the nuclei are oriented in the direction of the arrow.

[0324] Here, the junction between oxide 704a and oxide 704b, and the junction between oxide 704c and oxide 704b are At the junction of oxide 704b, the conduction band edge changes gradually. a and oxide 704b, and oxide 704c and oxide 704b. The conduction band edge can be said to change continuously or to be a continuous junction. In order to achieve this, the interface between oxide 704a and oxide 704b and the interface between oxide 704c and oxide 704d must be It is preferable to reduce the defect level density of the mixed layer formed at the interface with 04b.

[0325] Specifically, the oxide 704a, the oxide 704b, and the oxide 704c contain, in addition to oxygen, By having a common element (as the main component), a mixed layer with a low defect level density can be formed. For example, when the oxide 704b is an In-Ga-Zn oxide, the oxide 704a , and oxide 704c includes In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, This allows the interface between the oxide 704a and the oxide 704b and The defect state density at the interface between the oxide 704c and the oxide 704b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the memory transistor MT can obtain a high on-current.

[0326] For a more detailed description of metal oxides that can be used as the oxide 704, see , as will be described later.

[0327] FIG. 39(A) shows the memory transistor MT surrounded by the dashed line 791 in FIG. As shown in FIG. 39(A), the oxide 704b is a mixture of the oxide 704a and the oxide In this configuration, the oxide 704 is sandwiched between the oxide 704c. From the conductor 705 to the conductor 706, or from the conductor 706 to the conductor 705 When carriers are caused to flow in the direction of the gate electrode, the carriers mainly flow in the component having the narrow gap. Therefore, when the above-mentioned configuration is used, the oxide 704b, which is a narrow gap, is changed to a wide gap. The oxide 704 is sandwiched between the oxide 704a and oxide 704c. The carriers can be trapped in the oxide 704b, and in the on-state of the transistor A high current driving force, that is, a large on-current and a high field effect mobility can be obtained.

[0328] Furthermore, by providing the oxide 704a between the oxide 704b and the insulator 703c, The oxide 704b, which serves as a carrier path, does not come into direct contact with the insulator 703c. The formation of a pit center can be suppressed at the interface between the semiconductor (oxide semiconductor) and the insulator. The trap centers formed in the In order to vary in direction, there is a risk of affecting the reliability of the transistor and its on / off characteristics. Therefore, the transistor using this oxide is not affected by the electrical characteristics of the trap center, and thus can obtain a higher current driving force in the on state, that is, a large on-current, and a high field-effect mobility. Also, the said transistor and the semiconductor device using the said transistor can obtain high reliability.

[0329] In addition, in order to provide a low-resistance region in the oxide 704, it is preferable to provide an insulator 719 that functions as a mask for the oxide 704. The insulator 719 is provided on the side surfaces of the conductor 701 and the conductor 702 via the insulator 703 and the oxide 704. Details will be described later, but the diameters of the openings formed in the conductor 701 and the conductor 702 are larger than the diameters of the openings formed in the insulator 721, the insulator 722, and the insulator 724, and the insulator 719 exists only in the same layer as the conductor 701 and the conductor 702. Therefore, a part of the oxide 704 has a region covered by the insulator 719. [[ID=二十]]The diameter of the opening formed in the insulator 721, the insulator 722, and the insulator 724, and the insulator 719 exists only in the same layer as the conductor 701 and the conductor 702. Therefore, a part of the oxide 704 has a region covered by the insulator 719.

[0330] By performing a low-resistance treatment on the oxide 704 not covered by the insulator 719, a region 731 that becomes a low-resistance region is formed in the oxide 704. As the low-resistance treatment, there are methods such as injecting a specific element such as argon, hydrogen, nitrogen, or metal into the oxide 704, or a method of extracting oxygen from the oxide 704.

[0331] When injecting a specific element into the oxide 704, plasma treatment, ion implantation treatment, ion doping treatment, etc. in an atmosphere containing the element can be used. Plasma <​​The laser treatment can be carried out using an etching device or a CVD device. The element is implanted into the oxide 704 by using a so-called reverse sputtering process using a sputtering device. It is possible to do so.

[0332] To selectively reduce the resistance of the oxide 704, for example, aluminum, ruthenium, titanium, Indium, tantalum, tungsten, chromium, and indium oxides, which increase the conductivity of the oxide 704. At least one of the metal element and the impurity may be added to the desired region. As the material, elements that form oxygen vacancies or elements that are captured by oxygen vacancies can be used. For example, the element may be hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, or chlorine. , titanium, and rare gas elements. Representative examples of rare gas elements include helium, Examples include neon, argon, krypton, and xenon.

[0333] Therefore, the region 731 contains the above-mentioned metal elements that increase conductivity, elements that form oxygen vacancies, and By increasing the content of elements captured by oxygen vacancies, the carrier density is increased, resulting in low resistance. It is possible to achieve this.

[0334] For example, to reduce the resistance of the region 731, an insulator such as a rare gas is used as a mask. The pure material is treated by plasma processing, ion implantation processing, ion doping processing, reverse scanning By implanting the oxide semiconductor into the region 731 using sputtering or the like, the resistance of the oxide semiconductor can be reduced. This can be done.

[0335] In this specification, the reverse sputtering process is a process using RF (Radio Frequency) y) Applying a voltage to the substrate side using a power supply to form plasma near the substrate and modify the surface. The reverse sputtering process is a process in which an inert gas (e.g., argon, It is preferable to introduce a rare gas such as helium or nitrogen.

[0336] In addition, impurities such as rare gases can be added by mass separation of the ionized source gas. ion doping, which adds ionized source gas without mass separation; The plasma immersion ion implantation method, etc. can be used. When performing mass separation, the ion species and their concentrations can be strictly controlled. On the other hand, if mass separation is not performed, high concentration ions can be added in a short time. Alternatively, an ion doping method may be used, which generates and ionizes atomic or molecular clusters. The impurities and metal elements to be added may be elements, dopants, ions, donors, Alternatively, it may be called an acceptor.

[0337] In order to reduce the resistance of the region 731, for example, the oxide 704 is in contact with the region 731, A metal film, an oxide film containing a metal element, or a nitride film containing a metal element may be formed. Specifically, a metal film or a metal element is formed in the region 731 that is not covered with the insulator 719. It is preferable to provide an oxide film or a nitride film containing a metal element so as to be in contact with the metal layer.

[0338] A metal film, an oxide film having a metal element, or a metal element is formed in contact with the region 731 of the oxide 704. By providing a nitride film having the above structure, metal elements are diffused from the film to the region 731 of the oxide 704. The metal compound is formed in the region 731, and the resistance is reduced. , an interface with an oxide film containing a metal element, or a nitride film containing a metal element, or near the interface Some of the oxygen in the neighboring oxide 704 is absorbed into the film, forming oxygen vacancies in region 731. Regardless of the means for reducing the resistance, the present specification and drawings In this case, the region where the oxide resistance is reduced is not limited to the region 731. The oxide 704a and the oxide 704b may also have a low resistance. It is not necessary to make all of the oxide 704b and oxide 704c low-resistive. For example, the oxide 704c and the oxide 704b may be formed as a low resistance layer. Only 704b may have a low resistance.

[0339] In addition, the region 731 and the metal film, the nitride film containing the metal element, or the oxide film containing the metal element It is preferable to perform heat treatment in a nitrogen-containing atmosphere while the two are in contact with each other. The oxide 70 is formed from a metal film, a nitride film containing a metal element, or an oxide film containing a metal element. The metal element diffuses into the region 731 of the fourth layer, and the metal element can be added to the region 731. At this time, the region 731 of the oxide 704 may be alloyed with the metal element. The region 731 of the region 704 and the metal element are alloyed to form the metal element added to the oxide semiconductor. Since the element is in a relatively stable state, a highly reliable semiconductor device can be provided.

[0340] Moreover, hydrogen in the oxide 704 diffuses into the region 731, and oxygen vacancies existing in the region 731 are filled. If the water enters the oxygen vacancy in the region 734, it will be in a relatively stable state. The element escapes from the oxygen vacancy by heat treatment at 250° C. or higher, diffuses into the region 731, and The oxygen enters the oxygen vacancies present in the region 731 and becomes relatively stable. Therefore, the region 731 has a lower resistance, and the region 734 has a high purity (free of impurities such as water and hydrogen). This reduces the resistance and makes the material more resistive.

[0341] On the other hand, the regions of the oxide 704 covered by the insulator 719 (regions 734 and 732) are Since the insulator 719 is interposed, the addition of the metal element is suppressed. In the region 734 and the region 732, the oxygen atoms in the oxide 704 are oxidized to the metal film described above. and the absorption into the nitride film containing the metal element or the oxide film containing the metal element is suppressed. do.

[0342] Here, the metal film, the oxide film containing a metal element, or the nitride film containing a metal element absorbs hydrogen. If the oxide 704 has the property of absorbing hydrogen, the hydrogen in the oxide 704 will be absorbed into the film. It is possible to reduce hydrogen impurities in the oxide 704. The oxide film or nitride film having metal elements absorbed from the oxide 704 in a later process. It may be removed together with hydrogen.

[0343] Note that metal films, oxide films containing metal elements, and nitride films containing metal elements are not necessarily excluded. For example, a metal film, an oxide film containing a metal element, or a film containing a metal element may be used. The nitride film is oxidized by the oxygen absorbed from the oxide 704, becomes an insulator, and becomes highly resistant. In that case, the second gate insulating layer may be left as is, similar to the insulator 711. It may function as a

[0344] In addition, for example, a metal film, an oxide film containing a metal element, or a nitride film containing a metal element may be used as a conductive film. If an electrically conductive region remains, it can be oxidized by heat treatment to make it insulating. The heat treatment is preferably carried out in an oxidizing atmosphere, for example. In addition, if there is an oxide film near a metal film, an oxide film containing a metal element, or a nitride film containing a metal element, When a structure having a metal element is present, a metal film, an oxide film having a metal element, or Alternatively, a nitride film containing a metal element may react with oxygen contained in the structure and be oxidized. There is.

[0345] Metal film, oxide film containing metal elements, or nitride film containing metal elements remains as an insulator. By forming the insulating layer 711 as the second gate insulating layer, the insulating layer 711 can function as a second gate insulating layer. do.

[0346] For example, a metal film, an oxide film containing a metal element, or a nitride film containing a metal element has a thickness of 0.5n It is preferable that the thickness of the film is 1 nm or more and 5 nm or less, and more preferably 1 nm or more and 2 nm or less. For example, when aluminum with a thickness of 0.5 nm or more and 5 nm or less is oxidized by heat treatment, the thickness becomes 0.7 nm. In some cases, aluminum oxide with a thickness of 8 nm or more may be formed. When the heat treatment is performed, the oxide 704 and the metal film, the oxide film containing a metal element, or the metal The nitride film containing the element is heat-treated once in a nitrogen-containing atmosphere while in contact with the nitride film. It is preferable to carry out the heat treatment once in a nitrogen-containing atmosphere. The oxygen in the oxide 704 forms a metal film, an oxide film containing a metal element, or a nitride film containing a metal element. It becomes easier to spread.

[0347] Here, the memory transistor and the select transistor using an oxide semiconductor are The presence of impurities and oxygen vacancies in the regions where channels are formed throughout the body can cause variations in electrical properties. In addition, the region in the oxide semiconductor where the channel is formed may be easily broken down, resulting in poor reliability. If oxygen vacancies are present in the region, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies in the region 734 where the channel is to be formed are reduced as much as possible. When the insulator 719 is made of a material that can supply oxygen to the oxide 704, This is preferable because it inhibits the generation of oxygen vacancies and repairs the oxygen vacancies.

[0348] When the conductor 712 is provided, the same material as the conductor 701 may be used for the conductor 712. The conductor 712 is formed inside the opening with a large aspect ratio (in other words, inside the oxide 70 4 and the recess of the insulator 711), so that It is preferable that the insulator 711 is formed by plating. Similar materials can be used.

[0349] In addition, when the insulator 711 is provided inside the oxide 704c, the insulator 711 is 04 is a material that can supply oxygen or impurities such as hydrogen and nitrogen. By using an oxide containing as little hydrogen or nitrogen as possible as the insulator 711, Oxygen can be supplied to the oxide 704. By supplying oxygen to the oxide 704, the oxide Impurities such as hydrogen and water contained in the oxide 704 can be removed. By using an oxide with as few impurities as possible as the oxide 704, The transistor MT and the semiconductor device using the memory transistor MT have high reliability. You can get sexuality.

[0350] In addition, by using an oxide containing hydrogen or nitrogen as the insulator 711, the oxide 704 In some cases, hydrogen or nitrogen can be supplied. By supplying hydrogen or nitrogen to the oxide 704, the oxide The resistance of the oxide 704 may be reduced so that it does not adversely affect the circuit operation. By lowering the voltage to a level that does not exceed the threshold voltage, the memory transistor MT can be operated at a lower drive voltage. In addition, when the memory transistor MT is in the on state, a high current driving force, i.e., A large on-current and a high field effect mobility can be obtained.

[0351] The opening formed in the stacked body in which the memory transistor MT is provided is shown in FIG. ) and the like, the upper surface is circular, but the present invention is not limited to this. For example, the upper surface may be elliptical. It may be a circular shape, or a polygonal shape such as a triangle or a square. In this case, the corners may be rounded. Accordingly, the top surface shapes of the insulator 703 and the oxide 704 may also change. The cross-sectional area of ​​the opening on the lower side (conductor 706 side) is larger than that of the opening on the upper side (conductor 705 side). The cross-sectional area of ​​the opening may be narrowed.

[0352] The oxide 704, the insulator 703, and the conductor 701 (conductors 701_1 to 701_2) 37 and 38, a memory transistor MT is configured by any one of the following: 38 shows an example in which memory transistors MT are stacked in m stages (m is a natural number of 2 or more). In addition, in FIG. 37 and FIG. 38, the conductor 701 is shown as a single conductor. Although 01 is displayed in four or more rows, this embodiment is not limited to FIG. 37 and may be at least It is sufficient that the conductor 701 has two or more stages.

[0353] The conductor 705 is electrically connected to the oxide 704 and is connected to the source line SL or the bit line BL The conductor 705 may be formed of a conductive material containing a metal element. Alternatively, the conductor 705 may be formed of the above-mentioned metal film, oxide film containing a metal element, Alternatively, among materials that can be used for nitride films containing metal elements, a material having conductivity is used. In this case, as described above, a part of the oxide 704 has a low resistance. In addition, at the interface between the conductor 705 and the oxide 704, the metal element of the conductor 705 and the oxide It is preferable that a metal compound layer containing the component 704 is formed. By forming the oxide 704, the contact resistance between the conductor 705 and the oxide 704 is reduced, which is preferable. Alternatively, the conductor 705 absorbs oxygen contained in the oxide 704, and the oxide 704 By reducing the resistance near the interface between the conductor 705 and the oxide 704, The contact resistance with the oxide 704 can be reduced.

[0354] The conductor 705 may be aluminum, ruthenium, titanium, tantalum, chromium, tungsten, or the like. Use a conductive material containing one or more metal elements selected from stainless steel and copper. is preferred.

[0355] The conductor 706 is a conductor that functions as a part of the bit line BL, as shown in FIG. The oxide 704 electrically connects to the conductive layer 705, and the conductive layer 704 functions as a part of the source line SL. 705 and the oxide 704 electrically connected to each other, The area enclosed by the dotted line in Figure 38(A) represents a memory string. That is, in FIG. 38A, a memory cell array 700 having four memory strings This shows:

[0356] The conductor 706 can be made of the same material as the conductor 705. 706, the above-mentioned metal film, oxide film containing a metal element, or nitride film containing a metal element Among the materials that can be used for the film, a material having electrical conductivity can be used. As described above, a part of the oxide 704 has low resistance. The same material as 705 may be used, or a different material may be used.

[0357] In addition, at the interface between the conductor 706 and the oxide 704, a metal element contained in the conductor 706 and an oxide It is preferable that a metal compound layer containing the metal compound 704 is formed. The formation of the layer reduces the contact resistance between the conductor 706 and the oxide 704. Alternatively, the conductor 706 absorbs oxygen contained in the oxide 704, and the oxide 704 is formed. By reducing the resistance near the interface between the conductor 706 and the oxide 704 in 04, the conductor 706 By doing so, the contact resistance with the oxide 704 can be reduced.

[0358] Conductor 707, conductor 708, conductor 709, conductor 710, conductor 714, and conductor The conductor 715 can be used for the conductor 701, the conductor 702, or the conductor 712. The materials can be the same or different. Fees may also be used.

[0359] (Memory cell array 700A) FIG. 40 shows a memory cell array 700 having six stages of memory transistors MT. 40 is a top view illustrating a memory cell array 700A in which the memory cells are combined. For simplicity, some components are omitted. Select transistors (bit line side transistor: SDT, and source line side transistor: S ST) and the conductor 702 that constitutes them are omitted. and a conductor 705 which functions as a part of the source line SL, and a conductor 706 which functions as a part of the word line WL. A wiring electrically connected to the conductor 708 and the conductor 712 that functions as a second gate The conductor 715 that functions as part of the BG is shown by a solid line.

[0360] In the memory cell array 700A, each memory cell array 700 has six stages of memory transistors. The memory cell has four memory strings each having a transistor MT.

[0361] The bit line side ends of the memory strings are connected to different bit lines BL (BL_1 to BL_B L_4), the source line side end of the memory string is electrically connected to the source line S The source line SL is electrically connected to the ground line L and is given a common potential. Alternatively, a constant potential may be applied. The position may be changed.

[0362] The conductors 701_1 to 701_6 are electrically connected to different word lines WL. The conductors 701_1 to 701_6 on the bit line side are connected to WLa_1 to WLa_6, respectively. The conductors 701_1 to 701_6 on the source line side are electrically connected to , are electrically connected to WLb_1 to WLb_6, respectively.

[0363] The conductors 712 are electrically connected to the wiring BG. Although an example in which the body 712 is electrically connected to the common wiring BG is shown, the present invention is not limited to this. The conductors 712 arranged in the row direction may be electrically connected to a common wiring BG. In addition, different potentials may be applied to each wiring BG. In this case, it is preferable that the plurality of wirings BG are electrically connected to each other. The plurality of wirings BG refers to all of the wirings BG included in the memory cell array 700A. There are cases where this happens.

[0364] In addition, in order to apply an arbitrary potential to the wiring BG, the wiring BG must be connected to a power supply that controls the potential of the wiring BG. The circuit that controls the It is sometimes called a driver or driver circuit. The BG driver circuit may be provided for each BG wiring, or one BG driver circuit may be provided for each BG wiring. For example, a plurality of wirings BG may be electrically connected to the memory cell array 700A. has one BG driver circuit and connects all the wiring BGs of the memory cell array 700A. may be electrically connected to the BG driver circuit.

[0365] The bit lines BL (BL_1 to BL_4) and the word lines WL (WLa_1 to WLa WLb_1 to WLb_6) are appropriately selected to form the memory cell array 70 0 can be selected. Data can be written to, read from, erased, etc., from the transistor MT.

[0366] In addition, each memory string is provided with a selection transistor (not shown). Therefore, an arbitrary memory cell array 700 in the memory cell array 700A is selected, and the selected Write and read operations can be performed on any memory transistor MT in the memory cell array 700. You can then erase it, etc.

[0367] (Configuration example of storage device 750) FIG. 41 shows a memory device 700A in which a memory cell array 700A is stacked on a circuit 300. 41 shows an example of the configuration of the memory cell array 700A. 301, transistor 302, and transistor 303. The transistor 301 and the transistor The transistor 302 constitutes a sense amplifier 304, and the transistor 303 serves as a column selection switch. Specifically, the bit lines BL of the memory cell array 700A function as transistors. The gate of the transistor 301 is electrically connected to one of the source and drain of the transistor 301. , electrically connected to one of the source and drain of the transistor 302, The gate of transistor 302 is electrically connected to the other of the source and drain of transistor 301. In addition, one of the source and drain of the transistor 301 and the source of the transistor 302 The other of the source and drain is connected to the source of transistor 303, which functions as a column selection switch. This allows the layout of the memory device 750 to be In FIG. 41, ten stages of memory transistors MT are set. An example is shown in which 20 memory transistors MT are provided per memory string. However, the number of layers in which the memory transistors MT are stacked is not limited to this. For example, , 32, 64, 128, or even 200 or more layers may be stacked.

[0368] The bit lines BL of the memory cell array 700A are embedded in the insulators 726, 722, etc. The sense amplifier 304 and the column selection switch 306 are connected to the conductor 752 formed to be embedded therein. The circuit 300 is electrically connected to a transistor 303 that functions as a switch. The circuits and transistors shown are examples, and are not limited to the circuit configurations and transistor structures. In addition to the above, there are also control circuits, row decoders, row drivers, source line drivers, input / output circuits, Appropriate circuits and transistors are set depending on the configuration of the memory device 750 and its driving method. It can be done.

[0369] The transistor 301, the transistor 302, and the transistor 303 are formed on a substrate 311. conductor 316, insulator 315, and semiconductor made up of a part of substrate 311, respectively. region 313, and a low resistance region 314a that functions as a source or drain region; and low resistance region 314b. As shown in FIG. 41, one low resistance region is The source region or drain region of one of the transistors 301 and 302 , and may share the other as a source region or a drain region.

[0370] The transistor 301, the transistor 302, and the transistor 303 have a channel formed The semiconductor region 313 (part of the substrate 311) formed thereon has a convex shape. The side and top surfaces of the heat sink 13 are covered with a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. The transistor 301, the transistor 302, and the transistor 303 utilize the protruding portion of the semiconductor substrate. It is also called a FIN type transistor because it uses a The insulating layer may have an insulating material that functions as a mask for forming the semiconductor portion. Although the case where a convex portion is formed by processing a part of a conductor substrate has been shown, it is also possible to process an SOI substrate to form a convex shape. Alternatively, a semiconductor film having the following structure may be formed.

[0371] The transistor 301, the transistor 302, and the transistor 303 are p-channel transistors. The transistor 301 and the transistor 302 may be either a n-channel or n-channel type. The transistors 302 are preferably transistors each having a different polarity.

[0372] The region where the channel of the semiconductor region 313 is formed, the region nearby, the source region, or the drain region In the low resistance region 314a and the low resistance region 314b, which are the drain region, silicon is It preferably contains a semiconductor such as a silicon-based semiconductor, and preferably contains single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gallium It may be formed of a material containing gallium aluminum arsenide (GaAlAs), GaAlAs (Gallium Aluminum Arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, we can control the effective mass of silicon. Alternatively, GaAs and GaAlAs may be used to form a transistor. The transistor 301, the transistor 302, and the transistor 303 are HEMT (High Electrical MEMS) It may also be called a power transistor mobility transistor.

[0373] The low resistance region 314a and the low resistance region 314b are semiconductor regions applied to the semiconductor region 313. In addition to the body material, elements that impart n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. The element imparting electrical conductivity is included.

[0374] The insulator 315 separates the transistors 301, 302, and 303. It functions as a gate insulating film.

[0375] The conductor 316 that functions as the gate electrode is made of an element that gives n-type conductivity, such as arsenic or phosphorus. Semiconductor materials such as silicon that contain elements that impart p-type conductivity, such as silicon or boron A conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0376] Since the work function is determined by the conductor material, the threshold can be adjusted by changing the conductor material. Specifically, titanium nitride, tantalum nitride, etc. are used as the conductor. Furthermore, in order to achieve both electrical conductivity and embeddability, it is preferable to use a material such as It is preferable to use metal materials such as tungsten and aluminum as the lamination material, and particularly tungsten. It is preferable to use tin in terms of heat resistance.

[0377] An insulator 317 is provided above the conductor 316 to function as an etching stopper. In addition, it is preferable that the side of the insulator 315 is provided with an insulating layer that functions as a spacer. It is preferable that an insulator 318 is provided. As a result, the low resistance region 314a and the low resistance region 314b are electrically connected to the conductor 328. Therefore, the low resistance region 314a and the low resistance region 314b can be determined in a self-aligned manner. Misalignment occurred when forming the opening to expose a portion of the resist region 314b. In this way, an opening can be formed to expose the intended area. A conductor 328 is formed in the opening, forming a low resistance region 314a and a low resistance A good contact with reduced contact resistance is obtained between region 314b and conductor 328. The low resistance region 314a and the low resistance region 314b formed in this way are electrically conductive. The contact with the insulator 328 is sometimes called a self-aligned contact. 317, and a conductor electrically connected to the conductor 316 so as to be embedded in the insulator 322. An electrical current 329 may be provided.

[0378] The transistors 301, 302, and 303 are covered with an insulator. 320, insulator 322, insulator 324, insulator 326, and insulator 327 are stacked in this order. It is set up as follows.

[0379] As insulator 320, insulator 322, insulator 324, insulator 326, and insulator 327 For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide Aluminum, aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, etc. That's good enough.

[0380] The insulator 322 smooths out the steps caused by the transistor 301 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a planarizing film. To improve flatness, the surface is flattened by a planarization process such as chemical mechanical polishing (CMP). It's fine.

[0381] The insulator 324 also includes a substrate 311, a transistor 301, and the like. The region where the array 700A is provided has a barrier property that prevents hydrogen and impurities from diffusing. It is preferred to use a membrane.

[0382] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, a semiconductor having an oxide semiconductor such as a memory transistor MT can be used. When hydrogen diffuses into the conductive element, the characteristics of the semiconductor element may be deteriorated. , the diffusion of hydrogen is suppressed between the memory transistor MT and the transistor 301, etc. It is preferable to use a film that suppresses the diffusion of hydrogen. Specifically, the film that suppresses the diffusion of hydrogen is a film that suppresses the amount of hydrogen desorption. Use a small film.

[0383] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of hydrogen desorption from the insulator 324 can be measured by TDS analysis when the surface temperature of the film is 5 In the range of 0 to 500°C, the amount of desorption converted to hydrogen atoms is Converted to 10 x 10 15 atoms / cm 2 Less than or equal to 5 x 10 15 at oms / cm 2 The following is fine.

[0384] It is preferable that the insulators 326 and 327 have a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 and the insulator 327 is preferably less than 4, and more preferably 3. For example, the relative dielectric constant of the insulator 326 and the insulator 327 is preferably less than 1000 kJ / cm. The dielectric constant is preferably 0.7 times or less, more preferably 0.6 times or less, of the dielectric constant of the insulating body 324. By using a material with a low resistance as the interlayer film, the parasitic capacitance occurring between wirings can be reduced.

[0385] Also, insulator 320, insulator 322, insulator 324, insulator 326, and insulator 327 conductors 328 and 329, which are electrically connected to the memory cell array 700A, The conductor 330 and the like are embedded. 330 has a function as a plug or wiring. In the case of a conductor having a function, multiple structures may be collectively assigned the same symbol. In the specification and the like, the wiring and the plug electrically connected to the wiring may be integrated into one body. That is, when a part of the conductor functions as a wiring, and when a part of the conductor functions as a plug, Sometimes it works.

[0386] The materials of each plug and wiring (conductor 328, conductor 329, conductor 330, etc.) Examples of the conductive material include metals, alloys, metal nitrides, and metal oxides. Tungsten and other materials that have both heat resistance and electrical conductivity can be used as single layers or laminated layers. It is preferable to use a high melting point material such as molybdenum, and it is more preferable to use tungsten. Alternatively, it is preferable to form the wiring board from a low-resistance conductive material such as aluminum or copper. By using a resistive conductive material, the wiring resistance can be reduced.

[0387] A wiring layer may be provided on the insulator 327 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring. The conductors 328, 329, and 330 can be formed using the same materials. Cut.

[0388] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. In addition, the conductor 356 has a barrier property against hydrogen. It is preferable that the insulating material 350 contains a conductor. In particular, the insulating material 350 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 301 and the like can be separated from the memory transistor MT by a barrier layer. Therefore, the diffusion of hydrogen from the transistor 301 to the memory transistor MT can be suppressed. can be done.

[0389] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, It is possible to suppress the diffusion of hydrogen from the transistor 301 and the like while maintaining the conductivity of the transistor. In this case, the tantalum nitride layer, which has a barrier property against hydrogen, acts as a barrier against hydrogen. It is preferable that the insulating material 350 has a structure in which the insulating material 350 is in contact with the insulating material 350.

[0390] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in FIG. An insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed on the insulators 360, 362, and 364. The conductor 366 functions as a plug or wiring. The conductors 328, 329, and 330 can be formed using the same materials. Cut.

[0391] For example, the insulator 360 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. The conductor 366 has a barrier property against hydrogen. It is preferable that the insulating material 360 contains a conductor. In particular, the insulating material 360 has a barrier property against hydrogen. A conductor having a barrier property against hydrogen is formed in the opening. The transistor 301 and the like can be separated from the memory transistor MT by a barrier layer. Therefore, the diffusion of hydrogen from the transistor 301 to the memory transistor MT can be suppressed. can be done.

[0392] An insulator 722 is provided on the insulator 364 and the conductor 366. The memory cell array 700A is provided above the insulator 364 and the insulator 722. A barrier film made of a material similar to that of the insulator 324 may be provided between them.

[0393] In FIG. 41, a U-shaped memory is shown in which two pillar-shaped oxides 704 are electrically connected by a conductor 706. Although an example of the memory cell array 700A having strings has been shown, the present invention is not limited to this. FIG. 42 shows a memory cell with eight memory transistors MT and two select transistors (SDT, SS In the columnar oxide 704 having the gate electrode T, the bottom end of one columnar oxide 704 is connected to the bit line B The upper end of the conductor 705B functions as a source line SL. In other words, one columnar oxide 70 is electrically connected to the conductor 705S. 4 constitute one memory string. In FIG. 42, the conductor 705B is Although the lower ends of the four pillar-shaped oxides are electrically connected, the present invention is not limited to this. One conductor 705B may be electrically connected to the columnar oxide 704, or two or more columnar oxides may be electrically connected to the columnar oxide 704. One conductor 705B may be electrically connected to the oxide 704. Although 5S is electrically connected to the top ends of the two pillar-shaped oxides, the present invention is not limited to this. One conductor 705S may be electrically connected to one columnar oxide 704, or two or more conductors may be electrically connected to one columnar oxide 704. One conductor 705S may be electrically connected to the upper columnar oxide 704.

[0394] A selection transistor SDT is provided between the conductor 705B and the memory transistor MT. A selection transistor SST is provided between the conductor 705S and the memory transistor MT. The conductor 705B, which functions as the bit line BL, is connected to the circuit 30 provided below. 0, and electrically connects the memory cell array 700A and the circuit 300. The number of wirings (routing wirings) and plugs for the storage device 750 can be reduced. This is preferable because it can further reduce the out area. Although the number of memory transistors MT is eight, the present invention is not limited to this. For example, 32, 64, or 128 layers can be stacked. Alternatively, 200 or more layers may be stacked.

[0395] Regarding the metal oxide applicable to the oxide 704 according to the present invention, the Reference may be made to metal oxides.

[0396] (Method of manufacturing memory cells) Next, one embodiment of a method for producing a memory transistor MT that functions as a memory cell of the present invention. This will be explained with reference to Figures 43 to 48. Note that Figures 43 to 48 show memory transistors. 1A to 1C are diagrams showing cross sections of the fabrication process of the TAMT.

[0397] First, as shown in FIG. 43(A), conductors 701 and insulators 722 are alternately stacked. .

[0398] Next, as shown in FIG. 43(B), the conductor 701 and the insulator 722 are processed to form a conductor An opening having a diameter of φ1 is formed in the insulating material 701 and the insulating material 722.

[0399] Next, as shown in FIG. 43(C), the conductor 701 is subjected to isotropic etching to form a conductive The opening diameter of the body 701 is expanded. The diameter of the opening at this time is set to φ2 (φ2>φ1). The conductor 701 has a recess on the side of the insulator 722 sandwiched between it and the conductor 701. do.

[0400] Next, as shown in FIG. 44(A), an insulator 703 and an oxide 704 are formed inside the opening. Although not shown in FIG. 44(A), the insulator 703 is made up of an insulator 703a, an insulator 703b, and an insulator 703c. The oxide 704 is formed by stacking the oxide 703b and the insulator 703c in this order. The oxide 704a, the oxide 704b, and the oxide 704c are stacked in this order. It is preferable to remove the insulator 703 at the bottom of the opening before forming the oxide 704. The oxide 703 and the oxide 704 are formed with good coating properties even in the recesses of the conductor 701. The insulator 703a is formed on the side surface of the conductor 701, the side surface of the insulator 722, a part of the upper surface, and the lower surface. It is formed so as to contact a part of the surface.

[0401] Next, as shown in FIG. 44(B), an insulating film 719A is formed inside the opening. 9A is formed so as to fill the inside of the recess with an insulator 703 and an oxide 704 sandwiched between them. However, the present invention is not limited to this. An insulating film 719A may be formed to fill the gap.

[0402] Next, the insulating film 719A is processed to form the insulator 719. The insulating film 719A is processed as follows: The insulating film 719A may be etched by isotropic etching or anisotropic etching. In the formation, as shown in FIG. 44(B), the insulating film 719A fills the recessed portion and the opening is completely If the insulating film 719A is not filled in the insulating film 719A, isotropic etching should be used to process the insulating film 719A. On the other hand, when the insulating film 719A is formed so as to fill the recess and the opening, In this case, it is preferable to use anisotropic etching. An insulator 719 can be formed on the insulating film 714 (see FIG. 44C).

[0403] Next, as shown in FIGS. 45 and 46, the oxide 704 is formed using the insulator 719 as a mask. FIG. 45(B) shows the area surrounded by the dashed line in FIG. 45(A). FIG. 45(A) shows the area of ​​oxide 704 formed by argon plasma. In this example, argon is added to the region 731 to reduce the resistance. The elements to be added are not limited to those mentioned above. In addition to argon, hydrogen, boron, carbon, nitrogen, fluorine, etc. Addition of nitrogen, phosphorus, sulfur, chlorine, titanium, helium, neon, krypton, xenon, etc. Also, aluminum, ruthenium, titanium, tantalum, tungsten, chromium A metal element such as indium may be added to increase the conductivity of the oxide 704. The treatment can be carried out using an etching device or a CVD device. The processing method is not limited to plasma processing, but also includes ion implantation processing, ion doping A sputtering process, a reverse sputtering process using a sputtering device, or the like can be used.

[0404] FIG. 46 shows a film made of a metal film, an oxide film containing a metal element, or a nitride film containing a metal element. A film 718 made of the above-mentioned material is formed in contact with a region 731 of the oxide 704, and the region 731 is made into a low resistance As shown in FIG. 46(A), a film 718 is formed, and if necessary, a heat treatment is performed. By performing the treatment, the resistance of the region 731 of the oxide 704 is reduced. 45(B), the film 718 may be removed. 6(B), this also corresponds to the area surrounded by the dashed line.

[0405] Note that metal films, oxide films containing metal elements, and nitride films containing metal elements are not necessarily excluded. For example, a metal film, an oxide film containing a metal element, or a film containing a metal element may be used. If the nitride film is an insulator, or if it is oxidized by the oxygen absorbed from the oxide 704, it becomes an insulator. If the insulating layer 711 becomes an insulator and has a high resistance, it may be left. Similarly, it may function as a second gate insulating layer.

[0406] The film 718 has the functions of supplying hydrogen to the oxide 704, supplying nitrogen to the oxide 704, and and a function of extracting oxygen from the oxide 704. When the film 718 having such a function comes into contact with the oxide 704, the catalyst is formed in the oxide 704. A carrier is generated.

[0407] Specifically, oxygen is extracted from the oxide 704, and the oxide 704 contains oxygen. A defect occurs. Hydrogen is trapped in this oxygen defect, generating carriers. Alternatively, if nitrogen is trapped in the resulting oxygen vacancy, it will bond with two indium atoms. When nitrogen bonds to these two indium atoms, Nitrogen has an unpaired electron and is thought to function as a carrier.

[0408] As a material that has the function of supplying hydrogen to the oxide 704, silicon nitride containing hydrogen is used. In addition, a material formed using a gas containing hydrogen can be used. It can be formed using monosilane, disilane, ammonia, etc., and is a silicon, silicon oxide Silicon oxide, silicon oxynitride, silicon nitride oxide, etc. can be used. Nitrides containing silicon or metal elements are used as materials with the function of supplying nitrogen. Such materials include silicon nitride, silicon nitride oxide, and silicon oxynitride. , etc. Also, one or more of aluminum, tantalum, and titanium can be used. Specifically, nitrides containing aluminum nitride, tantalum nitride, and nitrides containing tantalum nitride can be used. titanium nitride, nitrides containing aluminum and tantalum, nitrides containing aluminum and titanium, etc. etc. can be used.

[0409] For example, the film 718 has a thickness of 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 2 nm or less. For example, it is preferable to heat an aluminum film having a thickness of 0.5 nm or more and 5 nm or less. When oxidized by processing, aluminum oxide with a thickness of 0.7 nm to 8 nm may be formed. When the heat treatment is performed in the oxidizing atmosphere, the oxide 704 and the metal film and metal element In a state where an oxide film containing a metal element or a nitride film containing a metal element is in contact with the oxide film, the nitride film is exposed to a nitrogen-containing atmosphere. It is preferable to carry out the heat treatment once under a nitrogen-containing atmosphere. By performing heat treatment once, oxygen in the oxide 704 is converted into a metal film, an oxide film containing a metal element, Alternatively, the metal element is more likely to diffuse into the nitride film containing the metal element.

[0410] The oxide 704 is in contact with a film 718 containing any one of a metal element, hydrogen, and nitrogen. After the formation of the film, it is preferable to perform a heat treatment. By performing the heat treatment, oxygen is extracted and water is removed. The supply of oxygen or nitrogen is promoted, and the resistance of the oxide 704 is effectively reduced partially. It is possible.

[0411] As described above, by providing a low resistance region in the oxide 704, the memory cells are stacked. To reduce the series resistance between memory cells in a memory string or memory cell array It is possible.

[0412] Next, an insulator 711 is formed inside the oxide 704 and the insulator 719. A conductor 712 is formed inside the insulating film 1 (see FIG. 47A). It is not necessary to provide the insulating material 711, and the inside of the oxide 704 may be filled with the insulating material 711. FIG. 47(B) is an enlarged view of the part surrounded by the dashed line in FIG. 47(A). The k-1th conductor 701_k-1 and the insulator 722_k-1 are connected to the k-1th conductor 701_k, an insulator 722_k, and a conductor 701_k+1 in the (k+1)th stage (k is , an integer of 2 or more and m-1 or less).

[0413] Next, a heat treatment may be performed. The heat treatment provides oxygen from the insulator 719 to the oxide 704. Furthermore, since impurities such as hydrogen are removed from the region 734, the region 734 is highly pure. The region 732 (region 733) between the region 731 and the region 734 is preferable because it has a high conductivity and a high resistance. Region 732a and region 732b serve as bonding regions. It is preferable that the resistance of the region 732 is lower than that of the region 731. , and may have a higher resistance than region 731.

[0414] The region 734 of the oxide 704 functions as a channel forming region of the memory transistor MT. The region 731a is used as one of the source and drain of the memory transistor MT. The region 731b functions as the other of the source and drain. _k serves as the first gate of the memory transistor MT, and the conductor 712 serves as the second gate of the memory transistor MT. The insulator 703a functions as a gate, and the insulator 70 3b functions as a charge storage layer, and insulator 703c functions as a tunnel insulating layer. The conductor 711 functions as a second gate insulating layer. The source or drain of the memory transistor MT is connected to the transistors located above and below it. For example, the region 731b may function as a drain or a source. When the region 701_k functions as the source of a transistor having the conductor 701_k as the gate, 31b functions as the drain of a transistor whose gate is the conductor 701_k+1. There are cases where this happens.

[0415] Through the above steps, a memory transistor MT that functions as a memory cell can be formed. By the above method, patterns for fabricating memory transistors MT for each layer can be formed. It is possible to fabricate multiple layers of memory transistors MT at once without forming a gate. Furthermore, when a memory cell array is fabricated by the above method, the memory transistor MT Even if the number of layers is increased, the process of pattern formation and etching of the memory transistor MT In this way, the process of manufacturing the memory cell array can be shortened. A semiconductor device with high productivity can be provided.

[0416] FIG. 48(A) is a diagram showing a different example of the conductor 701. In FIG. The body 701 has a three-layer structure of a conductor 701c, a conductor 701d, and a conductor 701e. The conductor 701d is recessed relative to the side surfaces of the conductors 701c and 701e. The conductor 701 has a region 734 of the oxide 704 and a side of the region 732, The upper and lower sides are surrounded by an insulator 703. By doing so, an electric field is applied from the conductor 701 not only to the region 734 but also to the region 732. This is preferable as it improves the on-characteristics of the memory transistor MT.

[0417] The conductor 701d has a recess with respect to the side surfaces of the conductors 701c and 701e. In order to achieve this, the etching rate of the conductor 701d in the isotropic etching is set to be equal to or larger than that of the conductor 701d. 01c and a material having an etching rate greater than that of the conductor 701e, or For example, the conductor 701d is made of tungsten, and the conductor 70 1c, and the conductor 701e are made of a conductive material containing tantalum or titanium, or nitrides thereof. Alternatively, the conductor 701d may be selectively etched using a gas containing chlorine. The conductor 701d is made of aluminum, and the conductors 701c and 701e are made of tantalum. The conductor 701d is selectively formed of a conductive material containing titanium or titanium nitride. Alternatively, the conductor 701d may be made of a material containing silicon, The conductor 701c and the conductor 701e are made of a small amount of tantalum, titanium, and tungsten. The conductor 701d is selectively formed of a conductive material containing at least one of these or a nitride thereof. Wet etching may also be performed.

[0418] FIG. 48B is a diagram showing another example of the conductor 712. In FIG. 48B, The insulator 719 has been removed and the conductor 712 fills the area where the insulator 719 was located. By adopting such a shape, the conductive material is 712 can be effectively applied, and as will be described later, the circuit operation of the memory device can be This is also preferable because it allows for a reduction in the power consumption of the storage device.

[0419] (Method of manufacturing a memory cell array) Next, one embodiment of a method for manufacturing a memory cell array of the present invention will be described with reference to FIGS. In each of Figures 49 to 67, (A) is a top view seen from the z-axis direction. (B) is a cross-sectional view of the area indicated by the dashed line A1-A2 in (A). ) is a cross-sectional view of the portion indicated by the dashed line A3-A4 in (A). and Fig. 62(D) are the dashed lines in Fig. 59(B) and Fig. 62(B), respectively. FIG. 1 is an enlarged cross-sectional view of the area surrounded by the arrow.

[0420] First, a conductor 706 is formed on a substrate 720 having an insulating surface, and a metal film is formed on the substrate 720 so as to cover the conductor 706. Thus, an insulator 721 is formed (see FIG. 49).

[0421] First, a conductive film is formed, and the conductive film is processed by lithography to form a conductor 706. However, the method for forming the conductor 706 and the insulator 721 is not limited to this. An insulator 721 is formed on the substrate 720, and unnecessary portions of the insulator 721 are removed to form grooves and An opening may be formed and the conductor 706 may be embedded in the groove or the opening. Such a method for forming a conductor is called the damascene method (single damascene method, dual damascene method). In some cases, an insulating layer is formed on the conductor 706 and the insulator 721 formed by the damascene method. By forming the film, the structure shown in FIG. 49 can be obtained.

[0422] The conductor 706 and the insulator 721 can be formed by a sputtering method, a CVD method, an MBE method, a P This can be done using the LD method, ALD method, or the like.

[0423] This processing can be performed by dry etching or wet etching. The etching method is suitable for microfabrication.

[0424] The conductive film to be the conductor 706 is formed by sputtering a conductive film containing a metal element. It is also possible to form it by using a CVD method.

[0425] The surface of the insulator 721 is preferably subjected to planarization treatment as necessary. The planarization process can be performed by chemical mechanical polishing (CMP) or reflow.

[0426] A conductive film 701A and an insulating film 722A are alternately formed on the conductor 706 and the insulator 721. In this embodiment, the conductive film 701A is formed over the insulator 721, and the conductive film 70 1A, the order of formation is not limited to this. An insulating film 722A is formed on the insulating film 722A, and a conductive film 701A is formed on the insulating film 722A. The conductive film 701A and the insulating film 722A can be formed by a CVD method. Alternatively, a sputtering method may be used.

[0427] In this embodiment, the conductive film 701A and the insulating film 722A are each formed into four layers. However, the number of layers is not limited to this. For example, the conductive film 701A and the insulating film 722A may be formed in five or more layers. The number of layers may be 32, 64, 128, or 200 or more.

[0428] A conductive film 702A is formed on the top layer of the insulating film 722A. The conductive film 702A is formed by the same method as the conductive film 701A. The conductive film 702A can be formed using the same material as the conductive film 7 It may be formed by the same method as that of the conductive film 70. 2A may be made of the same material as the conductive film 701A, or may be made of a different material.

[0429] Next, the conductive film 702A, the conductive film 701A, and the insulating film 722A are processed, and the resultant structure shown in FIG. ) Step-like conductive films 701B, 702B, and insulating films 722B are formed. In processing the conductive film 702A, the conductive film 701A, and the insulating film 722A, 702A, the conductive film 701A, and the insulating film 722A are etched, and the mask 723 is slit. By alternately performing etching, the conductive film 701B, the conductive film 702B, and the insulating film 7 22B can be formed. By processing A, the mask 723 is reduced in both width and thickness to become a mask 723A (FIG. 51 reference.).

[0430] Next, the mask 723A is removed and an insulator 724 is formed. The insulator 724 is formed by a CVD method. The insulator 724 can be formed by using a CMP method or a reflow method. A mask 725 is formed on the insulator 724. Planarization By forming a mask 725 on the insulating layer 724, the accuracy of lithography is improved. (See Figure 52.)

[0431] Next, using a mask 725, the insulator 724, the conductive film 702B, the conductive film 701B, and the insulating film 724 are The film 722B and the insulator 721 are processed. A conductor 701 that functions as a gate and is electrically connected to a word line and a gate of a select transistor A conductor 702 that functions as a gate is formed. This forms an insulator 722 (see FIG. 53).

[0432] Next, the mask 725 is removed. Next, the insulator 724, the conductive film 702B, and the conductive film 701 B, the insulating film 722B, and the insulator 721 are filled with the portions removed by the above processing. The insulator 726 is formed as shown in FIG. 7. The insulator 726 is formed by using a CVD method or an ALD method. In particular, the ALD method allows for the formation of grooves and openings with a large aspect ratio. It is preferable to use the ALD method because it is possible to form a film with a uniform thickness. The insulator 726 may be formed by a combination of a VD method. It is preferable that the planarization process is performed using a flow method. When performing the above, the insulator 726 may be polished until the surface of the insulator 724 is exposed. The insulators 724 and 726 may be polished together. In this case, the thickness of the insulator 724 is , become thinner.

[0433] Next, the insulator 724 is processed by lithography to form the conductor 701 and the conductive A first opening is formed to expose the body 702. The first opening is formed by a stepped conductive layer. This is formed for each of the conductors 701 (see FIG. 54).

[0434] Next, a conductor 707 electrically connected to the conductor 701 is embedded in the first opening. A conductor 709 is formed to be electrically connected to the conductor 702 (see FIG. 55). The body 707 and the conductor 709 can be formed using a CVD method or an ALD method. In particular, the ALD method allows for uniform thickness even for grooves and openings with large aspect ratios. Alternatively, the ALD method and the CVD method may be combined to form a uniform film. The conductor 707 and the conductor 709 may be formed in combination. The conductor 707 and the conductor 709 may have a laminated structure made up of multiple layers. The conductor 709 is disposed on the insulator 724 and inside the first opening, and the conductor 707 is disposed on the insulator 724 and inside the first opening. A conductive film that will become the body 709 is formed, and unnecessary conductive film is removed by using CMP or the like. It can be achieved.

[0435] Next, a mask 729 is formed on the insulator 724 and the insulator 726. The conductor 702, the conductor 701, the insulator 722, and the insulator 721 are formed by a lithography method. 56. Then, a second opening is formed to expose the conductor 706 (see FIG. 56). .

[0436] Next, the conductor 701 and the conductor 702 are subjected to isotropic etching, and the conductor 70 1 and the diameter of the opening of the conductor 702 (see FIG. 57). The diameter of the opening of the insulator 721, the insulator 722, and the insulator 724 is larger than the diameter of the opening of the insulator 721, the insulator 722, and the insulator 724. In addition, the conductor is not connected to the insulators (insulator 721, insulator 722) located above or below the conductor. 22, or the side of the insulator 724) has a recess. The process involves isotropic etching using dry etching with gas, radicals, plasma, etc. For example, isotropic etching such as wet etching using a liquid or the like can be used. The liquid used in wet etching is sometimes called an etchant. When isotropic etching is performed using a gas containing at least one of chlorine, bromine, and fluorine, In this embodiment, an isotropic edge, radicals, plasma, etc. can be used. Although the etching is performed without removing the mask 729 in the above example, the present invention is not limited to this. After removal of the mask 729, an isotropic etch may be performed.

[0437] Next, the insulator 724, the insulator 726, and the mask 729 are covered, and a second opening is formed inside the second opening. Then, an insulating film 703A that will become the insulator 703 is formed (see FIG. 58). Although not shown, the insulating film 703A is made up of an insulating film that becomes the insulator 703a and an insulating film that becomes the insulator 703b. The insulating film 703A and the insulating film that will become the insulator 703c may be sequentially stacked. The film can be formed by using a CVD method or an ALD method. In particular, by using an ALD method, It is possible to form a film with a uniform thickness even in grooves and openings with a large aspect ratio. Alternatively, the insulating film 703A may be formed by combining the ALD method and the CVD method. The insulating film that becomes the insulator 703a, the insulating film that becomes the insulator 703b, and the insulating film that becomes the insulator 703c may be formed by the insulating film 703b. The insulating film to be formed as O3c may be formed in the same film forming apparatus or in a different film forming apparatus. In addition, the thickness of the insulator 703 may be adjusted so that the insulator 703c is thinner than the insulator 703a. The insulating film to be the insulator c is preferably formed thinner than the insulating film to be the insulator 703a.

[0438] The insulating film 703A formed by the above method has good coating properties and can cover the conductor 701 and the The insulating film 703A can also be formed in the recessed portion of the conductor 702. 1, and the side of the conductor 702, and the insulators 721, 722, and 724. In addition to the side surfaces, parts of the top surfaces of the insulators 721, 722, and 724, and The insulating film 703A can be formed so as to contact with the upper surface and a part of the lower surface.

[0439] Next, the insulating film 703A formed on the bottom of the second opening is removed to obtain the insulator 703. It is preferable to use anisotropic etching to remove the insulating film 703A. Since the insulating film 703A on the 729 is also removed, the insulator 703 is left only on the sidewall of the second opening. (See FIG. 59.) By removing the insulating film 703A at the bottom of the second opening, The conductor 706 is exposed.

[0440] Here, as shown in FIG. 59(D), the insulator 703 located above the second opening 59(B) and the insulating material 703b and the insulating material 703c may be removed. First, the inside of the second opening is easily opened in a later process. A removable material 727 (also called a sacrificial layer) is formed to fill the second opening. The insulator 7 exposed by the etching is removed to a desired depth. By sequentially removing the conductor 702, the horizontal direction (x-y The insulator 703 located in the direction (the direction of the insulating film 703) can be only the insulator 703a. The gate insulating film of the select transistors SST and SDT is made of an insulator 703a. After removing insulator 703c and insulator 703b, material 727 is removed.

[0441] Next, an oxide film 704A that will become the oxide 704 is formed inside the second opening (see FIG. 60). The oxide film 704A is formed on the mask 729 and in the second opening, and the oxide film 704a is formed on the mask 729 and in the second opening. The oxide film that becomes oxide 704b, the oxide film that becomes oxide 704c are sequentially formed. The oxide film 704A can be formed by insulating the conductive film 704A with the insulator 703 interposed therebetween. The oxide film 704A is formed along the recesses of the conductor 701 and the conductor 702. It is formed so as to be in contact with the conductor 706 .

[0442] The oxide film that becomes oxide 704a, the oxide film that becomes oxide 704b, and the oxide film that becomes oxide 704c. The oxide film can be formed by using a CVD method or an ALD method. In particular, the ALD method This allows for the formation of a film with a uniform thickness even in grooves and openings with a large aspect ratio. Alternatively, the oxide film may be formed by combining the ALD method and the CVD method. Also, different film forming methods and film forming apparatuses may be used for each oxide film.

[0443] Next, an insulating film 719A is formed inside the second opening (see FIG. 60). A is connected to the conductor 701 and the insulating film 703 through the oxide film 704A. The conductive material 702 may be formed so as to fill the recess of the second opening. It is not necessary to fill the entire area. The insulating film 719A can be formed by using a CVD method or an ALD method. In particular, the ALD method allows for the formation of grooves and openings with a large aspect ratio. The ALD method is also preferable because it can form a film with a uniform thickness. The insulating film 719A may be formed by combining the method D.

[0444] Next, the insulating film 719A is processed to form the insulator 719 (see FIG. 61). 719A can be processed using isotropic or anisotropic etching. In forming the insulating film 719A, as shown in FIG. 60, the insulating film 719A fills the recessed portion. If the opening is not completely filled, the insulating film 719A is processed by isotropic etching. On the other hand, an insulating film 719A is formed so as to fill the recesses and openings. In this case, it is preferable to use anisotropic etching. An insulator 719 can be formed inside the recess.

[0445] Next, using the insulator 719 as a mask, a low resistance region is formed in part of the oxide film 704A. As a method for forming the low resistance region, argon, hydrogen, boron, carbon, nitrogen, etc. are added to the oxide film 704A. , fluorine, phosphorus, sulfur, chlorine, helium, neon, krypton, xenon, and other elements. Aluminum, ruthenium, titanium, tantalum, tungsten, chromium, indium, etc. A metal element that increases the conductivity of the oxide 704 may be added. plasma treatment, ion implantation treatment, ion doping treatment, reverse sputtering Plasma treatment can be performed using an etching device or a CVD device. The reverse sputtering process can be carried out using a sputtering device. In this embodiment, the region 73 of the oxide film 704A is etched by argon plasma treatment. 1 is made low resistance (see Figure 62).

[0446] In addition, as a method of adding the above elements to the oxide film 704A, a film containing the above elements may be added to the oxide film 704 A is formed so as to contact the region 731, and by performing heat treatment as necessary, the region 731 By such a treatment, when the element is implanted into the oxide film 704A, In addition, oxygen contained in the oxide film 704A may be extracted by the oxide film 704A. Carriers may be generated within the

[0447] It is not necessary to remove the film. For example, if the film is an insulator, Or, due to the oxygen absorbed from the oxide 704, it becomes an insulator and has high resistance. In this case, the insulating layer 711 may be left as the second gate insulating layer. This may work.

[0448] Next, an insulating film 711A is formed inside the oxide film 704A and the insulator 719. A conductive film 712A is formed inside the insulating film 711A. The insulating film 711A and the conductive film 712A are It can be formed by using the CVD method or the ALD method. In particular, by using the ALD method, It is possible to form a film with a uniform thickness even on grooves and openings with a large aspect ratio. Alternatively, the ALD method and the CVD method may be combined to form the film (see FIG. 63). .).

[0449] The insulator 711 is a semiconductor layer including the memory transistor MT and the semiconductor layer including the memory transistor MT. According to the characteristics required for the device, a material that supplies oxygen to the oxide 704 or a material that supplies hydrogen to the oxide 704 is selected. Materials can be used.

[0450] Next, a heat treatment is performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C. Preferably, the heat treatment is carried out at a temperature of 300° C. or higher and 400° C. or lower. The method is not limited to the above, and may be carried out in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere. .

[0451] By performing a heat treatment while the oxide film 704A and the conductor 706 are in contact with each other, the oxide The oxide film 704A may have a low resistance. At the interface between the conductor 706 and the oxide film 704A, the metal element contained in the conductor 706 and the oxide film 704A are present. A metal compound layer containing the components of 704A may be formed. This is preferable because the contact resistance between the conductor 706 and the oxide film 704A is reduced. In addition, the conductor 706 may absorb oxygen contained in the oxide film 704A. When the oxide film 704A is heated, the resistance in the vicinity of the interface between the conductor 706 and the oxide film 704A is reduced, and the conductor This is preferable because the contact resistance between the conductor 706 and the oxide film 704A is reduced. By performing heat treatment while the oxide film 704A is in contact with the conductor 706, the oxide film 704A is more The resistance is lowered, and the contact resistance between the conductor 706 and the oxide film 704A is further reduced.

[0452] Next, from the mask 729 and the dotted line portion in Figure 63(B) and Figure 63(C), The unnecessary upper conductive film 712A, insulating film 711A, oxide film 704A, insulator 703, etc. , and are removed by a CMP method or the like to obtain an oxide 704, an insulator 711, and a conductor 712 (FIG. 6 4.) The heat treatment described above removes unnecessary conductive film 712A, insulating film 711A, and oxide film. Alternatively, the insulating film 703A may be removed after the first opening is formed. If the mask 729 is removed before the formation, it is necessary to remove the mask 729 in this step. There's no need.

[0453] Next, as shown in FIG. 65, the bit lines BL, the source lines SL, and some of the word lines WL are connected. The conductor 705 is formed by the oxide 704 and the conductor 7 7. A conductor 712 is provided inside the oxide 704. If the conductor 705 is provided with an opening that exposes at least the conductor 712, It is preferable to electrically separate the conductor 705 from the conductor 712. In this case, the opening is The insulator 711 may be exposed. It may be possible.

[0454] Next, as shown in FIG. 66, an insulator 717 is formed to cover the conductor 705. The oxide 717 has a part of the conductor 705 (a conductor electrically connected to the oxide 704 on the bit line side). An opening is provided to expose the conductive material 712. When forming the opening, the diameter of the opening is set to be larger than the diameter of the opening provided in the conductor 705. Since the opening is provided in the conductor 705, the opening exposing the conductor 712 may be The opening is formed in a self-aligned manner, and the diameter of the bottom of the opening is formed to an unintended size. This is preferable because it can prevent problems such as the opening being misaligned with the conductor 712.

[0455] Next, as shown in FIG. 67, an opening formed in the insulator 717 is inserted through which the conductor 712 is exposed. In this step, an insulator 713 is formed to cover the conductor 705. By forming an insulating film to be the insulator 713 using the ALD method or the like, and then performing anisotropic etching, The insulating film formed on the bottom of the opening is removed by this. The insulating film is also removed to form an insulator 713. At this time, the formed insulator 713 may also exist on the insulator 717. There is a match.

[0456] Next, the conductors 714 and 715 which function as the bit line BL and the wiring BG are In FIG. 67, the conductor 714 and the conductor 715 are shown as different layers. The conductor 714 and the conductor 715 are connected to one The conductors 714 and 715 may be formed together as a single conductor. In this case, the conductor 71 is formed on the insulator 717 and fills the opening formed in the insulator 717. The conductive film 4 is formed, and unnecessary conductive film is removed by CMP or the like to form a conductive film. Then, the conductor 715 can be formed. The formation of the insulating film may be performed by lithography or by a damascene method. The insulator 713 is provided on the side of the opening formed in the insulator 717 and the conductor 705. Therefore, the conductor 715 electrically connected to the conductor 712 is electrically connected to the conductor 705. When the conductor 714 and the conductor 715 are formed together, the insulating A conductive film is formed on the insulating film 717 so as to fill the opening formed in the insulating film 717. The conductors are processed using a lithography method to form conductors 714 and 715. It is possible.

[0457] By the above steps, a memory cell array can be manufactured. The memory cell array consists of four layers of memory transistors MT and four memory strings. It may include, but is not limited to, five or more layers of memory transistors MT. For example, the memory transistors MT may be arranged as follows: It is possible to manufacture memory cell arrays with 32 layers, 64 layers, and 128 layers. It is possible to fabricate a memory cell array having 0 or more layers of memory transistors MT.

[0458] By fabricating a memory cell array in this manner, memory transistors can be formed in each layer. Multiple layers of memory transistors MT can be fabricated without patterning to fabricate MT. Furthermore, when a memory cell array is fabricated by the above method, Even if the number of layers of the memory transistor MT is increased, the pattern formation of the memory transistor MT In this way, the number of steps for the memory cell array fabrication is reduced. Since the time required for the manufacturing can be shortened, a semiconductor device with high productivity can be provided.

[0459] The configuration example of the 3D NAND in this embodiment is the same as that of the 3D NAND described in the first embodiment. You can refer to the configuration example of D.

[0460] The circuit operations (erase operation, write operation, and read operation) of the memory device in this embodiment For the description of the circuit operation of the memory device described in Embodiment 1, refer to the description of the circuit operation of the memory device described in Embodiment 1. do.

[0461] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0462] (Embodiment 3) This embodiment mode will describe an application example of a memory device using the semiconductor device described in the above embodiment. The semiconductor device described in the above embodiment can be used in various electronic devices (for example, Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video playback devices, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (for example, D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 68 shows some examples of the configuration of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a flash memory and used in various storage devices and removable memory.

[0463] 68(A) is a schematic diagram of a USB memory. The USB memory 1100 is 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, controller chip 1106 is attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 105 or the like.

[0464] Figure 68(B) is a schematic diagram of the external appearance of an SD card, and Figure 68(C) is a schematic diagram of the internal structure of an SD card. The SD card 1110 is a schematic diagram of the structure. The SD card 1110 comprises a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, the SD card 1110 The capacity can be increased. In addition, a wireless chip having a wireless communication function can be installed on the substrate 1113. This allows the host device and the SD card 1110 to communicate wirelessly. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0465] Figure 68(D) is a schematic diagram of the external appearance of the SSD, and Figure 68(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a memory The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DRAM chip may be used. A memory chip 1154 is also provided on the back side of the substrate 1153. By providing the memory chip 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0466] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0467] (Fourth embodiment) In this embodiment mode, a semiconductor device according to the above embodiment mode is applied to a semiconductor device A. I will explain the system.

[0468] FIG. 69 is a block diagram showing an example of the configuration of the AI ​​system 4041. 1 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.

[0469] The calculation unit 4010 includes an analog calculation circuit 4011, a DOSRAM 4012, and a NOSR. It has AM4013, FPGA4014, and 3D-NAND4015.

[0470] Here, DOSRAM (registered trademark) is a trademark of Dynamic Oxide Semiconductor It is an abbreviation for "Inductor RAM" and is a 1T (transistor) 1C (capacitance) type memory. Refers to RAM with a resettable register.

[0471] NOSRAM (registered trademark) stands for "Nonvolatile Oxide Semiconductor It is an abbreviation for "Semiconductor RAM" and is a memory of the gain cell type (2T type, 3T type). DOSRAM and NOSRAM are RAMs that use oxide as a semiconductor. A memory device utilizing the low off-state current of an OS transistor (hereinafter referred to as an OS transistor) In the following, we will refer to memory using OS transistors such as NOSRAM. The device may be referred to as OS memory.

[0472] The control unit 4020 includes a CPU (Central Processing Unit) 40 21, GPU (Graphics Processing Unit) 4022, and P LL (Phase Locked Loop) 4023 and SRAM (Static R andom Access Memory) 4024 and PROM (Programma ble Read Only Memory) 4025 and memory controller 4026 , a power supply circuit 4027, and a PMU (Power Management Unit) 40 28 and has.

[0473] The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, and a video a codec 4033, a general-purpose input / output module 4034, and a communication module 4035; It has.

[0474] The calculation unit 4010 can perform learning or inference using a neural network. Cut.

[0475] The analog arithmetic circuit 4011 is an A / D (analog / digital) conversion circuit, a D / A (digital It has a digital / analog conversion circuit and a multiply-and-accumulate circuit.

[0476] The analog arithmetic circuit 4011 is preferably formed using an OS transistor. The analog arithmetic circuit 4011 using a transistor has an analog memory and performs learning or This makes it possible to perform the multiply-and-accumulate operations required for inference with low power consumption.

[0477] The DOSRAM4012 is a DRAM formed using OS transistors. The SRAM4012 temporarily stores digital data sent from the CPU4021. The DOSRAM4012 is a memory that uses memory cells that include OS transistors and Si The memory cell and the readout circuit section are stacked. Since the DOSRAM4012 can be placed on different layers, the total circuit area can be reduced It can be made smaller.

[0478] Calculations using neural networks can involve more than 1,000 pieces of input data. When storing the above input data in SRAM, the SRAM has a limited circuit area and memory capacity. Since the size of the memory is small, the input data must be divided into smaller pieces and stored. 2 allows memory cells to be highly integrated even in a limited circuit area, and SRA The memory capacity is larger than that of the M. Therefore, the DOSRAM4012 can efficiently store the above input data. It can be stored efficiently.

[0479] NOSRAM4013 is a non-volatile memory that uses OS transistors. The M4013 is a memory card that can be used with flash memory and ReRAM (Resistive Random Access Memory). Access Memory), MRAM (Magnetoresistive Ran Compared to other non-volatile memories such as DDR Memory (DDR3), writing data is It consumes less power when writing data. The elements do not deteriorate when writing, and there is no limit to the number of times data can be written.

[0480] In addition to 1-bit binary data, the NOSRAM4013 can also handle multi-level data of 2 or more bits. NOSRAM4013 can store multi-value data. The memory cell area per bit can be reduced.

[0481] In addition, NOSRAM4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 converts the NOSRAM 4013 into an analog memory. The NOSRAM4013 can also be used as a memory. Therefore, D / A conversion circuits and A / D conversion circuits are not required. The RAM 4013 can reduce the area of ​​the peripheral circuits. Analog data refers to data with a resolution of 3 bits (8 values) or more. Multi-valued data may also be included in analog data.

[0482] The data and parameters used in the neural network calculations are stored in NOSRA. The above data and parameters can be stored in the M4013 via the CPU4021. The data may be stored in a memory provided outside the AI ​​system 4041, but may also be stored in a memory provided inside the AI ​​system 4041. The NOSRAM4013, which is equipped with the DDR3 RAM, stores the above data and parameters at higher speeds and with lower power consumption. The NOSRAM4013 also has a higher bit rate than the DOSRAM4012. Since the bit lines can be made longer, the storage capacity can be increased.

[0483] The FPGA 4014 is an FPGA that uses OS transistors. 1 uses FPGA4014 to implement the deep neural network described below in hardware. Neural Networks (DNN), Convolutional Neural Networks (CNN), Recurrent Neural Networks (RNN) Neural Networks (RNN), Autoencoders, Deep Boltzmann Machines (DBM), Deep It is possible to configure the connections of neural networks, such as layered belief networks (DBNs). By configuring the above neural network connections in hardware, it is possible to achieve higher performance. It can be executed quickly.

[0484] The FPGA 4014 is an FPGA with OS transistors. The memory area can be made smaller than that of an FPGA that is configured with RAM. Even if a context switching function is added, the area increase is small. Sting allows data and parameters to be transmitted at high speed.

[0485] 3D-NAND4015 is a non-volatile memory that uses oxide semiconductors. The D4015 is a highly integrated memory with a large storage capacity per unit area.

[0486] In addition to 1-bit binary data, 3D-NAND4015 can also handle multi-value data of 2 or more bits. 3D-NAND4015 can store multi-level data. Therefore, the memory cell area per bit can be further reduced.

[0487] In addition, as the 3D-NAND 4015, for example, the semiconductor device shown in the above embodiment is used. This allows the area occupied by the memory cell to be reduced. Therefore, the 3D-NAND4015 can be further integrated. The storage capacity per unit area of ​​the ND4015 can be increased.

[0488] The AI ​​system 4041 is composed of an analog arithmetic circuit 4011, a DOSRAM 4012, and an NOS The RAM4013 and FPGA4014 can be mounted on a single die (chip). Therefore, the AI ​​system 4041 is designed to be fast and low power consumption, and to use neural networks. In addition, the analog arithmetic circuit 4011 and the DOSRAM4 The 012, NOSRAM4013, and FPGA4014 are manufactured using the same manufacturing process. Therefore, the AI ​​system 4041 can be manufactured at low cost. .

[0489] The calculation unit 4010 includes a DOSRAM 4012, a NOSRAM 4013, and an FP It is not necessary to have all of GA4014. Depending on the problem that AI system 4041 wants to solve, DOSRAM4012, NOSRAM4013, and FPGA4014. A plurality of the above may be selected and provided.

[0490] AI System 4041 uses deep neural networks to solve various problems. (DNN), Convolutional Neural Network (CNN), Recurrent Neural Network RNN, autoencoder, deep Boltzmann machine (DBM), deep belief network The PROM4025 can implement techniques such as DBN. It is possible to store a program for executing at least one program. Store some or all of the program in NOSRAM4013 or 3D-NAND4015. 3D-NAND4015 is a highly integrated memory, and the number of records per unit area is The large memory capacity allows for the storage of large programs.

[0491] Existing programs that exist as libraries are based on GPU processing. Therefore, it is preferable that the AI ​​system 4041 has a GPU 4022. The system 4041 performs the multiply-and-accumulate operation, which is the rate-limiting operation used in learning and inference. The multiplication and accumulation operations can be executed by the calculation unit 4010, and other multiplication and accumulation operations can be executed by the GPU 4022. This allows for faster learning and inference.

[0492] The power supply circuit 4027 not only generates a low power supply potential for the logic circuit but also The power supply circuit 4027 may also use an OS memory. 27 can reduce power consumption by storing the reference potential in the OS memory.

[0493] PMU4028 has the function of temporarily turning off the power supply to AI System 4041. do.

[0494] The CPU 4021 and the GPU 4022 preferably have OS memory as a register. The CPU 4021 and the GPU 4022 have OS memory, so the power supply is Even when the power is turned off, the data (logical values) can still be stored in the OS memory. As a result, the AI ​​system 4041 can save power.

[0495] The PLL 4023 has the function of generating a clock. It operates based on the clock generated by PLL4023. PLL4023 has OS memory. The PLL4023 has an OS memory, which allows it to adjust the clock oscillation period. It is possible to hold a controlling analog potential.

[0496] The AI ​​system 4041 may store data in external memory such as DRAM. Therefore, the AI ​​System 4041 uses memory that acts as an interface with external DRAM. It is preferable that the memory controller 4026 is included. It is preferable to place it near the CPU 4021 or the GPU 4022. This allows for high-speed data exchange.

[0497] Some or all of the circuits shown in the control unit 4020 are formed on the same die as the operation unit 4010. By doing so, the AI ​​system 4041 can achieve high speed and low power consumption. Neural network calculations can be performed.

[0498] The data used for neural network calculations is stored in an external storage device (HDD). Hard Disk Drive, SSD (Solid State Drive), etc.) Therefore, the AI ​​system 4041 does not have an interface with an external storage device. It is preferable that the external memory control circuit 4031 functions as an interface.

[0499] Learning and inference using neural networks often involves audio and video, so The I system 4041 has an audio codec 4032 and a video codec 4033 . The audio codec 4032 encodes and decodes audio data. The video codec 4033 encodes and decodes the video data.

[0500] The AI ​​system 4041 performs learning or inference using data obtained from external sensors. Therefore, the AI ​​system 4041 has a general-purpose input / output module 4034. The general-purpose input / output module 4034 is, for example, a USB (Universal Ser ial Bus) and I2C (Inter-Integrated Circuit), etc. Includes:

[0501] AI system 4041 uses data obtained via the internet to learn or Therefore, the AI ​​system 4041 can perform inference. It is preferred to have 5.

[0502] The analog arithmetic circuit 4011 uses a multi-level flash memory as an analog memory. However, flash memory has a limit to the number of times it can be rewritten. Flash memory is embedded (the arithmetic circuit and memory are formed on the same die). It is very difficult to

[0503] The analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limit on the number of rewritable times and also has problems in terms of memory accuracy. Furthermore, since it is an element with two terminals, the circuit design for separating data writing and reading becomes complex.

[0504] Also, the analog arithmetic circuit 4011 may use MRAM as an analog memory. However, MRAM has a low resistance change rate and has problems in terms of memory accuracy.

[0505] In view of the above, it is preferable that the analog arithmetic circuit 4011 uses the OS memory as an analog memory. That is preferable.

[0506] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments. That can be done.

[0507] (Embodiment 5) <Application Examples of AI System> ​​​​​​​​​​​​​​​​​​​​​​AI systems are arranged in parallel, enabling signals to be sent and received between systems via a network. The stem is 4041B.

[0511] The AI ​​system 4041B shown in FIG. 70(B) is a system including a plurality of AI systems 4041_1 The AI ​​systems 4041_1 to 4041_n are 041_n are connected to each other via a network 4099.

[0512] The network 4099 is a network of the AI ​​systems 4041_1 to 4041_n. Each of them may be provided with a communication module, and configured to perform wireless or wired communication. The communication module can communicate via an antenna. For example, World Wi The Internet, intranets, and extranets that form the foundation of the World Wide Web (WWW) PAN (Personal Area Network), LAN (Local A rea Network), CAN (Campus Area Network), MA N (Metropolitan Area Network), WAN (Wide Ar Network), GAN (Global Area Network), etc. It is possible to connect each electronic device to a computer network and communicate with it. In this case, LTE (Long Term Evolution) is used as the communication protocol or technology. tion), GSM (Global System for Mobile Commu) nication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Divisio n Multiple Access 2000), W-CDMA (registered trademark), etc. Communication standards, such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBe IEEE communication standard specifications such as IEEE e (registered trademark) can be used.

[0513] By using the configuration shown in Figure 70(A) and (B), analog signals obtained from external sensors, etc. It can be processed by separate AI systems. For example, biometric information such as brain waves, pulse, Information such as blood pressure and body temperature is transmitted via a brain wave sensor, pulse wave sensor, blood pressure sensor, and temperature sensor. It is possible to acquire data from various sensors and process the analog signals with separate AI systems. Each AI system processes signals or learns, creating a single AI system. Therefore, the amount of information processing required for signal processing or learning can be reduced. As a result, recognition accuracy can be improved. The system can instantly and comprehensively grasp complex changes in biological information. It is expected that this will be possible.

[0514] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0515] (Sixth embodiment) This embodiment shows an example of an IC in which the AI ​​system shown in the above embodiment is incorporated. .

[0516] The AI ​​system shown in the above embodiment is a digital processor such as a CPU, which is made up of Si transistors. logic circuits, analog arithmetic circuits using OS transistors, 3D-NAND, OS-FPG A and OS memory such as DOSRAM and NOSRAM can be integrated on a single die. do.

[0517] Figure 71 shows an example of an IC incorporating an AI system. The IC7000 has leads 7001 and a circuit section 7003. For example, the IC chip is mounted on a printed circuit board 7002. These are electrically connected to each other on the printed circuit board 7002, and electronic components are mounted on them. The circuit portion 7003 has the same structure as that shown in the above embodiment mode. The circuit section 7003 is similar to the circuit section 7001 shown in the previous embodiment. As shown, it has a stacked structure, and is made up of a Si transistor layer 7031, a wiring layer 7032, an OS transistor, The OS transistor layer 7033 is divided into a Si transistor layer 7031 and a Since the ICs can be stacked on top of each other, it is easy to miniaturize the AI ​​system IC7000.

[0518] In Figure 71, the AI ​​system IC7000 is packaged in a QFP (Quad Flat Packaging) However, the form of the package is not limited to this.

[0519] Digital processing circuits such as CPUs and analog arithmetic circuits using OS transistors, 3D- NAND, OS-FPGA and OS memories such as DOSRAM and NOSRAM are all Formed in a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033 In other words, the elements constituting the AI ​​system can be manufactured using the same manufacturing process. Therefore, the IC shown in this embodiment mode can be formed by increasing the number of constituent elements. Even if it is added, there is no need to increase the manufacturing process, and the AI ​​system can be incorporated at low cost. can.

[0520] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0521] (Embodiment 7) <Electronic equipment> The semiconductor device according to one embodiment of the present invention can be used in various electronic devices. 73A and 73B illustrate specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention.

[0522] The robot 2000 shown in FIG. 72(A) includes a computing device 2001, a sensor 2002, a light 2003, a lift 2004, a drive unit 2005, and a moving mechanism 2011. These robots can be used in security systems and surveillance equipment. It can be used as a visual system.

[0523] The robot 2000 further includes a communication means 2006, a speaker 2007, a microphone 2008, a display unit 2009, a light emitting unit 2010, etc.

[0524] The semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 2001. The arithmetic unit 2001 uses an IC incorporating an AI system according to one embodiment of the present invention. The sensor 2002 acts as a camera that captures the surroundings of the robot 2000. The light 2003 captures the surroundings of the robot 2000 using the sensor 2002. It can be used as a light when taking a still image with the sensor 2002. Preferably, the light 2003 functions as a flashlight. 2002 is connected to the robot body via a lift 2004. The height can be adjusted by the lift 2004. The lift 2004 is telescopic. The lift 2004 is preferably a foldable type consisting of multiple booms. The robot 2000 may also include a driving unit 2005 and a Since the moving mechanism 2011 is provided, the imaging range of the sensor 2002, i.e. This is preferable as it broadens the monitoring range.

[0525] The communication means 2006 communicates the information captured by the sensor 2002 to the administrator or the person in charge of the information. The information captured by the sensor 2002 can be transmitted to a server that performs calculations. If the device 2001 analyzes the data and determines that it is an emergency such as a crime, accident, or fire, the security committee You can contact the company, police, fire department, medical institution, land or building owner. Speaker 2 007 will be using robots to warn criminals, question injured or suddenly ill people, and guide them to safety. The microphone 2008 can transmit information to the surroundings of the robot 2000. The communication means 2006 and the speaker 2007 can be used to acquire the voice. When used in combination with the above, the robot 2000 can function as a telephone. People around the robot 2000 can converse with the administrator or any other person. 2009 can display any information. In case of an emergency, disaster information and evacuation routes can be displayed. In addition, the communication means 2006, the speaker 2007, and the microphone 2008 can be displayed. When used in conjunction with Phone 2008, Robot 2000 can function as a videophone. The people around the robot 2000 can communicate with the administrator or any other person on the display unit 20 You can have a conversation while looking at 09.

[0526] The light emitting unit 2010 can indicate the direction of travel and the stopped state of the robot 2000 with letters and light. It may also indicate an emergency.

[0527] Figure 72(B) is a block diagram showing the configuration of the robot 2000. Based on information such as images obtained by the sensor 2002, the system determines whether the light 2003 is turned on or off, The brightness can be adjusted. Also, the height of the lift 2004 or the drive unit 2005 can be adjusted. It controls the robot 2000 and the sensor 2002 and aligns them. The operating status of the communication means 200 can be displayed using the light emitting unit 2010. 6, the robot 2000's information obtained from the sensor 2002 and the microphone 2008 is It can send information about the surroundings to the administrator or a server owned by the administrator. The computer 2001, or at the discretion of the administrator, may use the speaker 2007 or the display unit 2009. The robot 2000 can transmit information to the surrounding area.

[0528] When a sensor capable of capturing an image even in a dark environment is used as the sensor 2002, the light 2 003 may not be provided. As such a sensor, selenium (Se) is used in the light receiving part. An image sensor can be used.

[0529] Such a robot 2000 can be used to guard commercial facilities and offices. The information obtained from the sensor 2002 and the microphone 2008 is transmitted to the computing device 2001 and the server. The stored information is analyzed by an AI system to detect lost or damaged items, It determines whether there are any abnormalities such as the intrusion of suspicious individuals or disasters such as fires. If it is determined that an abnormality has occurred, the robot 2000 Contact the person in question and send information to those around them, and record the situation in the surrounding area.

[0530] The robot 2000 may also be used to monitor the growth status of agricultural crops. The placed robot 2000 detects the shape and size of the leaves or fruit of the crops using a sensor 2002. It monitors the size and color of the plants to determine whether they are diseased or infested with pests. Robot 2 000 is equipped with a mobile mechanism 2011, allowing it to monitor the growth of crops over a wide area. In addition, the robot 2000 is provided with a lift 2004. It is possible to monitor leaves and fruits at any height, regardless of the type of crop or growth status. The results of the observation are sent to the producers using the communication means 2006, and the producers then purchase the necessary fertilizers and other necessary ingredients for their crops. The type, amount, and spraying time of pesticides can be determined. The monitoring results are analyzed by an AI system to determine the type, amount, and application of fertilizer and pesticides required for the crops. The system can determine the timing and notify producers. Deep learning is used to analyze the monitoring results. It may be used.

[0531] FIG. 73(A) shows a sorting system 3000 using a robot 3001. The robot 3001 includes a computing device 3002, a boom 3003, and an arm 3004. The robot 3001 may also be equipped with wired or wireless communication means 3011. Sorting system 3000 also includes a housing 3008 having a sensor 3009 . The housing 3008 includes a communication means 3010. The housing 3008 is a 00, or on the ceiling, wall, or beams (none of which are shown) of the sorting work area. The housing 3008 may be provided on the robot 3001. For example, the boom 3003 Alternatively, the housing 3008 may be provided on the arm 3004. If the sensor 3009 is connected to the communication means 3010, the information obtained by the sensor 3009 is transmitted to the communication means 3010, and The data may be sent to the arithmetic device 3002 and processed therein without going through the communication means 3011.

[0532] The boom 3003 is movable, and the arm 3004 can be positioned at a desired position. The arm 3004 may be extendable. The arm 3004 is extended, a desired item 3007 is grasped, and the arm 3004 is retracted. The boom 3003 may move the arm 3004 .

[0533] Sorting system 3000 moves item 3007 in container 3005 to container 3006. The container 3005 and the container 3006 may have the same shape or different shapes. In addition, multiple items 3007 placed in one container 3005 can be stored in multiple containers 3006. You can also move them by dividing them into

[0534] The containers 3005 and 3006 include containers, cardboard boxes, and boxes for packing products. , cases, films, bags, food storage trays, lunch boxes, etc. At least one of the containers 3005 and 3006 is a cooking utensil such as a pot or a frying pan. That's fine too.

[0535] The semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 3002. The arithmetic device 3002 uses an IC incorporating an AI system according to one embodiment of the present invention. It is possible.

[0536] The sensor 3009 detects the position and number of the containers 3005, the position and number of the containers 3006, and the number of the containers 3007. 3005 and the state of the item 3007 in the container 3005, and The information is transmitted to the arithmetic device 3002 via wireless or wired communication. The information may be transmitted by wire without using the communication means 3010. The transmitted information is analyzed. Here, the state of the item 3007 is the shape, number, and the same of the item 3007. The calculation device 3002 calculates the value of the shi based on the information from the sensor 3009. The analysis is performed to derive detailed information about the item 3007. By comparing it with the data stored on a server that can communicate with 001, the three-dimensional shape of the item 3007, Also, the hardness (softness) of the object 3007 is calculated from the three-dimensional shape and hardness (softness) of the object 3007. The shape of the arm 3004 can be changed depending on the shape and size of the article 3007. The location of the container 3006 may be changed as needed for sorting, or multiple different containers 30 may be used. You can also place it in 06 and sort it.

[0537] To derive detailed information about item 3007, analysis using an AI system can be used. Yes, deep learning can be used to analyze the information.

[0538] In FIG. 73(B), a pair of plates 3021 move horizontally and can hold an article 3007. The pair of plates 3021 move horizontally toward the center, allowing the item to be picked up. Such an arm can grasp the article 3007 by its surface. It is suitable for grasping a columnar object 3007 such as a cube or rectangular parallelepiped. (C) is an aerial photograph in which multiple bars 3022 move horizontally and can clamp an article 3007. The bars 3022 move horizontally toward the center, and the article 30 Such an arm can grasp the article 3007 at a point. The object 3007 has a spherical shape, or the object 3007 has an irregular shape, i.e., an irregular shape. It is suitable for grasping a regular object 3007. In FIG. 73(C), the number of bars 3022 However, the present embodiment is not limited to this. The number of bars 3022 may be three or five. FIG. 73(D) shows a pair of plates 3023 approaching each other around a common axis. By rotating like this, the arm can hold the article 3007. The camera can capture the object 3007 on its surface, and can capture thin-film-like objects such as paper and film. FIG. 73(E) shows a pair of hook-shaped plates 3024. By rotating the two around the axis so that their tips approach each other, the article 3007 can be clamped. Such an arm can capture the item 3007 as a point or a line. It can be used for thin film-like articles 3007 such as paper and film, or for smaller granular articles 3008. As shown in Figure 73(F), the tip of the arm A spatula 3025 may be attached to the .

[0539] The arms shown in Figures 73(A) to 73(F) are examples, and one aspect of the present invention is to The description of the uses of each arm is also an example, and one aspect of the present invention is not limited to these. This is not limited to the description.

[0540] The robot 3001 moves the boom 3003 based on a signal from the computing device 3002. The arm 3004 is moved onto the desired item 3007 in the container 3005. In the case of the arm 3004, the arm 3004 is extended and the tip of the arm 3004 is placed at the height of the article 3007. The tip of the arm is moved to grab the desired item 3007. The boom 3003 is moved again, and the arm 3004 is moved toward the container 300. At this time, the angle of the article 3007 relative to the container 3006 is adjusted. The arm 3004 may be rotated to accommodate the item 3007. The object 3007 is placed in the container 3006, and the arm 3004 releases the object 3007. The above operations are repeated. The robot 3001 moves the item 3007 from the container 3005 to the container 3006. This can be done.

[0541] The location information of the container 3005 and the container 3006, and the status of the item 3007 are sent to the AI ​​system. Since the analysis is performed using a system, the analysis can be performed reliably regardless of the shape or hardness of the object 3007. 7 can be moved. Examples of the object 3007 include a cube, a rectangular box, or or items packed in boxes or cases of any shape, as well as eggs, hamburgers, croquettes, etc. processed foods, irregular vegetables such as potatoes and tomatoes, screws and nails, etc. Examples of the materials include machine parts such as a mouse, thin films such as paper, and films. The sorting system 3000 changes the shape of the arm in consideration of the shape and hardness of the article 3007. Therefore, the above-mentioned example article 3007 can be stored in the container 3005 regardless of its shape or hardness. can be transferred from the container 3006.

[0542] For example, a memory device using the semiconductor device of one embodiment of the present invention can be used for the control information of the above-described electronic devices. The semiconductor device according to one aspect of the present invention can store information, control programs, and the like for a long period of time. By using the device, highly reliable electronic equipment can be realized.

[0543] In addition, for example, the AI ​​system is incorporated into the arithmetic unit of the electronic device. Therefore, the electronic device described in this embodiment can be implemented as an AI system. This allows for appropriate operation according to the situation to be performed with low power consumption.

[0544] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiment modes. It is Noh. [Explanation of symbols]

[0545] 100 storage device 105 Control circuit 110 memory cell array 112 Memory String 121 Line Decoder 122-line driver 123 Sense Amplifier 124 Source Line Driver 125 Input / Output Circuit 300 circuits 301 Transistor 302 Transistor 303 Transistor 304 Sense Amplifier 311 Substrate 313 Semiconductors 314a Low resistance area 314b Low resistance region 315 Insulator 316 Conductors 317 Insulators 318 Insulator 320 Insulator 322 Insulator 324 Insulators 326 Insulator 327 Insulators 328 Conductors 329 Conductors 330 Conductors 350 Insulator 352 Insulator 354 Insulators 356 Conductors 360 Insulator 362 Insulators 364 Insulators 366 Conductors 700 memory cell array 700A memory cell array 701 Conductors 701a Conductor 701A Conductive film 701b Electric conductor 701B Conductive film 701c Conductor 702 Conductors 702A Conductive film 702B Conductive Film 703 Insulators 703a Insulator 703A Insulating film 703b Insulator 703c Insulator 704 Oxides 704a Oxide 704A oxide film 704b oxide 704c...

Claims

[Claim 1] a first insulator having a first opening; a first conductor on the first insulator, the first conductor having a second opening; a second insulator having a third opening on the first conductor; an oxide provided so as to pass through the first opening, the second opening, and the third opening; and the oxide has a first region in the first opening, a second region in the second opening, and a third region in the third opening; The semiconductor device is characterized in that the first region and the third region have a lower resistance than the second region.

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