Semiconductor device and method of manufacturing the same

Abstract

To improve the reliability of a semiconductor device.SOLUTION: A position of an upper surface of a lead-out portion GE1b of a gate electrode GE1 is higher than a position of an upper surface of an active portion GE1a of the gate electrode GE1. An insulating film IF3 has a raised portion IFc positioned on a side surface of the active portion GE1a via a sidewall spacer SW and a raised portion IFf positioned on a side surface of the lead-out portion GE1b via the sidewall spacer SW. An active portion FPa of a field plate electrode FP is in contact with the raised portion IFc, and a position of an uppermost portion of a lead-out portion FPb of the field plate electrode FP is lower than a position of an uppermost portion of the insulating film IF3 positioned over the upper surface of the lead-out portion GE1b.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a laterally diffused metal oxide semiconductor (LDMOS) as a type of metal insulator semiconductor field effect transistor (MISFET). The LDMOS has a lightly doped drift region disposed between a heavily doped drain region and a gate electrode.

[0003] In a semiconductor device with multiple LDMOSs, the LDMOSs are arranged symmetrically with respect to the drain and source regions, and adjacent LDMOSs share the same drain or source region. A drift region with an impurity concentration lower than that of the drain region is formed between the semiconductor substrate located below the end of the gate electrode and the drain region.

[0004] In addition, a field plate electrode is formed from above the drift region to the top surface of the gate electrode. Because the electric field tends to concentrate near the edge of the gate electrode, the application of the field plate electrode alleviates the electric field near the edge of the gate electrode, thereby improving the breakdown voltage of the LDMOS. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-50048 Summary of the Invention [Problem to be solved by the invention]

[0006] When a field plate electrode is used, the field plate electrode is formed on the semiconductor substrate so as to cover the upper surface of the gate electrode. A semiconductor device includes other MISFETs in addition to the LDMOS, and the thickness of the field plate electrode tends to make the height of the LDMOS larger than the height of the other MISFETs. Therefore, the thickness of the interlayer insulating film formed on the LDMOS tends to be smaller than the thickness of the interlayer insulating film formed on the other MISFETs.

[0007] If there is a specific location where the thickness of the interlayer insulating film is partially reduced, there is a risk of unexpected defects occurring in subsequent manufacturing processes. For example, if the interlayer insulating film includes a lower layer film and an upper layer film made of a different material from the lower layer film, the lower layer film may be exposed at the specific location without being covered by the upper layer film. In this case, since the material of the interlayer insulating film at the specific location is different from the material of the interlayer insulating film at other locations, even if the same manufacturing process is subsequently performed, unexpected defects are likely to occur at the specific location, and the reliability of the semiconductor device may be reduced.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface and a lower surface, an isolation region formed in the semiconductor substrate, a gate insulating film formed on the upper surface of the semiconductor substrate, a gate electrode formed on the gate insulating film and on the upper surface of the isolation region, sidewall spacers formed on side surfaces of the gate electrode, a first insulating film formed on the upper surface of the semiconductor substrate and on the upper surface of the isolation region so as to cover the upper surface of the gate electrode and the sidewall spacers, and a field plate electrode formed on the first insulating film. The gate electrode has a first location located on the upper surface of the semiconductor substrate and a second location located on the upper surface of the isolation region. The first insulating film has a third location located on the upper surface of the semiconductor substrate, a fourth location located above the third location and on the side surface of the first location of the gate electrode with the sidewall spacer interposed therebetween, a fifth location located on the upper surface of the isolation region, and a sixth location located above the fifth location and on the side surface of the second location of the gate electrode with the sidewall spacer interposed therebetween. The field plate electrode has a seventh location located on the top surface of the semiconductor substrate and an eighth location located on the top surface of the element isolation portion. The top surface of the second location of the gate electrode is higher than the top surface of the first location of the gate electrode. The seventh location of the field plate electrode contacts the fourth location of the first insulating film, and the top of the eighth location of the field plate electrode is lower than the top of the first insulating film located on the top surface of the second location of the gate electrode.

[0010] In one embodiment, a method for manufacturing a semiconductor device includes the steps of: (a) preparing a semiconductor substrate having an upper surface and a lower surface; (b) forming an isolation region in the semiconductor substrate to a predetermined depth from the upper surface of the semiconductor substrate; (c) forming a gate insulating film on the upper surface of the semiconductor substrate; (d) forming a gate electrode on the gate insulating film and on the upper surface of the isolation region; (e) forming sidewall spacers on side surfaces of the gate electrode; (f) forming a first insulating film on the upper surface of the semiconductor substrate and on the upper surface of the isolation region so as to cover the upper surface of the gate electrode and the sidewall spacers; and (g) forming a field plate electrode on the first insulating film. The gate electrode has a first location located on the upper surface of the semiconductor substrate and a second location located on the upper surface of the isolation region. The first insulating film has a third location located on the top surface of the semiconductor substrate, a fourth location located above the third location and on the side surface of the first location of the gate electrode via the sidewall spacer, a fifth location located on the top surface of the element isolation portion, and a sixth location located above the fifth location and on the side surface of the second location of the gate electrode via the sidewall spacer. The field plate electrode has a seventh location located on the top surface of the semiconductor substrate and an eighth location located on the top surface of the element isolation portion. The top surface of the second location of the gate electrode is higher than the top surface of the first location of the gate electrode. The seventh location of the field plate electrode is in contact with the fourth location of the first insulating film, and the topmost location of the eighth location of the field plate electrode is lower than the topmost location of the first insulating film located on the top surface of the second location of the gate electrode. [Effects of the Invention]

[0011] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0012] [Figure 1]FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is an enlarged cross-sectional view of a main part of FIG. [Figure 4] FIG. 4 is a cross-sectional view showing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] 6A to 6C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 7] 7A to 7C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 8] 8A to 8C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 9] FIG. 9 is a cross-sectional view showing a manufacturing process of the semiconductor device subsequent to FIG. [Figure 10] FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 11] FIG. 11 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 12] 12A to 12C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to that shown in FIG. [Figure 13] 13A to 13C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 14] 14A to 14C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 15] 15A to 15C are cross-sectional views showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 16] 16 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 17] FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. [Figure 18] FIG. 18 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 19] FIG. 19 is a plan view showing a semiconductor device according to the third embodiment. [Figure 20] FIG. 20 is a cross-sectional view showing a semiconductor device according to the third embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the third embodiment. [Figure 22] FIG. 22 is a plan view showing a semiconductor device according to the fourth embodiment. [Figure 23] FIG. 23 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the fourth embodiment. [Figure 25] FIG. 25 is a plan view showing a semiconductor device in the study example. [Figure 26] FIG. 26 is a cross-sectional view showing a semiconductor device in the study example. [Figure 27] FIG. 27 is a cross-sectional view for explaining the problem in the study example. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0014] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, depth, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that a surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0015] (Embodiment 1) <Structure of semiconductor device> A semiconductor device according to a first embodiment will be described below with reference to FIGS. 1 to 4. The semiconductor device includes a plurality of n-type MISFETs 1Q and MISFETs 2Q. FIG. 1 is a plan view showing two MISFETs 1Q. FIG. 2 is a cross-sectional view of the two MISFETs 1Q taken along lines AA and BB shown in FIG. 1.

[0016] 1 and 2, each of the plurality of MISFETs 1Q includes a gate insulating film GI1, a gate electrode GE1, a p-type body region (impurity region) PB, a plurality of n-type source regions (impurity regions) NS, a p-type high-concentration diffusion region (impurity region) PR, a p-type well region (impurity region) HPW, an n-type drift region (impurity region) NLD, an n-type drain region (impurity region) ND, and a field plate electrode FP. Also, an element isolation portion STI is formed in the semiconductor substrate SUB.

[0017] The drain region ND extends in the Y direction. The multiple source regions NS are spaced apart in the Y direction. A high-concentration diffusion region PR is formed between each of the multiple source regions NS. The multiple MISFETs 1Q are arranged symmetrically with respect to the drain region ND and the source region NS. MISFETs 1Q adjacent to each other in the X direction share the drain region ND or the source region NS. The drain region ND is connected to a plug PG for supplying a drain potential. The source region NS and the high-concentration diffusion region PR are connected to a plug PG for supplying a source potential.

[0018] In a plan view, the gate electrode GE1 and the field plate electrode FP extend in the Y direction. The gate electrode GE1 has an active portion GE1a (cross section AA) located on the upper surface TS1 of the semiconductor substrate SUB and an extended portion GE1b (cross section BB) located on the upper surface TS2 of the element isolation portion STI. The field plate electrode FP has an active portion FPa (cross section AA) located on the upper surface TS1 of the semiconductor substrate SUB and an extended portion FPb (cross section BB) located on the upper surface TS2 of the element isolation portion STI.

[0019] In a plan view, the active portions GE1a and FPa are located between the drain region ND and the source region NS, and between the drain region ND and the heavily doped diffusion region PR. Of the gate electrode GE1 and the field plate electrode FP, the active portions GE1a and FPa contribute to the operation of the MISFET 1Q.

[0020] The lead-out portion GE1b connects the gate electrode GE1 to a plug PG for supplying a gate potential. The lead-out portion FPb connects the field plate electrode FP to a plug PG for supplying a potential. The field plate electrode FP is supplied with, for example, a source potential.

[0021] The well region HPW is formed between the drift region NLD and the element isolation portion STI in plan view. The well region HPW does not substantially contribute to the operation of the MISFET 1Q, and the boundary between the active portion FPa and the lead-out portion FPb is located on the well region HPW.

[0022] 2, the semiconductor substrate SUB has an upper surface TS1 and a lower surface BS1, and the element isolation portion STI has an upper surface TS2. The gate electrode GE1 and the field plate electrode FP are formed on the upper surface TS1 of the semiconductor substrate SUB and on the upper surface TS2 of the element isolation portion STI.

[0023] The semiconductor substrate SUB is made of p-type silicon. In the first embodiment, the semiconductor substrate SUB includes, for example, a support substrate SS and a semiconductor layer EP formed on the support substrate SS (see FIG. 5). The support substrate SS is, for example, a p-type silicon substrate. The semiconductor layer EP is, for example, a p-type silicon layer. In the following description, various impurity regions formed in the semiconductor substrate SUB may specifically be formed in the semiconductor layer EP. Note that the semiconductor substrate SUB may also be a single-layer silicon substrate.

[0024] An element isolation portion STI is formed in the semiconductor substrate SUB. The element isolation portion STI includes a trench formed in the semiconductor substrate SUB to reach a predetermined depth from an upper surface TS1 of the semiconductor substrate SUB, and an insulating film embedded in the trench. The insulating film is, for example, a silicon oxide film. In addition, as will be described in detail later with reference to FIG. 7, in the process of forming the element isolation portion STI, the position of an upper surface TS2 of the element isolation portion STI becomes higher than the position of an upper surface TS1 of the semiconductor substrate SUB.

[0025] An n-type drift region NLD, a p-type impurity region PLD, and an n-type buried region NBL are formed in the semiconductor substrate SUB. The drift region NLD is formed to a predetermined depth from the upper surface of the semiconductor substrate SUB and is located above the impurity region PLD and the buried region NBL. The impurity region PLD is located above the buried region NBL. The impurity region PLD and the buried region NBL are formed at positions deeper than the element isolation part STI.

[0026] Furthermore, a body region PB and a well region HPW are formed in the semiconductor substrate SUB. The body region PB and the well region HPW are formed to a predetermined depth from the upper surface of the semiconductor substrate SUB, and are formed to a position deeper than the element isolation part STI. The body region PB and the well region HPW are in contact with the impurity region PLD.

[0027] A source region NS is formed in the body region PB. As shown in FIG. 1, a heavily doped diffusion region PR is also formed in the body region PB. A drain region ND is formed in the drift region NLD. The drain region ND and the source region NS have higher impurity concentrations than the drift region NLD. The heavily doped diffusion region PR has a higher impurity concentration than the body region PB. A portion of the body region PB that is located between the source region NS and the drain region ND and below the gate electrode GE1 (below the active portion GE1a) functions as a channel region of the MISFET 1Q.

[0028] A gate insulating film GI1 is formed on an upper surface TS1 of the semiconductor substrate SUB. The gate insulating film GI1 is, for example, a silicon oxide film. As shown in the AA and BB cross sections, a gate electrode GE1 is formed on the gate insulating film GI1 and on an upper surface TS2 of the element isolation portion STI. The gate electrode GE1 is made of, for example, an n-type polycrystalline silicon film. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE1. The sidewall spacers SW include, for example, a silicon oxide film and a silicon nitride film formed on the silicon oxide film.

[0029] The insulating film IF1 covers at least a part of the upper surface of the active region GE1a, the sidewall spacers SW formed on the side surfaces of the active region GE1a, and a part of the upper surface TS1 of the semiconductor substrate SUB. In the first embodiment, the insulating film IF1 also covers a part of the upper surface of the leading region GE1b, the sidewall spacers SW formed on the side surfaces of the leading region GE1b, and a part of the upper surface TS2 of the element isolation portion STI. The insulating film IF1 is, for example, a silicon oxide film.

[0030] The silicide film SI is formed on the upper surface of the gate electrode GE1 exposed from the insulating film IF1, on the source region NS, on the drain region ND, and on the heavily doped diffusion region PR. The source region NS and the heavily doped diffusion region PR formed in the body region PB are electrically connected to each other by the same silicide film SI. The silicide film SI is, for example, a cobalt silicide (CoSi2) film, a nickel silicide (NiSi) film, or a nickel platinum silicide (NiPtSi) film.

[0031] An insulating film IF2 is formed on the upper surface TS1 of the semiconductor substrate SUB and on the upper surface TS2 of the element isolation part STI so as to cover the upper surface of the gate electrode GE1 and the sidewall spacer SW. The insulating film IF2 covers the upper surface of the gate electrode GE1 via the insulating film IF1 or the silicide film SI. The insulating film IF2 is, for example, a silicon nitride film. An insulating film IF3 is formed on the insulating film IF2. The insulating film IF3 is made of a material different from that of the insulating film IF2, for example, a silicon oxide film.

[0032] A field plate electrode FP is formed on the insulating film IF3. The field plate electrode FP is, for example, a tungsten silicide (WSi2) film. A main feature of the first embodiment is that the active portion FPa of the field plate electrode FP covers part of the upper surface of the active portion GE1a of the gate electrode GE1, but the leading portion FPb of the field plate electrode FP does not cover the upper surface of the leading portion GE1b of the gate electrode GE1. The reason for this will be explained in detail later.

[0033] The insulating film IF2 mainly serves to function as an etching stopper film when the hole CH is formed, and also serves to generate tensile stress in the channel region of the MISFET 1Q to increase the mobility of electrons.

[0034] The insulating film IF3 mainly serves to protect the insulating film IF2. If the insulating film IF3 is not formed, there is a risk that the insulating film IF2 will be removed by etching when the field plate electrode FP is formed by patterning. If the thickness of the insulating film IF2 changes and the magnitude of the tensile stress also changes, the characteristics of the MISFET 1Q may fluctuate. Therefore, the insulating film IF3 protects the insulating film IF2. However, if the fluctuation in the characteristics of the MISFET 1Q is within an allowable range, the insulating film IF3 does not need to be formed.

[0035] An interlayer insulating film IL0 is formed on the insulating film IF3 so as to cover the field plate electrode FP. An interlayer insulating film IL1 is formed on the interlayer insulating film IL0. The upper surface of the interlayer insulating film IL1 is flat.

[0036] The interlayer insulating film IL0 is, for example, a silicon oxide film doped with phosphorus (PSG: Phosphorus Silicate Glass) film or a silicon oxide film doped with boron and phosphorus (BPSG: Boro Phospho Silicate Glass) film. The interlayer insulating film IL1 is made of a different material from the interlayer insulating film IL0 and is, for example, a silicon oxide film.

[0037] A plurality of holes CH are formed in the interlayer insulating film IL1 and the interlayer insulating film IL0. A plug PG is formed inside each of the holes CH. The plug PG includes, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film includes, for example, a titanium film and a titanium nitride film, and the conductive film is, for example, a tungsten film.

[0038] Some of the holes CH reach the lead-out portion FPb of the field plate electrode FP. Of the holes CH, the holes CH that reach the lead-out portion GE1b of the gate electrode GE1, the silicide film SI formed on the upper surfaces of the source region NS, the drain region ND, and the heavily doped diffusion region PR penetrate the interlayer insulating film IL1, the interlayer insulating film IL0, the insulating film IF3, and the insulating film IF2.

[0039] FIG. 3 shows an enlarged view of the vicinity of the field plate electrode FP in FIG.

[0040] As shown in the AA cross section, the insulating films IF2 and IF3 have a flat portion IFa located on the upper surface TS1 of the semiconductor substrate SUB, a flat portion IFb located on the upper surface of the active portion GE1a of the gate electrode GE1, and a raised portion IFc connecting the flat portion IFa and the flat portion IFb.

[0041] The raised portion IFc extends from the upper surface TS1 of the semiconductor substrate SUB toward the upper surface of the active portion GE1a of the gate electrode GE1. The raised portion IFc is located above the flat portion IFa and on the side surface of the active portion GE1a of the gate electrode GE1 via the sidewall spacer SW and the insulating film IF1.

[0042] As shown in the BB cross section, the insulating films IF2 and IF3 have a flat portion IFd located on the upper surface TS2 of the element isolation portion STI, a flat portion IFe located on the upper surface of the lead-out portion GE1b of the gate electrode GE1, and a raised portion IFf connecting the flat portion IFd and the flat portion IFe.

[0043] The raised portion IFf extends from the upper surface TS2 of the element isolation part STI toward the upper surface of the lead-out portion GE1b of the gate electrode GE1. The raised portion IFf is located above the flat portion IFd and on the side surface of the lead-out portion GE1b of the gate electrode GE1 via the sidewall spacer SW and the insulating film IF1.

[0044] Note that, hereinafter, the relationship between the field plate electrode FP and the insulating film IF3 is described using the elevated portion IFc of the insulating film IF3 and the elevated portion IFf of the insulating film IF3. However, as described above, there are cases where the insulating film IF3 is not formed. In such cases, the description of the insulating film IF3, the elevated portion IFc of the insulating film IF3, and the elevated portion IFf of the insulating film IF3 can also be replaced with the description of the insulating film IF2, the elevated portion IFc of the insulating film IF2, and the elevated portion IFf of the insulating film IF2.

[0045] Electric field concentration is likely to occur near the end of the gate electrode GE1 facing the drain region ND, but by applying the field plate electrode FP, the electric field near the end of the gate electrode GE1 can be alleviated, thereby improving the breakdown voltage of the MISFET1Q.

[0046] Therefore, it is preferable that the active portion FPa of the field plate electrode FP be located as close to the end of the gate electrode GE1 as possible. The active portion FPa is in contact with the raised portion IFc, so that the function of the field plate electrode FP can be fully exhibited. Furthermore, in the first embodiment, the active portion FPa covers a part of the insulating film IF3 located on the upper surface of the active portion GE1a.

[0047] On the other hand, the lead-out portion FPb of the field plate electrode FP located on the element isolation portion STI is formed for the purpose of supplying a potential to the field plate electrode FP, and therefore the lead-out portion FPb may be spaced apart from the rising portion IFf. Furthermore, the lead-out portion FPb does not cover a portion of the insulating film IF3 located on the upper surface of the lead-out portion GE1b. In other words, the position of the top of the lead-out portion FPb is lower than the position of the top of the insulating film IF3 located on the upper surface of the lead-out portion GE1b.

[0048] 4 is a cross-sectional view showing MISFET 1Q and MISFET 2Q formed in a region different from the region in which MISFET 1Q is formed. MISFET 2Q can operate at a higher speed than MISFET 1Q and has a lower breakdown voltage than MISFET 1Q.

[0049] As shown in FIG. 4, the MISFET 2Q has a gate insulating film GI2, a gate electrode GE2, a p-type well region (impurity region) PW, an n-type extension region (impurity region) NEX, and an n-type high-concentration diffusion region (impurity region) NR.

[0050] A well region PW is formed in the semiconductor substrate SUB. The well region PW is formed to a predetermined depth from the upper surface of the semiconductor substrate SUB, and is formed to a position deeper than the element isolation parts STI.

[0051] An extension region NEX and a heavily doped diffusion region NR are formed in the well region PW. The heavily doped diffusion region NR has a higher impurity concentration than the extension region NEX. The heavily doped diffusion region NR and the extension region NEX constitute the source region or the drain region of the MISFET 2Q.

[0052] A gate insulating film GI2 is formed on an upper surface TS1 of the semiconductor substrate SUB. The gate insulating film GI2 is, for example, a silicon oxide film. A gate electrode GE2 is formed on the gate insulating film GI2. The gate electrode GE2 is, for example, made of an n-type polycrystalline silicon film. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE2. A silicide film SI is formed on the upper surfaces of the gate electrode GE2 and the heavily doped diffusion region NR.

[0053] An insulating film IF2 is formed on the upper surface TS1 of the semiconductor substrate SUB and on the upper surface TS2 of the element isolation part STI so as to cover the upper surface of the gate electrode GE2 and the sidewall spacer SW. The insulating film IF2 covers the upper surface of the gate electrode GE2 via the silicide film SI. An insulating film IF3 is formed on the insulating film IF2. An interlayer insulating film IL0 is formed on the insulating film IF3. An interlayer insulating film IL1 is formed on the interlayer insulating film IL0.

[0054] A plurality of holes CH are formed in the interlayer insulating film IL1 and the interlayer insulating film IL0. A plug PG is formed inside each of the plurality of holes CH. Of the plurality of holes CH, the hole CH that reaches the silicide film SI formed on the upper surface of the high-concentration diffusion region NR penetrates the interlayer insulating film IL1, the interlayer insulating film IL0, the insulating film IF3, and the insulating film IF2.

[0055] The thickness of the gate insulating film GI2 is smaller than the thickness of the gate insulating film GI1. Furthermore, the insulating film IF1 and the field plate electrode FP are not formed on the upper surface of the gate electrode GE2. Therefore, the height of MISFET2Q is smaller than the height of MISFET1Q. In other words, the total thickness of the interlayer insulating film IL1 and the interlayer insulating film IL0 formed on the upper surface of the gate electrode GE2 is greater than the total thickness of the interlayer insulating film IL1 and the interlayer insulating film IL0 formed on the field plate electrode FP covering the upper surface of the gate electrode GE1.

[0056] <Method of manufacturing a semiconductor device> Each manufacturing step included in the method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS.

[0057] As shown in Figure 5, a semiconductor substrate SUB is prepared. The semiconductor substrate SUB may be a single-layer p-type silicon substrate, but in the first embodiment, the semiconductor substrate SUB includes a support substrate SS and a semiconductor layer EP. First, a support substrate SS made of p-type silicon is prepared. Next, the semiconductor layer EP, which is a p-type silicon layer, is formed on the support substrate SS by epitaxial growth.

[0058] Next, a buried region NBL is formed in the semiconductor substrate SUB by photolithography and ion implantation. Note that after the buried region NBL is formed in the support substrate SS, the semiconductor layer EP may be formed on the support substrate SS.

[0059] 6, an element isolation portion STI is formed in the semiconductor substrate SUB so as to reach a predetermined depth from an upper surface TS1 of the semiconductor substrate SUB. A detailed manufacturing process for forming the element isolation portion STI will be described below with reference to FIG.

[0060] 7, first, an insulating film such as a silicon nitride film is formed on the upper surface TS1 of the semiconductor substrate SUB by a film formation process using, for example, a CVD method. Next, the insulating film is patterned to form a hard mask HM. Next, a trench GR is formed in the semiconductor substrate SUB by performing an anisotropic etching process using the hard mask HM as a mask.

[0061] Next, an insulating film IF0 is formed on the upper surface TS1 of the semiconductor substrate SUB so as to fill the inside of the trench GR. The insulating film IF0 is, for example, a silicon oxide film. Next, the insulating film IF0 located outside the trench GR is removed by a polishing process using the CMP method so as to leave the insulating film IF0 filled inside the trench GR. In this way, the element isolation part STI including the trench GR and the insulating film IF0 is formed.

[0062] Thereafter, the hard mask HM is selectively removed by, for example, isotropic etching to expose the upper surface TS1 of the semiconductor substrate SUB. At this point, the position of the upper surface TS2 of the element isolation part STI is higher than the position of the upper surface TS1 of the semiconductor substrate SUB.

[0063] 8, the impurity region PLD, the drift region NLD, and the well region HPW are formed in this order in the semiconductor substrate SUB by photolithography and ion implantation. The order in which these are formed does not matter.

[0064] As shown in FIG. 9, a gate insulating film GI1 and a conductive film CF1 are formed. First, the gate insulating film GI1 is formed on an upper surface TS1 of the semiconductor substrate SUB, for example, by thermal oxidation. Next, a conductive film CF1 is formed on the gate insulating film GI1 and on an upper surface TS2 of the element isolation portion STI, for example, by film formation using a CVD method. The conductive film CF1 is, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0065] As shown in FIG. 10, a gate pattern GP and a body region PB are formed. First, a resist pattern RP1 is formed on the conductive film CF1. The resist pattern RP1 has openings that expose portions of the conductive film CF1 located on the gate insulating film GI1. Next, an anisotropic etching process is performed using the resist pattern RP1 as a mask to selectively remove the conductive film CF1 exposed from the resist pattern RP1, thereby forming multiple gate patterns GP from the conductive film CF1.

[0066] Next, oblique ion implantation is performed using the resist pattern RP1 as a mask to form the body region PB in the drift region NLD. In this oblique ion implantation, ions are implanted from a direction tilted at an angle of, for example, 20 degrees or more and 45 degrees or less with respect to a direction (Z direction) perpendicular to the upper surface TS1 of the semiconductor substrate SUB. The body region PB is also formed in portions of the semiconductor substrate SUB located between the multiple gate patterns GP in a plan view, and in parts of the semiconductor substrate SUB located below each gate pattern GP. Thereafter, the resist pattern RP1 is removed by ashing.

[0067] As shown in FIG. 11, a gate electrode GE1 is formed. First, a resist pattern RP2 is formed to cover the body region PB and a portion of the gate pattern GP. Next, an anisotropic etching process is performed using the resist pattern RP2 as a mask to selectively remove the gate pattern GP exposed from the resist pattern RP2, and the gate electrode GE1 is formed from the gate pattern GP. After that, the resist pattern RP2 is removed by ashing.

[0068] As shown in FIG. 12, sidewall spacers SW are formed on the side surfaces of the gate electrode GE1. First, a stacked film including, for example, a silicon oxide film and a silicon nitride film is formed on the upper surface TS1 of the semiconductor substrate SUB by a film formation process using, for example, a CVD method so as to cover the gate electrode GE1. Next, the stacked film is anisotropically etched to form sidewall spacers SW from the stacked film remaining on the side surfaces of the gate electrode GE1. Note that the anisotropic etching also removes the gate insulating film GI1 exposed from the gate electrode GE1.

[0069] 13, first, a source region NS is formed in the body region PB and a drain region ND is formed in the drift region NLD by photolithography and ion implantation. Next, although not shown, a high-concentration diffusion region PR is formed in the body region PB by photolithography and ion implantation.

[0070] 14, an insulating film IF1 and a silicide film SI are formed. First, the insulating film IF1 is formed on the upper surface TS1 of the semiconductor substrate SUB and on the upper surface TS2 of the element isolation part STI by a film formation process using, for example, a CVD method so as to cover the upper surface of the gate electrode GE1 and the sidewall spacer SW.

[0071] Next, the insulating film IF1 is patterned so as to cover at least a part of the upper surface of the active region GE1a, the sidewall spacers SW located on the side surfaces of the active region GE1a, and a part of the upper surface TS1 of the semiconductor substrate SUB. In the first embodiment, the insulating film IF1 is patterned so as to cover a part of the upper surface of the leading-out region GE1b, the sidewall spacers SW located on the side surfaces of the leading-out region GE1b, and a part of the upper surface TS2 of the element isolation portion STI.

[0072] Next, a silicide film SI is formed by salicide technology on the upper surface of the gate electrode GE1 exposed from the insulating film IF1 and on the upper surface TS1 of the semiconductor substrate SUB. The silicide film SI is formed on the upper surfaces of the drain region ND, the source region NS, and the high-concentration diffusion region PR.

[0073] 15, insulating films IF2, IF3, and a conductive film CF2 are formed. First, the insulating film IF2 is formed on the upper surface TS1 of the semiconductor substrate SUB and on the upper surface TS2 of the element isolation portion STI by a film formation process using, for example, the CVD method so as to cover the upper surface of the gate electrode GE1 and the sidewall spacer SW. Next, the insulating film IF3 is formed on the insulating film IF2 by a film formation process using, for example, the CVD method.

[0074] Next, a conductive film CF2 is formed on the insulating film IF3 by a film formation process using, for example, a CVD method. The conductive film CF2 is, for example, a tungsten silicide film. Next, a resist pattern RP3 is formed on the conductive film CF2. The resist pattern RP3 has openings that expose the drain region ND, part of the active region GE1a, the source region NS, and the lead-out region GE1b.

[0075] 16, a field plate electrode FP, an interlayer insulating film IL0, and an interlayer insulating film IL1 are formed. First, an anisotropic etching process is performed using a resist pattern RP3 as a mask to pattern the conductive film CF2, thereby forming the field plate electrode FP. Next, the resist pattern RP3 is removed by ashing.

[0076] In the first embodiment, the active portion FPa is in contact with the raised portion IFc and covers a part of the insulating film IF3 located on the upper surface of the active portion GE1a. The lead-out portion FPb is spaced apart from the raised portion IFf, and the position of the top of the lead-out portion FPb is lower than the position of the top of the insulating film IF3 located on the upper surface of the lead-out portion GE1b.

[0077] Next, an interlayer insulating film IL0 is formed on the insulating film IF3 by a film formation process using a CVD method so as to cover the field plate electrode FP. Next, an interlayer insulating film IL1 is formed on the interlayer insulating film IL0 by a film formation process using a plasma CVD method. The interlayer insulating film IL0 is used to satisfactorily fill the spaces between the multiple gate electrodes GE1. That is, the filling ability of the interlayer insulating film IL0 is higher than that of the interlayer insulating film IL1.

[0078] 17, first, the interlayer insulating film IL1 is subjected to planarization processing using the CMP method. At this point, the interlayer insulating film IL0 located on the upper surfaces of the active portions GE1a and the leading portions GE1b is covered with the interlayer insulating film IL1.

[0079] Next, the upper surface of the interlayer insulating film IL1 is subjected to a cleaning process. This cleaning process uses at least one of an aqueous solution containing hydrofluoric acid and hydrogen peroxide and an aqueous solution containing ammonia and hydrogen peroxide. The etching rate of the interlayer insulating film IL0 in the cleaning process is faster than the etching rate of the interlayer insulating film IL1 in the wet etching process.

[0080] 2 is obtained through the following manufacturing steps. First, a plurality of holes CH are formed in the interlayer insulating film IL1 and the interlayer insulating film IL0 by photolithography and anisotropic etching. Next, plugs PG are formed in the plurality of holes CH.

[0081] To form the plugs PG, first, a titanium film, for example, is formed inside the holes CH and on the interlayer insulating film IL1 by a film formation process using, for example, a sputtering method. Next, a titanium nitride film, for example, is formed on the titanium film by a film formation process using, for example, a CVD method. The titanium film and the titanium nitride film become a barrier metal film. Next, a tungsten film, for example, is formed on the barrier metal film by a film formation process using, for example, a CVD method so as to fill the insides of the holes CH. Next, the tungsten film and the barrier metal film formed outside the holes CH are removed by a polishing process using, for example, a CMP method.

[0082] <Problems in the study example and main features of the first embodiment> A semiconductor device as an example studied by the inventors of the present invention will be described below with reference to FIGS.

[0083] In the first embodiment, the lead-out portion FPb of the field plate electrode FP is not formed on the upper surface of the lead-out portion GE1b of the gate electrode GE1. On the other hand, in the study example, the lead-out portion FPb is formed on the upper surface of the lead-out portion GE1b, as shown in FIGS.

[0084] As described above, in the process of forming the element isolation portion STI, the position of the upper surface TS2 of the element isolation portion STI becomes higher than the position of the upper surface TS1 of the semiconductor substrate SUB. That is, the position of the upper surface of the lead-out portion GE1b of the gate electrode GE1 becomes higher than the upper surface of the active portion GE1a of the gate electrode GE1. Therefore, the total thickness of the interlayer insulating film IL1 and the interlayer insulating film IL0 formed on the lead-out portion FPb covering the upper surface of the lead-out portion GE1b is smaller than the total thickness of the interlayer insulating film IL1 and the interlayer insulating film IL0 formed on the active portion FPa covering the upper surface of the active portion GE1a.

[0085] Therefore, when the interlayer insulating film IL1 is planarized by the CMP method, the interlayer insulating film IL1 located on the pull-out portion FPb is not left, and the interlayer insulating film IL0 is exposed, increasing the possibility that the planarization process will also be performed on the interlayer insulating film IL0. Furthermore, in the planarization process by the CMP method, dents or linear scratches called microscratches are generated in the interlayer insulating film IL0 due to particles contained in the slurry, etc.

[0086] 27 is a cross-sectional view illustrating a defect caused by a microscratch 10. After the planarization process, a cleaning process is performed to clean the upper surface of the interlayer insulating film IL1. If the interlayer insulating film IL0 is exposed, the aqueous solution used in the cleaning process will penetrate into the interlayer insulating film IL0. The cleaning process uses at least one of an aqueous solution containing hydrofluoric acid and hydrogen peroxide and an aqueous solution containing ammonia and hydrogen peroxide.

[0087] Here, the etching rate of the interlayer insulating film IL0 in the cleaning process is faster than the etching rate of the interlayer insulating film IL1 in the cleaning process, and therefore the cleaning process expands the micro-scratches 10 occurring in the interlayer insulating film IL0, making it easier for the micro-scratches 10 to connect with each other.

[0088] Thereafter, when forming plugs PG in the interlayer insulating film IL0, a barrier metal film BM is formed, followed by a conductive film CF3 such as a tungsten film. To form the barrier metal film BM, first, a titanium film, for example, is formed by a film formation process using a sputtering method. Next, a titanium nitride film, for example, is formed on the titanium film by a film formation process using a CVD method. If these film formation processes using the CVD method are performed while the micro-scratches 10 are connected to each other, a titanium nitride film will be formed within the micro-scratches 10, which may result in the formation of a leak path between two adjacent plugs PG.

[0089] In the first embodiment, as shown in FIGS. 2 and 3, the lead-out portion FPb does not cover a part of the insulating film IF3 located on the upper surface of the lead-out portion GE1b, and is spaced apart from the raised portion IFf.

[0090] Therefore, the interlayer insulating film IL0 is not exposed on the upper surface of the active region GE1a, nor on the upper surface of the lead-out region GE1b, but is covered by the interlayer insulating film IL1. This prevents the micro-scratches 10 from connecting with each other due to the cleaning process, and suppresses the formation of leak paths, thereby improving the reliability of the semiconductor device. At the same time, the active region FPa is in contact with the rising region IFc, allowing the field plate electrode FP to fully function.

[0091] (Embodiment 2) A semiconductor device and a manufacturing method thereof according to the second embodiment will be described below with reference to Fig. 18. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0092] In the second embodiment, the insulating film IF1 used for selectively forming the silicide film SI is not formed on the upper surface of the leading portion GE1b of the gate electrode GE1. Moreover, the insulating film IF1 is not formed between the leading portion FPb of the field plate electrode FP and the upper surface TS2 of the element isolation part STI.

[0093] Therefore, the thickness of the interlayer insulating film IL1 can be increased directly above the portion where the insulating film IF1 was formed in embodiment 1. Therefore, in embodiment 2, the interlayer insulating film IL0 is even less likely to be exposed on the upper surface of the pull-out portion GE1b than in embodiment 1.

[0094] 14, the insulating film IF1 is patterned so that the insulating film IF1 is not left on a part of the upper surface of the leading portion GE1b, on the sidewall spacer SW located on the side surface of the leading portion GE1b, and on a part of the upper surface TS2 of the element isolation portion STI. The insulating film IF1 is patterned so that at least the insulating film IF1 covering the upper surface of the leading portion GE1b is removed.

[0095] (Embodiment 3) 19 to 21, a semiconductor device and a manufacturing method thereof according to the third embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0096] In the first embodiment, the lead-out portion FPb of the field plate electrode FP is separated from the raised portion IFf, so that the lead-out portion FPb does not cover a part of the insulating film IF3 located on the upper surface of the lead-out portion GE1b of the gate electrode GE1.

[0097] 19 and 20, the lead-out portion FPb is in contact with the raised portion IFf, but the position of the top of the lead-out portion FPb is lower than the position of the top of the insulating film IF3 located on the upper surface of the lead-out portion GE1b. Also, the active portion FPa of the field plate electrode FP is in contact with the raised portion IFc, and the position of the top of the active portion FPa is lower than the position of the top of the insulating film IF3 located on the upper surface of the active portion GE1a of the gate electrode GE1.

[0098] In the third embodiment, similarly to the first embodiment, the function of the field plate electrode FP is maintained, and the interlayer insulating film IL0 can be prevented from being exposed on the upper surface of the lead-out portion GE1b.

[0099] Furthermore, the active portion FPa does not cover a part of the insulating film IF3 located on the upper surface of the active portion GE1a. Therefore, in the third embodiment, the interlayer insulating film IL0 is even less likely to be exposed on the upper surface of the active portion GE1a than in the first embodiment.

[0100] To obtain the structure of the third embodiment, the position of the openings in the resist pattern RP3 used in the manufacturing process of FIG. 15 is changed as shown in FIG. 21. The resist pattern RP3 of the third embodiment has openings that expose the drain region ND, the active portion GE1a, the source region NS, and the leading portion GE1b. The ends of the openings are set midway through the rising portion IFc and the rising portion IFf. The active portion FPa and the leading portion FPb are formed by patterning the conductive film CF2 using the resist pattern RP3 of the third embodiment.

[0101] The technique disclosed in the third embodiment can be applied in combination with the technique disclosed in the second embodiment. That is, in the third embodiment, the insulating film IF1 does not have to be formed on the upper surface of the lead-out portion GE1b of the gate electrode GE1, and the insulating film IF1 does not have to be formed between the lead-out portion FPb of the field plate electrode FP and the upper surface TS2 of the element isolation part STI.

[0102] (Fourth embodiment) 22 to 24, a semiconductor device and a manufacturing method thereof according to the fourth embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and explanations of points that overlap with the first embodiment will be omitted.

[0103] In the fourth embodiment, as shown in FIGS. 22 and 23, the side surface of the lead-out portion GE1b is set back from the side surface of the active portion GE1a in the X direction. In other words, the width of the lead-out portion GE1b in the X direction is smaller than the sum of the width of each of the two active portions GE1a and the distance between two adjacent active portions GE1a separated by the source region NS1. In other words, the distance from the side surface of the lead-out portion GE1b to the virtual extension line VEL in the X direction is smaller than the width of the active portion GE1a. As shown in FIG. 22, the virtual extension line VEL extends the side surface of the active portion GE1a facing the source region NS1 in the Y direction.

[0104] Therefore, the lead-out portion FPb is separated from the raised portion IFf and does not cover a part of the insulating film IF3 located on the upper surface of the lead-out portion GE1b. In addition, the position of the top of the lead-out portion FPb is lower than the position of the top of the insulating film IF3 located on the upper surface of the lead-out portion GE1b.

[0105] In the fourth embodiment, similarly to the first embodiment, the interlayer insulating film IL0 is less likely to be exposed on the upper surface of the lead-out portion GE1b.

[0106] To obtain the structure of the fourth embodiment, the position of the opening of the resist pattern RP2 used in the manufacturing process of FIG. 11 is changed as shown in FIG. 24. The resist pattern RP2 of the fourth embodiment has an opening such that the width of the gate pattern GP left on the element isolation part STI is smaller than that of the resist pattern RP2 of the first embodiment. The gate pattern GP is patterned using the resist pattern RP2 of the fourth embodiment to form the lead-out portion GE1b.

[0107] The technique disclosed in the fourth embodiment can be applied in combination with the techniques disclosed in the second and third embodiments. That is, in the fourth embodiment, the insulating film IF1 does not have to be formed on the upper surface of the lead-out portion GE1b of the gate electrode GE1, and the insulating film IF1 does not have to be formed between the lead-out portion FPb of the field plate electrode FP and the upper surface TS2 of the element isolation part STI. Furthermore, in the fourth embodiment, the position of the top of the lead-out portion FPb may be lower than the position of the top of the insulating film IF3 located on the upper surface of the lead-out portion GE1b, and the position of the top of the active portion FPa may be lower than the position of the top of the insulating film IF3 located on the upper surface of the active portion GE1a of the gate electrode GE1.

[0108] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to these embodiments and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0109] 1Q, 2Q MISFET 10 Micro Scratches BM Barrier metal film BS1 Bottom surface of semiconductor substrate CF1, CF2, CF3 conductive film CH hole EP semiconductor layer FP field plate electrode FPa active area FPb pull-out point GE1, GE2 gate electrodes GE1a active area GE1b pull-out point GI1, GI2 gate insulating film GP Gate Pattern GR Groove HM Hard Mask HPW p-type well region IF0, IF1, IF2, IF3 insulating film IFa, IFb, IFd, IFe flat areas IFc, IFf rising point IL0, IL1 Interlayer insulating film NBL n-type buried region ND n-type drain region NEX n-type extension region NLD n-type drift region NR n-type heavily doped diffusion region NS n-type source region PB p-type body region PG plug PLD p-type impurity region PR p-type high concentration diffusion region PW p-type well region RP1, RP2, RP3 resist patterns SI silicide film SS support board STI element isolation section SUB Semiconductor substrate SW Sidewall Spacer TS1 Top surface of semiconductor substrate TS2 Top surface of element isolation part VEL Virtual extension line

Claims

1. a semiconductor substrate having an upper surface; an isolation portion having a predetermined depth from the upper surface of the semiconductor substrate and formed in the semiconductor substrate; a gate insulating film formed on the upper surface of the semiconductor substrate; a gate electrode formed on the gate insulating film and on an upper surface of the element isolation portion; a sidewall spacer formed on a side surface of the gate electrode; a first insulating film covering an upper surface of the gate electrode and the sidewall spacer, and formed on the upper surface of the semiconductor substrate and the upper surface of the element isolation portion; a field plate electrode formed on the first insulating film; Equipped with The gate electrode is a first location located on the top surface of the semiconductor substrate; a second location located on the top surface of the element isolation portion; and The first insulating film is a third location located on the top surface of the semiconductor substrate; a fourth portion located above the third portion and on the side surface of the first portion of the gate electrode via the sidewall spacer; a fifth location located on the top surface of the element isolation portion; a sixth portion located above the fifth portion and on the side surface of the second portion of the gate electrode via the sidewall spacer; and The field plate electrode is a seventh location located on the top surface of the semiconductor substrate; an eighth location located on the top surface of the element isolation portion; and a position of the upper surface of the second portion of the gate electrode is higher than a position of the upper surface of the first portion of the gate electrode; the seventh portion of the field plate electrode contacts the fourth portion of the first insulating film; a top position of the eighth portion of the field plate electrode is lower than a top position of the first insulating film located on the upper surface of the second portion of the gate electrode.

2. 2. The semiconductor device according to claim 1, a top surface of the element isolation portion being higher than a top surface of the semiconductor substrate;

3. 2. The semiconductor device according to claim 1, the seventh portion of the field plate electrode covers a portion of the first insulating film located on the upper surface of the first portion of the gate electrode.

4. 2. The semiconductor device according to claim 1, the eighth location of the field plate electrode is spaced apart from the sixth location of the first insulating film.

5. 4. The semiconductor device according to claim 3, In a plan view, the gate electrode extends in a first direction from above the upper surface of the semiconductor substrate toward above the upper surface of the element isolation portion, In a second direction perpendicular to the first direction in a plan view, the side surface of the second portion of the gate electrode is recessed from the side surface of the first portion of the gate electrode.

6. 2. The semiconductor device according to claim 1, the eighth portion of the field plate electrode contacts the sixth portion of the first insulating film; a seventh portion of the field plate electrode is located at a position lower than a top portion of the first insulating film located on the top surface of the gate electrode at the first portion;

7. 2. The semiconductor device according to claim 1, a second insulating film covering at least a part of the upper surface of the first portion of the gate electrode, the sidewall spacer located on the side surface of the first portion of the gate electrode, and a part of the upper surface of the semiconductor substrate; a silicide film formed on the upper surface of the gate electrode exposed from the second insulating film; Further provided with The first insulating film covers at least the top surface of the first portion via the second insulating film or the silicide film.

8. 8. The semiconductor device according to claim 7, the second insulating film is arranged so as not to be formed on the upper surface of the second portion of the gate electrode.

9. 2. The semiconductor device according to claim 1, a first interlayer insulating film covering the field plate electrode and formed on the first insulating film; a second interlayer insulating film formed on the first interlayer insulating film; Further provided with the upper surface of the second interlayer insulating film is flat; the first interlayer insulating film located on the upper surface of the first portion of the gate electrode and on the upper surface of the second portion of the gate electrode is covered with the second interlayer insulating film.

10. 2. The semiconductor device according to claim 1, a first conductivity type drift region formed in the semiconductor substrate and having a predetermined depth from the upper surface of the semiconductor substrate; a well region of a second conductivity type opposite to the first conductivity type, the well region having a predetermined depth from the upper surface of the semiconductor substrate and formed in the semiconductor substrate; a body region of the second conductivity type formed in the drift region; a source region of the first conductivity type formed in the body region; a drain region of the first conductivity type formed in the drift region; Further provided with the first location of the gate electrode and the seventh location of the field plate electrode are located between the drain region and the source region in a plan view; In a plan view, the well region is formed between the drift region and the element isolation portion.

11. (a) providing a semiconductor substrate having an upper surface; (b) forming an isolation portion in the semiconductor substrate, the isolation portion having a predetermined depth from the top surface of the semiconductor substrate; (c) forming a gate insulating film on the top surface of the semiconductor substrate; (d) forming a gate electrode on the gate insulating film and on the upper surface of the element isolation portion; (e) forming sidewall spacers on the side surfaces of the gate electrode; (f) forming a first insulating film on the upper surface of the semiconductor substrate and on the upper surface of the element isolation portion so as to cover the upper surface of the gate electrode and the sidewall spacer; (g) forming a field plate electrode on the first insulating film; Equipped with The gate electrode is a first location located on the top surface of the semiconductor substrate; a second location located on the top surface of the element isolation portion; and The first insulating film is a third location located on the top surface of the semiconductor substrate; a fourth portion located above the third portion and on the side surface of the first portion of the gate electrode via the sidewall spacer; a fifth location located on the top surface of the element isolation portion; a sixth portion located above the fifth portion and on the side surface of the second portion of the gate electrode via the sidewall spacer; and The field plate electrode is a seventh location located on the top surface of the semiconductor substrate; an eighth location located on the top surface of the element isolation portion; and a position of the upper surface of the second portion of the gate electrode is higher than a position of the upper surface of the first portion of the gate electrode; the seventh portion of the field plate electrode contacts the fourth portion of the first insulating film; a top position of the eighth portion of the field plate electrode is lower than a top position of the first insulating film located on the upper surface of the second portion of the gate electrode.

12. The method for manufacturing a semiconductor device, wherein the upper surface of the element isolation portion is positioned higher than the upper surface of the semiconductor substrate.

13. 12. The method for manufacturing a semiconductor device according to claim 11, The method for manufacturing a semiconductor device, wherein the seventh portion of the field plate electrode covers a portion of the first insulating film located on the upper surface of the first portion of the gate electrode.

14. 12. The method for manufacturing a semiconductor device according to claim 11, the eighth location of the field plate electrode is spaced apart from the sixth location of the first insulating film.

15. 15. The method for manufacturing a semiconductor device according to claim 14, In a plan view, the gate electrode extends in a first direction from above the upper surface of the semiconductor substrate toward above the upper surface of the element isolation portion, A method for manufacturing a semiconductor device, wherein the side surface of the second portion of the gate electrode is recessed from the side surface of the first portion of the gate electrode in a second direction perpendicular to the first direction in a plan view.

16. 12. The method for manufacturing a semiconductor device according to claim 11, the eighth portion of the field plate electrode contacts the fourth portion of the first insulating film; a seventh portion of the field plate electrode is located at a position lower than a top portion of the first insulating film located on the top surface of the first portion;

17. 12. The method for manufacturing a semiconductor device according to claim 11, (h) forming a second insulating film on the upper surface of the semiconductor substrate and on the upper surface of the element isolation portion so as to cover the upper surface of the gate electrode and the sidewall spacer between the steps (d) and (f); (i) between the step (h) and the step (f), patterning the second insulating film so as to cover at least a part of the upper surface of the first location, the sidewall spacers located on the side surfaces of the first location, and a part of the upper surface of the semiconductor substrate; (j) forming a silicide film on the upper surface of the gate electrode exposed from the second insulating film and on the upper surface of the semiconductor substrate between the step (i) and the step (f); Further provided with In the step (f), the first insulating film covers at least the upper surface of the first portion of the gate electrode via the second insulating film or the silicide film.

18. 18. The method for manufacturing a semiconductor device according to claim 17, In the step (i), the second insulating film covering the upper surface in the second location is removed.

19. 12. The method for manufacturing a semiconductor device according to claim 11, (k) forming a first interlayer insulating film on the first insulating film so as to cover the field plate electrode; (l) forming a second interlayer insulating film on the first interlayer insulating film; (m) performing a planarization process on the second interlayer insulating film; (n) after the step (m), performing a cleaning process on the upper surface of the second interlayer insulating film; Further provided with after the step (m), the first interlayer insulating film located on the upper surface of the first portion of the gate electrode and the upper surface of the second portion of the gate electrode are covered with the second interlayer insulating film; In the step (n), at least one of an aqueous solution containing hydrofluoric acid and hydrogen peroxide and an aqueous solution containing ammonia and hydrogen peroxide is used; a first interlayer insulating film having a higher etching rate with respect to the aqueous solution used in the step (n) than a second interlayer insulating film having a higher etching rate with respect to the aqueous solution used in the step (n).

20. 12. The method for manufacturing a semiconductor device according to claim 11, (o) forming a drift region of a first conductivity type in the semiconductor substrate, the drift region having a predetermined depth from the top surface of the semiconductor substrate; (p) forming a well region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate, the well region having a predetermined depth from the top surface of the semiconductor substrate; (q) forming a body region of the second conductivity type in the drift region; (r) forming a source region of the first conductivity type in the body region and a drain region of the first conductivity type in the drift region; Further provided with the first location of the gate electrode and the seventh location of the field plate electrode are located between the drain region and the source region in a plan view; a well region formed between the drift region and the element isolation portion in a plan view;

Images