Photoelectric conversion device

Abstract

To improve the efficiency of element layout.SOLUTION: A photoelectric conversion device includes a plurality of pixels including first pixels and second pixels. Each of the plurality of pixels has a stacked configuration including a stack of a first semiconductor layer having a photoelectric conversion part and a first reading circuit for reading a signal based on photoelectric conversion at the photoelectric conversion part, and a second semiconductor layer having a memory for storing a voltage dependent on the signal and an output circuit for outputting the voltage retained in the memory. The first reading circuit of the first pixel includes a first amplification transistor, and the first reading circuit of the second pixel includes a second amplification transistor. Tthe first amplification transistor is connected to a first current source through a first switch, the second amplification transistor is connected to the first current source through a second switch, and the first amplification transistor and the second amplification transistor share the first current source.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] It has been proposed that a photoelectric conversion device perform a global electronic shutter operation that simultaneously resets the photoelectric conversion elements arranged in each of a plurality of pixels and reads out charges from the photoelectric conversion elements. Patent Document 1 shows an image sensor equipped with a voltage-holding global electronic shutter function that converts signal charges into voltage and holds them. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-051548 Summary of the Invention [Problem to be solved by the invention]

[0004] An imaging device having a voltage-holding global electronic shutter function as described in Patent Document 1 has many components per unit pixel, which limits the pixel layout. [Means for solving the problem]

[0005] a first semiconductor layer including a first pixel and a second pixel, each of the plurality of pixels having a stacked configuration of a first semiconductor layer including a photoelectric conversion unit and a first readout circuit that reads out a signal based on photoelectric conversion in the photoelectric conversion unit, and a second semiconductor layer including a memory that holds a voltage corresponding to the signal and an output circuit that outputs the voltage held in the memory; wherein the first readout circuit of the first pixel includes a first amplification transistor, and the first readout circuit of the second pixel includes a second amplification transistor, the first amplification transistor is connected to a first current source via a first switch, and the second amplification transistor is connected to the first current source via a second switch, and the first amplification transistor and the second amplification transistor share the first current source. [Effects of the Invention]

[0006] According to the present invention, it is possible to reduce restrictions on pixel layout. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic diagram of an overall configuration of a photoelectric conversion device. [Figure 2] 2A and 2B are diagrams illustrating a laminated structure of a substrate of a photoelectric conversion device. [Figure 3] 2 is a circuit diagram of a column signal processing circuit from a pixel of the photoelectric conversion device according to the first embodiment. FIG. [Figure 4] FIG. 2 is a driving timing chart for one frame of the photoelectric conversion device according to the first embodiment. [Figure 5] FIG. 2 is a drive timing chart of the photoelectric conversion device according to the first embodiment. [Figure 6] FIG. 2 is a plan view showing the positions of junctions and current sources in the photoelectric conversion device according to the first embodiment. [Figure 7] FIG. 10 is a circuit diagram of a column signal processing circuit from a pixel of a photoelectric conversion device according to a second embodiment. [Figure 8] FIG. 10 is a driving timing chart for one frame of the photoelectric conversion device according to the second embodiment. [Figure 9] FIG. 10 is a drive timing chart of the photoelectric conversion device according to the second embodiment. [Figure 10] FIG. 10 is a plan view showing the positions of junctions and current sources in a photoelectric conversion device according to a second embodiment. [Figure 11] FIG. 10 is a circuit diagram of a column signal processing circuit from a pixel of a photoelectric conversion device according to a third embodiment. [Figure 12] FIG. 10 is a drive timing chart of a photoelectric conversion device according to a third embodiment. [Figure 13] FIG. 10 is a circuit diagram of a column signal processing circuit from a pixel of a photoelectric conversion device according to a third embodiment. [Figure 14] FIG. 10 is a functional block diagram of a photoelectric conversion system according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The embodiments shown below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (for example, "upper," "lower," "right," "left," and other terms including these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the embodiments with reference to the drawings, and the meaning of these terms does not limit the technical scope of the present invention.

[0010] In this specification, a planar view refers to a view from a direction perpendicular to the light incident surface of the semiconductor layer. A cross-sectional view refers to a view of a cross section perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is a rough surface when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0011] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0012] (First embodiment) The photoelectric conversion device according to the first embodiment will be described with reference to FIGS.

[0013] Fig. 1 is a schematic diagram showing one embodiment of a photoelectric conversion device. The photoelectric conversion device 10 has a configuration in which a pixel chip 100 (first chip), a memory chip 200 (second chip), and a signal processing chip 300 (third chip) are stacked as shown in Fig. 2. Signals can be exchanged between the chips by connecting the wiring provided on each chip.

[0014] The pixel chip 100 shown in FIGS. 1 and 2 includes a first semiconductor layer and a first wiring structure, and is equipped with a pixel region 110, a vertical scanning circuit 120, and a pixel control circuit 20. The pixel region 110 is an area in which pixels 30, which are unit pixels, are arranged in a matrix array. The pixels 30 include photoelectric conversion elements such as photodiodes and output pixel signals (signal voltages) corresponding to the amount of incident light. In addition to effective pixels that output pixel signals corresponding to the amount of incident light, the pixel region 110 may also include optical black pixels whose photoelectric conversion units are shielded from light and dummy pixels that do not output signals. The number of rows and columns of the pixel array arranged in the pixel region 110 is not particularly limited. The pixel control circuit 20 is a logic circuit that generates timing for operating the pixels 30 and outputs drive pulses for the pixels 30 to the vertical scanning circuit 120. The vertical scanning circuit 120 has drivers that drive the pixels 30 row by row.

[0015] The memory chip 200 includes a second semiconductor layer and a second wiring structure, and is equipped with a memory region 210, a memory vertical scanning circuit 220, a current source 230, and a memory control circuit 21. The memory region 210 is an area in which pixel memories 40 are arranged in an array in the row and column directions. The pixel memories 40 have the function of holding signal voltages output from the pixels 30. Note that the number of pixels 30 and the number of pixel memories 40 do not need to be the same. For example, pixel memories 40 do not need to be arranged for dummy pixels that do not output signals. Furthermore, dummy pixel memories that do not output signals may be arranged corresponding to the dummy pixels.

[0016] The current source 230 supplies a reference current to the pixel memory 40. The memory control circuit 21 has a logic circuit that generates timing for operating the pixel memory 40 and controls circuits arranged around the pixels, such as the current source 230. The drive pulses output from the memory control circuit 21 are input to the memory vertical scanning circuit 220. The memory vertical scanning circuit 220 has a driver that drives the pixel memory 40 row by row.

[0017] The signal processing chip 300 includes a third semiconductor layer and a third wiring structure, and is equipped with a signal processing unit 310, a column control circuit 320, a ramp generator 340, a current source 330, and a signal processing control circuit 22. The signal processing unit 310 has column signal processing circuits 50, which are output circuits, arranged in an array in the row direction. The column signal processing circuit 50 has the function of performing AD conversion on the signal voltage output from the pixel memory 40 based on a reference voltage generated by the ramp generator 340, and outputs the converted digital signal to the outside of the signal processing chip 300 as image data.

[0018] Although this embodiment uses ramp-type AD conversion, the AD conversion method is not limited to a specific method. The column signal processing circuit 50 may also have a function of performing digital processing such as noise reduction on image data. A current source 330 supplies a reference current to the column signal processing circuit 50. The signal processing control circuit 22 has a logic circuit that generates timing for operating the column signal processing circuit 50 and sets the functions of a ramp generator 340 and the current source 330. A drive pulse output from the signal processing control circuit 22 is input to a column control circuit 320. The column control circuit 320 has a drive driver that outputs a drive pulse to the column signal processing circuit 50.

[0019] 2, the pixel chip 100, the memory chip 200, and the signal processing chip 300 are stacked to form the photoelectric conversion device 10. The signal generated by the pixel chip 100 passes through wiring connecting the pixel chip 100 and the memory chip 200, and is output to the outside of the photoelectric conversion device through wiring of the signal processing chip 300.

[0020] The photoelectric conversion device according to this embodiment is a photoelectric conversion device that performs a so-called voltage holding type global electronic shutter operation.

[0021] FIG. 3 shows circuit diagrams of the pixel 30, memory 40, and column signal processing circuit 50 in this embodiment.

[0022] In this embodiment, the pixels 30, the memory 40, and the column signal processing circuit 50 are arranged on different semiconductor layers. The power supply and ground for the pixels 30 are SVDD and SGND, the power supply and ground for the memory 40 are MVDD and MGND, and the power supply and ground for the column signal processing circuit 50 are AVDD and AGND.

[0023] In the photoelectric conversion device according to this embodiment, two amplification transistors corresponding to a first pixel 30-1 and a second pixel 30-2 included in a plurality of pixels 30 share one current source. The first pixel 30-1 is connected to a first memory 40-1 via a first junction 1100-1, and the second pixel 30-2 is connected to a second memory 40-1 via a second junction 1100-2. The first memory 40-1 is connected to a column signal processing circuit 50, which is a first readout circuit, via a junction 2100-1. The second memory 40-1 is connected to a column signal processing circuit 50, which is a second readout circuit, via a junction 2100-2.

[0024] The first pixel 30-1, which is one of the pixels 30, will be described below.

[0025] The first pixel 30-1 has a photodiode (PD) 1001-1, a photodiode (PD) 1002-1, a transfer transistor 1003-1, a transfer transistor 1004-1, an amplification transistor 1005-1, and a reset transistor 1006-1.

[0026] The photoelectric conversion device according to this embodiment is a photoelectric conversion device that supports so-called PDAF, in which PD1001-1 and PD1002-1 form one pixel and the signals of each PD are used for phase difference detection. The photoelectric conversion device according to this embodiment is also an imaging device (here, a CMOS sensor) that uses the signal of at least one of these two PDs for image generation.

[0027] One terminal of PD1001-1 is connected to the source of transfer transistor 1003-1, and one terminal of PD1002-1 is connected to the source of transfer transistor 1004-1. The drains of transfer transistor 1003-1 and 1004-1 are connected to the gate of amplifier transistor 1005-1. The node connected to the gate of amplifier transistor 1005-1 acts as a floating diffusion when reading out charges photoelectrically converted by PD1001-1 and PD1002-1.

[0028] The drain of the amplifier transistor 1005-1 is connected to SVDD. The source of the amplifier transistor 1005-1 is connected to the first memory 40-1 via a first junction 1100-1. The reset transistor 1006-1 is connected in series between the gate of the amplifier transistor 1005-1 and SVDD.

[0029] The components of the second pixel 30-2 can be understood by replacing the "-1" in the numbers in the description of the components of the first pixel 30-1 with "-2," and therefore a description thereof will be omitted.

[0030] Next, the first memory 40-1, which is one of the memories 40, will be described.

[0031] The first memory 40-1 has a signal holding unit 2003-1, a signal holding unit 2005-1, and a signal holding unit 2007-1. The signal holding unit 2003-1 is connected to a switch 2002-1, the signal holding unit 2005-1 is connected to a switch 2004-1, and the signal holding unit 2007-1 is connected to a switch 2006-1. The first memory 40-1 further includes a selection transistor 2001-1, a reset transistor 2008-1, a first amplification transistor 2009-1, and a selection transistor 2010-1.

[0032] The source of the amplification transistor 1005-1 of the first pixel 30-1 is connected to the drain of the selection transistor 2001-1 (first switch) via the first junction 1100-1, thereby connecting the source of the amplification transistor 1005-1 to the drain of the first current source 2020 via the selection transistor 2001-1.

[0033] In this embodiment, it is possible to selectively control the state to obtain one of the following states: a state in which the selection transistor 2001-1 is ON and the selection transistor 2001-2 (second switch) is OFF; a state in which the selection transistor 2001-1 is OFF and the selection transistor 2001-2 is ON; or a state in which both the selection transistors 2001-1 and 2001-2 are OFF.

[0034] The signal holding unit 2003-1 has one terminal connected to GND and the other terminal connected to the source of the switch 2002-1, the drain of which is connected to the gate of the first amplification transistor 2009-1.

[0035] Similarly, one terminal of the signal holding unit 2005-1 is connected to GND, and the other terminal is connected to the source of the switch 2004-1, the drain of which is connected to the gate of the first amplification transistor 2009-1.

[0036] The signal holding unit 2007-1 has one terminal connected to GND and the other terminal connected to the source of the switch 2006-1, the drain of which is connected to the gate of the first amplification transistor 2009-1.

[0037] Each of the signal holding units 2003-1, 2005-1, and 2007-1 may be an element having a function of holding a signal, and examples thereof include DRAM and MIM capacitors.

[0038] WR_N1 is input to the gate of switch 2002-1, and WR_A1 is input to the gate of switch 2004-1. WR_AB1 is input to the gate of switch 2006-1. When switch 2002-1 is turned on by WR_N1, the signal voltage output from amplifying transistor 1005-1 is written to signal holding unit 2003-1. Similarly, a signal voltage can be written to signal holding unit 2004-1 in accordance with WR_A1, and a signal voltage can be written to signal holding unit 2006-1 in accordance with WR_AB1.

[0039] The drain of the reset transistor 2008-1 is connected to a power supply line that supplies a reference power supply MVDD. The source of the reset transistor 2008-1 is connected to the gate of the first amplifying transistor 2009-1. When PMRST1 is Hi, the gate of the first amplifying transistor is reset.

[0040] The components of the second memory 40-2 can be considered by replacing the "-1" in the numbers in the description of the components of the first memory 40-1 with "-2," and therefore a description thereof will be omitted.

[0041] Here, the source of the selection transistor 2001-1 (first switch) of the first memory 40-1 and the source of the selection transistor 2001-2 (second switch) of the second memory 40-1 are each connected to the drain of the first current source 2020. A switch 2021 is connected in series between the first current source 2020 and MGND.

[0042] A voltage bias1 is applied to the gate of the first current source 2020, and a voltage PWR is applied to the gate of the switch 2021. The voltage bias1 can be set arbitrarily according to the value of the current desired to flow through the amplification transistor 1005-1 and the amplification transistor 1005-2.

[0043] Generally, in a voltage-holding global electronic shutter configuration, a dedicated current source is provided for the amplification transistor of each pixel to read out a signal from the pixel 30. In this embodiment, the amplification transistors 1005-1 and 1005-2 of the first pixel 30-1 and the second pixel 30-2 share a single first current source 2020. This reduces the number of elements (components) included in the photoelectric conversion device and alleviates restrictions on pixel layout. Reducing restrictions on pixel layout advantageously allows pixels to be configured with a smaller area.

[0044] The column signal processing circuit 50 includes ADCs 303-1 and 303-2 as AD converters. The input terminal of the ADC 303-1 is connected to the drain of a current source 301-1 and the source of a selection transistor 2010-1 of the first memory 40-1 via a junction 2100-1. A switch 302-1 is connected in series between the source of the current source 301-1 and AGND.

[0045] The input terminal of the ADC 303-2 is connected to the drain of the current source 301-2 and the source of the selection transistor 2010-2 of the second memory 40-2 via a junction 2100-2. A switch 302-2 is connected in series between the source of the current source 301-2 and AGND.

[0046] A voltage bias2 is supplied to the gate of the current source 301-1 and the gate of the current source 301-2. The voltage bias2 can be set arbitrarily depending on the value of the current desired to flow through the first amplification transistor 2009-1 and the second amplification transistor 2009-2.

[0047] The operations of the pixel 30, memory 40, and column signal processing circuit 50 will be described with reference to FIGS.

[0048] As shown in Figure 4, in this embodiment, one frame is made up of a T1 period, a T2 period, and a T3 period_all. The T1 period is a period in which each photodiode is reset, and the T2 period is a period in which signals output from pixels are written to memory. The T3 period is a period in which signals are read from memory to the column signal processing circuit, and the T3 period_all is a collective term for multiple T3 periods.

[0049] In this embodiment, during the T3 period, signals are read from the memory 40 to the column signal processing circuit 50 simultaneously for two pixels aligned in the vertical direction (column direction). Therefore, if the number of rows of pixels 30 arranged in the pixel array is N, the T3 period is sequentially repeated N / 2 times during the T3 period_all. Note that if two pixels aligned in the horizontal direction (row direction) share a readout period, the T3 period is repeated N times. Here, the number of times the T3 period is repeated can be reduced by increasing the number of pairs of pixels 30 that are simultaneously read out from the memory 40 to the column signal processing circuit 50.

[0050] In FIG. 4, the T1 period and the T3 period_all overlap, but for example, the operation described as the T3 period may be stopped while the operation described as the T1 period is being performed.

[0051] FIG. 5(a) shows the reset operations of PD1001-1, PD1002-1, PD1001-2, and PD1002-2 during a period T1 from time t1-0 to time t1-4.

[0052] During the period from time t1-1 to time t1-3, PRES1 and PRES2 are Hi. PRES1 is a control signal supplied to the gate of reset transistor 1006-1, and PRES2 is a control signal supplied to the gate of reset transistor 1006-2. When PRES1 is Hi, reset transistor 1006-1 is ON, and when PRES1 is Lo, reset transistor 1006-1 is OFF. Similarly, when PRES2 is Hi, reset transistor 1006-2 is ON, and when PRES2 is Lo, reset transistor 1006-2 is OFF.

[0053] At time t1-2, PTX1A and PTX1B change from Low to Hi. PTX1A is a control signal supplied to the gate of transfer transistor 1003-1, and PTX1B is a control signal supplied to the gate of transfer transistor 1004-1. When PTX1A is Hi, the transfer transistor 1003-1 turns ON, and when PTX1A is Lo, the transfer transistor 1003-1 turns OFF. When PTX1B is Hi, the transfer transistor 1004-1 turns ON, and when PTX1A is Lo, the transfer transistor 1004-1 turns OFF.

[0054] During the period ΔTx from time t1-2, PTXA1 and PTXB1 maintain Hi. During this time, the reset transistor 1006-1, transfer transistor 1003-1, and transfer transistor 1004-1 turn ON, resetting PD1001-1 and PD1002-1.

[0055] After ΔTx has elapsed, PTXA1 and PTXB1 become Lo, the transfer transistors 1003-1 and 1004-1 turn OFF, and the resetting of PD1001-1 and PD1002-1 is completed.

[0056] After ΔTa from time t1-2, PTXA2 and PTXB2 become Hi and then maintain the Hi state for the period ΔTx.

[0057] PTXA2 is a control signal input to the gate of the transfer transistor 1003-2 of the second pixel 30-2, and PTXB2 is a control signal input to the gate of the transfer transistor 1004-2. While PTXA2 and PTXB2 are Hi, PRES2 is also Hi, so PD1001-2 and PD1002-2 are reset.

[0058] At time t1-3, PRES1 and PRES2 go low, the reset transistors 1006-1 and 1006-2 are turned off, and the gates of the amplifying transistors 1005-1 and 1005-2 become floating.

[0059] 5A, PSEL1 and PSEL2 are fixed at Lo. WR_N1, WR_N2, WR_A1, WR_A2, WR_AB1, WR_AB2, PMRST1, PMRST2, PMSEL1, and PMSEL2 are fixed at Lo or operate in pulse mode.

[0060] Next, the operation of writing the signal output from the pixel 30 to the memory 40 will be described using Figure 5(b). The period from time t2-1 to t2-13 shown in Figure 5(b) is called the T2-1 period, and the period from time t2-13 to t2-14 is called the T2-2 period. The T2-1 period and the T2-2 period are collectively called the T2 period. During the T2 period, by sequentially performing driving during the T2-1 period and driving during the T2-2 period, the operation of reading the output signal from the first pixel 30-1 to the first memory 40-1 and the operation of reading the output signal from the second pixel 30-2 to the second memory 40-1 can be performed exclusively.

[0061] The operation of reading the output signal of the first pixel 30-1 to the first memory 40-1 during the T2-1 period will be described.

[0062] During the period from time t2-1 to time t2-13, PSEL1 is Hi and PSEL2 is Lo.

[0063] During the period from time t2-1 to time t2-13, the source of the amplification transistor 1005-1 of the first pixel 30-1 is connected to the first current source 2020 through the selection transistor 2001-1.

[0064] 5(b), the switch 2021 is turned ON when reading out signals from the first pixel 30-1 and the second pixel 30-2. In other words, the switch 2021 is turned ON when the first current source 2020 is used as a current source load for the amplification transistor 1005-1 or the amplification transistor 1005-2, and may be turned OFF during other periods.

[0065] At time t2-1, PRES1 goes high, the reset transistor 1006-1 turns on, and the gate of the amplification transistor 1005-1 is reset by SVDD.

[0066] At time t2-2, PRES1 goes low, completing the resetting of the gate of the amplifying transistor 1005-1.

[0067] During the period from time t2-3 to time t2-4, WR_N1 becomes Hi. WR_N1 is a control signal for switch 2002-1, and during this period, the voltage that resets the gate of amplifier transistor 1005-1 is written to signal holding unit 2003-1 via amplifier transistor 1005-1. This signal is called the N signal.

[0068] Between time t2-5 and time t2-6, PTXA1 goes high, the transfer transistor 1003-1 turns on, and the charge photoelectrically converted by the PD 1001-1 is read out to the gate of the amplification transistor 1005-1.

[0069] During the period from time t2-7 to time t2-8, WR_A1 becomes Hi. WR_A1 is a control signal for switch 2004-1. During the period from time t2-5 to time t2-6, the charge of PD 1001-1 read out to the gate of amplifying transistor 1005-1 is converted into a voltage by amplifying transistor 1005-1 and written to signal holding unit 2005-1. The written signal is called the SA signal.

[0070] During the period from time t2-9 to time t2-10, PTXA1 and PTXB1 are Hi. The transfer transistor 1003-1 and transfer transistor 1004-1 are turned ON, and the charges photoelectrically converted by PD1001-1 and PD1002-1 are read out to the gate of the amplification transistor 1005-1.

[0071] During the period from time t2-11 to time t2-12, WR_AB1 becomes Hi. WR_AB1 is a control signal for switch 2006-1. During the period from time t2-9 to t2-10, the charges of PD1001-1 and PD1002-1 that are read out to the gate of amplifier transistor 1005-1 are written to signal holding unit 2007-1 via amplifier transistor 1005-1. This signal is called the SAB signal.

[0072] At time t2-13, PSEL1 becomes Lo and PSEL2 becomes Hi, which turns off the selection transistor 2001-1 and electrically disconnects the electrical path between the amplification transistor 1005-1 of the first pixel 30-1 and the first current source 2020. On the other hand, the selection transistor 2001-2 turns on, connecting the amplification transistor 1005-2 of the second pixel 30-2 and the first current source 2020.

[0073] During the subsequent period from time t2-13 to time t2-14, an operation of writing the signal of the second pixel 30-2 into the second memory 40-1 is performed in the same manner as the operation of writing the signal of the first pixel 30-1 into the memory.

[0074] Here, the lengths of the T2-1 period and the T2-2 period are both ΔTa.

[0075] To synchronize the charge accumulation times of the photodiodes of the first pixel 30-1 and the second pixel 30-2, the timing at which PTXA2 and PTXB2 operate is ΔTa later than the timing at which PTXA1 and PTXB1 operate during the T1 period. During the T2 period, the timing at which the signal of the second pixel 30-2 is written to the second memory 40-1 is shifted by ΔTa from the timing at which the signal of the first pixel 30-1 is written to the first memory 40-1.

[0076] If the photodiode reset period of the first pixel 30-1 and the photodiode reset time of the second pixel 30-2 are not shifted during the T1 period, the resulting difference in accumulation time may be corrected either inside or outside the chip.

[0077] In addition, in the T2 period, PMRST1, PMRST2, PMSEL1, and PMSEL2 are Lo.

[0078] Next, a method for reading signals from the memory 40 to the column signal processing circuit 50 will be described with reference to FIG. 5(c). The period from t3-0 to t3-14 in FIG. 5(c) is called the T3 period. PRES1, PRES2, PTXA1, PTXA2, PTXB1, and PTXB2 are driven at Lo or pulse-driven.

[0079] Between time t3-1 and time t3-13, PMSEL1 and PMSEL2 are set to Hi. This turns on the selection transistors 2010-1 and 2010-2. The source of the first amplification transistor 2009-1 in the first memory 40-1 is connected to the current source 301-1, and the source of the second amplification transistor 2009-2 in the second memory 40-2 is connected to the current source 301-2.

[0080] The switches 302-1 and 302-2 are controlled by a control signal PWR2 (not shown). The control signal PWR2 is Hi during the period T3, and is at an arbitrary value during other periods.

[0081] During the period from time t3-1 to time t3-2, PMRST1 and PMRST2 are set to Hi, which turns on the reset transistors 2008-1 and 2008-2, resetting the gate of the first amplification transistor 2009-1 and the gate of the second amplification transistor 2009-2 to MVDD.

[0082] During the period from time t3-3 to time t3-4, WR_N1 and WR_N2 are set to Hi, and switches 2002-1 and 2002-2 are turned ON. The N signal of the first pixel 30-1 held in the signal holding unit 2003-1 is read out to the ADC 303-1 via the first amplification transistor 2009-1. The N signal of the second pixel 30-2 held in the signal holding unit 2003-2 is read out to the ADC 303-2 via the second amplification transistor 2009-2. Between time t3-4 and time t3-5, each ADC performs AD conversion of each N signal.

[0083] During the period from time t3-5 to time t3-6, PMRST1 and PMRST2 are set to Hi, and the reset transistors 2008-1 and 2008-2 are turned ON. The gate voltage of the first amplification transistor 2009-1 and the gate voltage of the second amplification transistor 2009-2 are reset to MVDD.

[0084] During the period from time t3-7 to time t3-8, WR_A1 and WR_A2 are set to Hi, and switches 2004-1 and 2004-2 are turned ON. The SA signal held in signal holding unit 2005-1 is read out to ADC 303-1 via first amplification transistor 2009-1. The SA signal held in signal holding unit 2005-2 is read out to ADC 303-2 via second amplification transistor 2009-2. Between time t3-8 and time t3-9, each ADC performs AD conversion of each SA signal.

[0085] During the period from time t3-9 to time t3-10, PMRST1 and PMRST2 are set to Hi, and the reset transistors 2008-1 and 2008-2 are turned ON. The gate voltage of the first amplification transistor 2009-1 and the gate voltage of the second amplification transistor 2009-2 are reset to a voltage based on MVDD.

[0086] During the period from time t3-11 to time t3-12, WR_AB1 and WR_AB2 are set to Hi, and switches 2006-1 and 2006-2 are turned ON. The SAB signal held in signal holding unit 2007-1 is read out to ADC 303-1 via first amplification transistor 2009-1. The SAB signal held in signal holding unit 2007-2 is read out to ADC 303-2 via second amplification transistor 2009-2. During the period from time t3-12 to time t3-13, each ADC performs AD conversion of the SAB signal.

[0087] FIG. 6 is a plan view showing the positions of the first junction 1100-1, the second junction 1100-2, and the first current source 2020 of the photoelectric conversion device of this embodiment.

[0088] 6, a first pixel 30-1 and a second pixel 30-2 are arranged adjacent to each other in the vertical direction (for example, the column direction), with a first junction 1100-1 arranged in the first pixel 30-1 and a second junction 1100-2 arranged in the second pixel 30-2. Between the first junction 1100-1 and the junction 1100-2 is a 2020 arrangement region in which a first current source 2020 is arranged.

[0089] Here, each joint is formed by joining a first connection part provided in a first wiring layer included in the first wiring structure and a second connection part provided in a second wiring layer included in the second wiring structure. The first connection part and the second connection part are conductors made of, for example, Cu, and the joint surfaces including the sea surfaces between the joint parts also connect the insulators adjacent to each of the first and second connection parts. The first and second joint parts may be so-called Cu-Cu bonding.

[0090] In this embodiment, the first pixel 30-1 and the second pixel 30-2 are adjacent to each other, but this arrangement is not limiting. The first current source 2020 may be arranged between the junctions 1100 of the multiple pixels 30 that share the first current source 2020.

[0091] Furthermore, sensors that acquire color images by providing color filters on the light incident surface side of each pixel are generally known. The pixels of the photoelectric conversion device according to this embodiment may also be provided with color filters. In this case, the first pixel 30-1 and the second pixel 30-2 may be pixels provided with color filters corresponding to the same color (color filters of the same color), or may be pixels provided with color filters corresponding to different colors (color filters of different colors).

[0092] According to this embodiment, the first current source 2020 is shared by two pixels, thereby improving the layout efficiency of elements including the first current source 2020, and making it easier to form a layout pattern with a reduced pixel area.

[0093] Furthermore, peak current can be reduced by sequentially reading pixel signals from multiple pixels 30 that share the first current source 2020. In a global electronic shutter configuration, all pixel signals are read simultaneously, resulting in a large current flow during peak periods, potentially causing electromigration. Furthermore, the increased heat generated by the current requires a larger thermal capacity for the photoelectric conversion device, potentially resulting in issues such as an increased housing size. Furthermore, this can result in a reduction in the number of images that can be captured per unit time and faster battery consumption. By sequentially reading pixel signals from multiple pixels 30 to the memory 40, peak current is less likely to occur, thereby resolving these issues. Note that the readout timing lag when sequentially reading pixel signals from multiple pixels 30 to the memory 40 is sufficiently small, approximately several tens of microseconds.

[0094] Although this embodiment has been described assuming that the current source is provided in the second semiconductor layer of the memory chip 200, the current source may also be provided in the first semiconductor layer of the pixel chip or the third semiconductor layer of the signal processing chip depending on the arrangement of elements in each semiconductor layer.

[0095] (Second embodiment) In this embodiment, the number of pixels 30 sharing the first current source 2020 is increased to four. The following description will mainly focus on the differences from the first embodiment, and a description of the commonalities will be omitted.

[0096] FIG. 7 shows a circuit diagram of the pixel 30, memory 40, and column signal processing circuit 50 of this embodiment.

[0097] A third pixel 30-3, a fourth pixel 30-4, a third memory 40-3, and a fourth memory 40-4 are added to the first embodiment. Also, ADCs 303-3, ADCs 303-4, current sources 301-3, and current sources 301-4 are added as column signal processing circuits 50 corresponding to the third memory 40-3 and the fourth memory 40-4.

[0098] The source of the selection transistor 2001-3 (third switch) of the third memory 40-3 and the source of the selection transistor 2001-4 (fourth switch) of the fourth memory 40-4 are connected to the drain of the first current source 2020. The first current source 2020 is shared as a current source load for the first amplification transistor 2009-1, the second amplification transistor 2009-2, the third amplification transistor 2009-3, and the fourth amplification transistor 2009-4 corresponding to the first pixel 30-1 to the fourth pixel 30-4.

[0099] The operation of this embodiment will be described with reference to FIGS.

[0100] The relationship between the T1 period, the T2 period, and the T3 period in this embodiment will be described with reference to FIG.

[0101] The difference from the first embodiment is that the T2 period is composed of a T2-1 period, a T2-2 period, a T2-3 period, and a T2-4 period. As in the first embodiment, the T3 period_all is a collective term for a plurality of T3 periods.

[0102] In this embodiment, signals are simultaneously read from the memory 40 to the column signal processing circuit 50 for four pixels during the T3 period. Therefore, assuming that the four pixels sharing the first current source 2020 are in different rows, if the number of rows of pixels 30 is N, the T3 period is repeated N / 4 times during the T3 period_all. Here, the pixels sharing the current source may be arranged in the horizontal direction (row direction). In this case, the number of times the T3 period is repeated increases. The number of times the T3 period is repeated can be reduced by increasing the number of pairs of pixels 30 read from the memory 40 to the column signal processing circuit 50.

[0103] 9(a) is a pulse diagram for the T1 period, and FIG. 9(b) is a pulse diagram for the T2 period. The T3 period is the same as in the first embodiment, so the drawings and explanation will be omitted.

[0104] The difference between the first embodiment and the T1 period in FIG. 9(a) is that between time t1-0 and time t1-4, photodiode reset operations are sequentially performed not only on the first pixel 30-1 and the second pixel 30-2 but also on the third pixel 30-3 and the fourth pixel 30-4.

[0105] As in the first embodiment, after PTXA1 and PTXB1, which are the photodiode reset operation of the first pixel 30-1, go to Hi, PTXA2 and PTXB2 of the second pixel 30-2 go to Hi after ΔTa. After that ΔTa, PTXA3 and PTXB3 of the third pixel 30-3 go to Hi, and further after ΔTa, PTXA4 and PTXB4 of the fourth pixel 30-4 go to Hi. As in the first embodiment, each PTXA and PTXB is Hi for a period ΔTx and then goes to Lo.

[0106] The reason why PTXA and PTXB of each pixel have a phase difference of ΔTa is to match the accumulation time of each photodiode, as in the first embodiment. If the accumulation times are not matched by driving, correction corresponding to the accumulation time difference may be performed inside or outside the chip.

[0107] During the time from T1-0 to T1-4, PSEL is fixed to Lo. On the other hand, the T1 period and the T3 period may be operated so as to overlap, and WR_N, WR_A, WR_AB, PMRST, and PMSEL are fixed to Lo or operate in pulse mode.

[0108] The difference between the T2 period in FIG. 9B and the first embodiment is that the T2-2 period is followed by the T2-3 period and the T2-4 period. In this embodiment, the current source 2020 is shared by the first pixel 30-1, the second pixel 30-2, the third pixel 30-3, and the fourth pixel 30-4. This is because the signals of the first pixel 30-1, the second pixel 30-2, the third pixel 30-3, and the fourth pixel 30-4 are written to the first memory 40-1, the second memory 40-1, the third memory 40-3, and the fourth memory 40-4 in sequence. A detailed description of the operation is omitted here, as it is the same as in the first embodiment.

[0109] The T3 period is the same as that shown in FIG. 5(c) in the first embodiment. In the first embodiment, the first memory 40-1 and the second memory 40-2 are simultaneously read out to the column signal processing circuit. However, in this embodiment, the first memory 40-1, the second memory 40-2, the third memory 40-3, and the fourth memory 40-4 are simultaneously read out to the column signal processing circuit.

[0110] 10(a) and 10(b) are plan views showing the arrangement positions of a plurality of junctions 1100 and a current source 2020 in this embodiment.

[0111] 10(a) shows pixels 30 arranged in the vertical direction (column direction) that share a current source 2020. The current source 2020 is disposed between the second junction 1100-2 of the second pixel 30-2 and the third junction 1100-3 of the third pixel 30-3.

[0112] FIG. 10(b) shows a case where a current source 2020 is shared by four pixels, two vertically and two horizontally. The first pixel 30-1 and the third pixel 30-3 are aligned horizontally, while the first pixel 30-1 and the second pixel 30-2, and the third pixel 30-3 and the fourth pixel 30-4 are aligned vertically. The first pixel 30-1 has a first junction 1100-1, and the second pixel 30-2 has a second junction 1100-2. The third pixel 30-3 has a third junction 1100-3, and the fourth pixel 30-4 has a fourth junction 1100-4. The current source 2020 is disposed between the first junction 1100-1 and the fourth junction 1100-4 and between the second junction 1100-2 and the third junction 1100-3.

[0113] 10(a) and 10(b), a current source 2020 is arranged between two or more junctions 1100. When the photoelectric conversion device according to this embodiment is compatible with color images, the pixels sharing the current source 2020 may be pixels 30 corresponding to the same color or pixels 30 corresponding to different colors. Furthermore, four pixels 30 arranged in a Bayer pattern may share one current source 2020.

[0114] In this embodiment, the number of pixels sharing the current source 2020 is increased to four compared to the first embodiment, but the number of pixels sharing the current source 2020 is not limited to four. For example, the current source 2020 may be shared by nine pixels or sixteen pixels.

[0115] In this embodiment, similarly to the first embodiment, the current source 2020 is shared by multiple pixels, which reduces the limitations on the layout of the elements that make up the pixel and makes it easier to form a layout pattern with a reduced pixel area. Furthermore, by sequentially reading out pixel signals from multiple pixels 30 that share the current source 2020, the peak current can be reduced.

[0116] (Third embodiment) A photoelectric conversion device according to the third embodiment will be described with reference to Fig. 11 to Fig. 13. Fig. 11 shows a circuit diagram of the pixel 30, memory 40, and column signal processing circuit 50 of this embodiment. In the photoelectric conversion devices according to the first and second embodiments, each memory 40 has an amplifying transistor 2009. In the photoelectric conversion device according to this embodiment, one amplifying transistor 2009 is connected to and shared by multiple memories 40.

[0117] In the photoelectric conversion device according to this embodiment, the source of the selection transistor 2001-1 of the first memory 40-1 and the source of the selection transistor 2001-2 of the second memory 40-2 are connected to the drain of the current source 2020. If the drain of the current source 2020 is designated as node A, one terminal of each of the switches 2002-1, 2004-1, and 2006-1 of the first memory 40-1 is connected to node A. Furthermore, one terminal of each of the switches 2002-2, 2004-2, and 2006-2 of the second memory 40-2 is connected to node A.

[0118] Furthermore, a reset transistor 2008 is connected in series to MVDD at node A, and is further connected to the gate of an amplifying transistor 2009. The drain of the amplifying transistor 2009 is connected to MVDD, and the source is connected to the drain of a selection transistor 2010. The source of the selection transistor 2010 is connected to the input of the ADC 303 of the column signal processing circuit 50 and the drain of the current source 301 via a junction 2100. A switch 302 is connected in series between the source of the current source 301 and AGND. By providing the switch 302, it is possible to reduce power consumption by turning off the switch 302 when signals are not being read from the memory 40.

[0119] The operation of the photoelectric conversion device according to this embodiment during the T3 period will be described with reference to Fig. 12. The operation of the T1 period and the operation of the T2 period are the same as those shown in Figs. 5(a) and 5(b) described in the first embodiment, and therefore will not be described here.

[0120] The period from time t3-0 to time t3-13 is defined as the T3-1 period, and the period from time t3-13 to time t3-27 is defined as the T3-2 period. The T3-1 period is a period during which the first memory 40-1 is read out to the column signal processing circuit 50, and the T3-2 period is a period during which the second memory 40-1 is read out to the column signal processing circuit 50.

[0121] During the period from time t3-1 to time t3-26, PMSEL is set to Hi. The selection transistor 2010 is turned ON, and the source of the amplification transistor 2009 is connected to the input of the ADC 303 via the junction 2100.

[0122] During the period from time t3-1 to time t3-2, PMRST goes high, the reset transistor 2008 turns on, and the node A is reset to MVDD.

[0123] During the period from time t3-3 to time t3-4, WR_N1 goes Hi, switch 2002-1 turns ON, and the N signal held in signal holding unit 2003-1 is read out to node A. The N signal read out to node A is input to ADC 303 via amplifier transistor 2009.

[0124] During the period from time t3-4 to time t3-5, the N signal is AD converted by the ADC 303.

[0125] During the period from time t3-5 to time t3-6, PMRST goes high. Node A is reset again by MVDD.

[0126] During the period from time t3-7 to time t3-8, WR_A1 becomes Hi. The switch 2004-1 turns ON, and the SA signal held in the signal holding unit 2005-1 is read out to the node A.

[0127] During the period from time t3-8 to time t3-9, the SA signal read out to the ADC 303 via the signal amplifying transistor 2009 is AD converted.

[0128] During the period from time t3-9 to time t3-10, PMRST goes high. Node A is reset again by MVDD.

[0129] During the period from time t3-11 to time t3-12, WR_AB1 becomes Hi. The switch 2006-1 turns ON, and the SAB signal held in the signal holding unit 2007-1 is read out to node A.

[0130] Between time t3-12 and time t3-13, the SAB signal read out to the ADC 303 via the amplifying transistor 2009 is subjected to AD conversion.

[0131] During the period from time t3-14 to time t3-15, PMRST goes high. Node A is reset by MVDD.

[0132] During the period from time t3-16 to time t3-17, WR_N2 becomes Hi. The switch 2002-2 turns ON, and the N signal held in the signal holding unit 2003-2 is read out to the node A.

[0133] Between time t3-17 and time t3-18, the N signal read out to the ADC 303 via the amplifying transistor 2009 is AD converted.

[0134] During the period from time t3-18 to time t3-19, PMRST goes high. Node A is reset again by MVDD.

[0135] During the period from time t3-20 to time t3-21, WR_A2 becomes Hi. The switch 2004-2 turns ON, and the SA signal held in the signal holding unit 2005-2 is read out to the node A.

[0136] Between time t3-21 and time t3-22, the SA signal read out to the ADC 303 via the amplifying transistor 2009 is AD converted.

[0137] During the period from time t3-22 to time t3-23, PMRST goes high. Node A is reset again by MVDD.

[0138] During the period from time t3-24 to time t3-25, WR_AB2 becomes Hi. The switch 2006-2 turns ON, and the SAB signal held in the signal holding unit 2007-2 is read out to node A.

[0139] Between time t3-25 and time t3-26, the SAB signal read out to the ADC 303 via the amplifying transistor 2009 is AD converted.

[0140] At time 3-26, PMSEL goes low and the selection transistor 2010 turns off, thereby disconnecting the electrical connection between the amplification transistor 2009 and the ADC 303.

[0141] As described above, in this embodiment, not only the current source 2020 but also the reset transistor 2008, the amplifying transistor 2009, and the selection transistor 2010 are configured to be shared by the first memory 40-1 and the second memory 40-2. This allows for even greater layout efficiency than the photoelectric conversion devices according to the first and second embodiments.

[0142] 13 shows a circuit diagram of a modification of the third embodiment in which the select transistors 2001-1 and 2001-2 are arranged on the first semiconductor layer in which the photodiodes are formed. The operation is similar to that of the circuit shown in FIG. 11. Whether the select transistor 2001 is arranged on the first semiconductor layer or on the second semiconductor layer in which the memory is formed can be selected appropriately from the viewpoint of improving the performance of the device, such as the balance of the element areas arranged on each semiconductor layer and the amount of heat generation.

[0143] (Fourth embodiment) The fourth embodiment can be applied to any of the first to third embodiments. FIG. 14(a) is a schematic diagram illustrating a device 9191 including a semiconductor device 930 of this embodiment. The photoelectric conversion device of each of the above-described embodiments can be used for the semiconductor device 930. The device 9191 including the semiconductor device 930 will be described in detail. In addition to the semiconductor device 910, the semiconductor device 930 can include a package 920 that houses the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0144] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0145] The portion including at least one of the processing device 960, the display device 970, the storage device 980, and the mechanical device 990 is a processing unit having the function of processing signals from the semiconductor device 930 and generating an image.

[0146] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0147] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0148] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0149] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0150] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0151] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0152] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 14(b) and 14(c).

[0153] FIG. 14(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 80. The photoelectric conversion device 80 is the photoelectric conversion device (image capture device) described in any of the above embodiments. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 80, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0154] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0155] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear.

[0156] 14(c) shows the photoelectric conversion system when capturing an image of the area ahead of the vehicle (image capturing range 850). A vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 80. This configuration can further improve the accuracy of distance measurement.

[0157] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, and control of automatic driving to prevent deviation from a lane. Furthermore, the photoelectric conversion system is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0158] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0159] The disclosure of this embodiment includes the following configurations and methods.

[0160] (Configuration 1) The photoelectric conversion device has a plurality of pixels including a first pixel and a second pixel. Each of the plurality of pixels has a stacked configuration of a first semiconductor layer having a photoelectric conversion unit and a first readout circuit that reads out a signal based on photoelectric conversion in the photoelectric conversion unit, and a second semiconductor layer having a memory that stores a voltage corresponding to the signal and an output circuit that outputs the voltage stored in the memory. The first readout circuit of the first pixel includes a first amplification transistor, and the first readout circuit of the second pixel includes a second amplification transistor. The first amplification transistor is connected to a first current source via a first switch, and the second amplification transistor is connected to the first current source via a second switch, and the first amplification transistor and the second amplification transistor share the first current source.

[0161] (Configuration 2) 2. The photoelectric conversion device according to configuration 1, wherein the first current source is disposed in the second semiconductor layer.

[0162] (Configuration 3) The photoelectric conversion device according to configuration 1 or 2, wherein the plurality of pixels include a third pixel and a fourth pixel, the first readout circuit of the third pixel includes a third amplification transistor, and the first readout circuit of the fourth pixel includes a fourth amplification transistor. The third amplification transistor is connected to the first current source via a third switch, and the fourth amplification transistor is connected to the first current source via a fourth switch. The first amplification transistor, the second amplification transistor, the third amplification transistor, and the fourth amplification transistor share the first current source.

[0163] (Configuration 4) The photoelectric conversion device according to any one of Structures 1 to 3, further comprising: a first junction electrically connecting the first readout circuit of the first pixel to the memory, and a second junction electrically connecting the first readout circuit of the second pixel to the memory, wherein the first current source is disposed between the first junction and the second junction in a plan view.

[0164] (Configuration 5) The photoelectric conversion device according to any one of configurations 1 to 4, characterized in that a color filter is arranged in each of the first pixel and the second pixel, and the color filter arranged in the first pixel and the color filter arranged in the second pixel are color filters of the same color.

[0165] (Configuration 6) The photoelectric conversion device according to any one of configurations 1 to 4, characterized in that a color filter is arranged in each of the first pixel and the second pixel, and the color filter arranged in the first pixel and the color filter arranged in the second pixel are color filters of different colors.

[0166] (Configuration 7) 7. The photoelectric conversion device according to any one of configurations 1 to 6, wherein the first switch is disposed in the first semiconductor layer.

[0167] (Configuration 8) 8. The photoelectric conversion device according to any one of Structures 1 to 7, wherein the first switch and the second switch operate such that when one is ON, the other is OFF.

[0168] (Configuration 9) The photoelectric conversion device according to configuration 3, wherein the first switch, the second switch, the third switch, and the fourth switch operate such that when one is ON, the remaining three are OFF.

[0169] (Configuration 10) The photoelectric conversion device according to any one of configurations 1 to 9, wherein a third semiconductor layer having a second readout circuit that reads out a signal corresponding to the voltage held in the memory is further stacked on the second semiconductor layer.

[0170] (Configuration 11) The photoelectric conversion device according to configuration 4 includes a first chip and a second chip stacked on the first chip, wherein the first chip includes the first semiconductor layer and a first wiring structure electrically connected to the photoelectric conversion unit and the first readout circuit, and the second chip includes the second semiconductor layer and a second wiring structure electrically connected to the memory and the output circuit, and wherein a first connection portion provided in a first wiring layer included in the first wiring structure and a second connection portion provided in a second wiring layer included in the second wiring structure are joined to form the first joint portion.

[0171] (Configuration 12) The photoelectric conversion device described in configuration 11 further comprises a third chip, the third chip including a third semiconductor layer having a second readout circuit that reads out a signal corresponding to the voltage stored in the memory, and a third wiring structure electrically connected to the second readout circuit.

[0172] (Configuration 13) 13. The photoelectric conversion device according to configuration 12, wherein a signal passing through a wiring connecting the first chip and the second chip passes through a wiring of the third chip.

[0173] (Configuration 14) 14. The photoelectric conversion device according to any one of configurations 1 to 13, wherein the first switch and the second switch are disposed in the second semiconductor layer.

[0174] (Configuration 15) 14. The photoelectric conversion device according to any one of configurations 11 to 13, wherein the first switch and the second switch are disposed in the first semiconductor layer.

[0175] (Configuration 16) 16. A photoelectric conversion system comprising: the photoelectric conversion device according to any one of configurations 1 to 15; and a processing unit that generates an image using a signal output by the photoelectric conversion device.

[0176] (Configuration 17) 16. A moving body comprising the photoelectric conversion device according to any one of configurations 1 to 15, characterized in that the moving body has a control unit that controls the movement of the moving body using a signal output by the photoelectric conversion device. [Explanation of symbols]

[0177] 30 pixels 40 memory 1005 Amplifying transistor 1100 Joint 2020 current source 2021 Switch

Claims

1. A photoelectric conversion device having a plurality of pixels including a first pixel and a second pixel, Each of the plurality of pixels comprises: a first semiconductor layer having a photoelectric conversion unit and a first readout circuit that reads out a signal based on photoelectric conversion in the photoelectric conversion unit; a second semiconductor layer having a memory for storing a voltage corresponding to the signal and an output circuit for outputting the voltage stored in the memory; the first readout circuit of the first pixel includes a first amplification transistor; the first readout circuit of the second pixel includes a second amplification transistor; the first amplifying transistor is connected to a first current source via a first switch; the second amplifying transistor is connected to the first current source via a second switch; The photoelectric conversion device according to claim 1, wherein the first amplifying transistor and the second amplifying transistor share the first current source.

2. 2. The photoelectric conversion device according to claim 1, wherein the first current source is disposed in the second semiconductor layer.

3. the plurality of pixels includes a third pixel and a fourth pixel, the first readout circuit of the third pixel includes a third amplification transistor; the first readout circuit of the fourth pixel includes a fourth amplification transistor; the third amplifying transistor is connected to the first current source via a third switch; the fourth amplifying transistor is connected to the first current source via a fourth switch; 2. The photoelectric conversion device according to claim 1, wherein the first amplifying transistor, the second amplifying transistor, the third amplifying transistor, and the fourth amplifying transistor share the first current source.

4. a first junction electrically connecting the first readout circuit of the first pixel and the memory; a second junction electrically connecting the first readout circuit of the second pixel and the memory; 2. The photoelectric conversion device according to claim 1, wherein the first current source is disposed between the first junction and the second junction in a plan view.

5. a color filter is disposed in each of the first pixel and the second pixel; 2. The photoelectric conversion device according to claim 1, wherein the color filter disposed in the first pixel and the color filter disposed in the second pixel are color filters of the same color.

6. a color filter is disposed in each of the first pixel and the second pixel; 2. The photoelectric conversion device according to claim 1, wherein the color filter disposed in the first pixel and the color filter disposed in the second pixel are color filters of different colors.

7. The photoelectric conversion device according to claim 1 , wherein the first switch is disposed in the first semiconductor layer.

8. 2. The photoelectric conversion device according to claim 1, wherein the first switch and the second switch operate such that when one is ON, the other is OFF.

9. 4. The photoelectric conversion device according to claim 3, wherein the first switch, the second switch, the third switch, and the fourth switch operate such that when one is ON, the remaining three are OFF.

10. 2. The photoelectric conversion device according to claim 1, further comprising a third semiconductor layer stacked on the second semiconductor layer, the third semiconductor layer having a second readout circuit that reads out a signal corresponding to the voltage held in the memory.

11. a first chip and a second chip stacked on the first chip; the first chip includes the first semiconductor layer and a first wiring structure electrically connected to the photoelectric conversion unit and the first readout circuit, the second chip includes the second semiconductor layer and a second wiring structure electrically connected to each of the memory and the output circuit; a first connection portion provided in a first wiring layer included in the first wiring structure; The photoelectric conversion device according to claim 4 , wherein the first joint portion is formed by joining the first connecting portion and a second connecting portion provided in a second wiring layer included in the second wiring structure.

12. The photoelectric conversion device described in claim 11, further comprising a third chip, the third chip including a third semiconductor layer having a second readout circuit that reads out a signal corresponding to the voltage stored in the memory, and a third wiring structure electrically connected to the second readout circuit.

13. 13. The photoelectric conversion device according to claim 12, wherein a signal passing through a wiring connecting the first chip and the second chip passes through a wiring of the third chip.

14. 2. The photoelectric conversion device according to claim 1, wherein the first switch and the second switch are disposed in the second semiconductor layer.

15. 2. The photoelectric conversion device according to claim 1, wherein the first switch and the second switch are disposed in the first semiconductor layer.

16. The photoelectric conversion device according to any one of claims 1 to 15, a processing unit that generates an image using a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

17. A moving object comprising the photoelectric conversion device according to any one of claims 1 to 15, A moving body comprising a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

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