Image sensor packaging and methods for forming the same

Abstract

To provide a device structure which reduces a pixel size and eliminates the need for forming a substrate penetration via of a high aspect ratio.SOLUTION: A device structure of an image sensor element 40 may include a first chip 10 having a first substrate 102 and a first interconnect structure 110 which is disposed on the first substrate, a second chip 20 having a second substrate 202 and a second interconnect structure 210 which is disposed on the second substrate, and a third chip 30 having a third interconnect structure 310 and a third substrate 302 which is disposed on the third interconnect structure. The first interconnect structure is bonded to the second substrate via a first plurality of bonding layers 120. The second interconnect structure is bonded to the third interconnect structure via a second plurality of bonding layers 220. The third substrate includes a plurality of photodiodes 304 and a transfer gate transistor 306 which is disposed on the third substrate.SELECTED DRAWING: Figure 4

Description

[Background technology]

[0001] Complementary Metal Oxide Semiconductor (CMOS) Image Sensors (CIS) are a type of image sensor that is different from conventional charge-coupled devices. CMOS image sensors are becoming more popular than CCDs. Typically, CMOS image sensors are sensitive to light. It contains an array of picture elements (pixels) that convert photons into electrons using CMOS circuitry. The photodiode may typically be formed in a semiconductor substrate. When the photodiode is exposed to light, a charge is induced in the photodiode. , it can generate electrons proportional to the amount of incident light that hits the pixel. converted into a voltage signal within the The image sensor packaging is not suitable for its intended purpose. is generally adequate, but not entirely satisfactory. Summary of the Invention [Problem to be solved by the invention]

[0002] In recent years, complementary metal-oxide semiconductor (CMOS) image sensors (CIS) have become popular. In some existing technologies, the CIS image sensor is stacked on the logic chip. The pixel chip may include a photodiode and a pixel transistor. In some cases, logic chips include application specific integrated circuits (ASICs). The cell transistors are transfer gate (TX), source follower (SF), and reset These existing In this technology, numerous transistors in the pixel chip take up the space of the photodiode. This can make it difficult to reduce pixel size.

[0003] According to one aspect of the present invention, a first substrate and a first interconnect structure disposed on the first substrate are provided. a first die having a structure, a second substrate, and a second interconnect structure disposed on the second substrate; a second die having a third interconnect structure and a third interconnect structure disposed on the third interconnect structure; and a third die having a substrate of the first interconnect structure. The second interconnect is bonded to a second substrate by a first plurality of bonding layers. The structure is bonded to a third interconnect structure by a second plurality of bonding layers. The third substrate includes a plurality of photodiodes and a first transistor disposed on the third substrate. The second die includes a source electrically connected to the drain of the first transistor. a second transistor having a drain of the first transistor and a second transistor a third transistor having a gate electrically connected to the source of the third transistor; and a fourth transistor having a drain electrically connected to a source of the first transistor.

[0004] According to another aspect of the present invention, a semiconductor device includes a first plurality of bonding pad structures and a first die. The first die includes a device structure including a first plurality of bonding layers including the first plurality of bonding layers. a first interconnect structure disposed on the bonding layer; and a second interconnect structure disposed on the first interconnect structure. a first substrate on which a plurality of photodiodes are disposed; and a plurality of floating diffusion regions disposed between the diodes. Each is vertically aligned with one of the first plurality of bonding pad structures.

[0005] In accordance with yet another aspect of the present invention, a first plurality of bonding pad structures and a first die The method includes forming a first die including a first plurality of bonding layers including a first die. a first interconnect structure disposed on the bonding layer; and a second interconnect structure disposed on the first interconnect structure. a first substrate on which a plurality of photodiodes are disposed; a plurality of floating diffusion regions disposed between the diodes, each of the plurality of floating diffusion regions is vertically aligned with one of the first plurality of bonding pad structures. [Effects of the Invention]

[0006] The present invention provides a three-chip structure of an image sensor. The image sensor according to the present invention comprises: A first chip includes logic transistors, and a second chip includes pixel transistors. and a third chip containing a photodiode and a transfer gate. A source follower (SF), a reset transistor (RST), and a row selector ( By moving the SEL (e.g., SEL) to the second chip, more space is available in the third chip. This allows the use of a photodiode with a larger source, reducing the pixel size. Furthermore, the bonding layer can be used to bond the second and third chips together. This eliminates the need for high aspect ratio through-substrate vias after bonding. [Brief explanation of the drawings]

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. In accordance with standard industry practice, various features are not drawn to scale. Indeed, for clarity of illustration, the dimensions of various features may be arbitrarily increased or decreased. The accompanying drawings depict only typical embodiments of the invention and therefore should not be considered limiting in scope, as the invention is applicable to other embodiments as well. It is also emphasized that this is not the case.

[0008] [Figure 1] FIG. 1 is a schematic circuit diagram of an exemplary image sensor element. [Figure 2] 1 is a schematic circuit diagram of an image sensor element according to various aspects of the present invention; [Figure 3] 1 is a schematic circuit diagram of an alternative image sensor element according to various aspects of the present invention; [Figure 4] 1 is a schematic cross-sectional view of one embodiment of an image sensor structure constructed in accordance with various aspects of the present invention; [Figure 5] 1 shows a flowchart of a method for forming an image sensor element in accordance with one or more aspects of the present invention. [Figure 6] FIG. 2 is a schematic cross-sectional view of a third die including a photodiode according to various embodiments of the present invention. [Figure 7] 1 is a schematic cross-sectional view of a second die including a photodiode sensing circuit according to various embodiments of the present invention. [Figure 8] 8 is a schematic cross-sectional view of the second die of FIG. 7 bonded to the third die of FIG. 6 in accordance with various embodiments of the present invention. [Figure 9] 9 is a schematic cross-sectional view of the bonded die stack of FIG. 8 with the second die thinned, in accordance with various embodiments of the present invention. [Figure 10] 10 is a schematic cross-sectional view of the bonded die stack of FIG. 9 with bonding features formed on the second die, according to various embodiments of the present invention. [Figure 11] 11 is a schematic cross-sectional view of a first die bonded to the die stack of FIG. 10 in accordance with various embodiments of the present invention. [Figure 12]FIG. 12 is a schematic cross-sectional view of the die stack of FIG. 11 with the third die thinned in accordance with various embodiments of the present invention. [Figure 13] 1 is a schematic cross-sectional view of another embodiment of an image sensor structure constructed in accordance with various aspects of the present invention. [Figure 14] FIG. 10 is a schematic cross-sectional view of a third die including a photodiode according to various embodiments of the present invention. [Figure 15] FIG. 2 is a schematic cross-sectional view of a second die including photodiode sensing circuitry according to various embodiments of the present invention. [Figure 16] 16 is a schematic cross-sectional view of the second die of FIG. 15 bonded to the third die of FIG. 14 in accordance with various embodiments of the present invention. [Figure 17] FIG. 17 is a schematic cross-sectional view of the bonded die stack of FIG. 16 with the second die thinned in accordance with various embodiments of the present invention. [Figure 18] 18 is a schematic cross-sectional view of the bonded die stack of FIG. 17 with bonding features formed on the second die according to various embodiments of the present invention. [Figure 19] 18 is a schematic cross-sectional view of a first die bonded to the die stack of FIG. 17 in accordance with various embodiments of the present invention. [Figure 20] FIG. 20 is a schematic cross-sectional view of the die stack of FIG. 19 with the third die thinned in accordance with various embodiments of the present invention. [Figure 21] 1A-1C show schematic top views of two adjacent image sensor clusters according to various embodiments of the present invention. [Figure 22] 1 illustrates a schematic top view of an image sensor cluster and electrical routing therearound, in accordance with various aspects of the present invention. [Figure 23] 1 shows a schematic cross-sectional view of an image cluster and electrical routing therearound in accordance with various aspects of the present invention; [Figure 24] 1A-1C show schematic cross-sectional views of a first type of bonding layer according to various embodiments of the present invention. [Figure 25] 3A-3C show schematic cross-sectional views of a second type of bonding layer according to various embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following disclosure provides a number of different embodiments for implementing different features of the provided subject matter. To simplify the present invention, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, In the following description, the formation of a first feature above or on a second feature refers to the formation of a first and This may include embodiments in which the second feature is formed in direct contact, and the additional feature is formed in the first and Embodiments in which the second feature can be formed between the first and second features without direct contact Furthermore, the present invention may also include repeated numbers and / or descriptions in various examples. This repetition is for the purposes of simplicity and clarity and is not, in itself, an explanatory The present disclosure does not necessarily imply a relationship between the various embodiments and / or configurations.

[0010] Spatially relative terms such as "below," "belower," "low," "upper," and "above" are used to make explanations easier. For ease of illustration, the relationship between one component or feature and another component or feature may be omitted from the drawings. Spatially relative terms may be used herein to describe the It is intended to encompass various orientations of the device in use or operation in addition to the orientation in which it is used. The device may be oriented in other ways (rotated 90 degrees or at other orientations) and the terms used herein may be used interchangeably. The spatially relative descriptors used may likewise be interpreted accordingly.

[0011] Furthermore, when a number or range of numbers is described as "about," "approximately," or the like, the term is used to refer to a range of values ​​that are within the skill of the art. As understood by the person skilled in the art, the number should be within a reasonable range, taking into account the variations inherent in manufacturing. For example, a number or range of numbers is intended to include the features associated with the numbers. ±10% of the stated number based on known manufacturing tolerances associated with manufacturing the features For example, a thickness of "about 5 nm" is used to refer to a reasonable range inclusive of the stated number. The layer of material to be formed can encompass a dimension range of 4.25 nm to 5.75 nm, and the material The manufacturing tolerances associated with the placement of material layers are known by those skilled in the art to be ±15%. Furthermore, the present invention may repeat symbols and / or characters in various examples. The repetition is for the purposes of simplicity and clarity and, as such, may be misleading in the various embodiments described. and / or does not imply any relationship between the components.

[0012] In recent years, complementary metal-oxide semiconductor (CMOS) image sensors (CIS) have become popular. In some existing technologies, the CIS image sensor is stacked on the logic chip. The pixel chip may include a photodiode and a pixel transistor. In some cases, logic chips include application specific integrated circuits (ASICs). The cell transistors are transfer gate (TX), source follower (SF), and reset These existing In this technology, numerous transistors in the pixel chip take up the space of the photodiode. This can make it difficult to reduce pixel size.

[0013] The present invention provides a three-chip structure of an image sensor. The image sensor according to the present invention comprises: A first chip includes logic transistors, and a second chip includes pixel transistors. and a third chip containing a photodiode and a transfer gate. The second chip includes a first substrate and a first interconnect structure disposed on the first substrate. The third chip includes a second interconnect structure disposed on the second substrate. a third substrate disposed on the first chip and the third interconnect structure; The first interconnect structure is bonded to the second substrate via a bonding layer. The second interconnect structure is also bonded to a third interconnect structure via a bonding layer. The pixel transistors (source follower (SF), reset transistor Moving transistors (RST) and row selectors (SEL) to a second chip This allows more space in the third chip to be used for the photodiode. This allows for a reduction in pixel size. This allows for high aspect ratio through-substrate vias after bonding the second and third chips. There is no need to form

[0014] FIG. 1 shows a schematic circuit diagram of an image sensor device 40 having a two-chip configuration. In the image sensor element 40, a complementary metal-oxide semiconductor (CMOS) image sensor As shown in FIG. 1, the image sensor element 40 includes an ASIC circuit 12, A row selector transistor 22, a source follower transistor 24, and a reset transistor 26, a transfer gate transistor 32, and a photodiode 34. Thus, the photodiode 34 is connected to the ground G and the source of the transfer gate transistor 32. The drain of the transfer gate transistor 32 and the reset transistor 26 are connected between the The source of the source follower transistor 24 and the gate of the source follower transistor 25 are all connected to the floating diffusion (FD) node. The source of the source follower transistor 24 is connected together at the row selector The source of row selector transistor 22 is coupled to the drain of AS In some existing technologies, the ASIC circuit 12 is coupled to the first chip. A row selector transistor 22, a source follower transistor 24, a resistor 26, a resistor 28, a resistor 29, a resistor 30, a resistor 31, a resistor 32, a resistor 33, a resistor 34, a resistor 35, a resistor 36, a resistor 37, a resistor 38, a resistor 39 ... The set transistor 26, the transfer gate transistor 32, and the photodiode 34 are In the example shown in FIG. 1, the first chip 10 is fabricated on a logic chip 30. The third chip 30 is also called a pixel chip 3. The third chip 30 is bonded to the first chip 10 and is shown in FIG. In the two-chip structure shown in FIG. The chip 30 includes not only a photodiode 34 but also a row selector transistor 22, a source Follower transistor 24, reset transistor 26, and transfer gate transistor 3 2. The presence of these transistors takes up space in the third chip 30 and The light-sensitive area of ​​the photodiode 34 can be limited. The diode 34 has four transistors, which allows for the ability to reduce pixel dimensions. Power is hindered.

[0015] FIG. 2 is a schematic diagram of an image sensor device 40 having a three-chip structure according to various embodiments of the present invention. 2. Similar to the image sensor element 40 shown in FIG. The image sensor element 40 also includes the ASIC circuit 12, the row selector transistor 22, and the source filter. a follower transistor 24, a reset transistor 26, and a transfer gate transistor 32 and a photodiode 34, which are electrically connected in the same manner. The node 34 is connected between ground G and the source of the transfer gate transistor 32 . The drain of the transfer gate transistor 32, the source of the reset transistor 26, and the source The gates of the follower transistors 24 are all connected together at a floating diffusion (FD) node 36. The source of the source follower transistor 24 is connected to the row selector transistor 22. The drain and source of row selector transistor 22 are coupled to ASIC circuit 12 . As shown in Figure 2, the ASIC circuit 12 is fabricated on a first chip 10. a source follower transistor 22, a source follower transistor 24, and a reset transistor 2 6 and are fabricated on the second chip 20. The transfer gate transistor 32 and the photodiode Diode 34 is fabricated on the third chip 30. In the illustrated embodiment, the first chip The first chip is called the logic chip 10 or ASIC chip 10, and the second chip 20 is the pixel The third chip 30 is also called the pixel device chip 30. The first chip 10, the second chip 20, and the third chip 30 are bonded together. The three chips shown in FIG. In the structure, the third chip 30 contains a photodiode 34 and a transfer gate transistor 32. Compared to the image sensor element 40 of FIG. 2, the source follower transistor 24, and the reset transistor 26 are the third chip The transaction present in the third chip 30 is removed from the third chip 30 and moved to the second chip 20. The reduction in resistor not only increases the space available for the photodiode 34, This also helps reduce pixel size. The transfer gate transistor 32 is also moved to the second chip 20. The need to move the photodiode 34 to create more space for the photodiode 34 is It follows logically, but in state-of-the-art image sensor structures it extends to the photodiode 34. If not, the transfer gate transistor 32 does not need to be adjacent to the photodiode 34. Therefore, the transfer gate transistor 32 is shown in FIG. 2 and other figures of the present invention. The transfer gate transistor 32 remains located on the third chip 30. If new designs emerge that allow for further separation from node 34, the transfer gate transistor The star 32 may be moved to the second chip 20.

[0016] The image sensor element 40 of FIG. 2 has four transistors (i.e., row selector transistors). a source follower transistor 22, a source follower transistor 24, a reset transistor 26, and a transfer gate The image sensor element 40 includes four transistors (4T For example, the image sensor element 40 may include a photodiode. A pixel reset transistor for resetting the gate or a capacitor for storing charge Pasticated (e.g., metal-insulator-metal, The capacitor may include a metal-insulator-metal (MIM) capacitor or a deep trench capacitor. The image sensor includes an additional pixel device 28 representing a reset transistor or capacitor. The sensor element 40 is shown. To save space on the third chip 30, additional pixel elements are The additional pixel device 28 is fabricated on the second chip 20. Note that the electrical It should be understood that the electrical connections are for illustrative purposes only. The transistor 28 must be connected to the source of the row selector transistor 22 or the ASIC circuit 12. There is no.

[0017] Depending on design needs, the image sensor element 40 shown in FIG. 2 may be modified as shown in FIGS. Generally speaking, the image shown in FIG. The sensor element 40 is a small, compactly packed photodiode for increased pixel density. 12 includes a full-saturation capacitance (Ful Larger photodiodes to increase or maximize well capacity The former benefits from the three-chip structure of the present invention, which is Most of the transistors (except for the transfer gate transistor 32) are moved to the second chip. Since the elimination of the pixel transistor allows the photodiode size to be maximized, The latter also benefits from the three-chip structure of the present invention, which is This is because the movement of the photodiode allows the size of the photodiode to be minimized.

[0018] Reference is now made to Figure 4. The image sensor device 40 of Figure 4 comprises a first chip 10 and a second chip 11. The first chip 10 includes a first chip 20 and a third chip 30. The first chip 10 is mounted on a first substrate 102. and a first interconnect structure 110 disposed on the first substrate 102. A transistor 104 is fabricated in a first substrate 102. The first chip 10 The second chip 2 includes a first bonding layer 120 disposed on the interconnect structure 110. 0 includes a second substrate 202 and a second interconnect structure 210 disposed on the second substrate 202. a row selector transistor 204, a source follower transistor 206, and The reset transistor 208 is fabricated in the second substrate 202. 0 includes a second bonding layer 220 disposed on the second interconnect structure 210 and a second and a third bonding layer 240 disposed on the substrate 202. The bonding contacts of layer 240 are formed by through-substrate vias (TS) that extend completely through second substrate 202. The third chip 30 is electrically coupled to the third substrate 302. and a third interconnect structure 310 disposed on the substrate 302. The third substrate 302 is A plurality of deep trench isolation (DTI) features 330 are separated by The photodiode 304 includes a transfer gate transistor 306. 04 to collect the photoelectrons. The gates of the phototransistors 306 extend vertically into the respective photodiodes 304. Such a gate is also called a vertical transfer gate. The floating diffusion region 308 is formed by ion implantation. Thus, the photodiode 304 is formed in the third substrate 302. The opening of the photodiode 304 is formed by a metal grid. The third chip 30 is defined by a color filter layer 336 and a micro-pixel. For electrical connection, the third chip 30 has metal pads 3 The image sensor element 40 of FIG. 4 is disposed on the third interconnect structure. The image sensor element 40 includes a photodiode 304 illuminated on the back side. The third chip 30 is a third chip. A fourth bonding layer 320 is disposed on the interconnect structure 310 .

[0019] For the avoidance of doubt, the first chip 10 shown in FIG. 4 is generally the same as that shown in FIG. The second chip 20 shown in FIG. 4 corresponds to the first chip 10 shown in FIG. 3. The third chip 30 shown in FIG. Generally, this corresponds to the third chip 30 shown in Figures 2 or 3. For example, the first chip 30 in Figures 1 to 4 The chip 10 includes logic transistors (or ASIC transistors). The second chip 20 includes a row selector transistor, a source follower transistor, and a The third chip 30 in FIGS. 2 to 4 includes a photodiode and a set transistor. and a transfer gate transistor.

[0020] Continuing to refer to FIG. 4, the second chip 20 has the first bonding layer 120 connected to the third The first chip 10 is bonded by direct bonding to the bonding layer 240. Therefore, the second substrate 202 is adjacent to the first interconnect structure 110 and The second interconnect structure 210 is spaced apart from the first interconnect structure 110. 0 directly bonds the second bonding layer 220 to the fourth bonding layer 320. 2. The third interconnection The structure 310 is adjacent to the second interconnect structure 210, and the third substrate 302 is adjacent to the second interconnect structure 210. It is separate from the follow-up structure 210.

[0021] FIG. 5 illustrates a flow diagram of a method 500 for forming the image sensor element 40 shown in FIG. 4 or FIG. The method 500 is merely an example and should not be construed as limiting the invention to that explicitly illustrated. It is not intended to limit the scope of the present invention to the specific embodiments described herein, and additional steps may be provided before, during, and after method 500. Some steps described may be substituted for additional embodiments of the method. For ease of explanation, all references in this document are The steps will not be described in detail. 4, 6 to 25, which show partial cross-sectional views of different stages of the process. The X, Y, and Z directions in 25 are perpendicular to each other and are used consistently. Like numbers are used to denote like features throughout the present invention.

[0022] 4 and 6-12 illustrate the fabrication of the image sensor element 40 of FIG. 4 using the method 500 of FIG. 5 to 8, the method 500 includes block 502, where pixel The device chip is bonded to the pixel chip by a first plurality of bonding layers. FIG. 6 shows the third chip 30, which is a pixel chip. The third substrate 302 and the third interconnect structure 310 are shown. For ease of reference, the third The chip 30 has a front surface 30F adjacent to the third interconnect structure 310 and a third substrate 302. The third substrate 302 is a bulk silicon (Si) substrate and includes an adjacent back surface 30B. Alternatively, the third substrate 302 may be an elemental semiconductor such as germanium (Ge), Silicon (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide Indium (InP), indium arsenide (InAs), and / or indium antimonide ( Compound semiconductors such as InSb, silicon germanium (SiGe), and gallium arsenide (GaAs). GaAsP, aluminum indium arsenide (AlInAs), aluminum gallium arsenide gallium indium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide alloy semiconductors such as GaInP and / or GaInAsP, or combinations thereof It may also include a combination.

[0023] The third substrate 302 includes a plurality of photodiodes 304. The third substrate 302 may include various doped regions to form the diode 304. In one embodiment, the third substrate 302 is a phosphorus (P), arsenic (As), or other n-type dopant. The third chip 30 may include an n-type dopant such as a photodiode. A transfer gate is located adjacent to the photodiode 304 or extends into the photodiode 304 to collect photoelectrons. The third substrate 302 further includes a floating diffusion (FD) node 306. It further includes a heavily doped region between the photodiodes to form a 08. In this embodiment, the floating diffusion node 308 is heavily doped with n-type dopants (n+). The third interconnect structure 310 includes a plurality of metal layers. disposed on at least one etch stop layer and at least one intermetal dielectric (IMD) layer; The contact vias and metal lines are made of titanium, titanium nitride, or the like. Tantalum, tantalum nitride, cobalt, cobalt nitride, nickel, or nickel nitride The third interconnect structure 310 may include copper and a barrier layer formed by etching. The top layer may comprise silicon nitride, silicon carbide, silicon oxynitride, or a combination thereof. The IMD layer is made of tetraethoxysilane (TEOS) oxide, undoped ketone, and borophosphosilicate glass (BPSG), fused silica glass Ca glass, FSG), Phosphorus silicate glass (PSG), Boron-doped silicon glass (BS G), and / or other suitable dielectric materials.

[0024] The third chip 30 has a fourth bonding pad disposed on the front surface 30F of the third chip 30. That is, the fourth bonding layer 320 is connected to the third interconnect structure 310. These are placed on the board to provide a bonding surface and allow board-to-board communication. In this embodiment, the fourth bonding layer 320 is bonded to the first dielectric bonding layer 322. A plurality of bonding contacts 326 disposed on the second dielectric bonding layer 324. and a plurality of bonding pads 328 formed on the first dielectric bonding layer 322. and the second dielectric bonding layer 324 comprises silicon oxide or silicon oxynitride. The plurality of bonding contacts 326 and the plurality of bonding pads 328 may be made of copper (C u), Tantalum (Ta), Nickel (Ni), Cobalt (Co), Aluminum (Al) , combinations thereof, or alloys thereof. The bonding contact 326 and the plurality of bonding pads 328 comprise copper (Cu). As shown, each of the plurality of bonding pads 328 is formed by bonding a plurality of bonding pads along the Z direction. 326. As will be further described, each of the plurality of bonding pads 328 is connected to a floating diffusion (F D) Vertically aligned with 308.

[0025] 7 shows the second chip 20, which is a pixel device chip. , a second substrate 202 and a second interconnect structure 210. For ease of reference, The second chip 20 has a front surface 20F adjacent to the second interconnect structure 210 and a second substrate 20 The second substrate 202 is a bulk silicon (Si) substrate. Alternatively, the second substrate 202 may be an elemental semiconductor such as germanium (Ge). , silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), phosphorus Indium arsenide (InP), indium arsenide (InAs), and / or indium antimonide Compound semiconductors such as InSb, silicon germanium (SiGe), and gallium phosphide GaAsP, aluminum indium arsenide (AlInAs), aluminum arsenide gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium phosphide alloy semiconductors such as GaInP and / or GaInAsP, or It may also include a combination of these.

[0026] The second substrate 202 includes a row selector transistor 204, a source follower transistor 205, and a 06, and reset transistor 208. Row selector transistor 204, source The follower transistor 206 and the reset transistor 208 are connected to the row selector transistor 22, source follower transistor 24, and reset transistor 26 The row selector transistor 204, the source follower transistor 206, and the The set transistor 208 is a planar transistor or a multi-gate transistor. An exemplary multi-gate transistor is a Fin-Be FinFET or Gate-All-Around (GAA) transistors A planar transistor may include a transistor having a gate electrode along one surface of the active area. It is so named because it contains a gate structure that can induce a planar channel region. FinFETs consist of a fin-shaped active area that originates from the substrate and a fin-shaped active area that and a gate structure disposed on the top surface and sidewalls of the GAA transistor. at least one channel member extending between the source / drain features; and and a gate structure completely surrounding the channel members. Because the GAA transistor is surrounded by a Depending on the shape and orientation, the channel material of a GAA transistor can be a nanosheet, a semiconductor, or a It is also called a wire, nanowire, nanostructure, nanopost, nanobeam, or nanobridge. In some cases, GAA transistors are referred to by the shape of the channel material. For example, a GAA transistor having one or more nanosheet channel members can be It is also called a gate transistor or nanosheet FET.

[0027] The second interconnect structure 210 includes multiple metal layers. Each of the multiple metal layers includes at least at least one etch stop layer and at least one intermetal dielectric (IMD) layer. The contact vias and metal lines are made of titanium, titanium nitride, or tantalum, tantalum nitride, cobalt, cobalt nitride, nickel, or nickel nitride. The third interconnect structure 310 may include an etch stop layer formed on the copper and barrier layers. The top layer may comprise silicon nitride, silicon carbide, silicon oxynitride, or a combination thereof. The IMD layer is tetraethoxysilane (TEOS) oxide, an undoped silicon dioxide. borophosphosilicate glass (BPSG), fused silica glass glass, FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG ), and / or other suitable dielectric materials.

[0028] The second chip 20 has a second bonding pad disposed on the front surface 20F of the second chip 20. That is, the second bonding layer 220 is connected to the second interconnect structure 210. These are placed on the board to provide a bonding surface and allow board-to-board communication. In this embodiment, the second bonding layer 220 is disposed within the third dielectric bonding layer 222. The third dielectric bonding layer 222 includes a plurality of bonding contacts 224 disposed thereon. The plurality of bonding contacts 224 may include silicon oxide or silicon oxynitride. Copper (Cu), Tantalum (Ta), Nickel (Ni), Cobalt (Co), Aluminum ( Al), combinations thereof, or alloys thereof. The bonding contacts 224 of the second bonding layer shown in FIG. 220 includes only bonding contacts and is similar to bonding pad 328. Note that this does not include the tag pad. Some alternatives not explicitly shown in Figure 7 In an embodiment, the second bonding layer 220 is vertically aligned with the bonding contacts. The semiconductor device may further include a plurality of bonding pads to which the semiconductor device is bonded.

[0029] Referring to FIG. 8, the operations at block 502 are performed by splitting the second chip 20 shown in FIG. 6. This involves flipping it over and bonding it to a third chip 30 as shown in FIG. A second bonding layer is provided to bond the second chip 20 to the third chip 30. One of the bonding contacts 224 in 220 is connected to a bond in the fourth bonding layer 320. The direct bonding process is then performed. Then, the second chip 20 is bonded to the third chip 30. As will be further described, a dielectric surface may be bonded to a dielectric surface and a metal surface may be bonded to a metal surface. The second bonding layer 220 and the fourth bonding layer 320 are bonded to the surface. To ensure a strong bond between the second bonding layer 220 and the fourth bonding layer The surfaces of the second bonding layer 220 and the fourth bonding layer 320 are bonded to each other. The process is performed by washing to remove organic and metallic contaminants. mixture (SPM), a mixture of ammonium hydroxide and hydrogen peroxide (SC1), or both. The organic contaminants on the second bonding layer 220 and the fourth bonding layer 320 are removed by using A mixture of hydrochloric acid and hydrogen peroxide (SC2) can be used to remove metal contamination. In addition to cleaning, the bonding contacts 224 and the bonding The pad 328 is treated with an argon plasma or a nitrogen plasma. The bonding contacts 224 and the bonding pads 32 can be activated. After the first and third dielectric bonding layers 322 and 323 are aligned, Van der Waals bonding of the bonding layer 222 and the bonding pad 328 Annealing to promote surface activated bonding (SAB) of bonding contacts 224 In the illustrated example, the first plurality of bonding layers in block 502 is It includes a second bonding layer 220 and a fourth bonding layer 320 .

[0030] 5 and 9, a method 500 includes a block for thinning a substrate of a pixel device chip. The chip stack shown in FIG. 8 corresponds to a pixel device chip. At block 504, the second substrate 202 of the second chip is thinned. The chip stack shown in FIG. 9 includes the third chip 30 and the second chip 20. The second substrate 202 is then subjected to multiple thinning and polishing steps to reduce its thickness. In an exemplary process, diamond wheels are used for rough grinding, fine grinding, and Grinding or ultra-fine grinding can be performed, and chemical mechanical polishing (CMP) processes can be performed. The ground second substrate 202 can be polished. This contributes to reducing the aspect ratio of the through-substrate opening of the through-plate via 226 (described below).

[0031] 5 and 10, the method 500 includes block 506, where through-substrate vias is formed through the substrate of the pixel device chip. The chip 20 corresponds to a pixel device chip, and in block 506, through-substrate vias (T TSVs 226 are formed through the second substrate 202 of the second chip 20. 6 redirects the electrical signal to the backside 20B of the second chip 20 to connect the third bonding The insulating layer 240 functions to connect with the insulating layer 240. In an exemplary process, reactive ion etching is used. Via openings through the second substrate 202 using dry etching such as (RIE) After the via opening is formed, a conductive material is placed in the via opening to form a TS. V226 is formed. The conductive material may include copper (Cu). To prevent migration, the via opening is lined with a barrier layer before the conductive material is deposited. In some cases, the barrier layer may include titanium nitride.

[0032] After the formation of the TSVs 226, a third bonding layer 240 is formed on the thinned second substrate 202. The third bonding layer 240 is formed within the fourth dielectric bonding layer 242. A plurality of bonding contacts 246 are disposed within the fourth dielectric bonding layer 242. and a plurality of bonding pads 248 disposed on the fourth dielectric bonding layer 242. and the fifth dielectric bonding layer 244 comprises silicon oxide or silicon oxynitride. The plurality of bonding contacts 246 and the plurality of bonding pads 248 may be made of copper ( Cu), Tantalum (Ta), Nickel (Ni), Cobalt (Co), Aluminum (Al ), combinations thereof, or alloys thereof. The bonding contact 246 and the plurality of bonding pads 248 comprise copper (Cu). As shown in FIG. 0, each of the plurality of bonding pads 248 is arranged along the Z direction. It is vertically aligned with or overlaps one of the bonding contacts 246. Each of the plurality of bonding contacts 246 is vertically aligned with one of the TSVs 226. are aligned.

[0033] 5 and 11, the method 500 includes block 508, where the logic chip The chip is bonded to the pixel device chip by a second plurality of bonding layers. The first chip 10 corresponds to the logic chip and is also called the logic chip 10. The chip 10 includes a first substrate 102 and a first interconnect structure disposed on the first substrate 102. For ease of reference, the first chip 10 includes a first interconnect structure 110. 110 and a back surface 10B adjacent to the front surface of the first substrate 102. The first substrate 102 may be a bulk silicon (Si) substrate. The substrate 102 may be an elemental semiconductor such as germanium (Ge), silicon carbide (SiC), or gas arsenide. Sodium (GaAs), Gallium Phosphide (GaP), Indium Phosphide (InP), Indium Arsenide Indium (InAs), and / or compound semiconductors such as indium antimonide (InSb) Conductors, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), arsenide Aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), Gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc. It may include any alloy semiconductor and / or GaInAsP, or a combination thereof.

[0034] The first substrate 102 includes a plurality of logic transistors 104. The transistor 104 corresponds to the ASIC circuit 12 shown in FIG. 104 is implemented using a planar transistor or a multi-gate transistor. An exemplary multi-gate transistor is a fin-based field-effect transistor. It may include FinFET or gate-all-around (GAA) transistors. A planar transistor has a planar channel along one surface of the active area. FinFETs are so named because they contain a gate structure that can induce a channel region. The fin-shaped active region originating from the substrate and the top surface and sidewalls of the fin-shaped active region are The GAA transistor includes two source / drain filters and a gate structure arranged on the At least one channel member extending between the channels, and and a completely surrounding gate structure. Because the gate structure encases the channel member, G AA transistors are also called surround gate transistors (SGT). Accordingly, the channel material of the GAA transistor may be a nanosheet, a semiconductor wire, or a nanowire. , nanostructures, nanoposts, nanobeams, or nanobridges. AA transistors are sometimes referred to by the shape of the channel material. For example, one or more The GAA transistor having the above nanosheet channel material is also called a nanosheet transistor. is also called nanosheet FET.

[0035] The first interconnect structure 110 includes multiple metal layers. Each of the multiple metal layers includes at least at least one etch stop layer and at least one intermetal dielectric (IMD) layer. The contact vias and metal lines are made of titanium, titanium nitride, or tantalum, tantalum nitride, cobalt, cobalt nitride, nickel, or nickel nitride. The first interconnect structure 110 may include an etch stop layer formed on the copper and a barrier layer. The top layer may comprise silicon nitride, silicon carbide, silicon oxynitride, or a combination thereof. The IMD layer is tetraethoxysilane (TEOS) oxide, an undoped silicon dioxide. borophosphosilicate glass (BPSG), fused silica glass glass, FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG ), and / or other suitable dielectric materials.

[0036] The first chip 10 has a first bonding pad disposed on a front surface 10F of the first chip 10. That is, the first bonding layer 120 is connected to the second interconnect structure 210. The boards are placed on top of each other to provide bonding surfaces and allow board-to-board communication. In some embodiments, the first bonding layer 120 is formed within a sixth dielectric bonding layer 122. The sixth dielectric bonding layer 122 includes a plurality of bonding contacts 124 disposed on the sixth dielectric bonding layer 122. The bonding contacts 12 may include silicon oxide or silicon oxynitride. 4 is copper (Cu), tantalum (Ta), nickel (Ni), cobalt (Co), aluminum In one embodiment, the material may include aluminum (Al), a combination thereof, or an alloy thereof. The plurality of bonding contacts 124 includes copper (Cu). The bonding layer 120 includes only the bonding contact 124 and is the same as the bonding pad 328. Note that this does not include similar bonding pads. In some alternative embodiments, the first bonding layer 120 is perpendicular to the bonding contact. It may further include a plurality of vertically aligned bonding pads.

[0037] Referring to FIG. 11, the acts of block 502 include bonding the third bonding layer 240 and the first bonding layer 240 together. The first chip 10 is bonded to the second chip 20 by the bonding layer 120. In order to bond the first chip 10 to the second chip 20, The bonding contact 124 in the bonding layer 120 is connected to the third bonding layer 240. The direct bonding process is then performed. is performed to bond the first chip 10 to the second chip 20, as described below. so that dielectric surfaces are bonded to dielectric surfaces and metal surfaces are bonded to metal surfaces. The strong bonding between the first bonding layer 120 and the third bonding layer 240 To ensure bonding, the first bonding layer 120 and the third bonding layer 240 The surface is cleaned to remove organic and metallic contaminants. Sulfuric acid and hydrogen peroxide mixture (SPM), ammonium hydroxide and hydrogen peroxide mixture (SC1) , or both, to form the first bonding layer 120 and the third bonding layer 24 It is possible to remove organic contaminants on the surface of the scrubber using a mixture of hydrochloric acid and hydrogen peroxide (SC2). In addition to cleaning, it can also be used to remove metal contaminants. The points 124 and the bonding pads 248 are etched with an argon or nitrogen plasma. The bonding contacts 124 and the bonded After the bonding pads 248 are aligned, the sixth dielectric bonding layer 122 and the fifth The van der Waals force bonding of the dielectric bonding layer 244, as well as the bonding facilitating surface activated bonding (SAB) of the bonding pad 248 and the bonding contact 124. In the illustrated example, annealing is performed to remove the second plurality of blocks in block 508. The bonding layers include a first bonding layer 120 and a third bonding layer 240 .

[0038] 5 and 12, the method 500 includes block 510, where pixel The substrate of the chip is thinned. In FIG. 12, the third chip 30 corresponds to the pixel chip. , the third substrate 302 corresponds to the substrate of the pixel chip. After being bonded to the third chip 30, the back surface 30B of the third chip 30 is The chip stack shown in FIG. 11 is flipped over so that the third The third substrate 302 of the chip 30 may be thinned by a number of processes to reduce the thickness of the third substrate 302. In an exemplary process, a diamond wheel and a polishing step can be performed. The tool can be used to perform coarse, fine or ultra-fine grinding and chemical mechanical polishing (CM P) A process can be performed to polish the ground third substrate 302.

[0039] 4 and 5, the method 500 includes block 512, where an image sensor Further processing is performed to form the image sensor element 4 of FIG. 0 corresponds to the image sensor element referred to in block 512. The process includes forming deep trench isolation (DTI) features 330, Formation of metal grid 332, placement of passivation layer 334, and deposition of color filter layer 336. This may include forming a metal pad 340, forming a microlens 338, and forming a metal pad 340. Deep trenches are drilled into the third substrate 302 from the backside 30B to form I-features 330. (See Figure 12.) Next, the liner and filler are placed in the deep trench to form a D The DTI features 330 can be formed on the backside 30B. Since it is formed on the back surface, the DTI feature 330 is a back surface DTI (BDTI) feature 330. In some embodiments, the liner is made of aluminum (Al), tungsten (W). containing metals such as tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu) The filler may be silicon oxide, aluminum oxide, hafnium oxide, titanium oxide, Barium tantanoate, zirconium oxide, lanthanum oxide, barium oxide, strontium oxide , yttrium oxide, or a combination thereof.

[0040] The passivation layer 334 may be, for example, a first passivation layer and a second passivation layer. The composition of the passivation layer 334 may be such that the DTI features 33 The metal grid 332 may have the same composition as the filler of the first passivation layer. The metal grid 332 may be embedded in the first passivation layer and the second passivation layer. A grid-like structure or structure extending across some, if not all, of the diodes 304 is a framework. In some embodiments, the metal grid 332 is made of tin (Sn ), aluminum copper (AlCu), aluminum (Al), tungsten (W), ruthenium The metal grid 332 may include ruthenium (Ru), cobalt (Co), or copper (Cu). In an exemplary process for forming a metal layer, a metal layer is disposed over a first passivation layer. Then, using photolithography and etching processes, the metal layer is removed by metal grid. Next, a second passivation layer is formed on top of the metal grid 332. The layers are arranged.

[0041] The color filter layer 336 may be formed from a polymer material or a resin containing color pigments. At block 512, a color is applied to the second passivation layer of the passivation layer 334. A filter layer 336 is formed. The color filter layer 336 filters out light having a specific wavelength range. It includes multiple filters, each of which allows transmission of radiation (e.g., light) outside a specified range. Further referring to FIG. 4, the microlenses 338 are color filters. The microlenses 338 are formed on the filter layer 336. The microlenses 338 are made of a highly transparent acrylic polymer. It can be made of any material that can be patterned and formed into a microlens, such as In one embodiment, the microlens layer can be formed using a liquid state material and spin-on techniques. This method provides a substantially flat surface and a substantially uniform 338. It has been found to provide excellent uniformity. Other methods such as CVD and PVD can be used. The planar microlenses 338 corresponding to the photodiodes 304 may be arranged in an array. Using photolithography and etching techniques to pattern the material, The planar material of the lens layer can then be patterned. The planar material is then reflowed. This allows the microlens 338 to have an appropriate curved surface. can be cured using ultraviolet (UV) treatment.

[0042] To allow electrical connections through the thickness of the third substrate 302, the second substrate 202 is Cutting along the scribe lines exposes the contact features in the third interconnect structure 310. An opening is then formed to expose the metal pad. A metal layer is then placed over the opening. In some embodiments, the metal layer of the metal pad 340 is copper (C u), aluminum (Al), aluminum copper (AlCu) alloy, or titanium nitride But that's okay.

[0043] Continuing with reference to Figure 4, bonding pads 248 in third bonding layer 240 The bonding pads of the fourth bonding layer 320 are arranged at a first pitch P1 along the X direction. The pads 328 are arranged at a second pitch P2 along the X direction. A source follower (SF) 206, a reset transistor (RST) 208, and a row Selector (SEL) 204, etc.) to the second chip, This allows more space within the photodiode 304 to be available for the photodiode 304. As a result, the second pitch P2 is smaller than the first pitch In some embodiments, the second pitch relative to the first pitch P1 is The ratio of the first pitch P to the second pitch P can be from about 0.2 to about 0.75. The first pitch P1 may be between about 1.5 μm and about 2.5 μm, and the second pitch P2 may be between about 0.3 μm and about 2.5 μm. It may be between about 1.5 μm and about 1.5 μm.

[0044] 13-25 illustrate the fabrication of image sensor element 40 of FIG. 13 using method 500 of FIG. 5. 5 and 14-16, the method 500 includes block 502, where The pixel device chip is bonded to the pixel chip by a first plurality of bonding layers. FIG. 14 shows a third chip 30 corresponding to the pixel chip and a pixel device 2 and a corresponding second chip 20. A similar second chip 20 and a third chip 3 are shown. 0 has been described above, so a detailed explanation will be omitted. The differences between the embodiments will be described. Instead, the third substrate 302 contains a large photodiode 3040. As a result, as shown in FIG. The floating diffusion (FD) nodes 36 in the third chip 30 are spaced further apart. By installing a large photodiode 3040, the second chip 202 A small row selector transistor 204, a source follower transistor 206, and a reset The fourth bond pad 328 may include a second bond transistor 208. The bonding contact 326 in the bonding layer 320 is vertically aligned with the FD node 36 and is larger than the The bonding pads of the second bonding layer 220 are spaced apart to have a larger pad pitch. The bonding contacts 224 are configured to align with the bonding pads 328, The bonding contacts 224 are also more dispersed and spaced at a larger pitch. As shown, the second chip 20 has the second bonding layer 220 and the fourth bonding layer 32. 0 to the third chip 30.

[0045] Referring to FIGS. 5 and 17, a method 500 thins the substrate of a pixel device chip. The chip stack shown in FIG. 17 includes a pixel device chip. At block 504, the second substrate 202 of the second chip is The same operation has been described above with reference to FIG. 9, so a detailed description of FIG. 17 will be omitted. do.

[0046] 5 and 18, the method 500 includes block 506, where through-substrate vias As shown in FIG. 18, the second chip The chip 20 corresponds to a pixel device chip, and in block 506, through substrate vias (TSV ) 226 are formed through the second substrate 202 of the second chip 20. After formation, a third bonding layer 240 is formed on the thinned second substrate 202. As shown in FIG. 18, each of the plurality of bonding pads 248 includes a plurality of bonding pads. vertically aligned with or overlapping one of the contacts 246 along the Z direction. Furthermore, each of the plurality of bonding contacts 246 is perpendicular to one of the TSVs 226. The same operation was described above with reference to FIG. 10, so the detailed description of FIG. The explanation will be omitted.

[0047] 5 and 19, the method 500 includes block 508, where the logic chip The first substrate is bonded to the pixel device chip by a second plurality of bonding layers. The chip 10 corresponds to the logic chip and is also called the logic chip 10. includes a first bonding layer 120 disposed on the front surface 10F of the first chip 10. In some embodiments shown in FIG. 19, the first bonding layer 120 is a sixth dielectric The substrate bonding layer 122 includes a plurality of bonding contacts 124 disposed thereon. The first bonding layer 120 shown in FIG. 9 includes only bonding contacts 124. Note that this does not include a bonding pad similar to bonding pad 328. In some alternative embodiments not explicitly shown in Figure 9, the first bonding layer 120 The block further includes a plurality of bonding pads vertically aligned with the bonding contacts. In block 508, the first chip 10 is bonded to the third bonding layer 240 and the first bonding layer 241. The second chip 20 is bonded to the second chip 20 by a bonding layer 120. A similar operation is shown in FIG. 19 has been described above with reference to FIG. 1, so a detailed description of FIG. 19 will be omitted.

[0048] 5 and 20, a method 500 includes a block for thinning the substrate of a pixel chip. 20, the third chip 30 corresponds to the pixel chip, and the third substrate 3 02 corresponds to the substrate of the pixel chip. The same operation has been described above with reference to FIG. A detailed description of FIG. 20 will be omitted.

[0049] 5 and 13, the method 500 includes block 512, where an image sensor Further processing is performed to form the image sensor element. 40 corresponds to the image sensor element referred to in block 512. The process includes forming deep trench isolation (DTI) features 330; Formation of metal grid 332, placement of passivation layer 334, color filter layer 336 The formation of the metal pads 340 may include the formation of the microlenses 338. Such operations have been described above with reference to FIG. 4, and therefore detailed description of FIG. 13 will be omitted.

[0050] For the photodiode 304 of FIG. 4 or the large photodiode 3040 of FIG. To help maximize space, the photodiode 304 (or a large photodiode) The diodes 3040 can be grouped into clusters or units. A schematic top view of two adjacent clusters 400 is shown. In some embodiments, the clusters 400 each have four photodiodes 304 or four large photodiodes In these embodiments, two adjacent photodiodes 304 in FIG. Alternatively, the two adjacent large photodiodes 3040 in FIG. 13 may actually be clusters 40 Of the four photodiodes 304 (or large photodiodes 3040) in For ease of reference, FIG. 21 includes four photodiodes 304. It should be understood that this configuration is also applicable to larger photodiodes 3040. As shown, four photodiodes 304 are arranged around the FD node 308. Along the Z direction, each of the FD nodes 308 is connected to the fourth bond. The transfer gate transistor is aligned with a bonding pad 328 in the transfer gate layer 320. The photodiode 304 is connected to a common FD node 308. In this way, the four transfer gate transistors 306 are arranged in a The photoelectrons generated in the diode 304 can be collected and directed to the FD node 308. Each transfer gate transistor 306 is coupled to a contact 360. As shown, the photodiodes 304 are arranged at a third pitch P3, and the FD nodes 308 are arranged at a third pitch P4. In the embodiment shown in FIG. 21, the second pitch P2 is equal to the third pitch P3. In one embodiment, the second pitch P2 is approximately twice the third pitch P3. Note that the FD node 308 is vertically aligned with the bonding pad 328. Therefore, both the FD node 308 and the bonding pad 328 are aligned along the X direction. Note that they are arranged at a pitch P2.

[0051] FIG. 22 shows a schematic top view of the electrical routing around the image sensor cluster 400. In some embodiments, each of the contacts 360 is formed on the first metal layer (M1). In FIG. 22, the metal lines of the first metal layer (M1) are electrically connected to the metal lines in the X direction. The two metal lines of the second metal layer (M2) extend vertically along the Y direction. , sandwiching the cluster 400. In some cases, the two metal wires are connected to ground (G or GND). Since the current flows only along the Z direction from the FD node 36 to the second chip 20, The FD node 36 is electrically connected to a metal island 314 (shown in FIG. 23) in the first metal layer (M1). Unlike the metal lines in the first metal layer (M1), the metal islands 314 23 shows the image sensor cluster 400. FD node 36 is shown as a cross-sectional schematic diagram of the electrical routing around the Physically and electrically coupled to contact feature 312 that is electrically coupled to land 314 The metal islands 314 are connected to the second metal layer (M2) by contact vias 316. The upper metal feature 318 is coupled to the upper metal feature 318. Two ground lines 319 are also located in the second metal layer (M2). A bonding contact 326 is disposed on the upper metal feature 318, and the bonding Bonding pads 328 are vertically aligned and make contact with bonding contacts 326 .

[0052] As mentioned above, the bond between the first tip 10, the second tip 20 and the third tip 30 The bonding is achieved through a bonding layer. Two types of bonding layers may be implemented in accordance with embodiments of the present invention. The bonding layer includes a plurality of bonding contacts on the first dielectric bonding layer and a plurality of bonding contacts on the second dielectric bonding layer. The conductive bonding layer includes a plurality of bonding pads. The second type of bonding layer is a dielectric layer. The first type of bonding includes a plurality of bonding contacts disposed within the bonding layer. An example of a layer is the fourth bonding layer 320 shown in FIG. 6, which is a second type of bonding layer. An example of a bonding layer is the second bonding layer 220 shown in Figure 7. In general, the second type of bonding The bonding pads in the bonding layer must be thick enough to ensure satisfactory chip bond integrity and longevity. It functions to provide a uniform distribution of metal features, which is essential to achieve. Second, when metal features or bonding contacts are not uniformly distributed on the surface of the chip. It can be seen that two types of bonding layers are provided. The first type of bonding layer is The first type of bonding layer and the second type of bonding layer are Further details of the padding layer are provided in connection with FIGS. 24 and 25.

[0053] FIG. 24 shows a schematic cross-sectional view of a first type of bonding layer according to various embodiments of the present invention. For each of the upper metal features 318, the first type of bonding layer is The bonding contacts 326 and bonding pads 328 are aligned vertically. The bonding layer of type 1 has dummy boards that are not electrically connected to the bonding contacts below. These dummy bonding pads 3280 may also be included. are inserted to provide uniform metal feature density. In some embodiments, The upper metal feature 318 is formed by a first etch stop layer (ESL) 345 and a second etch stop layer (ESL) 346. The IMD layer 347 is embedded in an IMD layer 347 disposed on top of an ESL 346. The MD layer 347 is made of tetraethoxysilane (TEOS) oxide, undoped silicate Salt glass, or borophosphosilicate glass (BPSG), fused silica glass glass (FSG), phosphosilicate glass (PSG), or boron-doped silicon glass (B The first ESL 345 may comprise a doped silicon oxide such as silicon carbide. The second ESL 346 may include silicon oxide. The third ESL 348 is disposed on the IMD layer 347, and the first dielectric bonding layer 322 is 48. The bonding contact 326 is located on the third ESL 348 and the first dielectric The first dielectric bonding layer 322 extends through the first dielectric bonding layer 322. The third ESL 34 may share the same composition as the second ESL 346, which may include silicon dioxide. The fourth ESL 350 is formed on the first dielectric bonding layer 322. and a second dielectric bonding layer 324 is disposed on top of the fourth ESL 350 . The fourth ESL 350 may comprise silicon nitride, and the second dielectric bonding layer 324 may comprise silicon nitride. In some embodiments, the blocking layer 359 is a second dielectric layer. The blocking layer 359 may be disposed on the bonding layer 324. The blocking layer 359 may comprise silicon oxynitride. The metal bonding contacts or bonding pads from other chips may be perfectly aligned. It acts to prevent electromigration when the bond is not properly aligned. The bonding pad 328 is connected to the blocking layer 359, the second dielectric bonding layer 324, and In some embodiments shown in FIG. Pads 328 and bonding contacts 326 are formed using a dual damascene process. The top gold layer is continuous to prevent electromigration and oxygen diffusion. The metal feature 318 is separated from the IMD layer 347 by a first barrier layer 317. The bonding contact 326 and the bonding pad 328 are surrounded by a second barrier layer 327. The first barrier layer 317 and the second barrier layer 327 are separated from the surrounding dielectric layer. The dummy bonding pads 3280 may comprise titanium or tantalum nitride. It shares a similar structure with the swivel pad 328.

[0054] FIG. 25 shows a schematic cross-sectional view of a second type of adhesive layer according to various embodiments of the present invention. As shown in FIG. 5, the second type of bonding layer is a first dielectric bonding layer 32. 2. The other chip (to be bonded) contains only the embedded bonding contact 326. The metal bonding contact or bonding pad from the chip is completely connected to the bonding contact 326. To prevent electromigration when the block is not aligned to the A dielectric layer 359 is disposed on the first dielectric bonding layer 322 .

[0055] Thus, in some embodiments, the present invention provides a first substrate and a a first die having a first interconnect structure formed thereon; a second substrate and a a second die having a second interconnect structure formed thereon, and a third interconnect structure and a third interconnect a third die having a third substrate disposed on the structure. The first interconnect structure is bonded to the second substrate by a first plurality of bonding layers. The second interconnect structure is connected to a third interconnect structure by a second plurality of bonding layers. The third substrate is bonded to the structure. The second die includes a first transistor disposed on the drain of the first transistor. a second transistor having a source electrically connected to the drain of the first transistor; and a third transistor having a gate electrically connected to the source of the second transistor. a fourth transistor having a drain electrically connected to the source of the third transistor; and a .

[0056] In some embodiments, the first plurality of bonding layers are arranged at a first pitch. The first plurality of bonding pad structures includes a second plurality of bonding layers. The second plurality of bonding pad structures are arranged at a second pitch different from the first pitch. In some implementations, the second pitch is smaller than the first pitch. In one embodiment, the first pitch is about 1.5 μm to about 2.5 μm and the second pitch is about 0.3 μm to about 1.5 μm. In some embodiments, the second pitch relative to the first pitch is from about 1.5 μm to about 1.5 μm. In some embodiments, the third die has a pitch ratio of about 0.2 to about 0.75. a plurality of floating diffusion regions, each of the plurality of floating diffusion regions being connected to a second plurality of bonding pads; In some cases, the first transistor is vertically aligned with one of the gate structures. The gate structure is in physical contact with one of the photodiodes. In one embodiment, the second die includes a plurality of through-substrate vias (TSVs) extending through the second substrate. ) is included.

[0057] According to another aspect of the present invention, a semiconductor device includes a first plurality of bonding pad structures and a first die. The first die includes a device structure including a first plurality of bonding layers including the first plurality of bonding layers. a first interconnect structure disposed on the bonding layer; and a second interconnect structure disposed on the first interconnect structure. a first substrate on which a plurality of photodiodes are disposed; a plurality of floating diffusion regions disposed between the diodes, each of the plurality of floating diffusion regions Each is vertically aligned with one of the first plurality of bonding pad structures.

[0058] In some embodiments, the device structure includes a second die including a second substrate; and a second interconnect structure disposed on the plate. The second interconnect structure is The first interconnect structure is bonded to the second interconnect structure by multiple bonding layers. In one embodiment, the die structure comprises a third substrate and a third interconnect structure disposed on the third substrate. The third interconnect structure is connected to the second plurality of bonding layers. Optionally, a second plurality of bonding layers are bonded to the second substrate. The second substrate includes a second plurality of bonding pad structures, and the second substrate includes a plurality of through-substrate vias (TS V). In some embodiments, each of the second plurality of bond pad structures is vertically aligned with one of the TSVs. The first plurality of bonding pad structures are arranged at a first pitch, and the second plurality of bonding pad structures are arranged at a first pitch. The pad structures are arranged at a second pitch different from the first pitch. In the embodiment, the first pitch is about 0.3 μm to about 1.5 μm and the second pitch is about 1. 5 μm to about 2.5 μm.

[0059] In accordance with yet another aspect of the present invention, a first plurality of bonding pad structures and a first die a first die including a first plurality of bonding layers including a first die; a first interconnect structure disposed on the layer; and a first a substrate; a plurality of photodiodes disposed in the first substrate; and a plurality of photodiodes. and a plurality of floating diffusion regions disposed between the first and second electrodes, each of the plurality of floating diffusion regions including a first and being vertically aligned with one of a plurality of bonding pad structures. do.

[0060] In some embodiments, the device structure comprises a second substrate and a second substrate disposed on the second substrate. and a second interconnect structure. The second interconnect structure is connected to the first plurality of interconnect structures. The first interconnect structure is bonded to the second interconnect structure by multiple bonding layers. In one embodiment, the device structure includes a third substrate and a third interconnect structure disposed on the third substrate. The third interconnect structure further includes a third die including a second plurality of bonding In some embodiments, the second plurality of bonding layers are bonded to the second substrate. The bonding layer includes a second plurality of bonding pad structures, and the second substrate includes a plurality of through-substrate In some embodiments, the second plurality of bonding pad structures includes through-silicon vias (TSVs). Each of the structures is vertically aligned with one of the TSVs. In this case, the first plurality of bonding pad structures are arranged at a first pitch. The bonding pad structures are arranged at a second pitch different from the first pitch. In some cases, the first pitch is about 0.3 μm to about 1.5 μm and the second pitch is about 1 0.5μm to approximately 2.5μm.

[0061] The foregoing description of several embodiments will be provided in order that those skilled in the art may better understand the detailed description that follows. The features have been outlined, and those skilled in the art can carry out the same purpose as the embodiments introduced herein and / or or as a basis for designing or modifying other processes and structures to achieve the same benefits. It should be understood that the present invention can be readily used in such a manner. and other configurations do not depart from the spirit and scope of the present invention, and Various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention. It should be understood that, for example, providing different thicknesses for the bit line conductors and the word line conductors can However, the resistance of the metal conductors can be varied by Other techniques for varying the .DELTA..times ... [Industrial Applicability]

[0062] Image sensor packaging and method of forming image sensor packaging of the present invention can be used in applications requiring high performance in image sensing. [Explanation of symbols]

[0063] 10: First Chip 20: Second Chip 30: Third Chip 40: Image sensor element 102: First substrate 104: Logic transistor 110: Interconnection Structure 120: First bonding layer 202: Second substrate 204: Row selector transistor 206: Source follower transistor 208: Reset transistor 210: Second interconnect structure 220: Second bonding layer 226: Through-substrate via 240: Third bonding layer 248, 328: Bonding pads 302: Third board 304: Photodiode 306: Transfer gate transistor 308: Floating diffusion region, floating diffusion node 310: Third interconnect structure 320: Fourth bonding layer 332: Metal grid 334: Passivation layer 336: Color filter layer 338: Microlens 340: Metal pad P1: First pitch P2: Second pitch

Claims

1. A first die comprising a first substrate and a first interconnect structure disposed on the first substrate. I and a second daisy chain including a second substrate and a second interconnect structure disposed on the second substrate; I and a third interconnect structure and a third substrate disposed on the third interconnect structure; Dai and Equipped with The first interconnect structure is bonded to the second substrate by a first plurality of bonding layers. Bonded, The second interconnect structure is connected to the third interconnect by a second plurality of bonding layers. Bonded to a connecting structure, The third substrate includes a plurality of photodiodes and a first photodiode disposed on the third substrate. a transistor; The second die has a source electrically connected to the drain of the first transistor. a second transistor having a first gate connected to the drain of the first transistor and the second gate; a third transistor having a gate electrically connected to the source of the first transistor; a fourth transistor having a drain electrically connected to the source of the third transistor; Sta and, including, Device structure.

2. The first plurality of bonding layers includes a first plurality of bonding layers arranged at a first pitch. including a pad structure, The second plurality of bonding layers are arranged at a second pitch different from the first pitch.

10. The device structure of claim 1, further comprising a second plurality of bonding pad structures.

3. The device structure of claim 2 , wherein the second pitch is smaller than the first pitch.

4. the first pitch is from about 1.5 μm to about 2.5 μm; 3. The device of claim 2, wherein the second pitch is from about 0.3 μm to about 1.5 μm. Structure.

5. a ratio of the second pitch to the first pitch is from about 0.2 to about 0.75; 3. The device structure of claim 2.

6. the third die includes a plurality of floating diffusion regions; Each of the plurality of floating diffusion regions is connected to one of the second plurality of bonding pad structures. The device structure of claim 2 which is vertically aligned.

7. The gate structure of the first transistor is connected to one of the plurality of photodiodes. The device structure of claim 1 in physical contact.

8. The second die has a plurality of through-substrate vias (TSVs) extending through the second substrate. The device structure of claim 1 , comprising:

9. a first plurality of bonding layers including a first plurality of bonding pad structures; a first interconnect structure disposed on the first plurality of bonding layers; and a first substrate disposed over the interconnect structure; and a plurality of photoresists disposed within the first substrate. a plurality of floating diffusion regions disposed between the plurality of photodiodes; a first die including: Including, Each of the plurality of floating diffusion regions is connected to one of the first plurality of bonding pad structures. vertically aligned, Device structure.

10. a second substrate and a second interconnect structure disposed on the second substrate; It further includes The second interconnect structure is connected to the first interconnect by the first plurality of bonding layers. The device structure of claim 9 coupled to a connecting structure.

11. a third substrate; and a third interconnect structure disposed on the third substrate. It further includes The third interconnect structure is connected to the second substrate by the second plurality of bonding layers. The device structure of claim 10 , wherein the device structure is bonded to a

12. the second plurality of bonding layers including a second plurality of bonding pad structures; The device of claim 11 , wherein the second substrate includes a plurality of through-substrate vias (TSVs). Chair structure.

13. Each of the second plurality of bonding pad structures is perpendicular to one of the plurality of TSVs. The device structure of claim 12 , wherein the device structure is aligned in the direction of the arrows.

14. the first plurality of bonding pad structures are arranged at a first pitch; The second plurality of bonding pad structures are arranged at a second pitch different from the first pitch. The device structure of claim 12 , arranged in a ch.

15. the first pitch is from about 0.3 μm to about 1.5 μm; 15. The device of claim 14, wherein the second pitch is from about 1.5 μm to about 2.5 μm. Chair structure.

16. a first substrate; a first interconnect structure disposed on the first substrate; and receiving a first die including a first plurality of bonding pads on the connecting structure; a second substrate; a second interconnect structure disposed on the second substrate; and receiving a second die including a second plurality of bonding pads on the connecting structure; The first plurality of bonding pads are perpendicular to the second plurality of bonding pads. and bonding the second die to the first die so that they are aligned and in physical contact with each other. and After bonding the second die to the first die, the thickness of the second substrate is reduced. forming a thinned second substrate; forming a plurality of vias through the thinned second substrate; Each of the plurality of vias is vertically positioned with respect to one of the third plurality of bonding pads. forming a third plurality of bonding pads on the thinned second substrate so as to be aligned with the first and second substrates; Forming and a third substrate; a third interconnect structure disposed on the third substrate; and a fourth plurality of bonding pads on the connecting structure; and The fourth plurality of bonding pads are perpendicular to the third plurality of bonding pads. and bonding the third die to the second die so that they are aligned and in physical contact with each other. and After bonding the third die to the second die, reducing the thickness of the third substrate; forming a thinned third substrate; and depositing a color filter layer on the thinned third substrate.

17. the thinned third substrate includes a plurality of photodiodes disposed on the third substrate; , and a plurality of floating diffusion regions disposed between the plurality of photodiodes.

6. The method according to claim 6.

18. Each of the plurality of floating diffusion regions is perpendicular to one of the fourth plurality of bonding pads. The method of claim 17, wherein the alignment is directionally aligned.

19. The first and second plurality of bonding pads are Arranged in pitch, The third plurality of bonding pads and the fourth plurality of bonding pads are 17. The method of claim 16, wherein the first pitch is different from the second pitch.

20. 20. The method of claim 19, wherein the first pitch is greater than the second pitch.

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