Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing a decrease in a gate service life due to the rise of an equipotential line.SOLUTION: A semiconductor device comprises a second deep layer 17 including a stripe part 171 where a plurality of lines linked to a base region 18 and a first deep layer 14 and extending in the same direction as a longitudinal direction of a trench 21 are arranged between a first deep layer 14, a first current dispersion layer 13, and a base region 18 on the active region 1a side in an active region 1a or a non-active region 1b. The semiconductor device also comprises a second current dispersion layer 15 formed between the first current dispersion layer 13 and the bas region 18 and arranged between a plurality of lines constituting the stripe part 171. Each line constituting a first stripe portion 141 includes a tip part 141a linked to a frame-like part 142 and an inside part 141b located inside the tip part 141a. A width of the tip part 141a is greater than or equal to a width of the inside part 141b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a trench gate structure. [Background technology]

[0002] Conventionally, silicon carbide (hereinafter referred to as SiC) semiconductor devices and the like have adopted a trench gate structure with a high channel density to allow a large current to flow. In SiC semiconductor devices with a trench gate structure, the application of electric field stress to the bottom of the trench can cause dielectric breakdown of the gate insulating film. For this reason, Patent Document 1 proposes a SiC semiconductor device that suppresses the application of a high electric field to the bottom of the trench, thereby suppressing dielectric breakdown of the gate insulating film.

[0003] This SiC semiconductor device has a structure in which n-type first current spreading layers and p-type first deep layers are alternately arranged in stripes below the trench gate structure. The first deep layers are connected to the p-type base region via second deep layers arranged on both sides of the trench gate structure and are fixed to the source potential.

[0004] By using this structure, the first deep layer prevents the equipotential lines from rising toward the trench gate structure, and prevents a high electric field from being applied to the bottom of the trench gate structure, making it possible to prevent dielectric breakdown of the gate insulating film. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-46908 Summary of the Invention [Problem to be solved by the invention]

[0006] If the region of the cell region where the trench gate structure is formed and where device operation occurs is defined as the active region, the remaining region of the cell region is defined as the inactive region that surrounds the active region and where device operation does not occur. In the structure of Patent Document 1 described above, we have investigated a structure in which this inactive region is made the first deep layer over a wide area, thereby suppressing the rise of equipotential lines based on the electric field relaxation effect of the first deep layer.

[0007] As a result, it was confirmed that the width of the portion of the first deep layer where the striped portion within the cell region (hereinafter referred to as the stripe portion) and the portion located in the outer edge region surrounding it (hereinafter referred to as the frame portion) are connected becomes wider. If such a wide portion where the first deep layer is not formed exists, the electric field relaxation effect in that portion decreases and it becomes impossible to suppress the rise of equipotential lines, which raises concerns about a decrease in gate life.

[0008] Furthermore, it was confirmed that the distance between the frame and the stripe, more specifically, the distance between the part of the frame parallel to the stripe and the outermost line of the stripe arranged opposite it, was wider than the distance between the lines constituting the stripe. This wider distance also reduces the electric field relaxation effect between the frame and the stripe, making it impossible to suppress the rise of equipotential lines, raising concerns about a reduction in gate life.

[0009] Furthermore, when the first and second deep layers are formed in stripes and have a structure in which they intersect, the portion of the first deep layer that intersects with the trench gate structure becomes a source of obstruction to the current path, which increases the on-resistance.

[0010] Furthermore, it has been confirmed that in a SiC semiconductor device having an n-type drift layer and a p-type base region, the forward voltage Vf fluctuates due to the influence of holes generated when a current is passed through the formed PN diode.

[0011] Although a SiC semiconductor device using SiC as a semiconductor material is taken as an example here, the same can be said for semiconductor devices using semiconductor materials other than SiC.

[0012] In view of the above, a first object of the present invention is to provide a semiconductor device that can suppress a decrease in gate life due to the rise of equipotential lines. A second object is to provide a semiconductor device that can suppress an increase in on-resistance. A third object is to provide a semiconductor device that can suppress fluctuations in forward voltage Vf. [Means for solving the problem]

[0013] In a first aspect of the present disclosure, a semiconductor device is provided having an active region (1a) in which semiconductor switching elements having a plurality of trench gate structures are formed and which can be operated as elements, and an inactive region (1b) which surrounds the active region and cannot be operated as elements, the semiconductor device comprising: a semiconductor region (11) of a first conductivity type or a second conductivity type; a first impurity region (12) of the first conductivity type formed on the semiconductor region and having a lower impurity concentration than the semiconductor region; a base region (18) of the second conductivity type formed on the first impurity region; and a second impurity region (19) formed on the base region and having a higher impurity concentration than the first impurity region. The semiconductor device is provided with a plurality of trench gate structures each having a second impurity region (19) of a first conductivity type formed in the first impurity region and extending deeper than the base region, a gate insulating film (22) formed on the inner wall surface of a trench (21) formed with one direction as the longitudinal direction, and a gate electrode (23) formed on the gate insulating film in the trench, a first electrode (24) electrically connected to the second impurity region and electrically connected to the base region, and a second electrode (26) formed on the back surface of the semiconductor region and electrically connected to the semiconductor region.

[0014] The semiconductor device also includes a first current spreading layer (13) of a first conductivity type formed between the first impurity region and the base region and having a higher impurity concentration than the first impurity region, a first stripe portion (141) extending in one direction longitudinally on the active region side of the active region and the inactive region and having a plurality of lines arranged therein, and a frame-shaped portion (142) formed in the inactive region, surrounding the periphery of the first stripe portion and connected to each line constituting the first stripe portion, and a first deep layer (14) of a second conductivity type.

[0015] Furthermore, on the active region side of the active region and the inactive region, there is a second stripe portion (171) formed between the first deep layer and the first current spreading layer and the base region, connected to the base region and the first deep layer, and including a plurality of lines extending in the same direction as the longitudinal direction of the trench, and there is also provided a second deep layer (17) of a second conductivity type, and a second current spreading layer (15) of the first conductivity type formed between the first current spreading layer and the base region and arranged between the plurality of lines forming the second stripe portion. In this configuration, each line forming the first stripe portion includes a tip portion (141a) connected to the frame-shaped portion and an inner portion (141b) located inward from the tip portion, and the width of the tip portion is equal to or greater than the width of the inner portion.

[0016] In this way, the width of the tip of each line of the first stripe portion in the first deep layer is made equal to or greater than the width of the inner portion. In other words, even if the portion of the mask (3) used to form the first deep layer corresponding to the tip of the first deep layer narrows, the width of the tip can be made equal to or greater than the width of the inner portion. Therefore, the tip of the first current spreading layer can be prevented from widening, and the electric field relaxation effect of the first deep layer can suppress the electric field from rising up in that portion, thereby suppressing a decrease in the breakdown voltage and lifespan of the gate insulating film.

[0017] In the semiconductor device according to the second aspect of the present disclosure, each line constituting the second stripe portion includes a tip portion (171a) and an inner portion (171b) located more inward than the tip portion, and the width of the tip portion is wider than the width of the inner portion.

[0018] In this way, the width of the tip end of the second deep layer is wider than the width of the inner portion. Therefore, even if the distance between the frame portion and the stripe portion of the first deep layer becomes wider than the distance between the lines, reducing the electric field relaxation effect of the first deep layer, the electric field relaxation effect of the second deep layer can push back the equipotential lines, making it difficult for a high electric field to penetrate. This prevents the electric field from rising up in this area, even if the distance between the frame portion and the stripe portion of the first deep layer becomes wider than the distance between the lines. This makes it possible to prevent a decrease in the breakdown voltage and lifespan of the gate insulating film.

[0019] In a semiconductor device according to a third aspect of the present disclosure, the longitudinal direction of the trench intersects with the longitudinal direction of each line constituting the first stripe portion of the first deep layer, and each line constituting the first stripe portion is divided by providing a missing portion (14a) to form a broken line, and the trench gate structure is configured to pass through the missing portion provided in each line.

[0020] In this way, while the first stripe portion intersects with the trench gate structure, each line is partially divided by providing a defect, and the trench gate structure passes through the defect. This reduces the number of intersections between the first deep layer and the trench gate structure compared to when no defect is provided, making it possible to suppress an increase in on-resistance.

[0021] A semiconductor device according to a fourth aspect of the present disclosure includes a third deep layer (30) of a second conductivity type below the first deep layer and the first current spreading layer, the third deep layer (30) having a third stripe portion in which a plurality of lines are arranged with their longitudinal direction extending in the same direction as the longitudinal direction of the trench.

[0022] In this way, the deep layer has a three-layer structure, consisting of a first deep layer, a second deep layer, and a third deep layer. This structure lengthens the path along which carriers travel, allowing more carriers to recombine and disappear. This makes it possible to suppress increases in on-resistance and fluctuations in forward voltage Vf.

[0023] Note that the symbols in parentheses above and in the claims indicate the correspondence between the terms described in the claims and the concrete examples of those terms described in the embodiments below. [Brief explanation of the drawings]

[0024] [Figure 1] 1 is a perspective cross-sectional view of a SiC semiconductor device according to a first embodiment. [Figure 2] 4 is a cross-sectional view of the outer edge of the cell region and the peripheral region surrounding the cell region, corresponding to the cross section II-II in FIG. 3. FIG. [Figure 3] FIG. 3 is a layout diagram of FIG. 2 as viewed from above. [Figure 4] FIG. 4 is a top view layout diagram showing an enlarged view of the boundary position between the stripe portion and the frame portion of the first deep layer in an area IV surrounded by a dashed line in FIG. 3. [Figure 5A] 2A to 2C are cross-sectional views showing a manufacturing process of the SiC semiconductor device shown in FIG. [Figure 5B] 5B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5B. [Figure 5D] 5D is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 5C. [Figure 5E] FIG. 5E is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5D. [Figure 5F] FIG. 5B is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5E. [Figure 5G] FIG. 5C is a cross-sectional view showing the manufacturing process of the SiC semiconductor device subsequent to FIG. 5F. [Figure 6A] FIG. 10 is a diagram showing an example of a mask pattern design when forming a first deep layer. [Figure 6B] FIG. 6B is a diagram showing design values ​​of a mask when the mask is patterned based on the design example of the mask pattern shown in FIG. 6A. [Figure 6C] 6B is a diagram showing an image of a mask when a mask is actually patterned based on the example of the mask pattern design in FIG. 6A. FIG. [Figure 7] FIG. 10 is a cross-sectional view showing the rising of an electric field. [Figure 8A] FIG. 10 is a diagram showing the relationship between the breakdown voltage and the spacing between the lines of the stripe portion in the first deep layer. [Figure 8B] FIG. 10 is a diagram showing the relationship between the spacing between lines of the stripe portion in the first deep layer and the gate electric field strength. [Figure 9A] FIG. 10 is a diagram showing a top surface layout of a stripe portion of a first deep layer described in a modified example of the first embodiment. [Figure 9B] FIG. 10 is a diagram showing a top surface layout of a stripe portion of a first deep layer described in a modified example of the first embodiment. [Figure 10] 10 is a diagram showing the top surface layout of a second deep layer of the SiC semiconductor device according to the second embodiment, and corresponds to the region X indicated by the dashed line in FIG. [Figure 11A] FIG. 10 is a diagram showing a top surface layout of a stripe portion of a second deep layer described in a modified example of the second embodiment. [Figure 11B] FIG. 10 is a diagram showing a top surface layout of a stripe portion of a second deep layer described in a modified example of the second embodiment. [Figure 12] FIG. 10 is a diagram showing a top surface layout of a first deep layer, a second deep layer, and a trench gate structure of the SiC semiconductor device according to the third embodiment. [Figure 13] FIG. 10 is a diagram showing the relationship between the gate current Ig and the drain voltage Vd when gate breakdown occurs. [Figure 14A]FIG. 11 is a top view layout diagram illustrating the tip shapes of the lines at the dividing points of the first deep layer described in a modified example of the third embodiment. [Figure 14B] FIG. 11 is a top view layout diagram illustrating the tip shapes of the lines at the dividing points of the first deep layer described in a modified example of the third embodiment. [Figure 15A] FIG. 11 is a top view layout diagram illustrating a modified example of the third embodiment in which each dot in the stripe portion of the first deep layer has a circular shape. [Figure 15B] FIG. 10 is a top view layout diagram illustrating a modification of the third embodiment in which each dot in the stripe portion of the first deep layer is hexagonal. [Figure 16] FIG. 10 is a perspective cross-sectional view of a SiC semiconductor device according to a fourth embodiment. [Figure 17] 17 is a diagram showing the migration path of holes in the cross section taken along the line XVII-XVII in FIG. 16. FIG. [Figure 18] FIG. 11 is a perspective cross-sectional view of a SiC semiconductor device described as a modified example of the fourth embodiment. [Figure 19] 19 is a diagram showing the migration path of holes in the XIX-XIX cross section of FIG. 18. FIG. [Figure 20] FIG. 13 is a perspective cross-sectional view of a SiC semiconductor device described as a modified example of the fourth embodiment. [Figure 21] FIG. 21 is a diagram showing the migration path of holes in the cross section taken along the line XXI-XXI in FIG. 20. [Figure 22] FIG. 11 is a perspective cross-sectional view of a SiC semiconductor device described as a modified example of the fourth embodiment. [Figure 23] 23 is a diagram showing the migration path of holes in the cross section taken along the line XXIII-XXIII in FIG. 22. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0026] (First embodiment) A first embodiment will be described with reference to Figures 1 to 4. As shown in Figures 1 to 4, the SiC semiconductor device of this embodiment has a configuration including a cell region 1 in which a MOSFET with an inversion type trench gate structure is formed as a semiconductor switching element, and a peripheral region 2 in which a peripheral breakdown withstanding structure is formed so as to surround the cell region 1. Note that Figure 1 is a perspective cross-sectional view of one cell in the cell region 1 of the MOSFET.

[0027] As shown in FIGS. 1 and 2, the SiC semiconductor device is a n-type semiconductor device made of SiC. + The substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si plane, and the concentration of n-type impurities such as nitrogen and phosphorus is, for example, 1.0×10 19 / cm 3 The thickness is set to about 300 μm.

[0028] 1 to 3, the surface direction of substrate 11 is defined as the xy plane, the <11-20> direction in the xy plane is defined as the y-axis direction, the direction perpendicular to the y-axis direction is defined as the x-axis direction, and the direction normal to the surface direction of substrate 11 is defined as the z-axis direction.

[0029] The surface of the substrate 11 has an n-type impurity concentration of, for example, 5.0 to 10.0×10 15 / cm 3 The thickness is about 10 to 15 μm, and the n - A mold layer 12 is formed. - The impurity concentration of the mold layer 12 may be constant in the depth direction, but the concentration distribution may be graded to form an n - It is preferable that the concentration of the mold layer 12 on the substrate 11 side is higher than that on the side away from the substrate 11. For example, n - The mold layer 12 has an impurity concentration of 2.0×10 in a portion of the substrate 11 approximately 3 to 5 μm from the surface. 15 / cm 3 It is better to make the area higher than the other areas. - The internal resistance of the mold layer 12 can be reduced, and the on-resistance can be reduced.- The mold layer 12 corresponds to a first impurity region.

[0030] In cell area 1, n - The surface of the mold layer 12 is - The n-type first current spreading layer 13 has a higher impurity concentration than the type layer 12 and is doped with n-type impurities such as nitrogen or phosphorus, and the p-type first deep layer 14 has been doped with p-type impurities such as Al.

[0031] The first current spreading layer 13 is made of an n-type layer containing n-type impurities such as nitrogen and phosphorus, and has a depth of 0.3 to 1.5 μm. In this embodiment, the first current spreading layer 13 is formed only in the cell region 1. That is, in this embodiment, - The region where the first current spreading layer 13 is formed on the surface of the mold layer 12 is the cell region 1, and n - The region where the first current spreading layer 13 is not formed on the surface of the mold layer 12 is defined as the outer peripheral region 2. The first deep layer 14 is shallower than the first current spreading layer 13, but has a depth of 0.3 to 1.4 μm, which is approximately the same as the first current spreading layer 13. In other words, the first deep layer 14 is formed so that its bottom is located within the first current spreading layer 13, and - The first current spreading layer 13 is formed at a depth between the mold layer 12 and the first current spreading layer 13 .

[0032] The first current spreading layer 13 and the first deep layer 14 are each extended along the x-axis direction and arranged at equal intervals along the y-axis direction so as to form a stripe pattern of alternating lines in the active region 1a where the MOSFET operates. The stripe-shaped portion of the first deep layer 14 corresponds to the first stripe portion, and hereinafter this portion will be referred to as the stripe portion 141.

[0033] The width of each line of the striped portion of the first current spreading layer 13 is, for example, 0.25 μm, and the n-type impurity concentration is, for example, 5.0×10 16 ~2.0×10 18 / cm 3The width of each line constituting the stripe portion 141 is set to, for example, 0.9 μm, and the p-type impurity concentration is set to, for example, 3.0×10 17 ~1.0×10 18 / cm 3 In this embodiment, the first deep layer 14 has a constant p-type impurity concentration in the depth direction. - The surface opposite to the mold layer 12 is flush with the surface of the first current spreading layer 13 .

[0034] 3, the first deep layer 14 is also formed in the inactive region 1b, which is located between the active region 1a and the peripheral region 2 and in which the MOSFETs arranged to surround the active region 1a do not operate. In the inactive region 1b near the active region 1a, the first deep layer 14 has a structure in which a stripe portion 141 similar to that in the active region 1a is formed, and outside of that, the first deep layer 14 is formed all the way up to the boundary with the peripheral region 2, thereby forming a frame-shaped portion 142. The frame-shaped portion 142 surrounds the stripe portion 141 and is connected to each line that constitutes the stripe portion 141.

[0035] In this embodiment, the first deep layer 14 is formed by ion implantation, as described below. Taking into account the processing limitations of photolithography during ion implantation, the width of each line constituting the stripe portion 141, i.e., the length in the y-axis direction, is set to 0.3 μm or more, e.g., 0.9 μm. The width of each line constituting the stripe portion 141 (hereinafter simply referred to as the width of the first deep layer 14) will be described in detail later. As shown in FIG. 4, the width of each end portion 141a of the stripe portion 141 (hereinafter simply referred to as the width of the first deep layer 14) is equal to or greater than the width of the inner portion 141b located inside the end portion 141a. The width of the inner portion 141b is set to, e.g., 0.9 μm, and the end portion 141a is wider than that width. Therefore, the spacing between the lines constituting the stripe portion 141, i.e., the width of the first current spreading layer 13 along the y-axis direction (hereinafter simply referred to as the width of the first current spreading layer 13), is equal to or less than the width of the inner portion at both ends of the first current spreading layer 13. Note that a trench gate structure, described later, is indicated by a dashed line in FIG. 4. Here, the layout is such that the tip portion 141a and the trench gate structure overlap, but they do not necessarily have to overlap.

[0036] A second current spreading layer 15 is formed on the first current spreading layer 13 and the first deep layer 14. The second current spreading layer 15 contains n-type impurities such as nitrogen and phosphorus at a concentration of, for example, 1.0×10 16 ~5.0×10 17 In this embodiment, in addition to the second current spreading layer 15, n - The mold layer 12 and the first current spreading layer 13 form a drift layer 16 .

[0037] Furthermore, a plurality of second deep layers 17 are formed in the second current spreading layer 15 so as to penetrate the second current spreading layer 15. The second deep layers 17 have a p-type impurity concentration of Al or the like of, for example, 2.0×10 17 ~2.0×10 18The second deep layer 17 has a thickness equal to that of the second current spreading layer 15. In this embodiment, the second deep layer 17 is arranged in the active region 1a where the MOSFET operates as an element, so that the second deep layer 17 has a stripe shape with multiple lines aligned along the y-axis direction and arranged at equal intervals along the x-axis direction. The stripe-shaped portion of the second deep layer 17 corresponds to the second stripe portion, and hereinafter, this portion will be referred to as the stripe portion 171. Each line of the stripe portion 171 of the second deep layer 17 extends in a direction intersecting with the stripe portion 141 of the first deep layer 14, and each line of the stripe portion 171 has a width of, for example, 0.7 to 1.6 μm.

[0038] 3, the second deep layer 17 is also formed in the inactive region 1b located between the active region 1a and the peripheral region 2. In the inactive region 1b near the active region 1a, the second deep layer 17 has a structure in which a stripe portion 171 similar to that in the active region 1a is formed, and outside of that, the second deep layer 17 is formed all the way up to the boundary with the peripheral region 2, thereby forming a frame-shaped portion 172. The frame-shaped portion 172 surrounds the stripe portion 171 and is connected to each line that constitutes the stripe portion 171.

[0039] In each second deep layer 17, the portions of the stripe portions 171 that intersect with the stripe portions 141 and the portions of the frame portions 172 that overlap with the frame portions 142 are connected to the first deep layer 14. The stripe portions 171 are formed so as to sandwich trenches 21, which will be described later. In other words, the stripe portions 171 are formed away from the trenches 21. The second current spreading layers 15 are also arranged between the lines of the stripe portions 171 of the second deep layer 17, and therefore the second current spreading layers 15 also have a stripe shape.

[0040] A p-type base region 18 is formed on the second current spreading layer 15 and the second deep layer 17. An n-type base region 18 is formed on the base region 18. + Type source region 19 and p +A contact layer 20 is formed on the source region 19. The source region 19 is disposed on both sides of a trench gate structure, which will be described later, and the contact layer 20 is provided on the opposite side of the trench gate structure across the source region 19. In this embodiment, the source region 19 corresponds to a second impurity region.

[0041] The base region 18 has a p-type impurity concentration of Al or the like of, for example, 5.0×10 16 ~2.0×10 19 / cm 3 The source region 19 has an n-type impurity concentration of nitrogen, phosphorus, or the like in the surface layer, that is, a surface concentration of, for example, 1.0×10 20 / cm 3 The contact layer 20 has a p-type impurity concentration of Al or the like in the surface layer, i.e., a surface concentration of, for example, 1.0×10 21 / cm 3 , and is composed of a thickness of about 0.3 μm.

[0042] Further, trenches 21 having a width of, for example, 0.5 to 1.0 μm are formed so as to penetrate through the base region 18 and the source region 19 to reach the second current spreading layer 15 and have their bottom surfaces located within the second current spreading layer 15. The trenches 21 are formed so as not to reach the first current spreading layer 13 and the first deep layer 14, that is, so that the first current spreading layer 13 and the first deep layer 14 are located below the bottom surfaces of the trenches 21. Note that, since the trenches 21 are formed so as to penetrate through the base region 18 and the source region 19, the base region 18 and the source region 19 are in contact with the side surfaces of the trenches 21.

[0043] The trench 21 is filled with a gate insulating film 22 formed on the inner wall surface and a gate electrode 23 made of doped poly-Si formed on the surface of the gate insulating film 22. This forms a trench gate structure. Although not particularly limited, the gate insulating film 22 is formed by thermally oxidizing the inner wall surface of the trench 21, and has a thickness of about 100 nm on both the side and bottom sides of the trench 21.

[0044] The trenches 21 extend in the y-axis direction in FIG. 1, i.e., the <-1120> direction, as their longitudinal direction. By extending the trenches 21 in the <11-20> direction in this manner, the (1-100) plane, which is the sidewall surface of the trench 21, can be used as a channel, thereby reducing the influence of channel mobility dependence. Furthermore, as shown in FIG. 3, a plurality of trenches 21 are formed in a stripe pattern by being arranged along the x-axis direction. The trenches 21 have semicircular tips, and two adjacent trenches 21 form a pair, and the trenches 21 in each pair are connected at their tips. The source region 19 and contact layer 20 extend along the extension direction of the trenches 21.

[0045] A source electrode 24 and a gate wiring (not shown) are formed on the surfaces of the source region 19 and the contact layer 20 and on the surface of the gate electrode 23. In this embodiment, the source electrode 24 corresponds to a first electrode.

[0046] The source electrode 24 and the gate wiring are made of a plurality of metals, such as Ni / Al, and at least the portions in contact with n-type SiC, i.e., the source region 19 or the gate electrode 23 in the case of n-doping, are made of a metal that can make ohmic contact with n-type SiC. Also, at least the portions in contact with p-type SiC, i.e., the contact layer 20 or the gate electrode 23 in the case of p-doping, are made of a metal that can make ohmic contact with p-type SiC.

[0047] The source electrode 24 and gate wiring are electrically insulated by being formed on an interlayer insulating film 25. The source electrode 24 is electrically connected to the source region 19 and the contact layer 20 through a contact hole 25a formed in the interlayer insulating film 25. This allows the first deep layer 14 to be maintained at the same potential as the source electrode 24 via the contact layer 20, the base region 18, and the second deep layer 17. In addition, the gate wiring is electrically connected to the gate electrode 23 through a contact hole 25a formed in the interlayer insulating film 25 in a cross section different from that shown in FIGS. 1 and 2.

[0048] A drain electrode 26 electrically connected to the substrate 11 is formed on the back surface of the substrate 11. In this embodiment, the substrate 11 functions as a drain layer. In this embodiment, the drain electrode 26 corresponds to a second electrode.

[0049] As described above, an n-channel inversion trench gate structure MOSFET is configured in the cell region 1. As shown in Fig. 3, the portion of the cell region 1 where the trench gate structure, source region 19, and contact layer 20 are formed is the active region 1a, and the portion between the active region 1a and the peripheral region 2 is the inactive region 1b, with the device operating in the active region 1a.

[0050] The peripheral region 2 is provided to surround the active region 1a and the inactive region 1b in the cell region 1. In the peripheral region 2, as shown in FIGS. - A second deep layer 17 formed in the cell region 1 extends on the mold layer 12. - A plurality of p-type guard rings 27 are formed in the surface layer of the mold layer 12, and are connected to the second deep layer 17 and surround the cell region 1. In this embodiment, the guard rings 27 have the same impurity concentration and depth as the first deep layer 14.

[0051] The SiC semiconductor device of this embodiment is configured as described above. Next, the width of the first deep layer 14 and the width of the first current spreading layer 13 will be described in detail.

[0052] As described above, in the active region 1a, the first deep layer 14 forms a stripe portion 141 in which multiple lines are arranged. In the inactive region 1b, the first deep layer 14 forms a frame-shaped portion 142 that is formed over the entire surface up to the boundary with the peripheral region 2, except for the vicinity of the active region 1a. Each line of the stripe portion 141 in the first deep layer 14 has both end portions 141a with a width equal to or greater than the width of the inner portion 141b. In other words, the width of both end portions of the first current spreading layer 13 is equal to or less than the width of the portion located further inward.

[0053] In this embodiment, the width of the inner portion 141b is a constant dimension, for example, 0.9 μm, and the width of the tip portion 141a gradually increases toward the tip. Specifically, the tip portion 141a gradually increases in width at an equal rate on both sides in the width direction toward the tip, and at the tip-most position, the width of the tip portion 141a is approximately 0.1 to 0.2 μm wider on each side than the inner portion 141b. Therefore, both sides in the width direction of the tip portion 141a are linear. And, because the width of the tip portion 141a gradually increases toward the tip, conversely, the width of the tip portion of the first current spreading layer 13 gradually decreases toward the tip, and the tip shape is trapezoidal.

[0054] Next, the operation of the SiC semiconductor device configured as above will be described. First, in the above-described SiC semiconductor device, in the off state before a gate voltage is applied to the gate electrode 23, no inversion layer is formed in the base region 18. Therefore, even if a positive voltage, for example, 1600 V, is applied to the drain electrode 26, electrons do not flow from the source region 19 into the base region 18, and no current flows between the source electrode 24 and the drain electrode 26.

[0055] Furthermore, before a gate voltage is applied to the gate electrode 23, an electric field is applied between the drain and gate, which can cause electric field concentration at the bottom of the gate insulating film 22. However, in the above-described SiC semiconductor device, the first deep layer 14 and the first current spreading layer 13 are provided at a position deeper than the trench 21. Therefore, a depletion layer formed between the first deep layer 14 and the first current spreading layer 13 makes it difficult for a high electric field caused by the drain voltage to penetrate into the gate insulating film 22. In particular, the width of the tip portion 141a of the first deep layer 14 is set to be equal to or greater than the width of the inner portion 141b, so that the width of the tip portion of the first current spreading layer 13 is set to be equal to or smaller than the width of the inner portion thereof. Therefore, the wide tip portion of the first current spreading layer 13 can prevent the equipotential lines from rising, making it difficult for a high electric field to penetrate into the gate insulating film 22. Therefore, in this embodiment, destruction of the gate insulating film 22 can be suppressed.

[0056] When a predetermined gate voltage, for example, 20 V, is applied to the gate electrode 23, a channel is formed on the surface of the base region 18 that is in contact with the trench 21. Therefore, electrons injected from the source electrode 24 pass through the channel formed in the base region 18 from the source region 19 and then flow into the second current spreading layer 15. The electrons that flow into the second current spreading layer 15 then pass through the first current spreading layer 13 and become n - The electrons flow into the n-type layer 12, then pass through the substrate 11 as the drain layer and flow to the drain electrode 26. As a result, a current flows between the source electrode 24 and the drain electrode 26, and the SiC semiconductor device is turned on. In this embodiment, the electrons that have passed through the channel are transferred to the second current spreading layer 15, the first current spreading layer 13, and the n-type layer 14. - The current flows through the second current spreading layer 15, the first current spreading layer 13, and the n-type layer 12 to the substrate 11. - The mold layer 12 constitutes a drift layer 16 .

[0057] Next, a method for manufacturing the SiC semiconductor device of this embodiment will be described with reference to Figures 5A to 5G, which are cross-sectional perspective views showing the part corresponding to Figure 1 during the manufacturing process.

[0058] First, as shown in Figure 5A, + A mold substrate 11 is prepared. Then, a n-type silicon carbide (SiC) is deposited on the surface of the substrate 11. - The molybdenum layer 12 is then epitaxially grown. - A mask (not shown) is formed on the surface of the mold layer 12, and the mask is patterned by photolithography or the like so that the region where the first current spreading layer 13 is to be formed is opened. Specifically, the mask is patterned so that only the cell region 1 is opened. Then, n-type impurities such as nitrogen or phosphorus are ion-implanted from above the mask and heat treatment is performed, thereby forming the first current spreading layer 13 only in the cell region 1. Thereafter, the mask is removed. Note that, for example, an LTO (Low Temperature Oxide) film or the like is used as the mask. In this embodiment, masks are also used in the processes described below, and for each mask, for example, an LTO film or the like is used.

[0059] In this embodiment, the first current spreading layer 13 is formed by ion implantation in this manner. Therefore, compared to when the first current spreading layer 13 is formed from an epitaxial film, it is easier to control the impurity concentration of the first current spreading layer 13, and variations in characteristics can be suppressed.

[0060] 5B, a mask 3 is formed and patterned by photolithography or the like so as to open the region where the first deep layer 14 is to be formed. At this time, although the peripheral region 2 is not shown, the mask 3 is also opened in the region where the guard ring 27 is to be formed. Then, p-type impurities such as Al are ion-implanted from above the mask 3 and heat treatment is performed to form the first deep layer 14 and the guard ring 27. Note that, although the first deep layer 14 and the guard ring 27 are formed in the same process here, they may be formed in separate processes.

[0061] In this embodiment, the width of the tip portion 141a of each line of the stripe portion 141 in the first deep layer 14 is set to be equal to or greater than the width of the inner portion 141b. That is, the mask 3 is designed according to the layout shown in Fig. 4, and the width of the portion of the opening of the mask 3 corresponding to the tip portion 141a is set wider than the width of the portion corresponding to the inner portion 141b, so that even if the width of the tip portion 141a is narrower than the designed value, it remains equal to or greater than the width of the inner portion 141b.

[0062] If the mask 3 were designed so that the width of each line of the stripe portion 141 is the same at the tip 141a and the inner portion 141b, as shown in FIG. 6A, the design value of the mask 3 after patterning would have the shape shown in FIG. 6B. That is, as shown in FIG. 6B, the portion of the opening 3a of the mask 3 corresponding to the tip 141a is narrowed, and the mask 3 remains in a semicircular shape at the position corresponding to the tip of the first current spreading layer 13. FIG. 6C shows the actual mask 3, and it can be seen that the portion of the opening 3a of the mask 3 corresponding to the tip 141a is narrowed. Note that the white area surrounding the opening 3a indicates the tapered portion of the mask 3 remaining. Although FIGS. 6A and 6B are not cross-sectional views, the portion that will become the mask 3 is hatched for ease of understanding.

[0063] In this way, the portion of the opening 3a of the mask 3 corresponding to the tip 141a remains narrow, and when p-type impurities are ion-implanted using the mask 3, the tip 141a is formed narrower than the inner portion 141b. Therefore, the tip of the first current spreading layer 13 becomes wider, and as shown in FIG. 7, the rise of the electric field cannot be suppressed in this portion, causing drain-source leakage, a decrease in the breakdown voltage, and a voltage increase at the bottom of the trench gate structure. This results in a partial region of reduced breakdown voltage, which prevents avalanche resistance and switching resistance from being obtained, resulting in a shortened lifespan of the gate insulating film 22.

[0064] This phenomenon occurs because the density of the reaction solution during resist etching when patterning the mask 3 is thinner near the tip 141a than in other parts, leaving the resist behind and making it impossible to form an opening that follows the shape of the tip 141a. The mask 3 remains in a semicircular shape at the position corresponding to the tip of the first current spreading layer 13, narrowing the width of the tip 141a of each line of the stripe portion 141. When we checked how much the spacing between the lines of the stripe portion 141 had actually increased at the tip 141a, we found that it was 40 to 50% wider than the design value.

[0065] Simulations were conducted to investigate the relationship between the spacing between each line of the stripe portion 141 and the breakdown voltage, as well as the electric field strength applied to the gate insulating film 22. Specifically, the case where the spacing between each line is the designed value was defined as 100%, and the breakdown voltage and the electric field strength applied to the gate insulating film 22 were calculated when the spacing between each line was increased. FIGS. 8A and 8B show the results. As shown in these figures, when the spacing between each line is increased by 40% from the designed value, that is, to 140%, it was found that the breakdown voltage decreases by about 400 V from the designed value of 1200 V, and the electric field strength applied to the gate insulating film 22 increases by about 330%. These simulation results also raise concerns about a shortened lifespan of the gate insulating film 22.

[0066] In contrast to this, in this embodiment, the width of the portion of the opening in the mask 3 corresponding to the tip 141a is made wider than the width of the portion corresponding to the inner portion 141b, so that even if the width of the tip 141a is narrower than the design value, it remains equal to or wider than the width of the inner portion 141b. Therefore, the tip of the first current spreading layer 13 can be prevented from widening, and the electric field can be prevented from rising up in that portion, making it possible to prevent a decrease in the breakdown voltage and lifespan of the gate insulating film 22.

[0067] Next, as shown in FIG. 5C, - The second current spreading layer 15 made of SiC is epitaxially grown on the type layer 12, the first current spreading layer 13, and the first deep layer 14. As a result, the n -A drift layer 16 is formed having a mold layer 12, a first current spreading layer 13, and a second current spreading layer 15.

[0068] Next, a mask (not shown) is formed and patterned by photolithography or the like so that the region where the second deep layer 17 is to be formed is opened. Then, p-type impurities such as Al are ion-implanted from above the mask and heat treatment is performed to form the second deep layer 17. At this time, the second deep layer 17 is extended in a direction intersecting the extension direction of the first deep layer 14. Therefore, even if there is some positional misalignment when the second deep layer 17 is formed, it is possible to prevent the first deep layer 14 and the second deep layer 17 from being disconnected.

[0069] 5D, a base region 18 is formed by epitaxially growing a p-type impurity layer on the second current spreading layer 15 and the second deep layer 17. Subsequently, a source region 19 is formed on the base region 18 by epitaxially growing an n-type impurity layer.

[0070] 5E, a mask (not shown) is formed and patterned by photolithography or the like so that an opening is formed in the region where the contact layer 20 is to be formed. Furthermore, p-type impurities such as Al are ion-implanted from above the mask and heat treatment is performed, thereby forming the contact layer 20.

[0071] Next, as shown in FIG. 5F , a mask (not shown) is formed, and then the mask is patterned so as to open an area where the trench 21 is to be formed. Then, anisotropic etching is performed to form the trench 21. Specifically, the trench 21 is formed so as to penetrate the source region 19 and the base region 18 and have its bottom located within the second current spreading layer 15. In other words, the trench 21 is formed so that the first current spreading layer 13 and the first deep layer 14 are located below the bottom surface of the trench 21. After the anisotropic etching, isotropic etching or sacrificial layer oxidation may be performed as necessary.

[0072] Next, as shown in FIG. 5G, a gate insulating film 22 is formed in a location including the inside of the trench 21. For example, the gate insulating film 22 is formed by thermal oxidation, specifically gate oxidation using a pyrogenic method in a wet atmosphere. Subsequently, a polysilicon layer doped with n-type impurities is formed on the surface of the gate insulating film 22 to a thickness of about 440 nm at a temperature of, for example, 600° C., and then an etch-back process or the like is performed so that the gate insulating film 22 and the gate electrode 23 remain in the trench 21. This completes the trench gate structure.

[0073] The subsequent steps are not shown because they are the same as those of the conventional method, but include the steps of forming an interlayer insulating film 25, forming contact holes 25a, forming source electrodes 24 and gate wiring, and forming a drain electrode 26 on the back surface of the substrate 11. In this way, the SiC semiconductor device of this embodiment is manufactured.

[0074] As described above, in this embodiment, the width of the tip 141a of each line of the stripe portion 141 in the first deep layer 14 is set to be equal to or greater than the width of the inner portion 141b. In other words, even if the portion of the mask 3 corresponding to the tip 141a narrows, the width of the tip 141a can be set to be equal to or greater than the width of the inner portion 141b. This prevents the tip of the first current spreading layer 13 from widening, thereby suppressing the electric field from rising up in that portion, thereby suppressing a decrease in the breakdown voltage and lifespan of the gate insulating film 22.

[0075] (Modification of the first embodiment) In the first embodiment, the width of the tip portion 141a gradually increases toward the tip, while both sides of the tip portion 141a in the width direction are linear. In other words, the tip of the first current distribution layer 13 is trapezoidal. Alternatively, as shown in FIG. 9A , the width of the tip portion 141a gradually increases toward the tip, while both sides of the tip portion 141a in the width direction are curved, such as an elliptical arc. For example, the tip of the first current distribution layer 13 may be elliptical, including a circular shape. Alternatively, as shown in FIG. 9B , both sides of the tip portion 141a in the width direction may be linear, while the tip of the first current distribution layer 13 is triangular. Furthermore, both sides of the tip portion 141a in the width direction do not have to have the same shape, and the widths may be different.

[0076] In this embodiment, the longitudinal direction of each line in the stripe portion 141 is perpendicular to the longitudinal direction of the trench gate structure, but it may be in a direction other than perpendicular, intersecting the longitudinal direction, or may be parallel to the longitudinal direction. When the longitudinal direction of each line in the stripe portion 141 is parallel to the longitudinal direction of the trench gate structure, the pitch between each line and the second deep layer 17 may be equal.

[0077] (Second embodiment) The second embodiment will be described. This embodiment is different from the first embodiment in that it specifies the layout of the stripe portion 171 in the second deep layer 17, and is otherwise similar to the first embodiment, so only the differences from the first embodiment will be described.

[0078] In the first embodiment, a countermeasure was taken to address the reduction in gate life caused by the increase in the width of the first current spreading layer 13 at the end portions of each line of the stripe portion 141 due to the narrowing of the width at the end portions. On the other hand, as described above, it was confirmed that the distance between the frame portion 142 and the stripe portion 141 is wider than the distance between the lines constituting the stripe portion 141. Since the rise of the equipotential lines cannot be suppressed even between the frame portion 142 and the stripe portion 141 where this distance has increased, there is a concern that the gate life will be reduced. In the present embodiment, a countermeasure is taken to address this reduction in gate life.

[0079] As shown in FIG. 10 , in this embodiment, the tip 171a of each line of the stripe portion 171 in the second deep layer 17 is wider than the inner portion 171b located further inward. That is, the width of the second current spreading layer 15 is narrower at both ends than at the inner portion. For example, the inner portion 171b is approximately 0.7 to 1.6 μm, and the tip 171a gradually increases in width relative to the inner portion 171b on both sides of the width direction, and then becomes constant in width. Therefore, the second current spreading layer 15 has a rectangular shape with a constant width at the tip and 90° corners. The ratio of the increase in width of the tip 171a relative to the inner portion 171b is arbitrary, but is preferably approximately 10 to 30%, e.g., approximately 0.1 μm on each side of the width direction. The tip portion 171a of the second deep layer 17 is a portion located within the inactive region 1b, and the width of the tip portion 171a within the inactive region 1b is wider than the width of the inner portion 171b.

[0080] The start point for widening the tip portion 171a is arbitrary, but it is preferable to start from the line of the stripe portion 141 in the first deep layer 14 that is located closest to the frame-shaped portion 142.

[0081] As described above, the distance between the frame portion 142 and the stripe portion 141 may become wider than the distance between the lines that make up the stripe portion 141. When this distance becomes wider, the equipotential lines may not be prevented from rising up between the frame portion 142 and the stripe portion 141, which may result in a decrease in gate life.

[0082] In contrast, in this embodiment, the tip portion 171a of the second deep layer 17 is also set to be wider than or equal to the width of the inner portion 171b. This allows the distance between the frame portion 142 and the stripe portion 141 of the second deep layer 17 to be narrowed. Therefore, even if the electric field relaxation effect of the first deep layer 14 is reduced due to the widening of the gap between the frame portion 142 and the stripe portion 141, the electric field relaxation effect of the second deep layer 17 can push back the equipotential lines, making it difficult for a high electric field to penetrate. This makes it possible to suppress a decrease in the breakdown voltage and lifespan of the gate insulating film 22.

[0083] (Modification of the second embodiment) In the second embodiment, the width of the tip portion 171a gradually increases toward the tip and then becomes constant. In other words, the tip of the second current distribution layer 15 is rectangular, i.e., the corners of the tip are 90 degrees. Alternatively, as shown in FIG. 11A, both widthwise sides of the tip portion 171a may be linear, and the tip of the second current distribution layer 15 may be triangular. Alternatively, as shown in FIG. 11B, the width of the tip portion 171a may gradually increase toward the tip, while both widthwise sides of the tip portion 171a may be curved, such as in an arc shape. For example, the tip of the second current distribution layer 15 may be elliptical, including a circular shape. Furthermore, both widthwise sides of the tip portion 171a do not have to have the same shape, and the widths may be different.

[0084] (Third embodiment) The third embodiment will be described. This embodiment is different from the first and second embodiments in that the layout of the stripe portion 141 in the first deep layer 14 is changed, but the rest is the same as the first and second embodiments, so only the parts that are different from the first and second embodiments will be described.

[0085] When the stripe portion 141 of the first deep layer 14 and the stripe portion 171 of the second deep layer 17 are configured to intersect, the portion of the stripe portion 141 that intersects with the trench gate structure becomes a factor that obstructs the current path. This increases the on-resistance. In this embodiment, a measure is taken to address this increase in on-resistance.

[0086] 12, in this embodiment, the stripe portion 141 intersects with the trench gate structure, but each line is partially formed into a rectangular strip and divided by a cutout portion 14a, making each line a broken line. The trench gate structure passes through the cutout portion 14a, thereby ensuring a path for current to flow through that portion.

[0087] The locations of the cutouts 14a in each line of the stripe portion 141 are arbitrary, but it is preferable to arrange them in a staggered pattern as shown in Figure 12. That is, in adjacent lines, the cutouts 14a are formed so as to be shifted in the longitudinal direction of the line by the spacing between the trench gate structures, and the cutouts 14a in every other line are formed in a portion corresponding to the same trench gate structure. In this way, the lines of the stripe portion 141 can be arranged below every other trench gate structure, while the in-plane distribution of the cutouts 14a can be made uniform.

[0088] As described above, in this embodiment, while the stripe portion 141 intersects with the trench gate structure, each line is partially divided by the cutout portion 14a, and the trench gate structure passes through the cutout portion 14a. In this way, the number of intersections between the first deep layer 14 and the trench gate structure can be reduced compared to the first and second embodiments, making it possible to suppress an increase in on-resistance.

[0089] Here, the size of the line gaps 14a in the stripe section 141, i.e., the spacing between the lines separated in the longitudinal direction, is preferably 2.6 μm or less. The size of the gaps 14a was varied to investigate the breakdown voltage. Specifically, the drain voltage Vd at which gate breakdown occurred was determined based on the change in gate current Ig. Figure 13 shows the results, extracting the results when the line gaps were 2.6 μm, 4.8 μm, and 9.6 μm.

[0090] As shown in Figure 13, the greater the spacing between the lines, the smaller the breakdown voltage. If the preferred breakdown voltage for a SiC semiconductor device is 950 V, this can be met if the spacing between the lines is at least 2.6 μm or less. Of course, the lower limit of the spacing between the lines can be set according to the required breakdown voltage, and if the required breakdown voltage is 950 V or less, a spacing of 4.8 μm between the lines may be possible.

[0091] While the spacing between lines separated in the longitudinal direction has been described above, the same can be said for the spacing in the y direction between alternately arranged lines that are adjacent to each other at the cutout 14a. In other words, the diameter φ of a circle centered at the center of the cutout 14a, shown by the dashed line in Figure 12, is set to φ2.6 μm, and the layout should be such that both alternately arranged lines that are adjacent to each other across the cutout 14a are in contact with or inside this circle.

[0092] (Modification of the third embodiment) In the third embodiment, the angle of the corners of the divided portions of each line constituting the stripe portion 141 is 90°, and each divided portion is in the shape of a rectangular strip. However, each divided portion of each line may have a shape that gradually decreases in width toward the tip, for example, an elliptical shape including a semicircular shape as shown in Fig. 14A, or a triangular shape as shown in Fig. 14B. Furthermore, both sides of the tip of each divided portion of each line in the width direction do not have to have the same shape.

[0093] Furthermore, instead of forming the divided portions of each line in a strip-like shape as in the third embodiment, they can also be formed in a dot-like shape. Specifically, each dot may be formed in an elliptical shape including a circular shape. For example, as shown in FIG. 15A, if each dot is formed in a circular shape, the lines constituting the stripe portion 141 can be arranged in a polka dot shape. Furthermore, each dot may be formed in a polygonal shape. For example, as shown in FIG. 15B, if each dot is formed in a hexagonal shape, the lines constituting the stripe portion 141 can be arranged in a honeycomb shape. In this way, even if the divided portions of each line constituting the stripe portion 141 are formed in a dot-like shape, it is possible to reduce an increase in on-resistance while ensuring a breakdown voltage.

[0094] (Fourth embodiment) The fourth embodiment will be described. This embodiment is different from the first to third embodiments in the configuration of the deep layer, but is otherwise similar to the first to third embodiments, so only the differences from the first to third embodiments will be described.

[0095] In the first to third embodiments, the deep layer has a two-layer structure in which the first deep layer 14 and the second deep layer 17 are stacked. However, it has been confirmed that the forward voltage Vf fluctuates due to the influence of holes generated when a parasitically formed PN diode is energized. Furthermore, it has been confirmed that when the deep layer has a two-layer structure in which the first deep layer 14 and the second deep layer 17 are used, basal plane dislocations (hereinafter referred to as BPDs) present in SiC expand into stacking faults, which obstruct the current path and increase the on-resistance. In this embodiment, measures are taken to address these fluctuations in the forward voltage Vf and the increase in the on-resistance.

[0096] 16, this embodiment includes a third deep layer 30. That is, the deep layer has a three-layer structure including the first deep layer 14, the second deep layer 17, and the third deep layer 30.

[0097] In this embodiment, the third deep layer 30 is disposed below the first current spreading layer 13 and the first deep layer 14. Specifically, the third deep layer 30 is disposed below the first deep layer 14 at a position corresponding to the second current spreading layer 15, that is, directly below the trench gate structure. The third deep layer 30 has n - Although it may be formed in the mold layer 12, in this case, it is adjacent to the third deep layer 30 and - The third deep layer 30 and the third current spreading layer 31 have a higher n-type impurity concentration than the type layer 12. Both the third deep layer 30 and the third current spreading layer 31 have stripe portions in which a plurality of lines are arranged in a stripe pattern, and the lines constituting each stripe portion are arranged alternately.

[0098] At least in the active region 1a, the third deep layer 30 is a stripe portion in which a plurality of lines are arranged with their longitudinal direction being the same as that of the trench 21. The stripe portion in this third deep layer 30 corresponds to the third stripe portion. Although not shown, in the inactive region 1b, the third deep layer 30 is formed as a stripe portion only on the active region 1a side, and in the outer region, it is formed all over the surface up to the peripheral region 2, forming a frame-like portion surrounding the stripe portion, but it may also be just a stripe portion.

[0099] The SiC semiconductor device of this embodiment includes a MOSFET. Due to its structure, a PN diode is formed parasitically in the MOSFET. Specifically, the parasitic PN diode is formed by a PN junction between a p-type layer such as the base region 18 and an n-type layer constituting a drift layer such as the second current spreading layer 15. Therefore, when the MOSFET is applied to an inverter or the like, the parasitic PN diode can be used as a freewheeling diode, eliminating the need for a separate freewheeling diode, which is expected to reduce the number of components (hereinafter, this parasitic PN diode will be referred to as a parasitic FWD).

[0100] When the parasitic FWD operates as a diode, holes that diffuse from the base region 18 into the drift layer and act as minority carriers recombine with electrons in the drift layer. The holes generated when the parasitic FWD is energized cause fluctuations in the forward voltage Vf, affecting device operation. Furthermore, the energy generated when holes and electrons recombine expands BPDs in the drift layer, which is made of an epitaxial film, and turns into stacking faults. Because BPDs are linear defects, they occupy a small area within the cell region of a semiconductor device and have little effect on device operation. However, stacking faults expand their area within the cell region and significantly affect device operation. In particular, when a large current flows through the parasitic FWD, holes can reach the substrate 11 located below the drift layer. Because the BPD defect density in the substrate 11 is significantly higher than in the drift layer, the area occupied by stacking faults increases, further increasing the on-resistance.

[0101] In contrast, in the SiC semiconductor device of this embodiment, the deep layer has a three-layer structure including a first deep layer 14, a second deep layer 17, and a third deep layer 30. When the deep layer has a three-layer structure, holes generated in the base region 18 pass through the second current spreading layer 15, the first current spreading layer 13, and the third current spreading layer 31, as shown by the arrows in FIG. 17 . Therefore, when the deep layer has a three-layer structure, the hole migration path is longer by the amount indicated by the dashed line in the figure compared to when the deep layer has a two-layer structure, and more holes can be recombined and annihilated. Therefore, holes annihilate before reaching the substrate 11, making it possible to suppress fluctuations in the forward voltage Vf due to the influence of holes. It is also possible to suppress the expansion of BPDs into stacking faults. In particular, the n-type ... - The third current spreading layer 31 has a higher n-type impurity concentration than the type layer 12, which makes it easier for holes to recombine and disappear, and furthermore, prevents stacking faults from being formed.

[0102] As described above, in the SiC semiconductor device of this embodiment, the deep layer has a three-layer structure including the first deep layer 14, the second deep layer 17, and the third deep layer 30. This makes it possible to suppress the influence of fluctuations in forward voltage Vf on device operation, as well as to suppress the expansion of BPD into stacking faults, thereby suppressing an increase in on-resistance.

[0103] (Modification of the fourth embodiment) In the first embodiment, an example of a three-layer structure for the deep layer is shown, but other three-layer structures are also possible. For example, the structure shown in FIG. 18 can be used. Compared to the structure shown in FIG. 16, the structure shown in FIG. 18 has a narrower pitch between the lines constituting the stripe portion of the third deep layer 30 and the third current spreading layer 31. Specifically, the pitch between the lines constituting the stripe portion of the third deep layer 30 and the third current spreading layer 31 is narrower than the pitch between the lines of the stripe portion 171 of the second deep layer 17 and the stripe-shaped second current spreading layer 15.

[0104] Even in such a structure, holes generated in the base region 18 pass through the second current spreading layer 15, the first current spreading layer 13, and the third current spreading layer 31, as shown in Fig. 19. This lengthens the hole movement path, allowing more holes to recombine and disappear, thereby achieving the same effect as in the fourth embodiment.

[0105] Alternatively, the structure shown in FIG. 20 may be used. In the structure shown in FIG. 20, the second deep layer 17 is arranged directly below the trench gate structure rather than at a position away from the trench gate structure, as compared to the structure shown in FIG. 16. The second deep layer 17 is arranged so as to be in contact with the bottom of the trench 21, and the second current spreading layer 15 is arranged on both sides of the trench gate structure. The second current spreading layer 15 is in contact with the side surface of the trench 21 at a position below the base region 18 on the side surface of the trench gate structure, that is, the second current spreading layer 15 is interposed between the base region 18 and the second deep layer 17.

[0106] Furthermore, when the second deep layer 17 is disposed directly below the trench gate structure, a structure connecting the second deep layer 17 to the base region 18 is required. For this reason, the contact layer 20 is formed so as to intersect with the trench gate structure and reach the second deep layer 17. For example, a trench is formed so as to penetrate the source region 19 and the base region 18 and reach the second deep layer 17. Then, a p + A mold layer is formed and then etched back, or high-acceleration ion implantation using a mask (not shown) is used to form the contact layer 20 having the structure shown in FIG.

[0107] Even in such a structure, holes generated in the base region 18 travel along a migration path that passes from the second current spreading layer 15, bypasses the second deep layer 17, passes through the first current spreading layer 13, and then travels to the third current spreading layer 31, as shown in Fig. 21. This lengthens the migration path of the holes, allowing more holes to recombine and disappear, thereby achieving the same effect as in the fourth embodiment.

[0108] Furthermore, when the second deep layer 17 is disposed directly below the trench gate structure, the second deep layer 17 may be spaced apart from the bottom of the trench 21, as shown in Fig. 22. Even in such a structure, holes generated in the base region 18 travel along a migration path that bypasses the second deep layer 17 from the second current spreading layer 15, passes through the first current spreading layer 13, and then travels to the third current spreading layer 31, as shown in Fig. 23. This lengthens the migration path of the holes, allowing more holes to recombine and disappear, thereby achieving the same effect as in the fourth embodiment.

[0109] 20 and 22, the pitch of each line constituting the stripe portion of the third deep layer 30 or the third current spreading layer 31 is narrowed as shown in Fig. 18. In contrast, as in the fourth embodiment, the pitch of each line of the stripe portion 171 of the second deep layer 17 or the striped second current spreading layer 15 may be the same as the pitch of each line constituting the stripe portion of the third deep layer 30 or the third current spreading layer 31.

[0110] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment and encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0111] For example, in the above embodiments, an n-channel MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example, but the present invention can also be applied to a p-channel MOSFET in which the conductivity types of the components are reversed. Furthermore, in the above embodiments, a MOSFET with a trench gate structure has been described as an example of a semiconductor switching element, but the present invention can also be applied to an IGBT with a similar trench gate structure. The IGBT differs from the above embodiments in that the conductivity type of the substrate 11 is changed from n-type to p-type; other structures and manufacturing methods are the same as those of the above embodiments.

[0112] In each of the above embodiments, the stripe portion 141 of the first deep layer 14 may extend, for example, along the y-axis direction. That is, the first deep layer 14 may extend in the same direction as the second deep layer 17. In each of the above embodiments, the second current spreading layer 15 may extend, for example, in the n - The first current spreading layer 13 may have the same impurity concentration as the mold layer 12. The first current spreading layer 13 may be formed not only in the cell region 1 but also in the outer periphery region 2.

[0113] Furthermore, in each of the above embodiments, the second deep layer 17 is provided with a frame-shaped portion 172 in the inactive region 1b, but as long as the first deep layer 14 is provided with a frame-shaped portion 142, the second deep layer 17 may only have a stripe portion 171.

[0114] Furthermore, in each of the above embodiments, a SiC semiconductor device using SiC as a semiconductor material is described as an example, but similar effects can be obtained by applying the same configuration as in each of the above embodiments to semiconductor devices using other semiconductor materials, such as Si.

[0115] Furthermore, in the above embodiments, the case where the substrate 11 constitutes the semiconductor region has been described, but the semiconductor region does not necessarily have to be constituted by the substrate 11. For example, when silicon is used as the semiconductor material, the portion corresponding to the first impurity region can be constituted by the silicon substrate, and a high-concentration region having a higher impurity concentration than the silicon substrate can be formed on the back side of the silicon substrate by ion implantation or the like. In that case, the high-concentration region formed on the back side of the silicon substrate constitutes the semiconductor region.

[0116] When indicating the crystal orientation, a bar (-) should normally be placed above the desired number. However, due to limitations on expression based on electronic filing, in this specification, a bar will be placed before the desired number. [Explanation of symbols]

[0117] 11 Substrate (semiconductor region) 12n - Type layer (first impurity region) 13 1st current distribution layer 14 First Deep Layer 15 Second current distribution layer 17 Second Deep Layer 18 Base Area 19 Source region (second impurity region) 23 Gate electrode 24 Source electrode (first electrode) 26 Drain electrode (second electrode)

Claims

1. A semiconductor device having an active region (1a) in which a semiconductor switching element having a plurality of trench gate structures is formed and which is operable as an element, and an inactive region (1b) which surrounds the active region and is not operable as an element, a semiconductor region (11) of a first conductivity type or a second conductivity type; a first impurity region (12) of a first conductivity type formed on the semiconductor region and having a lower impurity concentration than the semiconductor region; a base region (18) of a second conductivity type formed on the first impurity region; a second impurity region (19) of the first conductivity type formed on the base region and having a higher impurity concentration than the first impurity region; a plurality of trench gate structures each having a gate insulating film (22) formed on an inner wall surface of a trench (21) formed from the surface of the second impurity region to a depth deeper than the base region, with one direction as a longitudinal direction, and a gate electrode (23) formed on the gate insulating film within the trench; a first electrode (24) electrically connected to the second impurity region and to the base region; a second electrode (26) formed on the back surface side of the semiconductor region and electrically connected to the semiconductor region, Furthermore, a first current spreading layer (13) of a first conductivity type formed between the first impurity region and the base region and having a higher impurity concentration than the first impurity region; a first stripe portion (141) extending in one direction on the active region side of the active region and the non-active region with a plurality of lines arranged; a second conductivity type layer (30) disposed below the first stripe portion and the first current spreading layer, extending in the same direction as the longitudinal direction of the trench, and having a stripe portion in which a plurality of lines are arranged; a first conductivity type layer (31) disposed below the first stripe portion and the first current spreading layer, disposed between each line constituting the stripe portion of the second conductivity type layer, and having an impurity concentration higher than that of the first impurity region.

2. 2. The semiconductor device according to claim 1, further comprising: a first deep layer (14) of a second conductivity type having the first stripe portion and a frame-shaped portion (142) formed in the inactive region, surrounding the periphery of the first stripe portion and connected to each line constituting the first stripe portion.

3. 3. The semiconductor device according to claim 1, wherein each line constituting the first stripe portion includes a tip portion (141a) connected to the frame-shaped portion and an inner portion (141b) located more inward than the tip portion, and the width of the tip portion is equal to or greater than the width of the inner portion.

4. 4. The semiconductor device according to claim 3, wherein the width of said tip portion gradually increases toward the tip, and said tip of said first current spreading layer has one of a trapezoidal, triangular and elliptical shape.

5. 4. The semiconductor device according to claim 3, wherein the width of the tip portion is gradually increased toward the tip, the width of the inner portion is 0.3 μm or more, and at the most distal position of the tip portion where it connects to the frame-shaped portion, the width of the tip portion is wider on one side than the width of the inner portion by 0.1 to 0.2 μm.

6. the trench gate structure is formed in a stripe shape by forming a plurality of the trenches aligned in a direction perpendicular to a longitudinal direction of the trenches, 6. The semiconductor device according to claim 3, wherein the tip portion is laid out so as to overlap an outermost portion of the trench gate structure having a stripe shape.

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