Fabrication stack for high density superconducting digital circuits.

Abstract

A stack (100) for manufacturing a superconducting chip includes at least one Josephson junction, at least one capacitor, and one or more high mechanical inductance wires comprising NbTiN, the mechanical inductance wires being configured to electrically couple the at least one Josephson junction to the at least one capacitor to form a superconducting circuit that facilitates switching the state of the Josephson junction via a single flux quantum (SFQ) pulse.

Description

[Technical field]

[0001] This application relates to superconducting circuits. In particular, this application discloses a fabrication stack for high integration density superconducting digital circuits. [Background technology]

[0002] Superconducting digital systems are capable of performing computations at clock speeds exceeding 100 GHz. In these systems, the circuits contain superconducting wires and Josephson junctions that form superconducting loops in which information in the form of single flux quantum (SFQ) is encoded and stored.

[0003] Superconducting circuits can be configured to implement conventional logic gates such as AND gates, OR gates, flip-flops, etc. These gates can also be configured to implement more complex logic such as shift registers, counters, processors, etc.

[0004] Manufacturing superconducting digital systems on a large scale is difficult due to manufacturing constraints related to power distribution, logic efficiency, and memory density. Summary of the Invention

[0005] In a first aspect, a fabrication stack includes at least one Josephson junction, at least one capacitor, and one or more high kinetic induction wires including NbTiN configured to electrically couple the at least one Josephson junction to the at least one capacitor to form a superconducting circuit that facilitates switching states of the Josephson junctions via single flux quantum (SFQ) pulses.

[0006] In a second aspect, a method of fabricating a superconducting circuit includes forming in a fabrication stack at least one Josephson junction, at least one capacitor, and one or more high-mechanical inductance wires comprising NbTiN, the one or more high-mechanical inductance wires configured to electrically couple the at least one Josephson junction to the at least one capacitor to form a superconducting circuit that facilitates switching a state of the Josephson junction via a single flux quantum (SFQ) pulse.

[0007] In a third aspect, a device includes a superconducting chip. The superconducting chip includes a fabrication stack including at least one Josephson junction, at least one capacitor, and one or more high-mechanical inductance wires including NbTiN. The one or more high-mechanical inductance wires are configured to electrically couple the at least one Josephson junction to the at least one capacitor to form a superconducting circuit that facilitates switching the state of the Josephson junction via a single flux quantum (SFQ) pulse. [Brief description of the drawings]

[0008] The above and additional features will be better understood through the following illustrative and non-limiting detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

[0009] [Figure 1] 1 illustrates a cross section of a fabrication stack in accordance with an example embodiment. [Diagram 2] 1 illustrates a back-end layer of a manufacturing stack in accordance with an example embodiment. [Figure 3A] 4 illustrates a Josephson junction formed in a first group of layers of a fabrication stack according to an example embodiment. [Figure 3B] 4 illustrates a Josephson junction formed in a first group of layers of a fabrication stack according to an example embodiment. [Figure 4] 1 illustrates a capacitor formed in a first group of layers of a fabrication stack according to an example embodiment. [Diagram 5] 1 illustrates a portion of an AC powered superconducting circuit that may be implemented via the manufacturing processes described herein according to example embodiments. [Figure 6] 1 illustrates operations that facilitate fabrication of a superconducting circuit in accordance with an example embodiment.

[0010] All figures are schematic, not necessarily to scale, and generally show only those parts necessary to elucidate the exemplary embodiments, other parts being omitted or merely suggested. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Various examples of systems, devices, and / or methods are described herein with reference to the accompanying drawings. Any embodiment, implementation, and / or feature described herein as being exemplary is not necessarily to be construed as preferred or advantageous over other embodiments, implementations, and / or features, unless so described. Thus, other embodiments, implementations, and / or features may be utilized and other changes may be made without departing from the scope of the subject matter presented herein.

[0012] Accordingly, the examples set forth herein are not meant to be limiting, as it will be readily understood that the aspects of the present disclosure, as generally described and illustrated in the Figures herein, can be arranged, substituted, combined, separated and designed in a wide variety of different configurations.

[0013] Moreover, unless the context suggests otherwise, the features illustrated in each figure may be used in combination with each other. Thus, the figures should generally be viewed as components of one or more overall embodiments, with the understanding that not all illustrated features are required for every embodiment.

[0014] Moreover, recitations of elements, blocks, or steps in the specification or claims are for the sake of clarity, and thus such recitations should not be construed as requiring or implying that these elements, blocks, or steps follow a particular arrangement or be performed in a particular order.

[0015] Furthermore, terms such as "substantially" or "about" may be used herein to mean that the referenced property, parameter, or value need not be achieved exactly, but that deviations or variations, including, for example, tolerances, measurement errors, limits of measurement accuracy, and other factors known to those of skill in the art, may occur in an amount that does not interfere with the effect that the property is intended to provide.

[0016] Additionally, terms such as "A coupled to B," "A electrically coupled to B," etc. do not necessarily mean that items A and B are directly coupled to one another. For example, a first component being electrically coupled to a second component is interpreted to mean that the components are either directly coupled (e.g., via conductors) or are coupled to one another via one or more resistors, capacitors, inductors, and / or other active or passive components.

[0017] As mentioned above, a superconducting circuit includes superconducting wires and Josephson junctions that form a superconducting loop in which information in the form of single flux quantum (SFQ) is encoded and stored. Examples of superconducting circuits include quantum flux paramatron (QFP) circuits and inverse quantum logic (RQL) circuits, which are both powered and clocked by multiphase AC signals.

[0018] Superconducting wire is made of materials that can carry direct current in the absence of an electric field. Such materials have almost zero resistance below a critical temperature. Niobium, an example of a superconductor, has a critical temperature (Tc) of 9.2 Kelvin. Below the critical temperature, niobium is superconducting. However, above the critical temperature, niobium behaves like a normal metal with electrical resistance.

[0019] A Josephson junction contains two superconductors coupled through a region that prevents current flow. Examples of this region include or correspond to a physical constriction of the superconductor itself, a metallic region, or a thin insulating barrier. Some examples of Josephson junctions include a niobium superconductor with an Al superconductor between them. 2 O 3 barrier. When the potential difference between the two superconductors is integrated with respect to time over one cycle of phase change, the magnetic flux through the loop changes by an integer multiple of a single quantum of magnetic flux. The voltage pulse associated with one quantum of magnetic flux corresponds to the SFQ pulse mentioned above. As an example, an overdamped Josephson junction can generate individual SFQ pulses. In an RQL circuit, each Josephson junction may be part of one or more superconducting loops. The phase difference across the junction may be modulated by the magnetic flux applied to the loop.

[0020] As mentioned above, large-scale manufacturing of this type of circuitry is difficult due to manufacturing constraints related to clock and power distribution, logic efficiency, and memory density. For example, conventional superconducting manufacturing processes for digital circuits use Nb interconnects and Nb / AlO xThe current technology utilizes Nb / Nb Josephson junctions. As an elemental superconductor, Nb has a relatively high critical temperature of 9.2 K and can be fabricated by conventional DC sputtering and etching processes. Nb-based processes have enabled numerous superconducting circuit demonstrations in academia and industry worldwide. However, recent attempts to use Nb in product prototypes with increasing numbers of metal layers and scaling feature sizes down to 0.25 μm have run into fundamental scalability limitations. These include 1) unstable material properties due to a low diffusion constant, affecting tolerances at submicron dimensions, 2) low inductance per unit length, limiting density and signal integrity, 3) high microwave losses due to inherent material properties and susceptibility to surface contamination, and 4) the need for relatively low processing temperatures, typically not exceeding 200 °C. The low processing temperatures result in a number of secondary issues, mainly with respect to the dielectric, with the overall effect limiting feature size, number of layers, and process control. Nb typically exhibits degradation of superconducting properties from top to bottom through the stack due to the cumulative effects of processing. The critical temperature distribution of the wires varies significantly from process to process and from wafer to wafer. Hydrogen poisoning causes further degradation in some fabrication processes. Material degradation misleads inductance models, resulting in parameter spreads that are more sensitive at smaller dimensions. A typical gate requires an inductance of 140 pH. Using Nb results in wiring area 100 times larger than Josephson junctions. Excessive wiring results in tight meanders and high overhead in the wiring layers, which is difficult to achieve with automated routing methods designed to minimize overall length. Nb wires without a superconducting ground plane can have mutual inductances up to 50% and are susceptible to parasitic cross-net coupling and isolated flux trench coupling.

[0021] Some examples disclosed herein improve some of these problems. For example, disclosed herein are some examples of fabrication stacks related to superconducting chips. The fabrication stack includes one or more Josephson junctions, a capacitor, and a high-mechanical inductance wire. The high-mechanical inductance wire is configured to electrically couple the Josephson junction to the capacitor to form a superconducting circuit that facilitates switching the state of the Josephson junction via a single flux quantum (SFQ) pulse. The high-mechanical inductance wire improves signal integrity and reduces parasitic magnetic coupling in superconducting digital circuits.

[0022] In some examples, the high mechanical inductance wire comprises NbTiN and has a London penetration depth of TIFF2025500393000002.tif7170 and L sq =μ 0 λ L 2 / d, where μ 0 is the magnetic permeability constant of the material, and d is the film thickness of the material. The inductance is set by adjusting the film thickness d of the material.

[0023] Furthermore, NbTiN is compatible with a wide range of fabrication processes, including conformal chemical vapor deposition (CVD) and atomic layer deposition (ALD), which allows for easy damascene fill and high aspect ratio through silicon vias (TSVs). Conformal high temperature NbTiN with stable superconducting properties and thickness control down to 5 nm is achievable by several of these processes.

[0024] FIG. 1 illustrates a cross-section of an example of a fabrication stack 100. The fabrication stack 100 includes various layers 115 in which one or more power and clock interconnects, inductors, capacitors, Josephson junctions, etc. are formed, and superconducting circuits, such as the RQL circuits described above. In some examples, one or more Josephson junctions 105, capacitors 110, high-mechanical inductance wires 107A, and intermediate grounds 116 are formed in a first layer group 115A. In one example, these high-mechanical inductance wires electrically couple the Josephson junctions to the capacitors to form one or more superconducting series circuits configured to support signals in the form of single flux quantum (SFQ). In some examples, high-mechanical inductance wires 107B that facilitate power and clock distribution are formed in a second layer group (hereafter, power distribution layers 115B). In some examples, high-mechanical inductance wires 107C that realize localized inductive lines and long passive transmission lines are formed in a third layer group (hereafter, back-end layers 115C). Although various superconducting elements are described as being in particular layers or layers, it is contemplated that these and / or other superconducting elements may be formed in different layers and that the order in which the elements are formed within those layers may vary. Additionally, while a particular number of layers are shown, it is understood that one or more embodiments disclosed herein may be implemented with a different number of layers.

[0025] In some examples, the high mechanical inductance wire comprises NbTiN. The use of such materials facilitates the formation of digital circuits with low manufacturing parameter spreads and high yields. The operating margins and speed of SFQ circuits are limited by the allowable spread in inductance σ L, with 1 sigma of 2% or better being a typical requirement. NbTiN interconnect layers facilitate this level of control or better at much smaller feature sizes. In addition, the ternary nitride NbTiN has a 1.8 times higher critical temperature (e.g., Tc=17.3K) and a 1.8 times higher gap voltage (e.g., Vg=5.2mV). NbTiN is less susceptible to contamination, which allows stable superconducting properties to be obtained at processing temperatures up to 1000°C. This also includes extremely low residual resistivity. NbTiN with a high Ti composition (e.g., 45%) produces a low vacancy count and high stability. NbTiN interconnects have 100 times lower loss than Nb, which translates to 10 times higher throughput and 10 times lower energy per bit.

[0026] In some examples, the wires in the distribution layer 115B are configured to be electrically coupled to one or more alternating current (AC) voltage sources that output AC voltages of the same frequency but different phases. In some examples, the wires are configured to form a two-dimensional mesh or interconnect. In some examples, each wire is associated with a particular phase and includes a first portion implemented on a first layer and a second portion implemented on a second layer. In some examples, one or more vias are implemented between the first and second layers to couple the first and second conductor portions. In some examples, conductors associated with different phases are interleaved with each other.

[0027] Examples of back-end layers 105D include local inductive lines and long passive transmission lines. In some examples, resistive vias are used as terminations for passive interconnects, terminations for interconnects internal to RQL gates, and as shunts. Additional aspects of back-end layers 105D are described below with reference to FIG. 2.

[0028] Some examples of the fabrication stack 100 include a pair of ground planes 117A, 117B on which the layers described above are formed. The ground planes 117A, 117B are configured to mitigate parasitic flux failure modes, such as frozen Abrikosov vortices and thermally induced phase slips, that may otherwise occur within the fabrication stack 100 during cool down. Some examples of the ground planes 117A, 117B are formed from a NbTiN composition that has a higher concentration of Ti than the NbTiN composition used to form the inner layers, thereby increasing the critical temperature of the ground planes 117A, 117B. In one example, the difference between the respective critical temperatures is greater than 0.5 K.

[0029] FIG. 2 illustrates an example of a back-end layer 115C. The back-end layer 115C is comprised of wires of different cross-sections that can facilitate high density wiring. The wire cross-sections are sized to produce wires with different inductance values. In particular, as discussed above, the kinetic inductance of the wire is determined by L sq =μ 0 λ L 2 / d, and the amount of inductance can be adjusted by adjusting the film thickness d. For example, in the first back-end layer 205A, the wires have a thickness d=200 nm, and therefore an inductance L=2 pH / μm and an impedance Z=88 Ω. The wires in this layer have an inductive reach of 20 μm (about 10 gates) and a passive transmission line (PTL) reach of about 15 cm. In the second back-end layer 205B, the wires have a thickness d=100 nm, and therefore an inductance L=5 pH / μm and an impedance Z=155 Ω. The wires in this layer have an inductive reach of 8 μm (about 4 gates) and a PTL reach of about 400 μm. In the third back-end layer 205C, the wires have a thickness d=50 nm, and therefore an inductance L=20 pH / μm. The wires in this layer have an inductive reach of 2 μm (about 1 gate). The high mechanical inductance of NbTiN facilitates efficient routing because it makes inductance proportional to cross-sectional area, so that the third back-end layer 205C has 10 times more inductance per μm than the first back-end layer 205A. This simplifies the routing method for superconducting circuits that have tightly-tolerated fixed inductance value targets. Inductance targets can be met without meandering by accessing different layers.

[0030] Some examples of the back-end layer include resistive vias 210. In the context of superconductivity, resistive vias 210 can be used in a variety of applications, such as impedance matching for transmission lines and R / L (resistor / inductor) delay lines. In some examples, these resistive vias 210 have resistance values ​​of about 10 Ω to 100 Ω. Some examples of resistive vias 210 include high resistivity NbNx with ρ=190-210 μΩ·cm, suitable for fabricating resistors of desired values ​​in the via geometry.

[0031] FIG. 3A shows an example of a Josephson junction 105 formed in a first layer group 115 A of the fabrication stack 100 .

[0032] Some examples of Josephson junctions 105 include a pair of Nb electrode layers 105A, an amorphous silicon layer 105B between the pair of Nb electrode layers 105A, and a pair of NbTiN electrode layers 105C on the pair of Nb electrode layers 105A. The pair of Nb electrode layers 105A are configured to protect the pair of Nb electrode layers from contamination during formation of the fabrication stack 100. For example, the NbTiN electrode layer 105B protects the top and bottom surfaces of the Nb electrode layer 105A from contamination.

[0033] Some examples of the Josephson junction 105 further include a silicon nitride layer 305 configured to seal the other side (e.g., sidewalls, perimeter, etc.) of the pair of Nb electrode layers 105A. The silicon nitride layer 305 is configured to protect the other side of the pair of Nb electrode layers from contamination during formation of the fabrication stack 100. Thus, between the NbTiN electrode layer 105B and the silicon nitride layer 305, all sides of the Nb electrode layer 105A are protected from contamination.

[0034] 3B, in the example Josephson junction 105, a portion of the side of the Josephson junction 105 is sealed by a shunt / resistance layer 310 rather than the silicon nitride layer 305 described above. In particular, the shunt layer 310 is configured to resistively couple a pair of Nb electrode layers 105a to one another. The shunt layer 310 is electrically equivalent to a resistance across the Nb electrode 105B of the Josephson junction 105.

[0035] Some examples of the shunt layer include TaN or a material with similar resistivity. In some examples, the shunt layer 310 has a thickness between about 10 nm and 20 nm. TaN is a well-characterized alloy with a desired resistivity ρ=8-50 mΩcm at a thickness of 10-100 nm. Because TaN is “dirty” (short mean free path of electrons), it does not form a parasitic Josephson junction across the barrier. The shunt resistance is proportional to the junction perimeter, not the area. This means that the characteristic voltage and corresponding time constant of the Josephson junction depend on the device size, with larger junction sizes resulting in less attenuation. The overall range for junction sizes is about 35-100 μA. In some examples, the shunt layer 310 targets the middle of this range.

[0036] 4 illustrates an example of a capacitor 110 formed in a first layer group 115A of a fabrication stack 100. The capacitor 110 corresponds to a metal-insulator-metal (MIM) capacitor and includes a pair of NbTiN electrode layers 110A and a dielectric layer 110B between the pair of NbTiN electrode layers 110A.

[0037] Exemplary capacitors 110 exhibit high integration density and facilitate energy-efficient AC powering of superconducting circuits. For example, some exemplary superconducting circuits implement one or more local LC (e.g., inductor / capacitor)-based AC power networks in which MIM capacitors are elements.

[0038] In some examples, the capacitor 110 is deposited using ALD. The capacitor is sized to provide a bias current to the Josephson junction, typically TIFF2025500393000003.tif8170. This bias current to critical current ratio is in some cases the most important parameter in superconducting circuits. Therefore, tight process control of capacitor 110 is an important consideration. The target for a 35 μA junction is 2.6 fF, which scales linearly with junction size. The use of NbTiN for electrode 110A facilitates suppression of supercurrent leakage across capacitor 110 due to the shorter coherence length of the superconductor compared to Nb.

[0039] Some examples of dielectric layer 110B include hafnium oxide (HfOx) or other similar oxides. HfOx in particular is a good candidate material for capacitor 110 due to its high dielectric constant K. In one example, the minimum capacitor 110 area is A=0.1 μm 2 which corresponds to a capacitor 110 with K=32 and a thickness of 10 nm.

[0040] In some examples, the hafnium oxide is doped (e.g., with Si or Zn) to facilitate tuning the capacitance of the capacitor 110 via a DC voltage applied across a pair of NbTiN electrode layers 110a. Tuning the capacitor 110 facilitates tunability of an AC powered superconducting circuit.

[0041] FIG. 5 illustrates an example of a portion of an AC powered superconducting circuit 500 that can be implemented via the fabrication process described herein. The superconducting circuit 500 includes a pair of resonators 505A, 505B and a pair of Josephson junctions 510A, 510B. Each resonator 505 includes an inductor 515 and a capacitor 520 and has a resonant frequency that is a function of the inductance of the inductor 515 and the capacitance of the capacitor 520. In one example, the superconducting circuit 500 is one of many superconducting circuits 500 distributed across a chip to provide power and clock signals to RQL circuits across the chip. The first resonator 505A of each set of resonators 505 is driven by one of a group of AC voltage sources 525 that output a particular frequency but out of phase (e.g., 4-phase, 8-phase, etc.). This causes the first resonator 505A to resonate at a frequency and phase that substantially matches the frequency and phase of the driving AC voltage source 525, respectively, and the second resonator 505B to resonate at a frequency that substantially matches the frequency of the driving AC voltage source 525, but approximately 180° out of phase with the driving AC voltage source 525. Typically, these resonators 505 have a high loaded Q (e.g., Q>200). Without tuning, matching the resonant frequencies of the resonators 505 distributed across the chip in frequency would require extremely high tolerances on the geometric and material parameters of the wires and capacitors. However, by doping the capacitors 520 as described herein, the resonators 505 can be tuned, for example, by ±10%, by supplying a DC voltage 530 to the capacitor in the range of 1-5 V depending on the film. The DC voltage does not adversely affect the dynamics of the Josephson junctions 510. To compensate for local variations in fabrication parameters, different DC voltages can be applied to groups of resonators spread across the chip.

[0042] 6 illustrates an example of operations 600 for facilitating fabrication of a superconducting circuit. An operation at block 605 includes forming at least one Josephson junction 105 in a fabrication stack 100.

[0043] The operations of block 610 include forming at least one capacitor 110 in the fabrication stack 100 .

[0044] Operations at block 615 include forming one or more high-mechanical inductance wires comprising NbTiN in the fabrication stack 100. The one or more high-mechanical inductance wires are configured to electrically couple at least one Josephson junction to at least one capacitor 110 to form a superconducting circuit that facilitates switching states of the Josephson junctions 105 via single flux quantum (SFQ) pulses.

[0045] In some example operations, forming the at least one Josephson junction 105 includes forming a pair of Nb electrode layers 105A in the fabrication stack 100, forming an amorphous silicon layer 105B between the pair of Nb electrode layers 105A in the fabrication stack 100, and forming a pair of NbTiN electrode layers 105C on the pair of Nb electrode layers 105A. The NbTiN electrode layers 105C are configured to protect the pair of Nb electrode layers 105A from contamination during formation of the fabrication stack 100.

[0046] Some embodiments further include forming a silicon nitride layer 305 on one or more sides of the pair of Nb electrode layers 105A. The silicon nitride layer 305 is configured to protect the pair of Nb electrode layers 105A from contamination of the one or more sides of the pair of Nb electrode layers 105A during formation of the fabrication stack 100.

[0047] Some embodiments further include forming a shunt layer 310 on one or more sides of the pair of Nb electrode layers 105A configured to resistively couple the pair of Nb electrode layers 105A to one another.

[0048] In some embodiments of the operations, forming the shunt layer 310 includes forming a tantalum nitride layer on each side of a pair of Nb electrode layers 105A configured to resistively couple the pair of Nb electrode layers 105A to one another.

[0049] In some embodiments of the operations, forming at least one capacitor 110 includes forming a pair of NbTiN electrode layers in a fabrication stack and forming a dielectric layer 110B in the fabrication stack between the pair of NbTiN electrode layers 110A and the dielectric layer 110B.

[0050] In some embodiments of the operations, forming the dielectric layer 110B includes forming a layer of hafnium oxide between a pair of NbTiN electrode layers 110A.

[0051] Some embodiments of the operation further include doping the hafnium oxide to facilitate adjusting the capacitance of the at least one capacitor 110 via a DC voltage supplied between a pair of NbTiN electrode layers 110A of the at least one capacitor 110.

[0052] Some examples of the operations include forming a pair of ground planes 117A, 117B while the at least one Josephson junction 105, the at least one capacitor 110, and the one or more high mechanical inductance wires are formed. The pair of ground planes 117A, 117B comprises NbTiN. The pair of ground planes 117A, 117B is configured to have a higher critical temperature than the critical temperature of the at least one Josephson junction 105, the at least one capacitor 110, and the one or more high mechanical inductance wires to mitigate parasitic flux failure modes.

[0053] While some embodiments have been illustrated and described in detail in the accompanying drawings and the foregoing description, such illustrations and descriptions are illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be interpreted as limiting the scope.

Claims

1. 1. A manufacturing stack comprising: at least one Josephson junction; at least one capacitor; and one or more high mechanical inductance wires comprising NbTiN; The fabrication stack, wherein a high mechanical inductance wire is configured to electrically couple at least one Josephson junction to at least one capacitor to form a superconducting circuit that facilitates switching the state of the Josephson junction via a single flux quantum (SFQ) pulse.

2. At least one Josephson junction A pair of Nb electrode layers; an amorphous silicon layer between a pair of Nb electrode layers; and a pair of NbTiN electrode layers on a pair of Nb electrode layers; The fabrication stack of claim 1 , wherein the pair of NbTiN electrode layers are configured to protect the pair of Nb electrode layers from contamination during formation of the fabrication stack.

3. further comprising a silicon nitride layer on one or more sides of the pair of Nb electrode layers; The fabrication stack of claim 2 , wherein the silicon nitride layer is configured to protect one or more sides of the pair of Nb electrode layers from contamination during formation of the fabrication stack.

4. further comprising a shunt layer on one or more sides of the pair of Nb electrode layers; The fabrication stack of claim 2 , wherein the shunt layer is configured to resistively couple a pair of the Nb electrode layers to one another.

5. The manufacturing stack of claim 4 , wherein the shunt layer comprises tantalum nitride.

6. The at least one capacitor comprises: A pair of NbTiN electrode layers; and 10. The fabrication stack of claim 1 further comprising a dielectric layer between a pair of NbTiN electrode layers.

7. The fabrication stack of claim 6 , wherein the dielectric layer comprises hafnium oxide.

8. 8. The fabrication stack of claim 7, wherein the hafnium oxide is doped to facilitate tuning a capacitance of the at least one capacitor via a DC voltage supplied across a pair of NbTiN electrode layers of the at least one capacitor.

9. further comprising at least one inductor; at least one inductor, at least one capacitor, and at least one Josephson junction are configured to form a superconducting series circuit having a resonant frequency that is a function of an inductance of the inductor and a capacitance of the capacitor; The fabrication stack of claim 8 , wherein the resonant frequency is adjustable by adjusting a DC voltage across a pair of NbTiN electrode layers of the capacitor.

10. a pair of ground planes having at least one Josephson junction, at least one capacitor, and one or more high-mechanical inductance wires formed therebetween; the pair of ground planes comprises NbTiN; 10. The fabrication stack of any one of claims 1 to 9, wherein the pair of ground planes are configured to have a critical temperature higher than a critical temperature of at least one Josephson junction, at least one capacitor, and one or more high mechanical inductance wires to mitigate parasitic flux failure modes.

11. 1. A method for manufacturing a superconducting circuit, comprising the steps of: forming at least one Josephson junction in the fabrication stack; forming at least one capacitor in a fabrication stack; and forming one or more high mechanical inductance wires comprising NbTiN in a fabrication stack; The method, wherein one or more high-mechanical inductance wires are configured to electrically couple at least one Josephson junction to at least one capacitor to form a superconducting circuit that facilitates switching the state of the Josephson junction via a single flux quantum (SFQ) pulse.

12. Forming at least one Josephson junction includes: forming a pair of Nb electrode layers in a fabrication stack; forming an amorphous silicon layer between a pair of Nb electrode layers in a fabrication stack; forming a pair of NbTiN electrode layers over the pair of Nb electrode layers, the pair of NbTiN electrode layers configured to protect the pair of Nb electrode layers from contamination during formation of a manufacturing stack; forming a silicon nitride layer on one or more sides of the pair of Nb electrode layers, the silicon nitride layer being configured to protect the pair of Nb electrode layers from contamination on the one or more sides of the pair of Nb electrode layers during formation of a manufacturing stack; and The method of claim 11 , comprising forming a shunt layer on one or more sides of the pair of Nb electrode layers configured to resistively couple the pair of Nb electrode layers to one another.

13. 13. The method of claim 12, wherein forming the shunt layer includes forming a tantalum nitride layer on one or more sides of a pair of Nb electrode layers configured to resistively couple the pair of Nb electrode layers to one another.

14. Forming the at least one capacitor includes: forming a pair of NbTiN electrode layers in a fabrication stack; and forming a dielectric layer between a pair of NbTiN electrode layers in a fabrication stack; 12. The method of claim 11, comprising:

15. The method of claim 14 , wherein forming the dielectric layer comprises forming a hafnium oxide layer between a pair of NbTiN electrode layers.

16. 16. The method of claim 15, further comprising doping the layer of hafnium oxide to facilitate tuning the capacitance of the at least one capacitor via a DC voltage supplied across the pair of NbTiN electrode layers of the at least one capacitor.

17. forming a pair of ground planes having at least one Josephson junction, at least one capacitor, and one or more high-mechanical inductance wires formed therebetween; the pair of ground planes comprises NbTiN; the pair of ground planes are configured to have a critical temperature higher than a critical temperature of the at least one Josephson junction, the at least one capacitor, and the one or more high mechanical inductance wires to mitigate parasitic flux failure modes; The method according to any one of claims 11 to 16.

18. A device including a superconducting chip, The superconducting chip is at least one Josephson junction; at least one capacitor; and one or more high mechanical inductance wires comprising NbTiN; A device, wherein a high-mechanical inductance wire is configured to electrically couple at least one Josephson junction to at least one capacitor to facilitate switching the state of the Josephson junction via a single flux quantum (SFQ) pulse.

19. At least one Josephson junction A pair of Nb electrode layers; an amorphous silicon layer between a pair of Nb electrode layers; a pair of NbTiN electrode layers over the pair of Nb electrode layers, the pair of NbTiN electrode layers being configured to protect the pair of Nb electrode layers from contamination during formation of the manufacturing stack; a silicon nitride layer on one or more sides of the pair of Nb electrode layers, the silicon nitride layer being configured to protect the one or more sides of the pair of Nb electrode layers from contamination during formation of the fabrication stack; and 20. The device of claim 18, further comprising a shunt layer on one or more sides of the pair of Nb electrode layers, the shunt layer configured to resistively couple the pair of Nb electrode layers to one another.

20. The at least one capacitor comprises: A pair of NbTiN electrode layers; and a dielectric layer between a pair of NbTiN electrode layers; the dielectric layer comprises hafnium oxide; 20. The device of claim 18, wherein the hafnium oxide is doped to facilitate tuning the capacitance of the at least one capacitor via a DC voltage supplied across a pair of NbTiN electrode layers of the at least one capacitor.

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