Micro LED structure and micro display panel

Abstract

The micro light emitting diode (LED) structure includes a mesa structure. The mesa structure further includes a first semiconductor layer having a first conductivity type, a light emitting layer formed on the first semiconductor layer, a second semiconductor layer formed on the light emitting layer and having a second conductivity type different from the first conductivity type, a sidewall protection layer formed on a sidewall of the mesa structure, and a sidewall reflective layer formed on a surface of the sidewall protection layer. The first semiconductor layer further includes a first type semiconductor region and an ion implantation region formed around the first semiconductor region and having a resistance higher than that of the semiconductor region.

Description

[Technical field]

[0001] The present disclosure relates generally to the field of light emitting diode technology, and more particularly to a micro light emitting diode (LED) structure and a micro display panel comprising the micro LED structure. [Background technology]

[0002] Inorganic micro light-emitting diodes (also called "micro LEDs" or "μ-LEDs") are becoming increasingly important for use in a variety of applications, including, for example, self-luminous microdisplays, visible light communications, and optogenetics. μ-LEDs have greater output power than conventional LEDs due to better strain relief, improved light extraction efficiency, uniform current spreading, etc. Compared with conventional LEDs, μ-LEDs have the features of improved thermal effects, improved operation at higher current densities, better response speed, larger operating temperature range, higher resolution, higher color gamut, higher contrast, lower power consumption, etc.

[0003] μ-LEDs include III-V epitaxial layers to form multiple mesas. In some μ-LED designs, it is necessary to form a space between adjacent μ-LEDs to avoid carriers in the epitaxial layers spreading from one mesa to the adjacent mesa. The space formed between adjacent micro-LEDs can reduce the active light-emitting area and reduce the light extraction efficiency. Eliminating the space can increase the active light-emitting area, but it also causes carriers in the epitaxial layers to spread laterally across adjacent mesas, thus reducing the light-emitting efficiency. Furthermore, without the space between adjacent mesas, crosstalk occurs between adjacent μ-LEDs, which reduces the reliability or accuracy of the μ-LEDs.

[0004] Furthermore, in some μ-LED structures, small LED pixels with high current density are more likely to experience red shift, lower maximum efficiency, and non-uniform emission, which are usually caused by poor electrical injection during fabrication. Furthermore, the peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) of μ-LEDs can be significantly reduced with decreasing chip size. The reduction in EQE and IQE is caused by non-radiative recombination at the quantum well sidewalls that are not properly etched. The reduction in IQE is caused by poor current injection and electron leakage current in μ-LEDs. To improve EQE and IQE, it is necessary to optimize the quantum well sidewall area to reduce the current density. Summary of the Invention

[0005] According to the present disclosure, a micro LED structure is provided. The structure includes a mesa structure. The mesa structure further includes a first semiconductor layer having a first conductivity type, a light emitting layer formed on the first semiconductor layer, and a second semiconductor layer formed on the light emitting layer and having a second conductivity type different from the first conductivity type. The bottom surface area of ​​the first semiconductor layer is made larger than the bottom surface area of ​​the second semiconductor layer, the bottom surface area of ​​the second semiconductor layer is made larger than the top surface area of ​​the second semiconductor layer, and the bottom surface area of ​​the first semiconductor layer is made larger than the top surface area of ​​the first semiconductor layer. The first semiconductor layer further includes a first type semiconductor region and an ion implanted region formed around the first semiconductor region and having a resistance higher than the resistance of the semiconductor region.

[0006] Also provided in accordance with the present disclosure is a microdisplay panel including a microLED array including a first microLED structure and an integrated circuit (IC) backplane formed below the first microLED structure, the first microLED structure being electrically coupled to the IC backplane. [Brief description of the drawings]

[0007] [Figure 1]FIG. 1 is a schematic cross-sectional view of a micro LED structure according to an exemplary embodiment of the present disclosure. [Diagram 2] 2 is a flow chart of a method for manufacturing the micro LED structure shown in FIG. 1 according to an exemplary embodiment of the present disclosure. [Diagram 3] 3A-3C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 2 according to an exemplary embodiment of the present disclosure. [Figure 4] 3A-3C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 2 according to an exemplary embodiment of the present disclosure. [Diagram 5] 3A-3C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 2 according to an exemplary embodiment of the present disclosure. [Figure 6] 3A-3C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 2 according to an exemplary embodiment of the present disclosure. [Figure 7] 3A-3C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 2 according to an exemplary embodiment of the present disclosure. [Figure 8] 3A-3C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 2 according to an exemplary embodiment of the present disclosure. [Figure 9] 3A-3C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 2 according to an exemplary embodiment of the present disclosure. [Figure 10] 3A-3C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 2 according to an exemplary embodiment of the present disclosure. [Figure 11] 3A-3C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 2 according to an exemplary embodiment of the present disclosure. [Figure 12] 3A-3C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 2 according to an exemplary embodiment of the present disclosure. [Figure 13] 1 is a schematic cross-sectional view of at least a portion of an exemplary microdisplay panel, in accordance with an exemplary embodiment of the present disclosure. [Figure 14] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 15] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 16] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 17] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 18] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 19] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 20] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 21] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 22] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Diagram 23] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 24] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Diagram 25] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 26] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 27] 14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. [Figure 28]14A-14C are cross-sectional views that illustrate schematic steps for carrying out the method of FIG. 13 according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] DETAILED DESCRIPTION OF THE DRAWINGS Embodiments consistent with the present disclosure are now described with reference to the drawings, in which: Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like parts.

[0009] As mentioned above, state-of-the-art micro LEDs may experience problems such as red shift, low maximum efficiency, non-uniform light emission, etc. To solve these problems, embodiments of the present invention provide a micro LED structure. In some embodiments consistent with FIG. 1, the micro LED structure includes a mesa structure 01, a top contact 02, a bottom contact 03, a top conductive layer 04, a sidewall protective layer 104, and a sidewall reflective layer 105. The mesa structure 01 further includes a first type semiconductor layer 101, a light emitting layer 102, and a second type semiconductor layer 103. The light emitting layer 102 is formed on the first type semiconductor layer 101. The second type semiconductor layer 103 is disposed on the light emitting layer 102. In some embodiments, the first type and the second type refer to different conductivity types. For example, the first type is P type and the second type is N type. In another example, the first type is N type and the second type is P type.

[0010] 1, the bottom surface area of ​​the first semiconductor layer 101 is made larger than the bottom surface area of ​​the second semiconductor layer 103. In some embodiments, the bottom surface area of ​​the second semiconductor layer 103 is made larger than the top surface area of ​​the second semiconductor layer 103. The bottom surface area of ​​the first semiconductor layer 101 is made larger than the top surface area of ​​the first semiconductor layer 101. In some embodiments, the sidewalls of the first semiconductor layer 101, the light emitting layer 102, and the second semiconductor layer 103 are coplanar in this embodiment such that the sidewalls are flat. In some embodiments, the light emitting layer 102 and the second semiconductor layer 103 are not coplanar and the sidewalls are not flat. In some embodiments, the diameter of the second semiconductor layer 103 is smaller than the diameter of the light emitting layer 102. In some embodiments, the diameter of the first semiconductor layer 101 is smaller than the diameter of the light emitting layer 102. In some embodiments, the material of the first-type semiconductor layer 101 includes at least one of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, p-AlGaN, and the like. The material of the second-type semiconductor layer 103 includes at least one of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-InGaN, n-AlGaN, and the like. The light-emitting layer 102 is formed by a quantum well layer. The material of the quantum well layer includes at least one of GaAs, InGaN, AlGaN, AlInP, GaInP, AlGaInP, and the like. In some further embodiments, the thickness of the first-type semiconductor layer 101 is greater than the thickness of the second-type semiconductor layer 103, and the thickness of the light-emitting layer 102 is less than the thickness of the first-type semiconductor layer 101. In some embodiments, the thickness of the first-type semiconductor layer 101 is in the range of 700 nm to 2 μm, and the thickness of the second-type semiconductor layer 103 is in the range of 100 nm to 200 nm. In some embodiments, the quantum well layer has a thickness of 30 nm or less.In some embodiments, the quantum well layer includes 3 or fewer pairs of quantum wells.

[0011] In some embodiments, the first-type semiconductor layer 101 includes one or more reflectors 1011. In some embodiments, the reflector 1011 is formed on the bottom surface of the first-type semiconductor layer 101. In some embodiments, the reflector 1011 is formed inside the first-type semiconductor layer 101. In some embodiments, the material of the reflector 1011 is a mixture of a dielectric material and a metallic material. In some further embodiments, the dielectric material includes SiO2 or SiNx, where "x" is a positive integer. In some embodiments, the metallic material includes Au or Ag. In some embodiments, the multiple reflectors 1011 are formed horizontally one by one at different horizontal levels in the first-type semiconductor layer 1011, dividing the first-type semiconductor layer 101 into multiple layers.

[0012] In some embodiments, the top contact 02 is formed on the top surface of the second type semiconductor layer 103. The conductivity type of the top contact 02 is the same as the conductivity type of the second type semiconductor layer 103. For example, if the second type is N type, the top contact 02 is an N type contact, or if the second type is P type, the top contact 02 is a P type contact. In some embodiments, the top contact 02 is made of a metal or metal alloy including at least one of AuGe, AuGeNi, etc. The top contact 02 is used to form an ohmic contact between the upper conductive layer 04 and the second type semiconductor layer 103 and optimize the electrical properties of the micro LED. In some embodiments, the diameter of the top contact 02 is in the range of 20 nm to 50 nm, and the thickness of the top contact 02 is in the range of 10 nm to 20 nm.

[0013] In some embodiments, the first type semiconductor layer 101 includes a first type semiconductor region 1012 and an ion implanted region 1013. The first type semiconductor region 1012 is formed directly on the bottom contact 03. The ion implanted region 1013 is formed around the first type semiconductor region 1012. In some embodiments, the resistance of the ion implanted region 1013 is greater than the resistance of the first type semiconductor region 101. The ion implanted region 1013 is formed by a redundant ion implantation process into the ion implanted region 1013.

[0014] In some embodiments, the center of the bottom contact 03 is aligned with the center of the first type semiconductor region 1012 along an axis perpendicular to the bottom surface of the first type semiconductor region 101. In some further embodiments, the diameter of the ion implanted region 1013 is equal to or greater than the diameter of the bottom contact 03. The diameter of the first type semiconductor region 1012 is equal to or greater than the diameter of the bottom contact 03. Also, the diameter of the ion implanted region 1013 is greater than the diameter of the first type semiconductor region 1012. In some embodiments, the diameter of the first type semiconductor region 1012 is equal to or less than three times the diameter of the bottom contact 03. In some embodiments, the diameter of the ion implanted region 1013 is greater than two times the diameter of the first type semiconductor region 1012. In some embodiments, the diameter of the ion implanted region 1013 is in the range of 500 nm to 1250 nm and the diameter of the bottom contact 03 is in the range of 20 nm to 500 nm.

[0015] In some embodiments, the conductivity type of the ion implanted region 1013 is the same as the conductivity type of the first type semiconductor region 1012. In some further embodiments, the ion implanted region 1013 includes at least one type of implanted ion. In some embodiments, the implanted ions are selected from one or more of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. The metal ions are selected from one or more of the following ions: zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum.

[0016] In some further embodiments, the thickness of the first-type semiconductor region 1012 is equal to or greater than the thickness of the ion-implanted region 1013. In some embodiments, the thickness of the second-type semiconductor region 103 is in the range of 100 nm to 200 nm, the thickness of the first-type semiconductor region 1012 is in the range of 600 nm to 900 nm, and the thickness of the ion-implanted region 1013 is in the range of 500 nm to 800 nm.

[0017] 1, in some embodiments, the micro LED structure further comprises a top conductor layer 04 covering an upper surface of the second type semiconductor layer 103 and the top contact 02. The top conductive layer 04 is transparent and conductive. In some embodiments, the top conductive layer 04 comprises at least one of indium tin oxide (ITO) and fluorine doped tin oxide (FTO).

[0018] In some embodiments, the bottom contact 03 is formed on the bottom surface of the first-type semiconductor layer 101. The conductivity type of the bottom contact 03 is the same as the conductivity type of the first-type semiconductor layer 101. For example, if the first-type semiconductor layer 101 is P-type, the bottom contact 03 is also P-type. Similarly, if the first-type semiconductor layer 101 is N-type, the bottom contact 03 is also N-type. In some embodiments, light is emitted from the top surface of the mesa structure 01. For this purpose, the diameter of the bottom contact 03 is made larger than the diameter of the top contact 02, and the diameter of the top contact 02 is made as small as possible so that the top contact 02 is like a dot on the top surface of the second-type semiconductor layer 103. In some embodiments, the diameter of the bottom contact 03 is made equal to or smaller than the diameter of the top contact 02. In some embodiments, the bottom contact 03 is configured to connect to a bottom electrode, such as a contact pad in an IC backplane. In some embodiments, the diameter of the bottom contact 03 is in the range of 20 nm to 1 μm. In some embodiments, the diameter of the bottom contact 03 is in the range of 800 nm to 1 μm. In some embodiments, the center of the bottom contact 03 is aligned with the center of the top contact 02 along an axis perpendicular to the top surface of the first type semiconductor region. In some embodiments, the center of the bottom contact 03, the center of the top contact 02, and the center of the first type semiconductor region are all aligned along an axis perpendicular to the top surface of the first type semiconductor region. In some embodiments, the material of the bottom contact 03 comprises a transparent conductive material. In some further embodiments, the material of the bottom contact 03 comprises ITO or FTO. In some embodiments, the bottom contact 03 is not transparent and the material of the bottom contact is a conductive metal. In some embodiments, the material of the bottom contact comprises at least one of the following elements: Au, Zn, Be, Cr, Ni, Ti, Ag, and Pt.

[0019] Figure 2 is a flow chart of a method for fabricating a micro LED structure consistent with embodiments of the present disclosure. Figures 3-12 are cross-sectional views that generally illustrate steps for carrying out the method of Figure 2. It is believed that the disclosed fabrication method is not limited to the particular micro LED structure illustrated in Figures 3-12. In some embodiments consistent with Figures 3-12, methods of fabricating the micro LED structures described above are described.

[0020] In some embodiments consistent with FIG. 4-FIG. 7, an ion-implanted region 1013 in the first-type semiconductor layer 101 is formed (step 2 in FIG. 2). In some embodiments, the ion-implanted region 1013 is formed by an ion implantation process. In some embodiments consistent with FIG. 3, an epitaxial structure is provided (step 1 in FIG. 2). The epitaxial structure includes a first-type semiconductor layer 101, a light-emitting layer 102, and a second-type semiconductor layer 103. In some embodiments, the first-type semiconductor layer 101, the light-emitting layer 102, and the second-type semiconductor layer 103 are arranged in order from top to bottom. In some embodiments, the epitaxial structure can be formed on the substrate 00 by any epitaxial growth process known in the art. In some further embodiments, the first semiconductor layer 101 includes one or more reflectors 1011. The reflectors 1011 can be formed on a bottom surface of the first semiconductor layer 101.

[0021] In some embodiments consistent with FIG. 4, a mask M on the first-type semiconductor layer 101 is formed to define a predetermined first-type semiconductor region and a predetermined ion implantation region in the first-type semiconductor layer 103. More specifically, in some embodiments, in each mesa structure 01, the predetermined first-type semiconductor region is below the bottom contact 03, as shown in FIG. 4 as the region between the dotted lines. In some embodiments, the predetermined ion implantation region is around each predetermined first-type semiconductor region, as shown in FIG. 4 as the region outside the dotted lines. The predetermined first-type semiconductor region is provided to form the first-type semiconductor region 1012, and the predetermined ion implantation region is provided to form the ion implantation region 103.

[0022] 5, the mask M is patterned to expose the predetermined ion implantation region. More specifically, in some embodiments, the mask M is patterned by an etching process. In some embodiments, after the etching process, the mask M over the predetermined first type semiconductor region is retained, and the mask M over the predetermined ion implantation region is removed to expose the predetermined ion implantation region.

[0023] In some embodiments consistent with FIG. 6, ions are implanted into the pre-defined ion implantation regions. More specifically, in some embodiments, ions are implanted into the first-type semiconductor layer 101 to form ion implantation regions 1013. In some embodiments, the ion implantation process is performed by an embodiment of a conventional ion implantation technique, and the implanted ions include at least one of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some further embodiments, the metal ions include at least one of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum. In some embodiments, the implantation dose is in the range of 10E12 to 10E16. In some embodiments, ions are also implanted into the reflectors 1011 corresponding to each ion implantation region. In some further embodiments, the ion implantation process is performed before depositing the bottom contact 03. In some embodiments, an ion implantation process is performed after deposition of the bottom contact 03 to form an ion implantation region, and then the bottom contact 03 is deposited on the pre-defined first type semiconductor region as another mask covers the ion implantation region. In some embodiments consistent with FIG. 7, the mask M is removed by a chemical etching process known in the art.

[0024] In some embodiments consistent with Figure 8, the bottom contact 03 is deposited on the surface of the first-type semiconductor layer 101 (step 3 in Figure 2). The bottom contact 03 is deposited by chemical or physical vapor processes known in the art. In some further embodiments, a first patterned mask is provided to cover the entire surface of the mesa with a portion of the mesa top exposed during the deposition process. After deposition, the first patterned mask is removed by a chemical etching method.

[0025] In some embodiments consistent with Figures 9-10, a mesa structure is formed by etching the epitaxial structure (step 4 in Figure 2). In some embodiments consistent with Figure 9, the epitaxial structure is placed upside down to form mesa structure 01, and the substrate 00 is removed from mesa structure 01 by a conventional separation process known in the art to expose the top of mesa structure 01. In some embodiments consistent with Figure 9, the bottom of the second semiconductor layer 103 is presented as the top surface of the second-type semiconductor layer 103.

[0026] In some further embodiments, the mesa structure 01 is formed by sequentially etching the first-type semiconductor layer 101, the light emitting layer 102, and the second-type semiconductor layer 103. The sidewalls of the mesa are vertical or inclined with respect to a horizontal surface (e.g., the substrate 00). In some embodiments, the etching process is a dry etching process. In some embodiments, the etching process is a plasma etching process. In some embodiments, the sidewalls of the mesa are flat and the top surface of the mesa is made larger than the bottom surface.

[0027] In some embodiments consistent with FIG. 11, a top contact 02 is deposited on the second-type semiconductor layer 103 (step 5 in FIG. 2). The top contact 02 is deposited on the top surface of the second-type semiconductor layer 103 in a chemical vapor deposition process or a physical vapor deposition process. In some embodiments consistent with FIG. 11, the area of ​​the top contact 02 is made as small as possible. More specifically, in some further embodiments consistent with FIG. 11, the top contact 02 is a dot. In some embodiments consistent with FIG. 12, a top conductive layer 04 is formed on the mesa structure (step 6 in FIG. 2). More specifically, in some embodiments, the top conductive layer 04 is deposited on the second-type semiconductor layer 103 and on the top and sidewalls of the top contact 02, covering the exposed top surface of the second semiconductor layer 103 and the top contact 02. The deposition of the top conductive layer 04 is performed by chemical vapor deposition methods known in the art. In some embodiments consistent with FIG. 13, a microdisplay panel is provided. The micro display panel includes a micro LED array and an IC backplane 05 formed below the micro LED array. The micro LED array includes a plurality of the aforementioned micro LED structures. The micro LED structures are electrically coupled or connected to the IC backplane 05. In some embodiments, the entire length of the micro LED array is 5 cm or less. The length of the backplane is greater than the length of the micro LED array. In some embodiments, the length of the backplane is 6 cm or less. The area of ​​the micro LED array is the active display area. In some embodiments, the micro LED structure further includes a metal bonding structure. More specifically, the metal bonding structure includes a metal bonding layer or a connected hole. For example, as shown in FIG. 13, the metal bonding structure is a metal bonding layer 031, and the metal bonding layer 031 is coupled to a contact pad of the IC back panel 06. In some further embodiments, the top surface of the bottom metal bonding layer 031 is coupled (e.g., connected or bonded) to the bottom contact 03, and the bottom surface of the bottom metal bonding layer 031 is coupled (e.g., connected or bonded) to the contact pad of the IC back panel.In some embodiments, the top conductive layer 04 of the microdisplay panel is made to cover the entire display panel. Still referring to FIG. 13, the microdisplay panel further comprises a dielectric layer 08. The dielectric layer 08 is formed between adjacent mesa structures 01. The material of the dielectric layer 08 is not conductive, so that adjacent micro LEDs are electrically isolated. In some embodiments, the material of the dielectric layer comprises at least one of SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2, and ZrO2.

[0028] In some further embodiments, a reflective structure 07 is formed in the dielectric layer 08 between adjacent mesa structures 01 to avoid crosstalk. In some further embodiments, a reflective structure 07 is formed in the dielectric layer 08 between adjacent mesa structures 01 to avoid crosstalk. The cross-sectional structure of the reflective structure 07 can be an inverted triangle, an inverted rectangle, an inverted trapezoid, or any other inverted shape structure. In some embodiments, the ion implantation region is formed in the second type semiconductor layer 103, and the space between adjacent mesa structures 01 can be made as small as possible. FIG. 14 is a flow chart of a method for manufacturing a microdisplay panel consistent with the embodiment shown in FIG. 13. FIGS. 15-25 are cross-sectional views that are schematic diagrams illustrating steps for carrying out the method of FIG. 14. It is believed that the disclosed manufacturing method is not limited to the specific micro LED structures shown in FIGS. 15-28. In some embodiments consistent with FIGS. 15-28, a method for manufacturing the above-mentioned microdisplay panel is described.

[0029] In some embodiments consistent with FIG. 15, a substrate 00 having an epitaxial structure is provided (Step 1 in FIG. 14). More specifically, the epitaxial structure includes a first-type semiconductor layer 101, a light emitting layer 102, and a second-type semiconductor layer 103. In some embodiments, the first-type semiconductor layer 101, the light emitting layer 102, and the second-type semiconductor layer 103 are arranged in order from top to bottom. In some embodiments, the epitaxial structure can be formed on the substrate 00 by any epitaxial growth process known in the art. In some further embodiments, the first-type semiconductor layer 101 includes one or more reflectors 1011. The reflectors 1011 are formed on a surface of the first-type semiconductor layer 101.

[0030] In some embodiments consistent with FIGS. 16-19, the ion implantation region 1013 is formed in the second-type semiconductor layer 101 by an ion implantation process (step 2 of FIG. 14). In some embodiments consistent with FIG. 16, a mask M is formed on the first-type semiconductor layer 101. More specifically, in some embodiments, a preset first-type semiconductor region and a preset ion implantation region are defined in the first-type semiconductor layer 101. In some embodiments, the preset first-type semiconductor region is below the bottom contact 03, and the preset ion implantation region is around the preset first-type semiconductor region. More specifically, in some embodiments consistent with FIG. 16, the preset second-type semiconductor region is the region between the dotted lines, and the preset ion implantation region is the region other than the dotted lines. The preset first-type semiconductor region is configured to form the first-type semiconductor region 1012, and the preset ion implantation region is configured to form the ion implantation region 103. In some embodiments consistent with FIG. 17, the mask M is patterned to expose the preset ion implantation region. More specifically, the mask M is patterned by an etching process known in the art. After the etching process, the mask M is kept over the pre-defined first-type semiconductor region, and the mask M over the pre-defined ion implantation region is removed to expose the pre-defined ion implantation region. In some embodiments consistent with FIG. 18, ions are implanted into the pre-defined ion implantation region. More specifically, in some embodiments, ions are implanted into the first-type semiconductor layer 101 to form the ion implantation region 1013. The ion implantation process is performed by an ion implantation technique. In some embodiments consistent with FIG. 18, the implantation ions are selected from one or more of hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions. In some embodiments, the metal ions are selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum.More specifically, in some further embodiments, the implantation dose is in the range of 10E12 to 10E16 In some embodiments, ions are also implanted into each of the corresponding reflectors 1011.

[0031] In some embodiments, the ion implantation process is performed before depositing the formation of the mesa structure. In some embodiments, the ion implantation process is performed after the formation of the mesa structure and before the deposition of the bottom contact 03 to form the ion implantation region 1013, and then the bottom contact 03 is deposited on the pre-set first type semiconductor region when another mask covers the ion implantation region 1013. In some further embodiments, the ion implantation process is performed before the deposition of the bottom contact 03 to form the ion implantation region 1013, and then the bottom contact 03 is deposited on the mesa structure 01 when another mask covers the ion implantation region 1013. In some embodiments, the ion implantation process is performed after the deposition of the bottom contact to form the ion implantation region, and then the bottom contact 03 is deposited on the first type semiconductor region when another mask covers the ion implantation region.

[0032] 19, the mask M is removed from the first type semiconductor layer 101. In some embodiments, the mask M is removed by chemical etching methods known in the art.

[0033] In some embodiments consistent with Figure 4, the bottom contact 03 and metal bonding layer 031 are deposited on the surface of the first-type semiconductor layer 101 (step 3 in Figure 14). The bottom metal bonding layer 031 is deposited by chemical or physical vapor processes known in the art. In some further embodiments, a first patterned mask is provided to cover the entire surface of the mesa with a portion of the mesa top exposed during the deposition process. After deposition, the first patterned mask is removed by a chemical etching method.

[0034] In some embodiments consistent with FIG. 21, a bonding process between the epitaxial structure and the IC back panel 06 is performed and the substrate 00 is removed (step 4 in FIG. 14). The epitaxial structure is first placed upside down. More specifically, in some embodiments, the bottom of the second semiconductor layer 103 is placed as the top surface of the second-type semiconductor layer 103. In some embodiments, the metal bonding layer 031 is bonded with the contact pads of the IC back panel 06 by a metal bonding process. In some embodiments, the substrate 00 can be removed by a conventional separation process known in the art.

[0035] In some embodiments, Substrate 00 is removed prior to the bonding process by conventional substrate separation processes known in the art.

[0036] In some embodiments consistent with FIG. 22, multiple mesas are formed by etching the epitaxial structure (step 5 of FIG. 14). More specifically, the mesas are formed by sequentially etching the first-type semiconductor layer 101, the light emitting layer 102, and the second-type semiconductor layer 103. The sidewalls of the mesas are vertical or inclined with respect to a horizontal plane (e.g., substrate 00). In some embodiments, the etching process is a dry etching process. In some embodiments, the etching process is a plasma etching process.

[0037] In some embodiments consistent with Figures 23-24, a dielectric layer 08 is deposited on the substrate 00 (step 6 in Figure 14). More specifically, as shown in Figure 23, a dielectric layer 08 is deposited on the top and sidewalls of the mesas and on the bottom contact 03 such that the dielectric layer 08 covers the mesas and the bottom contact 03. In some further embodiments consistent with Figure 24, a reflective structure 07 is formed in the dielectric layer 08 between adjacent mesas. In some embodiments, a trench is formed in the dielectric layer 08 between adjacent mesas by etching the dielectric layer 08 with a first protective mask. The first protective mask is formed on the mesas and the dielectric layer 08 with the trench area exposed to protect the unexpected etched area. In some embodiments, a reflective material is filled into the trench to form a reflective structure between adjacent mesas. In some embodiments, a second protective mask is formed on the mesas and the dielectric layer 08 with the trench exposed. In some embodiments, after the aforementioned trenches are etched, the protective mask is etched to a certain thickness, leaving a portion of the protective mask to protect the unexpected fill areas while filling with the reflective material.

[0038] In some embodiments consistent with FIG. 25, a top contact 02 on the mesa structure 01 is deposited (step 7 in FIG. 14). In some further embodiments, the top contact 02 is deposited on the top surface of the second-type semiconductor layer 103 by a chemical vapor deposition process or a physical vapor deposition process known in the art. In some embodiments, the area of ​​the top contact 03 is configured to be as small as possible. In some embodiments, the area of ​​the top contact 03 is formed as a dot. In some embodiments, a patterned mask is provided to cover the mesa structure 01 exposing a portion of the surface of the second semiconductor layer 103. In some embodiments, the patterned mask is a patterned photoresist. In some further embodiments, a material can be deposited on the surface of the second semiconductor layer 103 to form the top contact 03. In some embodiments consistent with FIG. 26 (step 8 in FIG. 14), a top conductive layer 04 is formed on the mesa structure 01 and the dielectric layer 08. More specifically, the top conductive layer 04 is deposited on the second-type semiconductor layer 103, the top and sidewalls of the top contact 02 and the dielectric layer 08, covering the exposed top surface of the second semiconductor layer 103, the top contact 02 and the dielectric layer 08. The deposition of the top conductive layer 04 is performed by chemical vapor deposition methods known to those skilled in the art.

[0039] In some embodiments consistent with FIG. 27, the diameter of the bottom contact is made smaller than the diameter of the first type semiconductor region.

[0040] In some embodiments consistent with FIG. 28, the metal bonding layer 031 is a connected hole 05 configured to connect the bottom contact to an IC back panel. In some embodiments, the connected hole 05 is filled with a bonding metal. The top side of the connected hole 05 is connected to the bottom contact 03 and the bottom side of the connected hole 05 is connected to the IC backplane 06. In some embodiments, the top conductive layer 04 of the microdisplay panel is made to cover the entire display panel. In some embodiments, the bottom of the reflective structure 07 extends downwards lower than the bottom of the mesa structure 01.

[0041] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims

1. 1. A micro light emitting diode (LED) structure, comprising: a first semiconductor layer having a first conductivity type; a light emitting layer formed on the first semiconductor layer; a second semiconductor layer formed on the light emitting layer and having a second conductivity type different from the first conductivity type; A mesa structure comprising: Equipped with a bottom surface area of ​​the first semiconductor layer is larger than each of a top surface area of ​​the first semiconductor layer, a bottom surface area of ​​the second semiconductor layer, and a top surface area of ​​the second semiconductor layer; The first semiconductor layer is A semiconductor region; an ion implantation region formed around the semiconductor region; A micro light emitting diode (LED) structure comprising:

2. a top contact formed on the top surface of the second semiconductor layer and having the second conductivity type; a bottom contact formed on the bottom surface of the first semiconductor layer and having the first conductivity type; 10. The micro LED structure of claim 1 further comprising:

3. 3. The micro LED structure of claim 2, wherein a center of the bottom contact, a center of the top contact, and a center of the semiconductor region are aligned along a same axis perpendicular to the bottom surface of the first semiconductor layer, and a diameter of the ion implanted region is greater than or equal to a diameter of the bottom contact.

4. 3. The micro LED structure of claim 2, further comprising a top conductive layer formed on the second semiconductor layer and the top contact.

5. 3. The micro LED structure of claim 2, further comprising a top conductive layer formed on the second semiconductor layer and the top contact.

6. the thickness of the semiconductor region is equal to or greater than the thickness of the ion-implanted region; a diameter of the semiconductor region is equal to or greater than a diameter of the bottom contact; 10. The micro LED structure of claim 1 , wherein a diameter of the ion implanted region is greater than the diameter of the semiconductor region.

7. 7. The micro LED structure of claim 6, wherein the diameter of the semiconductor region is less than or equal to three times the diameter of the bottom contact, and the diameter of the ion implanted region is greater than two times the diameter of the semiconductor region.

8. 7. The micro LED structure of claim 6, wherein the thickness of the semiconductor region is in the range of 600 nm to 900 nm, the thickness of the ion implanted region is in the range of 500 nm to 800 nm, the diameter of the ion implanted region is in the range of 500 nm to 1250 nm, and the diameter of the bottom contact is in the range of 20 nm to 500 nm.

9. 10. The micro LED structure of claim 1, wherein the sidewalls are flat.

10. 10. The micro LED structure of claim 1, wherein the sidewalls are non-planar.

11. 10. The micro LED structure of claim 1, wherein the ion implanted region comprises at least one type of implanted ion.

12. 12. The micro LED structure of claim 11, wherein the implanted ions are selected from one or more of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions.

13. 13. The micro LED structure of claim 12, wherein the metal ions are selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum.

14. 10. The micro LED structure of claim 1 , wherein a thickness of the first semiconductor layer is greater than a thickness of the second semiconductor layer.

15. 15. The micro LED structure of claim 14, wherein the thickness of the first semiconductor layer is in the range of 700 nm to 2 μm and the thickness of the second semiconductor layer is in the range of 100 nm to 200 nm.

16. 10. The micro LED structure of claim 1 , wherein the light emitting layer has a thickness less than a thickness of the first semiconductor layer.

17. 10. The micro LED structure of claim 1 , wherein the light emitting layer is formed by a quantum well layer located between the first semiconductor layer and the second semiconductor layer.

18. 20. The micro LED structure of claim 17, wherein the quantum well layer has a thickness of 30 nm or less.

19. 20. The micro LED structure of claim 18, wherein the quantum well layer comprises three or less than three pairs of quantum wells.

20. 10. The micro LED structure of claim 1 further comprising a first reflector formed on the bottom surface of the first semiconductor layer.

21. 21. The micro LED structure of claim 20 further comprising a second reflector formed within the first semiconductor layer.

22. The micro LED structure of claim 1, wherein the ion implanted region has a resistance higher than a resistance of the semiconductor region.

23. 1. A microdisplay panel, comprising: A first micro LED structure according to claim 1 comprising a first mesa structure; an integrated circuit (IC) backplane formed beneath the first micro LED structure; A micro light emitting diode (LED) array comprising: Equipped with The first micro LED structure is electrically coupled to the IC backplane.

24. The micro LED structure comprises: Bottom contact and Bottom metal joint structure Further equipped with 24. The microdisplay panel of claim 23, wherein a top surface of the bottom metal bonding structure is bonded to the bottom contact and a bottom surface of the bottom metal bonding structure is bonded to the IC backplane.

25. The bottom metal bonding structure includes a connected hole or a metal bonding layer; 25. The microdisplay panel of claim 24, further comprising a top conductive layer formed on a top surface of the first mesa structure.

26. A second micro LED structure according to claim 1 comprising a second mesa structure; A dielectric layer Further equipped with the second mesa structure is disposed adjacent to the first mesa structure; 24. The microdisplay panel of claim 23, wherein the dielectric layer is not conductive and is formed between the first mesa structure and the second mesa structure.

27. The material of the dielectric layer is SiO ２ , Si ３ N ４ , Al ２ O ３ , AlN, HfO ２ , TiO ２ , and ZrO ２ 27. The microdisplay panel of claim 26, comprising at least one of:

28. 27. The microdisplay panel of claim 26, further comprising a reflective structure formed within the dielectric layer and between the first mesa structure and the second mesa structure, the reflective structure not contacting the first and second mesa structures.

29. The reflective structure is a top surface aligned with top surfaces of the first and second mesa structures; a bottom surface aligned with the bottom surfaces of the first and second mesa structures; 30. The microdisplay panel of claim 28, comprising:

30. 27. The microdisplay panel of claim 26, wherein the top surfaces of the first and second mesa structures are separated by a distance of 200 nm or less.

Images