Micro LED structure and micro display panel
Patent Information
- Application Number
- JP2024544958
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2022-01-31
- Publication Date
- 2025-02-06
- Estimated Expiration
- Not applicable · inactive patent
Smart Images
Figure 2025504034000001_ABST
Abstract
Description
[Technical field]
[0001] The present disclosure relates generally to the field of light emitting diode technology, and more particularly to a micro light emitting diode (LED) structure and a micro display panel comprising the micro LED structure. [Background technology]
[0002] Inorganic micro light-emitting diodes (also called "micro LEDs" or "μ-LEDs") are becoming increasingly important for use in a variety of applications, including, for example, self-luminous microdisplays, visible light communications, and optogenetics. μ-LEDs have greater output power than conventional LEDs due to better strain relief, improved light extraction efficiency, uniform current spreading, etc. Compared with conventional LEDs, μ-LEDs have the features of improved thermal effects, improved operation at higher current densities, better response speed, larger operating temperature range, higher resolution, higher color gamut, higher contrast, lower power consumption, etc.
[0003] μ-LEDs include III-V epitaxial layers to form multiple mesas. In some μ-LED designs, it is necessary to form a space between adjacent μ-LEDs to avoid carriers in the epitaxial layers spreading from one mesa to the adjacent mesa. The space formed between adjacent micro-LEDs can reduce the active light-emitting area and reduce the light extraction efficiency. Eliminating the space can increase the active light-emitting area, but it also causes carriers in the epitaxial layers to spread laterally across adjacent mesas, thus reducing the light-emitting efficiency. Furthermore, without the space between adjacent mesas, crosstalk occurs between adjacent μ-LEDs, which reduces the reliability or accuracy of the μ-LEDs.
[0004] Furthermore, in some μ-LED structures, small LED pixels with high current density are more likely to experience red shift, lower maximum efficiency, and non-uniform emission, which are usually caused by degraded electrical injection during fabrication. Furthermore, the peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) of micro-LEDs can be significantly reduced with decreasing chip size. The reduction in EQE and IQE is caused by non-radiative recombination at the quantum well sidewalls that are not properly etched. The reduction in IQE is caused by poor current injection and electron leakage current in μ-LEDs. To improve EQE and IQE, it is necessary to optimize the quantum well sidewall area to reduce the current density. Summary of the Invention
[0005] According to the present disclosure, a micro LED structure is provided. The structure includes a mesa structure. The mesa structure further includes a first semiconductor layer, a light emitting layer formed on the first semiconductor layer, a second semiconductor layer formed on the light emitting layer, a sidewall protection layer formed on the sidewall of the mesa structure, and a sidewall reflective layer formed on the surface of the sidewall protection layer. The top surface area of the second semiconductor layer is larger than each of the bottom surface area of the first semiconductor layer, the top surface area of the first semiconductor layer, and the bottom surface area of the second semiconductor layer.
[0006] Also provided in accordance with the present disclosure is a microdisplay panel including a microLED array including a first microLED structure and an integrated circuit (IC) backplane formed below the first microLED structure, the first microLED structure being electrically coupled to the IC backplane. [Brief description of the drawings]
[0007] [Figure 1] FIG. 1 is a schematic cross-sectional view of a micro LED structure according to an exemplary embodiment of the present disclosure. [Diagram 2] 1 is a schematic cross-sectional view of at least a portion of an exemplary microdisplay panel, in accordance with an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0008] DETAILED DESCRIPTION OF THE DRAWINGS Embodiments consistent with the present disclosure are now described with reference to the drawings, in which: Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like parts.
[0009] As mentioned above, state-of-the-art micro LEDs may experience problems such as red shift, low maximum efficiency, non-uniform light emission, etc. To solve these problems, embodiments of the present invention provide a micro LED structure. In some embodiments consistent with FIG. 1, the micro LED structure includes a mesa structure 01, a top contact 02, a bottom contact 03, a top conductive layer 04, a sidewall protective layer 104, and a sidewall reflective layer 105. The mesa structure 01 further includes a first type semiconductor layer 101, a light emitting layer 102, and a second type semiconductor layer 103. The light emitting layer 102 is formed on the first type semiconductor layer 101. The second type semiconductor layer 103 is disposed on the light emitting layer 102. In some embodiments, the first type and the second type refer to different conductivity types. For example, the first type is P type and the second type is N type. In another example, the first type is N type and the second type is P type.
[0010] 1, a sidewall protection layer 104 is formed on the sidewall of the mesa structure 01, and a sidewall reflective layer 105 is formed on the surface of the sidewall protection layer 104. In some further embodiments, the sidewall protection layer 104 comprises the same material as the material of the first semiconductor layer 101 or the second semiconductor layer 103. The sidewall protection layer 104 comprises a material that does not have conductive properties. In some embodiments, the sidewall protection layer 104 comprises InP or GaAs. The sidewall protection layer 104 is bonded to the sidewall of the mesa structure 01 via atomic bonds. In some embodiments, the sidewall reflective layer 104 comprises gold and silver. In some embodiments, the sidewall reflective layer 105 comprises a dielectric material combined with gold and silver.
[0011] 1, the top surface area of the second semiconductor layer 103 is made larger than the top surface area of the first semiconductor layer 101. In some embodiments, the top surface area of the second semiconductor layer 103 is made larger than the bottom surface area of the second semiconductor layer 103. The top surface area of the first semiconductor layer 101 is made larger than the bottom surface area of the first semiconductor layer 101. In some embodiments, the sidewalls of the first semiconductor layer 101, the light emitting layer 102, and the second semiconductor layer 103 are coplanar in this embodiment such that the sidewalls are flat. In some embodiments, the light emitting layer 102 and the second semiconductor layer 103 are not coplanar and the sidewalls are not flat. In some embodiments, the diameter of the second semiconductor layer 103 is smaller than the diameter of the light emitting layer 102. In some embodiments, the diameter of the first semiconductor layer 101 is smaller than the diameter of the light emitting layer 102. In some embodiments, the material of the first-type semiconductor layer 101 includes at least one of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, p-AlGaN, and the like. The material of the second-type semiconductor layer 103 includes at least one of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-InGaN, n-AlGaN, and the like. The light-emitting layer 102 is formed by a quantum well layer. The material of the quantum well layer includes at least one of GaAs, InGaN, AlGaN, AlInP, GaInP, AlGaInP, and the like. In some further embodiments, the thickness of the first-type semiconductor layer 101 is greater than the thickness of the second-type semiconductor layer 103, and the thickness of the light-emitting layer 102 is less than the thickness of the first-type semiconductor layer 101. In some embodiments, the thickness of the first-type semiconductor layer 101 is in the range of 700 nm to 2 μm, and the thickness of the second-type semiconductor layer 103 is in the range of 100 nm to 200 nm. In some embodiments, the quantum well layer has a thickness of 30 nm or less.In some embodiments, the quantum well layer includes 3 or fewer pairs of quantum wells.
[0012] In some embodiments, the first-type semiconductor layer 101 includes one or more reflectors 1011. In some embodiments, the reflector 1011 is formed on a bottom surface of the first-type semiconductor layer 101. In some embodiments, the reflector 1011 is formed inside the first-type semiconductor layer 101. In some embodiments, the material of the reflector 1011 is a mixture of a dielectric material and a metal material. In some further embodiments, the dielectric material is SiO 2 or SiNx, where "x" is a positive integer. In some embodiments, the metal material includes Au or Ag. In some embodiments, multiple reflectors 1011 are formed horizontally one by one at different horizontal levels in the first type semiconductor layer 1011, dividing the first type semiconductor layer 101 into multiple layers. In some embodiments, the top contact 02 is formed on the top surface of the second type semiconductor layer 103. The conductivity type of the top contact 02 is the same as the conductivity type of the second type semiconductor layer 103. For example, if the second type is N type, the top contact 02 is an N type contact, or if the second type is P type, the top contact 02 is a P type contact. In some embodiments, the top contact 02 is made of a metal or metal alloy including at least one of AuGe, AuGeNi, etc. The top contact 02 is used to form an ohmic contact between the upper conductive layer 04 and the second type semiconductor layer 103 and optimize the electrical properties of the micro LED. In some embodiments, the diameter of the top contact 02 ranges from 20 nm to 50 nm and the thickness of the top contact 02 ranges from 10 nm to 20 nm.
[0013] 1, in some embodiments, the micro LED structure further comprises a top conductor layer 04 covering an upper surface of the second-type semiconductor layer 103 and the top contact 02. The top conductive layer 04 is transparent and conductive. In some embodiments, the top conductive layer 04 comprises at least one of indium tin oxide (ITO) and fluorine doped tin oxide (FTO).
[0014] In some embodiments, the bottom contact 03 is formed on the bottom surface of the first-type semiconductor layer 101. The conductivity type of the bottom contact 03 is the same as the conductivity type of the first-type semiconductor layer 101. For example, if the first-type semiconductor layer 101 is P-type, the bottom contact 03 is also P-type. Similarly, if the first-type semiconductor layer 101 is N-type, the bottom contact 03 is also N-type. In some embodiments, light is emitted from the top surface of the mesa structure 01. For this purpose, the diameter of the bottom contact 03 is made larger than the diameter of the top contact 02, and the diameter of the top contact 02 is made as small as possible so that the top contact 02 is like a dot on the top surface of the second-type semiconductor layer 103. In some embodiments, the diameter of the bottom contact 03 is made equal to or smaller than the diameter of the top contact 02. In some embodiments, the bottom contact 03 is configured to connect to a bottom electrode, such as a contact pad in an IC backplane. In some embodiments, the diameter of the bottom contact 03 is in the range of 20 nm to 1 μm. In some embodiments, the diameter of the bottom contact 03 is in the range of 800 nm to 1 μm. In some embodiments, the center of the bottom contact 03 is aligned with the center of the top contact 02 along an axis perpendicular to the top surface of the first type semiconductor region. In some embodiments, the center of the bottom contact 03, the center of the top contact 02, and the center of the first type semiconductor region are all aligned along an axis perpendicular to the top surface of the first type semiconductor region. In some embodiments, the material of the bottom contact 03 comprises a transparent conductive material. In some further embodiments, the material of the bottom contact 03 comprises ITO or FTO. In some embodiments, the bottom contact 03 is not transparent and the material of the bottom contact is a conductive metal. In some embodiments, the material of the bottom contact comprises at least one of the following elements: Au, Zn, Be, Cr, Ni, Ti, Ag, and Pt.
[0015] In some embodiments consistent with FIG. 2, a microdisplay panel is provided. The microdisplay panel includes a microLED array and an IC backplane 06 formed below the microLED array. The microLED array includes a plurality of the aforementioned microLED structures. The microLED structures are electrically coupled or connected to the IC backplane 06. In some embodiments, the length of the entire microLED array is 5 cm or less. The length of the backplane 06 is greater than the length of the microLED array. In some embodiments, the length of the backplane 06 is 6 cm or less. The area of the microLED array is the active display area.
[0016] In some embodiments, the micro LED structure further includes a metal bonding structure. More specifically, the metal bonding structure includes a metal bonding layer or a connected hole. For example, as shown in FIG. 2, the metal bonding structure is a connected hole 05, which is filled with a bonding metal. The top side of the connected hole 05 is connected to the bottom contact 03, and the bottom side of the connected hole 05 is connected to a contact pad on the surface of the IC backplane 06. In some embodiments, the top conductive layer 04 of the micro display panel is made to cover the entire display panel.
[0017] 2, the microdisplay panel further comprises a dielectric layer 08. The dielectric layer 08 is formed between adjacent mesa structures 01. The material of the dielectric layer 08 is not conductive, so that adjacent micro LEDs are electrically isolated. In some embodiments, the material of the dielectric layer is SiO 2 , Si 3 N 4 , Al 2 O 3 , AlN, HfO 2 , TiO 2 , and ZrO 2In some further embodiments, a reflecting structure 07 is formed in the dielectric layer 08 between adjacent mesa structures 01 to avoid crosstalk. In some embodiments, the reflecting structure 07 does not contact the mesa structure 01. In some embodiments, the top surface of the reflecting structure 07 is aligned with the top surface of the mesa structure 01, and the bottom surface of the reflecting structure 07 is aligned with the bottom surface of the mesa structure 01. The cross-sectional structure of the reflecting structure 07 can be a triangular, rectangular, trapezoidal, or any other shaped structure. In some embodiments, the sidewall reflecting layer 105 is formed on the sidewall of the mesa structure 01, and the space between adjacent mesa structures 01 can be made as small as possible. In some embodiments, the bottom of the reflecting structure 07 extends downwardly lower than the bottom of the mesa structure 01.
[0018] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Claims
1. 1. A micro light emitting diode (LED) structure, comprising: It has a mesa structure. A first semiconductor layer; a light emitting layer formed on the first semiconductor layer; a second semiconductor layer formed on the light emitting layer; a sidewall protection layer formed on a sidewall of the mesa structure; a sidewall reflective layer formed on the surface of the sidewall protective layer; A mesa structure comprising: Equipped with A micro light emitting diode (LED) structure, wherein a top surface area of the second semiconductor layer is greater than each of a bottom surface area of the first semiconductor layer, a top surface area of the first semiconductor layer, and a bottom surface area of the second semiconductor layer.
2. 10. The micro LED structure of claim 1, wherein the sidewalls are flat.
3. 10. The micro LED structure of claim 1, wherein the sidewalls are non-planar.
4. 10. The micro LED structure of claim 1, wherein the sidewall protection layer comprises the same material as the first semiconductor layer or the second semiconductor layer and does not have conductive properties.
5. 5. The micro LED structure of claim 4, wherein a material of the sidewall protection layer comprises InP or GaAs.
6. 10. The micro LED structure of claim 1, wherein the sidewall protection layer is bonded to the sidewall of the mesa structure via atomic bonds.
7. 10. The micro LED structure of claim 1, wherein the material of the sidewall reflective layer comprises Au and Ag, or a dielectric material in combination with Au and Ag.
8. 10. The micro LED structure of claim 1 further comprising a first reflector formed on the bottom surface of the first semiconductor layer.
9. 10. The micro LED structure of claim 8, further comprising a second reflector formed within the first semiconductor layer.
10. 10. The micro LED structure of claim 1 , wherein a thickness of the first semiconductor layer is greater than a thickness of the second semiconductor layer.
11. 11. The micro LED structure of claim 10, wherein the thickness of the first semiconductor layer is in the range of 700 nm to 2 μm and the thickness of the second semiconductor layer is in the range of 100 nm to 200 nm.
12. 12. The micro LED structure of claim 11, wherein the first highly doped region has a thickness in the range of 100 nm to 200 nm and the second highly doped region has a thickness in the range of 100 nm to 150 nm.
13. 10. The micro LED structure of claim 1 , wherein the light emitting layer has a thickness less than a thickness of the first semiconductor layer.
14. 10. The micro LED structure of claim 1 , wherein the light emitting layer is formed by a quantum well layer located between the first semiconductor layer and the second semiconductor layer.
15. 15. The micro LED structure of claim 14, wherein the quantum well layer has a thickness of 30 nm or less.
16. 16. The micro LED structure of claim 15, wherein the quantum well layer comprises three or less than three pairs of quantum wells.
17. 10. The micro LED structure of claim 1, further comprising a top contact formed on the top surface of the second semiconductor layer, and an upper conductive layer formed on the second conductive layer and the top contact.
18. 1. A microdisplay panel, comprising: a micro light emitting diode (LED) array; A first micro LED structure according to claim 1 comprising a first mesa structure; an integrated circuit (IC) backplane formed beneath the first micro LED structure; A micro light emitting diode (LED) array comprising: The first micro LED structure is electrically coupled to the IC backplane.
19. The first micro LED structure comprises: Bottom contact and Top contact and an upper conductive layer; Connecting hole and Further equipped with 20. The microdisplay panel of claim 18, wherein an upper side of the connected hole is connected to the bottom contact and a bottom side of the connected hole is bonded to the IC backplane, and the upper conductive layer is formed on the display panel and electrically coupled to the top contact.
20. The micro light emitting diode (LED) array comprises:
13. A second micro LED structure as claimed in claim 1 comprising a second mesa structure disposed adjacent to the first mesa structure; a dielectric layer that is not conductive and is formed between the first mesa structure and the second mesa structure; 20. The microdisplay panel of claim 18, further comprising:
21. The material of the dielectric layer is SiO ２ , Si ３ N ４ , Al ２ O ３ , AlN, HfO ２ , TiO ２ , and ZrO ２ 21. The microdisplay panel of claim 20, wherein the at least one of
22. 22. The microdisplay panel of claim 21, wherein the sidewall reflective layers of the first and second mesa structures are connected at a top surface of the first and second mesa structures.
23. 23. The microdisplay panel of claim 22, wherein top surfaces of the first and second mesa structures are connected, and the microdisplay panel further comprises a reflective structure in the dielectric layer between the first and second mesa structures, a top surface of the reflective structure below the connected top surfaces of the first and second mesa structures.
24. 24. The microdisplay panel of claim 23, wherein the reflective structures are triangular in shape.
25. 25. The microdisplay panel of claim 24, wherein the reflective structure comprises a first sidewall parallel to the sidewall reflective layer of the first mesa structure and a second sidewall parallel to the sidewall reflective layer of the second mesa structure.