Quantized bistable resistively coupled Ising machine

Abstract

The computational node comprises an input, an output, a bistable node having an input and an output, the output configured to have at least two balanced output voltages, a first buffer circuit having an input and an output, the buffer input connected to the output of the bistable node and the buffer output connected to the output of the computational node, the buffer circuit configured to provide a first output voltage when a voltage at the buffer input is below a threshold and a second output voltage when a voltage at the buffer input is above a threshold, a current conveyor node having an input connected to the input of the computational node and an output connected to the input of the bistable node, the current conveyor configured to hold the input at a constant voltage and configured to mirror a current received at the input to the input of the bistable node. A network of resistively coupled computational nodes is also described.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63 / 298,859, filed January 12, 2022, which is incorporated by reference in its entirety. [Background technology]

[0002] For a long time, the industry has focused on improving general-purpose systems and significantly increasing computing power. However, in recent years, the adoption of purpose-built designs has increased due to their effectiveness in solving certain types of tasks, such as encryption and network operations. At the same time, computing requires better mechanisms to solve various modern problems. Machine learning tasks have become a new focus, and many specialized architectures have been proposed to accelerate their operations.

[0003] Many accelerator architectures have been proposed. These have low operational costs and control overhead, but most are in the von Neumann realm. In a related but different field of research, researchers are trying to exploit physical processes that naturally evolve to a final state that corresponds to the solution of some problem. In principle, such nature-based computing systems could achieve significantly improved performance and efficiency over traditional accelerators. As such, there has been a great deal of interest in these systems, especially in the physics community. The quantum computer sold by D-Wave Systems is a prime example, but many other prototypes exist, some of which have already demonstrated fascinating capabilities.

[0004] Simply put, the Ising model describes a system with a large number of nodes (e.g., atoms), where each node has a spin (σ i ) for all spin pairs (σ i and σ j ) is the specific coupling coefficient (J ij ), with each spin having a coefficient h iIt also interacts with the external field μ at θ. The energy of the entire system is therefore given by the Ising formula:

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[0005] This simplified version is more useful for the purposes of this disclosure. Hereinafter, any reference to the "Ising model" or the Ising formula refers to Equation 2.

[0006] A physical system with such a Hamiltonian naturally tends towards low-energy states. Therefore, the parameters (e.g., J ij ) can be chosen to suit the parameters of the problem, then solving the optimization problem using a formulation equivalent to the Ising formula can be used.

[0007] Many optimization problems map naturally onto Ising machines. Perhaps the easiest problem to map is the maximum cut problem. Given a graph G = (V,E), a "cut" is the process of dividing vertices into two sets, e.g. V + and V - where V - =VV + The goal is to find a cut that maximizes the total edge weight across two sets of vertices. In other words, a maximum cut is

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[0008] The similarities between Equation 2 and Equation 3 are easy to see.

[0009] Connection weight (J ij ) is the edge weight (-Wij ), the Ising formula is simply multiplied by twice the negative cut value with a problem-specific constant (ΣW ij ) (For simplicity of notation, for i ≥ j, W ij is set to 0).

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[0010] Thus, once the machine finds a ground state of the Hamiltonian, it returns the maximum cut. Finding a maximum cut of an arbitrary graph is an NP-hard problem; practical algorithms only attempt to find a good answer. Similarly, all existing Ising machines (including the disclosed design) are Ising sampling machines that typically provide good samples of low-energy states without guaranteeing optimality.

[0011] Designers of Ising machines often focus on max-cut problems because they can be easily mapped to the Ising formula, although other optimization problems can also be mapped to Ising machines.

[0012] However, building a fully programmable spin system is a difficult task. Various realizations of spin systems to date all have significant drawbacks (e.g., the need for cryogenic operating conditions) that manifest themselves to end users as high operating costs and / or limited problem-solving capabilities. The recently disclosed bistable resistively coupled Ising machine (BRIM) design is the first Ising machine without significant drawbacks. Further information regarding BRIMs is described in U.S. Patent Application No. 17 / 996,283, filed October 14, 2022, International Application No. PCT / US2021 / 070402, filed April 16, 2021, and U.S. Provisional Application No. 63 / 011,245, filed April 16, 2020, all of which are incorporated herein by reference.

[0013] To facilitate the computation of diverse workloads, researchers are attempting to map entire algorithms onto physical processes, with the resulting states representing the answer to the mapped algorithm. One example is D-Wave Systems' quantum annealer (Bunyk, et al., IEEE Transactions on Applied Superconductivity, 2014), where a combinatorial optimization problem is mapped onto a system of qubits, and the Hamiltonian of the system is the target for minimization. Careful control is required for the system to settle into an equilibrium state (i.e., the optimal solution), and the qubit state is read out as the solution to the mapped problem.

[0014] While it is not certain whether D-Wave's system can achieve any quantum speedup, it is clear that these Ising machines can indeed find good solutions to optimization problems in very short times (millisecond or microsecond delays). Recently, designs have emerged that show high quality solutions for non-trivial sizes. A common property of Ising machines is that a problem is mapped onto a physical setting, the internal state evolves according to machine-dependent physical properties, and that evolution optimizes a particular formula (the Ising model) and the physical state of the machine is read to achieve a solution to the mapped problem.

[0015] Unlike von Neumann machines, these nature-based machines do not follow an explicit algorithm; that is, nature is effectively performing the computation. Recently, a variety of Ising machines have been implemented in a variety of ways. These vary in the complexity of the underlying physical principles, and it is not clear whether any one form offers fundamental advantages over the other in large-scale systems. Note that these machines are not guaranteed to actually reach the ground state (optimal solution). Rather, these machines are capable of finding good solutions that are fast and generally energy efficient.

[0016] Despite the potential to outperform conventional computers in terms of solution-finding capability and time, building a robust and versatile Ising machine substrate remains challenging, with scalability being one of the key factors to consider. As the complexity of the problem to be solved increases, the amount of hardware components required grows exponentially. To maintain a small form factor and chip area comparable to (or larger than) conventional computing substrates, simple building blocks are preferred for Ising machine implementation. Disclosed herein is a resistively coupled Ising machine with bistable and quantized node interactions (QuBRIM), which reduces hardware complexity by directly coordinating the interactions between adjacent nodes.

[0017] To understand the rationale behind the disclosed design, this disclosure first analyzes why all-to-all connections are essential by showing in more detail the true cost of neighborhood connections (see below). Having all-to-all connections is not enough in itself. After all, any system with von Neumann computation can be simulated. It is shown herein that such emulation is inefficient in terms of both time and energy costs. Only with physical all-to-all connections can dynamical systems perform computations that are orders of magnitude faster than traditional computations. Summary of the Invention

[0018] In one aspect, the computational node comprises an input, an output, a bistable node having an input and an output, the output configured to have at least two balanced output voltages, a first buffer circuit having an input and an output, the input of the buffer connected to the output of the bistable node and the output of the buffer connected to the output of the computational node, the buffer circuit configured to provide a first output voltage when a voltage at the input of the buffer is below a threshold and to provide a second output voltage when a voltage at the input of the buffer is above a threshold, and a current conveyor node having an input connected to the input of the computational node and an output connected to the input of the bistable node, the current conveyor node configured to hold its input at a constant voltage and to mirror a current received at the input to the input of the bistable node.

[0019] In one embodiment, the first buffer circuit includes an inverter. In one embodiment, the computational node further comprises a second inverting output and a second buffer circuit having an input connected to the inverting output of the bistable node, the inverting output of the bistable node being configured to have an inverse value of the output of the bistable node, the second buffer circuit further comprising an output connected to the second inverting output of the computational node. In one embodiment, the first buffer circuit and the second buffer circuit each include an inverter. In one embodiment, the computational node further comprises a second current conveyor node having a second inverting input, an input connected to the second inverting input of the computational node and an output connected to the second input of the bistable node, the current conveyor configured to hold its input at a constant voltage and mirror a current received at the input to the second input of the bistable node.

[0020] In one aspect, the network includes at least a first and a second computational node as defined herein, and further includes a coupling node connecting an output of the first computational node to an input of the second computational node. In one embodiment, the coupling node includes a resistor. In one embodiment, the coupling node includes a pseudo resistor.

[0021] In one aspect, a network of resistively coupled computational nodes includes at least one computational node, each node having an input, an output, a bistable node including an input and an output, the output configured to have at least two balanced output voltages, a first inverter having an input and an output, the input of the inverter connected to the output of the bistable node and the output of the inverter connected to the output of the computational node, a current conveyor node having an input connected to the input of the computational node and an output connected to the input of the bistable node, and a resistive coupling connected to the output of the computational node.

[0022] In one embodiment, the at least one computational node includes a first and a second computational node, an input of the second computational node connected to an input of the first computational node. In one embodiment, an output of the first computational node and an output of the second computational node are connected to a multiplication node, the multiplication node configured to multiply the outputs and provide the multiplied output as a multiplication node output. In one embodiment, the multiplication node includes an exclusive NOR gate.

[0023] The above and other objects and features will become apparent from the following description and by reference to the accompanying drawings, which are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification, and in which like numerals represent like elements. [Brief description of the drawings]

[0024] [Figure 1] 1 is an exemplary computing device. [Figure 2A] A graph of all the physical nodes required for various logical node sizes. [Figure 2B] 13 is a graph of the embedding execution time. [Diagram 3]Figure 1 shows a graph of solution quality, measured as distance from the ground state, for two neighbor-coupled Ising machines. The annealing time for all systems is 20 μs. The solid lines represent the average, and the shaded regions represent the range of results across 50 runs for each problem. [Figure 4A] Figure 1 shows the impact of the local coupling architecture on the quality of the solution. Five different sizes of graphs are generated, ranging from 16 to 32 nodes. These graphs are then minor embedded to generate the target topology for a Chimera connected machine (e.g., D-Wave). All physical spins that map to a single logical spin are coupled with a parameterized strength k (x-axis). The fraction of broken chains (physical spins that represent the same logical spin) is shown. [Figure 4B] Graph showing the impact of local coupling architecture on solution quality. Five different sizes of graphs are generated, ranging from 16 to 32 nodes. These graphs are then minor embedded to generate the target topology for a Chimera connection machine (e.g., D-Wave). All physical spins that map to a single logical spin are coupled with a parameterized strength k (x-axis). The graph plots the distance from the ground state energy of the problem to the energy of the solution. The smaller the difference, the better. [Figure 5A] A sample max-cut problem mapped to a four-node resistive Ising machine. [Figure 5B] 5B is a graph of the solution (cut value +4.5) corresponding to the machine of FIG. 5A. [Figure 6A] FIG. 2 is a simplified schematic diagram of one BRIM node. [Figure 6B] 1 is a graph showing the IV characteristics of a ZIV diode. [Figure 6C] FIG. 1 shows an example of a ZIV diode CMOS implementation. [Figure 7] 1 is a graph showing a potential well of a bistable node. [Figure 8]Block diagram of the BRIM system components. The multicolored links are interconnect lines, while the red and blue lines represent the positive and negative node terminals, respectively. [Figure 9] Shown are two back-to-back PMOS devices forming a pseudo resistor. The equivalent resistance is controlled by Vctr, and the graph below shows the I-V characteristics of the pseudo resistor under different Vctr, where the inverse of the slope represents the resistance. [Figure 10] A schematic diagram of the BRIM combination unit (left: parallel CU, right: anti-parallel CU) is shown. The coloring of the interconnect lines IN+, IN-, Vdac, and CS matches the system-level block diagram in Figure 9. Here, CS is the column select signal generated by the column selector unit of the BRIM. [Figure 11] 1 is a set of graphs illustrating the tradeoff between ZIV diode strength and scaling resistance Rc. [Figure 12] 1 is a schematic diagram of an exemplary QuBRIM diode. CCCS stands for current controlled current source, implemented here as a current conveyor. Transistors M11 and M16 maintain constant voltages at current summing nodes IN+ and IN-. [Figure 13] A block diagram showing the components of QuBRIM, where nodes are labeled Ni and coupling units are labeled CUij. [Figure 14] FIG. 2 is a schematic diagram of one exemplary QuBRIM node half-circuit. [Figure 15] 1 is a schematic diagram of an exemplary QuBRIM coupling unit, on the right is an implementation of a programmable coupling resistor, where Vctr is the bias voltage. [Figure 16] Graph of the cumulative probability distribution of the distance from an optimal max-cut for a 32-node graph at a simulation time of 200ns. Note that the optimal max-cut for a 32-node graph is found by enumerating and comparing all 232 possible solutions. [Figure 17]A graph showing the solution quality of various Ising machines. The annealing time for all systems is 20 μs. The solid line represents the average, while the shaded area represents the range. [Figure 18] Here is a set of graphs. The top graph shows the Ising energy versus time, and the bottom graph shows the transient voltages at each node. The machine reaches a local minimum at about 15ns (dashed line), after which spin-fix annealing begins (solid line). DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] It should be understood that the drawings and description of the present invention have been simplified to illustrate elements relevant to a clear understanding of the present invention, but for clarity, omit many other elements found in related systems and methods. Those skilled in the art may recognize that other elements and / or steps are desirable and / or necessary in implementing the present invention. However, because such elements and steps are well known in the art, and because they do not facilitate a better understanding of the present invention, descriptions of such elements and steps are not provided herein. The disclosure herein covers all such variations and modifications to such elements and methods known to those skilled in the art.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, exemplary methods and materials are described.

[0027] As used herein, each of the following terms has the meaning associated with it in this section.

[0028] The articles "a" and "an" are used herein to refer to one or to more than one (i.e., to at least one) of the grammatical object of the article. By way of example, "an element" means one element or more than one element.

[0029] As used herein when referring to a measurable value, such as an amount, a temporal duration, and the like, "about" is intended to encompass variations of ±20%, ±10%, ±5%, ±1%, and ±0.1% from the specified value, as such variations are appropriate.

[0030] Throughout this disclosure, various aspects of the invention can be expressed in a range format. Of course, the description in range format is merely for convenience and brevity, and should not be construed as an inflexible limitation on the scope of the invention. Thus, a description of a range should be considered to have all possible subranges specifically disclosed, as well as individual numerical values ​​within that range. For example, a description of a range such as 1-6 should be considered to have specifically disclosed subranges such as 1-3, 1-4, 1-5, 2-4, 2-6, 3-6, and individual numerical values ​​within that range, such as 1, 2, 2.7, 3, 4, 5, 5.3, 6, and all whole and partial increments therebetween. This applies regardless of the breadth of the range.

[0031] In some aspects of the invention, software executing the instructions provided herein is stored on a non-transitory computer readable medium, which when executed on a processor performs some or all of the steps of the invention.

[0032] Aspects of the invention relate to algorithms implemented in computer software. Although certain embodiments may be described as being written in a particular programming language and executing on a particular operating system or computing platform, it is understood that the systems and methods of the invention are not limited to any particular computing language, platform, or combination thereof. Software executing the algorithms described herein may be written, compiled, or interpreted in any programming language known in the art, including, but not limited to, C, C++, C#, Objective-C, Java, JavaScript, MATLAB, Python, PHP, Perl, Ruby, or Visual Basic. Furthermore, it is understood that elements of the invention may be executed on any acceptable computing platform, including, but not limited to, a server, a cloud instance, a workstation, a thin client, a mobile device, an embedded microcontroller, a television, or any other suitable computing device known in the art.

[0033] Some of the present invention are described as software running on a computing device. Although the software described herein may be disclosed as running on one particular computing device (e.g., a dedicated server or workstation), it is understood in the art that software is portable in nature, and that most software running on a dedicated server may also be run, for the purposes of the present invention, on any of a wide range of devices, including desktop devices, mobile devices, laptops, tablets, smartphones, watches, wearable electronics or other wireless digital / cellular telephones, televisions, cloud instances, embedded microcontrollers, thin client devices, or any other suitable computing devices known in the art.

[0034] Similarly, portions of the invention are described as communicating over various wireless or wired computer networks. For purposes of the present invention, the terms "network," "networked," and "networking" are understood to encompass wired Ethernet, fiber optic connections, wireless connections including any of the various 802.11 standards, cellular WAN infrastructures such as 3G, 4G / LTE, or 5G networks, Bluetooth, Bluetooth Low Energy (BLE), or Zigbee communications links, or any other manner in which one electronic device can communicate with another electronic device. In some embodiments, elements of the networked portion of the invention may be implemented via a Virtual Private Network (VPN).

[0035] 1 and the following discussion are intended to provide a brief, general description of a suitable computing environment in which the invention may be implemented. Although the invention has been described above in the general context of program modules executing in combination with application programs running on a computer's operating system, those skilled in the art will recognize that the invention may also be implemented in combination with other program modules.

[0036] Generally, program modules include routines, programs, components, data structures, and other types of structures that perform particular tasks or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the present invention may be practiced with other computer system configurations including handheld devices, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The present invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0037] 1 illustrates an exemplary computer architecture of a computer 100 for implementing various embodiments of the present invention. The computer architecture illustrated in FIG. 1 illustrates a conventional personal computer including a central processing unit 150 ("CPU"), a system memory 105 including random access memory 110 ("RAM") and read only memory ("ROM") 115, and a system bus 135 coupling the system memory 105 to the CPU 150. A basic input / output system, including basic routines that help to transfer information between elements within the computer, such as during start-up, is stored in the ROM 115. The computer 100 further includes an operating system 125, applications / programs 130, and a storage device 120 for storing data.

[0038] Storage device 120 is connected to CPU 150 through a storage controller (not shown) that is connected to bus 135. Storage device 120 and its associated computer-readable media provide non-volatile storage for computer 100. Descriptions of computer-readable media contained herein refer to storage devices such as hard disks or CD-ROM drives, although those skilled in the art will appreciate that computer-readable media may be any available media that can be accessed by computer 100.

[0039] By way of example, and not limitation, computer readable media may include computer storage media. Computer storage media includes volatile and nonvolatile, removable and fixed media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EPROM, EEPROM, flash memory or other solid-state memory technology, CD-ROM, DVD or other optical storage devices, magnetic cassettes, magnetic tapes, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired information that can be accessed by a computer.

[0040] According to various embodiments of the present invention, computer 100 may operate in a networked environment using logical connections to remote computers through a network 140, such as a TCP / IP network such as the Internet or an intranet. Computer 100 may connect to network 140 through a network interface unit 145 connected to bus 135. Of course, network interface unit 145 may also be utilized to connect to other types of networks and remote computer systems.

[0041] Computer 100 may also include an input / output controller 155 for receiving and processing input from a number of input / output devices 160, including a keyboard, mouse, touch screen, camera, microphone, controller, joystick, or other type of input device. Similarly, input / output controller 155 may provide output to a display screen, printer, speaker, or other type of output device. Computer 100 may be connected to input / output devices 160 via a wired connection, including but not limited to optical fiber, Ethernet, or copper wire, or via wireless means, including but not limited to Wi-Fi, Bluetooth, Near Field Communication (NFC), infrared, or other suitable wired or wireless connection.

[0042] As briefly mentioned above, a number of program modules and data files may be stored in the storage device 120 and / or RAM 110 of the computer 100, which includes an operating system 125 suitable for controlling the operation of a networked computer. The storage device 120 and RAM 110 may also store one or more applications / programs 130. In particular, the storage device 120 and RAM 110 may store applications / programs 130 for providing various functions to a user. For example, the applications / programs 130 may include many types of programs, such as word processing applications, spreadsheet applications, desktop publishing applications, database applications, gaming applications, Internet browsing applications, email applications, messaging applications, and the like. According to an embodiment of the present invention, the applications / programs 130 include multi-function software applications for providing word processing functionality, slide presentation functionality, spreadsheet functionality, database functionality, and the like.

[0043] In some embodiments, computer 100 may include various sensors 165 for monitoring the environment around and within computer 100. These sensors 165 may include global positioning system (GPS) sensors, photosensitive sensors, gyroscopes, magnetometers, thermometers, proximity sensors, accelerometers, microphones, biometric sensors, barometers, humidity sensors, radiation sensors, or any other suitable sensors.

[0044] Ising machines are capable of mapping and solving optimization problems in an Ising formulation. Such problems are also expressed in an equivalent quadratic unconstrained binary optimization (QUBO) formulation. In the early stages of Ising machines, the emphasis is still on demonstrating the underlying physical principles. For this reason, neighborhood coupling is a common theme among designs, as coupling large numbers of spins is technically very challenging. Furthermore, existing Ising machines largely avoid all-to-all connectivity, so it is natural that designers would be right to avoid this challenge in new efforts. As we show here, careful analysis reveals that the problems it poses are numerous and significant.

[0045] The first challenge is the time cost of preprocessing. Given that Ising machines offer a limited connectivity scheme, any problem must go through an embedding process before it can be mapped to hardware. Figures 2A and 2B show the effect of this process on several machines that offer connectivity only to nearest neighbor graphs (NN), king graphs (KG), and chimeras (CH). These machines nominally have 2000-30,000 spins, but are practically limited to 127 logical spins. For such problem sizes, traditional simulated annealing codes can achieve very good results in under 5 ms. In contrast, the embedding process takes 1000-200,000 times longer just for preprocessing. The NN results shown in Figures 2A and 2B are nearest neighbor results with 20,000 spins, the KG is a king graph with 30,927 spins, and the CH is a chimera with 2048 spins.

[0046] The second challenge is the cost of hardware resources. Even if we ignore the embedding time, the number of physical spins required is essentially O(N 2 ), which means that a general QUBO problem with N binary variables grows in O(N 2 ) control parameters. In an Ising machine with a fixed degree topology, 2) programmable edges is necessarily O(N 2 ) physical spin. As a result, an Ising machine with fixed-order couplings simply provides a large number of nominal spins. This is shown as a concrete example in Table 1. [Table 1]

[0047] Table 1 shows an example showing the lower limit of the number of spins and the number of bond units (cu).

[0048] Existing Ising machines can be classified into three categories based on the technology used in their design: quantum annealers, optical annealers, and electronic annealers.

[0049] The latest quantum Ising annealers manufactured by D-wave can support up to 2000 qubits. The qubits are combined to form a Chimera graph. As a result of local combinations, D-wave machines can only map all-to-all connected graphs of up to 64 nodes. These annealers are also susceptible to noise and require cryogenic operating conditions that consume large amounts of power (25KW for the D-Wave 2000q).

[0050] The most popular light-based Ising machine is the Coherent Ising Machine (CIM). It uses optical parametric oscillators (OPOs) to generate and manipulate signals that represent one spin. Unlike D-Wave, CIM nodes are all-to-all coupled. The machine has two components: an optical cavity built using several kilometers of fiber, and an auxiliary computer to implement the coupling between the nodes. The amplitude and phase of every pulse in the optical cavity is detected, and the interaction with every other pulse is calculated using an auxiliary computer (FPGA). This calculation is then used to modulate new pulses that are injected back into the optical cavity. Strictly speaking, the current implementation is a hybrid Ising machine of natural simulation. Thus, in addition to the challenge of building a cavity, CIM also requires a significant supporting structure with fast conversion between optical and electrical signals.

[0051] The working principle of CIM can be considered as the Kuramoto model (see Takeda, et al., Quantum Science and Technology, 2017). Therefore, in theory, other oscillators can be used to achieve similar objectives. This led to the design of electronic oscillator-based Ising machines (OIMs). These systems use LC tanks for spin and (programmable) resistors as coupling units. However, in on-chip integration, inductors often cause practical challenges. They are area intensive and have undesirable parasitics such as reduced quality and increased phase noise, which cause practical challenges in maintaining frequency uniformity and phase synchrony among thousands of on-chip oscillators.

[0052] The disclosed BRIM design, detailed above, is an electronic design with resistive coupling, where the Ising spin is implemented as a capacitor voltage controlled by a feedback circuit to achieve bistability. The use of voltage (rather than phase) to represent spin allows for an easy interface to additional architectural support for computational tasks.

[0053] Researchers have also designed various chips to accelerate simulated annealing, or variants of classical algorithms. In these designs, the spins are virtual, in that they are bits in memory and are manipulated by an algorithm (simulated annealing). These machines are built specifically to accelerate that algorithm. Thus, the designs are called Accelerated Simulated Annealers (ASA). They are fundamentally different from regular Ising machines in that they follow a specific algorithm, whereas regular Ising machines are guided by the laws of physics themselves.

[0054] Consider a fully connected problem with 1000 spin variables and about 500,000 coupling coefficients. For a nearest-neighbor (mesh) system, we can calculate a very loose lower bound on the size of the system onto which the problem can be mapped. This can be done by assuming that all couplers are used to represent program coefficients. This is an optimistic view, since in reality, many of the couplers simply connect nearby spins to form logical spins. Even in this case, a 500x500 array is needed to have enough couplers for the coupling coefficients. In the nearest-neighbor architecture, 250,000 spins are needed just to get enough coupling units. This is what is actually needed. The cost of 250,000 spin units is real and substantial, but the idea that the system has that many nominal spins makes no sense. In fact, rather than arbitrarily referring to the problem as having 1000 spin variables, we could simply describe it as having 500,000 coupling coefficients. The most resource-efficient system would then be the all-to-all architecture, which requires only 1000 spins.

[0055] Another challenge is the cost in solution quality: fixed-order topologies are indeed wasteful in terms of the resources required to provide the same computational power. To make matters worse, the process of mapping a single logical spin to many physical spins introduces subtle problems that result in the additional problem of reduced solution quality. In this disclosure, we first present empirical observations and then explain why the reduced solution quality is fundamental.

[0056] First, consider two examples of machines using fixed-order coupling: D-Wave's 2000Q, which uses Chimera graphs, and the Accelerated Simulated Annealer (ASA), which uses King graphs. Figure 3 shows the two machines solving small graphs of up to 32 logical spins. At this scale, it is possible to quickly enumerate the phase space and obtain a deterministic ground state. Simulated annealing (and the disclosed simulated version of BRIM) can achieve a ground state with very high probability in an annealing time of 20 μs. However, as shown in Figure 3, it is difficult for both neighboring machines to achieve a ground state in the same annealing time. Further research reveals that the reason for the poor quality of the solutions is fundamental.

[0057] In the embedding problem, logical spins from the original problem are represented as a (large) chain of physical spins that are (hopefully) strongly coupled to have the same polarity. This is done by assigning a coupling strength k (assuming the coefficients in the problem have already been normalized to 1). Note that simply increasing k makes it less likely that a chain will be "broken" (physical spins in a chain have both polarities), but cannot guarantee that broken chains will not exist.

[0058] To illustrate the problem more concretely, consider a very small set of programs consisting of 16-32 logical spins that are transformed by minor embedding into a physical arrangement with chimera bonds. The transformed energy landscape may then be navigated using a state-of-the-art simulated annealing solver (Isakov, et al., Computer Physics Communications, 2015). Figure 4A shows the fraction of chains that break when varying the bond strength k. Note that because simulated annealing is used, the results only relate to the intrinsic properties of the energy landscape itself. Machine imperfections are not even a factor in this ideal experiment, and would exacerbate the problem in the real world.

[0059] Figures 4A and 4B show that at the end of the annealing schedule, 40%-75% of all chains are broken. Note that even if only one chain is broken, the original solution becomes illegal. In other words, the embedded problem represents a completely different topological space, much larger than the original (2 O(N^2) vs 2 O(N) ). In this new space, almost all topological points (2 O(N^2) -2 O(N) ) represents a technically illegal solution. It is no wonder that Annealer has such a low chance of finding a legal solution.

[0060] One might think that sampling illegal solutions is not a problem, or that in any case the problem can be easily mitigated by increasing k. Both are true, but only to a certain extent. First, obtaining illegal solutions is not a problem in itself. It is not difficult to transform a raw solution into a legal solution of the original problem. A common method is to use majority voting to determine the polarity of the entire chain. As shown in Figure 4A, it is clear that increasing k has the effect of decreasing the proportion of broken chains. However, an examination of the final results for the solution quality (Figure 4B) shows that while increasing k is effective at first, it becomes counterproductive beyond a certain point. Note that these graphs are very small and their entire phase space can be enumerated quickly. Traditional solvers always find ground state solutions very quickly.

[0061] The observations shown in the figure become much easier to understand if we consider a concrete example. For example, for a 32-node graph g (representing the 32-spin Ising formulation), the size of its topological space is 2 31 By minor embedding, the transformed graph g e has 320 nodes. e 2 of 32 Only phase points in g are legal, i.e., they correspond directly to the phase points of g. In other words, for every legal phase point, there are 2 illegal phase points. 288 The solver is in the topological space g e To obtain a solution by searching for

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[0062] To convert it to a legal solution by majority vote, essentially

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[0063] This problem can be mitigated to some extent. For example, using a larger k has the effect of increasing the penalty for illegal solutions. However, this is also not without cost. Increasing k beyond a certain point becomes counterproductive, as too much emphasis is placed on not breaking the chain and not enough emphasis is placed on the quality differences between the various legal solutions. Empirically, for these test problems, the optimal value of k=4 has been found. Since the dynamic range of coupling coefficients in realistic analog hardware is finite, increasing the value of k simply reduces the range that can be used to represent real problems. In the disclosed example, k=4 has the effect of reserving two bits for use in reducing the impact of broken chains. Unfortunately, as the size of the graph increases, so does the optimal value of k, as shown in the figure. That is, for real problems with thousands of spins, more dynamic range of the system is required to program k.

[0064] As shown above, the embedding process not only changes the number of spins required to map the problem and requires significant preprocessing, but also has a significant impact on the quality of the solution, since it forces the search in a proxy energy landscape rather than the energy landscape of the original problem. Overall, neighborhood coupling raises a large number of real problems that are often ignored in the literature. Everything suggests that neighborhood coupling is not the solution to the challenge of increasing the problem-solving ability of machines. While the barrier to building a proof-of-concept prototype is lowered, next-stage machines will need to efficiently support all-to-all coupling.

[0065] An obvious alternative to providing physical all-to-all coupling is to provide emulated coupling. Coherent Ising Machines (CIMs) (see Inagaki, et al., Science, 2016; Yamamoto, et al., npj Quantum Information, 2017; McMahon, et al., Science, 2016; Takata, et al., Scientific Reports, 2016; and Bohm, et al., Nature Communications, 2019) achieve this by measuring pulse i, numerically computing its coupling effect with another pulse j, and then injecting a corresponding signal representing the computed value back into the dynamical system. This approach also facilitates the construction of proof-of-concept prototypes, but issues arise in high-performance systems, as both computational delay and energy limit the overall system speed and energy efficiency.

[0066] A recent comparison of computational solutions, Simulated Bifurcation (SB) and CIM, reveals the truth (see Tatsumura, et al, 2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019).

[0067] In SB, the entire dynamic system is computationally simulated. In both SB and CIM, each round of interaction requires O(N 2) multiply-accumulate (MAC) operations are required. Since SB is a pure simulator, whereas CIM includes hardware, one would expect some advantage for CIM, but in fact SB is much faster. For a commonly used problem (K2000), SB required 25 rounds / steps to reach a certain solution quality, whereas CIM requires more than 150 rounds / steps. In other words, the software-based SB is faster and more energy-efficient than the hybrid Ising machine. This example clearly casts doubt on the usefulness of von Neumann-emulated coupling in Ising machines. Finally, recent versions of CIM have achieved an astounding 100,000 spins, in part by incorporating a piezo-based fiber stretcher to help achieve stable phase relationships among the many pulses in a 5 km fiber. The problems with such an approach become clear when one takes a closer look at the computational boards used to perform the so-called digitally assisted interactions. First, the entire machine is built for a special type of graph where the connection weights are only 1 or -1. Despite only supporting low-bit precision computations, 54 top-of-the-line FPGAs (XCVU13P-2FHGB2104I) were used for the von Neumann computing. The computational elements alone together consume about 6 kW (see Honjo, et al., Science Advances, 2021).

[0068] Intuitively, nature-based computational systems leverage the computations performed by nature to achieve extraordinary speed and energy efficiency. If von Neumann computing were to rely on emulating nature, such advantages would likely disappear entirely or be greatly reduced.

[0069] Existing Ising machines appear to offer a fair number of spins, but they fall into two categories, neither of which holds any promise for the future.

[0070] (1) Architectures with neighborhood connections, which create a larger number of nominal spins. There is no indication that these truly improve the machine's problem-solving ability (effective spins). Instead, they create very expensive pre-processing requirements, inappropriate use of hardware resources, and radically reduce the quality of the solution. All three of these technical problems are very difficult to address, and may not have any solution.

[0071] (2) Emulated all-to-all connections, which incur huge amounts of traditional (von Neumann) computing demands and associated energy overhead. Currently, the computing demands and associated energy requirements are much worse than traditional solvers.

[0072] Therefore, the best (though not the only) approach is to provide a hardware coupling mechanism that is very efficient (in terms of area and energy) and allows true all-to-all coupling at the hardware level. Only then can dynamical systems leverage nature to perform certain kinds of tasks orders of magnitude faster and more energy-efficiently than traditional von Neumann solvers. Everything preliminary shows that this is feasible. The focus of the disclosed hardware system is to provide exactly such hardware at scale. In most cases, the disclosed global all-to-all architecture has no drawbacks compared to less demanding architectures. In some rare situations, it may be worth considering the current neighborhood topology.

[0073] Given the technology of spin, it may not be technically feasible to couple a large number of nodes (such technology is not worth investigating). Another example of a use case that may be suitable for a neighborhood topology is when a custom architecture is built for a fixed problem where the connectivity matrix is ​​very sparse. In such cases, the disclosed technology can also be used with sparsely coupled architectures, resulting in a correspondingly smaller system.

[0074] In the Ising model, two nodes (i and j) are strongly and positively connected (J ij If σ is large and positive, their spins are likely to be parallel (σ i = σ j ) is intuitively obvious. Similarly, strong negative coupling leads to antiparallel spins (σ i =-σ j ), whereas a|J ij |≒0 suggests that the two spins are likely to be independent. This behavior can be easily mimicked with a resistively coupled capacitor, in which the spin of a node is coupled to the capacitor C i The voltage v applied to i The polarity of the resistor R ij =R c / |J ij |, where R c is a scaling constant equal to the minimum resistance achievable (or acceptable) for a particular technology. The sign of the coupling can be achieved by connecting the same or opposite polarity on the corresponding capacitors. Figure 5A shows a simple 4-node system mapped from a weighted max-cut problem with edge weights labeled. After the capacitor voltages are randomly initialized to ±1, the system actually seeks an equilibrium state as shown in Figure 5B. At this point, the node polarities (i.e., spins) separate the nodes into {1,4} and {2,3}, which represents the correct solution to the max-cut problem. A more realistic 6-node discrete component prototype is presented in Afoakwa, et al., International Symposium on High-Performance Computer Architecture (2021).

[0075] Bistability: A simplistic design supports intuition but is far from robust. For example, the trivial equilibrium state (v i=0), frustration (i.e., there are multiple equilibria with the same energy), or a leaking capacitor, the equilibrium voltage may be 0 or too low to be read reliably.

[0076] Therefore, a local feedback circuit is needed to move the node away from 0V and towards the power rail (i.e., making the node bistable). Such active feedback is realized in some embodiments by a ZIV diode (a ZIV diode has a sloped "Z" shaped IV curve g, as shown in FIG. 6B). ZIV (v i ), an exemplary ZIV diode implementation suitable for CMOS integration is shown in Figure 6C. Design details are given in Afoakwa, et al., International Symposium on High-Performance Computer Architecture (2021), but the key point to note is that the resulting dynamical system (whose nodes are shown in Figure 6A) is governed by the Lyapunov function shown in Equation 5 and Equation 6 below:

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[0077] A more complete system design is shown in Figure 8 and includes the bistable node 801, the digital interface, the combining unit 802, the programming unit (including memory 805, multiplexer 804, DAC 809) that configures the combining weights 810, and the annealing and randomized spin flip control 802. Each CU 803 includes a PMOS-based resistor whose equivalent channel resistance is programmed by the row-level DAC 809 by applying the appropriate gate voltage that is stored and held on the PMOS gate capacitance.

[0078] Coupling Unit (CU): Using an array of BRIM nodes gives us the flexibility to combine them in any desired topology. As quantitatively explained above, all-to-all coupling is a better choice since it is computationally more useful. BRIM coupling is achieved through an array of CUs, each of which contains several programmable / variable resistors.

[0079] The combined resistor may be implemented in standard CMOS using a single MOSFET biased in the triode region, but the linearity is expected to be poor due to the large applied voltages (e.g., the maximum expected voltage across a programmable resistor goes rail-to-rail). For this reason, a double PMOS based resistor (hereafter referred to as R-PMOS) is used. As shown at the top of Figure 9, the R-PMOS resistor 901 includes two identical PMOS devices connected in series with a common gate electrode. The resistance of the R-PMOS is a function of the gate voltage (V ctr ) to an appropriate value. ctr is set by a row-level digital-to-analog converter (DAC) (e.g., 809) and maintained by a MiM capacitor or MOSCAP 902 (inside the CU) during machine operation. The R-PMOS exhibits symmetric resistance with respect to the polarity of the voltage applied across its terminals. The simulated IV characteristics of a PMOS in 45 nm CMOS technology is shown in graph 903 of Figure 9, showing the improved linearity compared to a single PMOS in a triode.

[0080] In the disclosed system, the coupling is bidirectional and can in principle be achieved by using a total of N(N-1) / 2 CUs. However, to achieve bipolar coupling (both positive / parallel and negative / anti-parallel coupling) between any two node capacitors and support fully differential operation, each CU in the N(N-1) / 2 array would require four R-PMOS resistors (one pair for each coupling polarity selection), a 2x2 crossbar switch to select parallel or anti-parallel connection, and memory cells and logic gates to store and control the state of the crossbar switch. A more area-efficient design that alleviates the need for crossbar switches and local memory cells is to split each bidirectional CU in the N(N-1) / 2 design into two smaller units, each handling only one type of polarity. This approach produces a total of N(N-1) CUs (see Figure 8), but the area of ​​the split units is significantly smaller (half that) than the bidirectional CUs in the N(N-1) / 2 design. For example, the CUs in the upper triangular portion of the array in Figure 8 (i.e., i <jのCU ij The unit (CU) is dedicated to parallel connection, while the CU belonging to the lower triangle is dedicated to anti-parallel connection. i and N j R ij =R c / |J ij When combined in parallel with a resistance equal to |CU ij The pair of PMOS resistors is R ij It is programmed in the CU ji The R-PMOS in is set to a large enough value so that there is no negative (or anti-parallel) coupling between the two nodes. As shown in Figure 10, each CU has two programmable resistors, a control voltage V ctr The R-PMOS has two capacitors (one for each R-PMOS) to store the R-PMOS, and a column select access switch that connects the gate of the R-PMOS to a row-level DAC for programming.

[0081] Both the initial node values ​​and the coupling resistors are programmable. To the right of the array of coupling units in FIG. 8 is an array of programming units 810. A digital memory 805 (e.g., SRAM) stores the coupling coefficients to be loaded into the DAC array and the control signals for the MUX array. In the illustrated example, the programming process is performed in a time-interleaved manner (one column at a time) using column selectors and pull-up networks, as shown below the coupling units in FIG. 8. During the programming phase, the column selector selects a particular column (e.g., the jth column) by connecting its chip select (CS) line to 0V. This turns on all access switches that connect the gates of the RPMOS resistors in the jth column to the row-level programming units. At the same time, the pull-up logic pulls the vertical interconnect line IN + and IN - The terminal voltages of all R-PMOS in the jth column are V DD Depending on the coupling polarity, the MUX in each row (e.g., the i-th row) ij For example, the CU ij When is activated, its R-PMOS gate is charged to the voltage provided by the DAC, otherwise, the V provided by the ith MUX unit. DD The R-PMOS resistor is turned off and its resistance is set to a very high, practically infinite value. Note that CUs symmetrical with respect to the main diagonal of the CU array are either both deactivated or only one activated, depending on the coupling polarity. For example, the coupling coefficient J ij If is negative, CU ij The resistance of CU is set to infinity. ji The resistance of

number

[0082] From Equation 6 and Figure 7, we can see that a balance is needed between the strength of the ZIV diode currents and the coupling currents. As shown in Figure 11, if the ZIV diodes are too weak (graph 1101), the whole system may degenerate into a passive RC network and all node voltages may drop to zero. On the other hand, if the ZIV diodes are too strong (graph 1103), the node voltages will diverge to the nearest vertices in N-dimensional space, almost ignoring the Ising terms. Finding the right balance (graph 1102) is a key step in R c and g ZIV This is not straightforward, as it depends not only on the peak current of the current source, but also on the state of the machine. For this reason, some embodiments employ an annealing technique in which the ZIV diode current contribution is gradually introduced over time (i.e., the strength of the ZIV diode is dynamically adjusted). One way to achieve this is to adjust the duty cycle (i.e., the ZIV diode is switched on and off while the machine is running, gradually increasing the "on" time).

[0083] As noted above, a BRIM system may get stuck in a local maximum determined by the initial state. To allow BRIM to escape from a local maximum, some embodiments may use a strategy similar to that used in simulated annealing, that is, injecting perturbations into state variables. For example, the system may be moved to an adjacent state in the global phase space by performing a "spin flip" (i.e., changing the spin to an opposite value) of a selected node. This allows the system to escape from the region of attraction (e.g., the local maximum) and explore new regions. In simulated annealing, the probability of such a bit flip is a function of both the energy difference due to the bit flip and the current temperature. For implementation convenience, in some embodiments, the temperature is used to determine the probability / frequency of spin flips. In some embodiments, the temperature follows an exponential annealing schedule. In other words, the frequency of spin flips decreases exponentially. With this support, BRIM can be used similarly to other Ising machines. First, the weights / coupling coefficients are programmed, then the annealing time is selected, and finally the state of the node is read after the completion of the annealing schedule. The annealing schedule of the ZIV diodes and spin perturbations can be controlled either globally for all nodes or locally for each node individually.

[0084] There are several circuit non-idealities that can affect the coupling accuracy and dynamic range (DR), such as inherent kT / C noise, non-linearity of the R-PMOS resistor, gate oxide leakage current, charge injection from the CU access switches, etc. Below we present a preliminary analysis of DR and accuracy, but note that a more detailed analysis exploring the many degrees of freedom and associated tradeoffs is warranted.

[0085] Preliminary DR and accuracy analysis Assuming that the CU area for a standard 45nm CMOS is 1μm x 1μm, and the total capacitance seen by the gate of the R-PMOS is 4fF (including the gate capacitance and an additional 2fF metal-insulator-metal (MiM) capacitor per R-PMOS), the expected kT / C noise is approximately 1mV. rms Therefore, when the channel resistance is 60kΩ and 7MΩ, the error is 0.1% and 0.38%, respectively. ij |≒1 / R ij So, the coupling coefficient |J ij |DR is the minimum programmable resistance of the R-PMOS (CU of 45 nm in this example, minimum R ij = 60kΩ) ij |J defined by the upper limit of | and the error of the upper limit resistance value ij The relative error of the R-PMOS resistor due to kT / C noise flattens out to 0.38% at about 7 MΩ, and DR = 20 log 10 (7M / (0.0038*60k))=89dB, or about 15 bits of resolution. Meanwhile, the accuracy limit due to kT / C noise is defined by a peak relative error of about 0.38%, which corresponds to an effective resolution of about 8 bits.

[0086] Another important issue to consider that can limit the overall coupling accuracy is the nonlinearity of the R-PMOS resistor. Preliminary nonlinearity modeling in 45 nm CMOS shows that for voltage ranges between the R-PMOS terminals of ±0.4 V, ±0.6 V, and ±0.8 V, the relative error (calculated as the ratio of the RMS deviation from the best fit line in graph 903 of Figure 9 to the slope of the best fit line) is 1%, 3.4%, and 5%, respectively (corresponding effective resolutions of 6.6, 4.9, and 4.3 bits, respectively). Mitigating the nonlinearity may require reducing the voltage swing at the expense of a lower signal-to-noise ratio and / or increased circuit area and / or power, and it is clear that the nonlinearity imposes a greater constraint on the achievable coupling accuracy than errors due to intrinsic kT / C noise or charge injection.

[0087] It is also important to note that extensive statistical analysis is required to fully understand the extent of the impact of nonlinearities on the quality of BRIM solutions. More specifically, the types of problems solved by Ising machines, including BRIM, are often such that an optimal solution is not guaranteed, and suboptimal solutions are only expected. Thus, the true impact of nonlinearities on solution quality can only be assessed by thoroughly analyzing a large number of graph problems.

[0088] Quantized BRIM Coupling between nodes is a key element for building robust Ising machines, since the problem to be solved is directly embedded in it. Although spin can take only two discrete values, the physical quantity representing spin can vary widely, which can cause many problems. For example, in a resistively coupled Ising machine, the coupling resistance can vary widely, making it very likely that the machine will solve different problems at different times. Also, the trade-off between the size, power, and precise functionality of the building blocks limits scalability.

[0089] In addition to reducing the maximum voltage swing across the R-PMOS (e.g., by lowering the supply voltage), another technique to reduce the effects of nonlinearities is to employ an alternative BRIM design (so-called quantized BRIM, or QuBRIM, described in more detail below) in which the voltage swing across all R-PMOS is kept constant and the coupling between nodes is fully current-based. However, the QuBRIM design requires additional circuitry such as comparators / inverters and current conveyors for current summation per node, and therefore scales as O(N). Furthermore, since QuBRIM coupling is unidirectional (unlike BRIM's bidirectional coupling), two CU units are required per coupling, doubling the overall size of the CU array compared to the baseline BRIM.

[0090] The disclosed modified BRIM design (QuBRIM) requires more area and power than the baseline BRIM, but not only helps improve the linearity and accuracy of the coupling coefficients, but also creates a clear path to the implementation of CMOS-based Ising machines with many-body interactions (e.g., third- or higher-order terms in the Ising formula). The QuBRIM design performs a 1-D iteration on a node variable (e.g., capacitor voltage v) before coupling to the capacitor of the other node. i ) into binary values ​​(e.g., ±1 or rail-to-rail).

[0091] The resulting dynamic system is applied to Equation 7 below using the Lyapunov function shown in Equation 8, where Q(v i ) is v i quantization function that is equal to +1 if ≥ 0 and -1 otherwise (alternatively, v i ≧V dd / 2, Q(v i )=V dd , otherwise 0V).

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[0092] From another perspective, the dynamics of QuBRIM can be explained by the change in voltage of each node caused by the other nodes connected to it. Without loss of generality, in the following we focus on the dynamics of one node for simplicity of analysis, but this can be easily extended to the whole system [V1(t),V2(t),...,V N (t)] T .

[0093] The dynamics of node i is expressed as follows:

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[0094] Considering the above set of differential equations describing QuBRIM as a dynamical system, we find that there exists a Lyapunov function of the form

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[0095] The quantity Q(v j ) only takes values ​​of {-1,+1} and can be used to directly represent the spin of node j, so the Lyapunov function in Equation 11 is directly related to the Ising Hamiltonian in Equation 2. That is, by minimizing the Lyapunov function in Equation 11, QuBRIM simultaneously finds the minimum of the Ising Hamiltonian.

[0096] To demonstrate the optimal solution search capability of QuBRIM, we present the Lyapunov stability analysis below. This shows that for a point v e in

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[0097] Taking the time derivative of Equation 11 and applying the chain rule we get

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[0098] However, the above analysis does not guarantee that the system will converge to a global minimum, as it depends on the energy landscape and initial conditions. This is similar to other annealers. There is no strong guarantee that the ground state will be reached in typical usage scenarios (which differ from ideal conditions) or in an efficient manner. For example, simulated annealing has been shown to be able to reach the ground state in systems with finite phase space. However, doing so may take longer than enumerating the space.

[0099] As contemplated herein, in some embodiments, quantization of the QuBRIM node can be performed by a simple logic gate (e.g., inverter 1201 as shown in FIG. 12, which shows an exemplary schematic diagram of a QuBRIM node). Alternatively, if greater accuracy is required, a high-gain comparator such as a regenerative latch can be used. As with BRIM, from Equation 8, it can be seen that QuBRIM is the (local) minimum of the objective term (-Σ i<j Jij v j v i ), it is clear why we tend to look for P(v i ) The double well profile allows the voltage v i It is clear that when the quantized values ​​Q(v i ) could be directly coupled to the capacitor of another node, but this would result in a large voltage swing across the terminals of the R-PMOS resistor, which can lead to nonlinear errors similar to those of BRIM. In contrast to BRIM, QuBRIM in some embodiments employs current-mode coupling. The coupling current (Q(v j ) / R ij ) are summed to a constant voltage node (e.g., the virtual ground node of an amplifier) ​​with the help of a current conveyor CCCS shown in Figure 12. The current conveyor then sums this current as N i Mirroring the capacitor C at the node. Therefore, every R-PMOS combination resistor has a constant voltage swing across its terminals (for example, ±V dd / 2), which is essentially linear.

[0100] Node variable v i to a binary value before connecting it to the CU array or other nodes, we can use, for example, an XNOR logic gate to convert the quantized variable Q(v i ) to realize many-body interactions. For example, if the four-spin objective function with cubic terms to be minimized is H=-J 123 σ1σ2σ3-J 124 σ1σ2σ4-J 134 σ1σ3σ4-J 234 Assuming that σ2σ3σ4, the four-node QuBRIM that minimizes the function H is constructed from a set of differential equations shown in Equation 13 below, where:

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[0101] V CM is the common-mode voltage, which is usually equal to half the power supply voltage. The left side of Equation 13 is the common-mode voltage at node N i represents the current into the node capacitance of ijk The current through the diode is equal to the sum of all currents from the diode and the current through the ZIV diode.

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[0102] This technique can be extended to build QuBRIM machines that minimize objective functions involving Ising formulations that contain Ising terms of any order (greater than 2) as well as terms of mixed orders. For example, all-to-all QuBRIM with cubic terms requires O(N 3 ) hardware resources are required, and for the XNOR gate, O(N 2 It is also important to understand that a hardware resource of O(N 3 ) CU array.

[0103] System-Level Design An exemplary QuBRIM system is shown in Figure 13 and can be viewed as a group of subsystems as follows: The first subsystem is the node and combining unit. On the left side of the figure is a bistable node 1302 (N i) each of which contains two capacitors to perform the differential operation. The nodes are interconnected through a mesh of coupling units 1306 (CU), each of which has four terminals, inputs IN+ and IN- which receive currents from other nodes, and outputs OUT+ and OUT- which generate quantized voltage signals that are coupled to other nodes. The detailed working principle of these two components is further explained below. The D flip-flop array next to the nodes contains a set of D flip-flops 1301, one per node, and is used to store the spin configurations as needed.

[0104] The second subsystem is the programming unit. Both the initial node values ​​and the coupling resistors are programmable. To the right of the coupling unit array is the programming array. This array consists of a digital memory 1309 for storing the weights that drive an array of digital-to-analog converters (DACs) 1307. A small number of such DACs 1307 are sufficient to program all the coupling units in a time-interleaved manner. In the diagram, N DACs are shown programming Nx(N-1) coupling units. Such a configuration requires corresponding column selectors and pull-down logic 1303, 1306, which are displayed above and below the coupling units.

[0105] The third subsystem is the perturbation unit. As the graph complexity increases and the number of local minima in the Ising formulation increases, a machine following gradient descent is more likely to reach a local energy minimum. One possible way to escape from a local minimum is by flipping the polarity of some of the spins. However, this scheme requires several monitoring blocks to detect and change the polarity of each node, which significantly increases the hardware complexity. The disclosed device instead randomly selects a node and clips it to one of the power rails for a short time. The node's spin then either maintains its current state or switches to the opposite state for a certain time interval. This scheme is called "spin fix annealing". The control signal is sent by the annealer control unit 1304 in Figure 13. The occurrence of spin fixes occurs frequently at first, but gradually decreases. This approach makes sense because as the energy of the system approaches a global minimum, a single spin fix makes it less likely to escape.

[0106] Circuit Level Design In the following, one embodiment of a detailed circuit implementation of the disclosed design is described, focusing mainly on the analog core portion, i.e., QuBRIM nodes and combiners. Although the embodiments may refer to one particular implementation, such as the implementation shown in Figure 14, it is understood that the present disclosure contemplates alternative designs that use equivalent circuit elements to perform the functions disclosed herein.

[0107] Referring to Figure 14, one half of one QuBRIM node (e.g., 1302 in Figure 13) is shown. To achieve cross-coupling, the QuBRIM node needs to be made differential. The circuit shown includes three core functional subcircuits: current conveyor, quantizer, and spinfix switch. Each subcircuit is described in detail below.

[0108] The current conveyor is configured as a class AB current conveyor (see Wilson, International Journal of Electronics, 1992), designated 1401, and formed by M1 to M8 in FIG. 14. The detailed operating principle is as follows. B sets the bias voltage for M1-M4, and these four transistors then form a local feedback loop such that the voltage at junction X follows the voltage at junction Y. As a result, the bias currents in the left and center branches are the same. M5-M6 and M7-M8 form two pairs of current mirrors, directing the input current to the output in class AB fashion. The main advantage of this circuit is that it has an unlimited slew rate, allowing the input current to be larger than the bias current. A large I in flows into node X, M5 and M1 are turned off, and M4 and M7 absorb all the input current. Meanwhile, a large I in When the input current is low, M4 and M7 are turned off and M5 and M1 provide all the input current. For QuBRIM, node Y is V CM and the input current signal depends only on the voltages of the adjacent nodes. That is, node X is effectively grounded. I in and I out Note that although the directions of are opposite, the fully differential nature of QuBRIM may require the polarity of the outputs to be swapped in some embodiments.

[0109] As the name of the disclosed design suggests, the voltage signal of the capacitor of one node is quantized before being sent to the adjacent node. Since our system operates in a continuous-time manner, the quantizer 1402 can be simply constructed with two inverters connected in series. To increase the drive capability and reduce the delay, a fan-out design metric is adopted. As shown in Figure 14, M9 and M 10 forms the first inverter, and M 11 and M. 12 forms a second inverter having a larger aspect ratio than the first inverter.

[0110] Two pairs of switches (1403, 1404) are connected to two capacitors in one QuBRIM node to configure the initial spin of the system, after which the state of the machine is allowed to evolve in search of an energy minimum. Another function of these switches is to apply spin-fix perturbations. SF1 + and SF1 - are non-overlapping signals used to control S1 and S2, respectively, but due to differential operation, the same signals control S2 and S1, respectively, in the other half of the QuBRIM node circuit.

[0111] A detailed diagram of an exemplary coupling unit is shown in FIG. 15. For a one-way coupling design, node N i and N j Two separate coupling units (CUs) that connect the ij and C.U. ji The coupling coefficients in both directions are naturally the same (J ij =J ji ). As shown in different colors in Figure 13, each node has separate input and output terminals (two each for fully differential coupling). Similarly, each CU also has four input / output terminals, and as shown on the left side of Figure 15, a pair of coupling resistors (1501, 1503) connects input / output nodes of the same polarity (parallel coupling), and another pair of coupling resistors (1502, 1504) establishes anti-parallel coupling. The coupling coefficient (J ij ) depending on the polarity of S ij Only the resistor pairs controlled by V and their complements are turned on. The color scheme in Figure 15 matches the system level block diagram in Figure 13, where CS represents the column selector signal. On the right is an exemplary programmable coupled resistor implementation. Here, V ctr is the bias voltage.

[0112] For a fully connected network, the number of coupling units grows quadratically with the number of nodes, and it is expected that the coupling units will occupy the largest portion of the chip area. Therefore, it is impractical to implement the coupling elements as on-chip physical resistors, which tend to be area-large. Instead, in the disclosed embodiment, two p-type transistors connected back-to-back are used to form a pseudo resistor that shares similar I-V characteristics as a physical resistor, as shown on the right side of FIG. 15. The source-gate bias voltage (V ctr ) essentially sets the resistance of the pseudo resistors, which can be adjusted through the DAC. For example, to establish a negative (anti-parallel) coupling, the gates of the top right (1502) and bottom left (1504) pseudo resistors are tied to a non-zero voltage (V dac ) and bias the gates of 1501 and 1503 to 0V (GND).

[0113] One drawback of this implementation is that it offers only moderate linearity; as the terminal voltage exceeds a certain range, its resistance changes significantly, which can affect the machine's coupling accuracy and the quality of the overall solution. However, when used with QuBRIM, the magnitude of the terminal voltage of the pseudo resistor is always V dd / 2, making the pseudo resistor inherently linear. As can be seen from the schematic, one terminal of the pseudo resistor is always V CM =V dd The output of the quantizer is V DD or 0V, the terminal voltage of the pseudo resistor is ±V dd / 2.

[0114] Experimental Example The present invention will be described in more detail with reference to the following experimental examples.These examples are provided for illustrative purposes only, and are not intended to be limiting unless otherwise specified.Therefore, the present invention should not be construed as being limited to the following examples in any respect, but rather as embracing any and all variations that become evident as a result of the teachings provided herein.

[0115] Without further description, it is believed that one of ordinary skill in the art can, using the preceding description and the following illustrative examples, make and utilize the systems and methods of the present invention. Thus, the following examples specifically illustrate exemplary embodiments of the present invention, and are not to be construed as limiting in any way the remainder of the disclosure.

[0116] simulation We performed simulations using the disclosed design to evaluate its performance at both the circuit and behavioral levels. Due to its direct relationship to the Ising model, we adopted the max-cut problem as a benchmark. We first validated the design at the circuit level on small-scale graph problems, and then compared the performance between the disclosed design and other existing Ising machines on large-scale graphs.

[0117] Circuit Level Verification A 32-node QuBRIM was designed on a 45nm Generic Process Design Kit (GPDK) and simulated in the Virtuoso Analog Design Environment (ADE), both provided by Cadence. The test bench contained 20 fully connected graphs with binary weights. The optimal maximum cuts for these graphs are known. First, spin-fix annealing was disabled and each graph was simulated 100 times with different initial spin configurations. In the next simulation, spin-fix annealing was enabled. For a fair comparison, the same initial spin configuration was used, but different spin-fix sequences were applied in each run. Also, as explained above, the probability of spin-fix occurrence was set to decrease linearly over time.

[0118] The results show that regardless of whether spinfix annealing is on or off, the disclosed machine always ends up in a local minimum, which is as expected. We then used the distance to the best solution as a figure of merit and plotted these over time in Figure 16. As can be seen, the spinfix annealing technique significantly improves the quality of the solutions. Specifically, the probability of finding the best solution (distance 0) increases from 15.7% to 38.6%.

[0119] For non-best solutions, the average distance decreases from 8.09 to 3.75 after applying spin-fix annealing. Figure 16 shows a graph of the cumulative probability distribution of the distance from the best max-cut of the 32-node graph at a simulation time of 200 ns. Note that the best max-cut of the 32-node graph is found by enumerating and comparing all 232 possible solutions.

[0120] We also investigated the transient behavior of the system. We randomly selected a graph from the test bench above and captured the evolution of the Ising energy over time, as shown in the top graph in Figure 18. The top graph in Figure 18 shows the Ising energy versus time, and the bottom graph shows the transient voltages at each node. As shown in Figure 18, the machine reaches a local minimum at about 15 ns (dashed line), after which spin fix annealing is initiated (solid line). We can see that the Ising energy initially decreases rapidly and monotonically (spin fix annealing off), and then levels off as the machine settles into the local minimum. This is consistent with the bottom voltage waveforms where the nodes first interact and then enter a steady state a short time later (dashed line).

[0121] On the other hand, when spin fix annealing is enabled, the machine is busy exploring many regions of attraction in the energy landscape. Once it reaches the global minimum, the spin fix of a single or few nodes will temporarily increase the energy level, but it will be quickly brought back to the global minimum by the remaining nodes. This behavior can also be observed from the voltage waveform near the end of the annealing time.

[0122] Comparison with other Ising machines It is also worth comparing the disclosed design with other existing Ising machines. The following machines were evaluated:

[0123] 1) D-Wave: We used the latest quantum annealer, the 2000Q. Jobs were launched using the API provided by D-Wave. 50 samples were collected for each graph problem. Regarding timing, we did not specify any constraints and used D-Wave's default values. Specifically, these are 20 μs, 198 μs, 21 μs, and 11.7 ms for annealing, data readout, inter-sample delay, and qubit programming, respectively.

[0124] 2) OIM: An electronic oscillator-based Ising machine. For the simulation, we used the Kuramoto model based on the code provided by Wang et al. (2019).

[0125] 3) ASA: Refers to several related designs of accelerated simulated annealers. These accelerators use virtual spins and are easy to model based on descriptions in the literature. In the version used in this example, the nominal number of spins was 30,000. In this design, the connections followed a neighborhood pattern called the King graph. All nodes were grouped into groups of four. For each annealing step (0.22 μs), one node from a group is processed in parallel; that is, it reads the neighboring spins and associated weights and calculates whether keeping the same spin or flipping the current spin will result in a lower energy neighborhood. In addition, we also employed random bit flips similar to the standard simulated annealing algorithm.

[0126] Since most of the compared designs are based on behavioral models, we also created behavioral models of the disclosed designs to make a fair comparison. We generated small fully connected graphs with binary edge weights and node sizes ranging from 16 to 32 (in steps of 4). Each node size had 20 example graphs, for a total of 100 graphs. In these graphs, we enumerated all possible spin combinations to determine the actual maximum cut.

[0127] Figure 17 shows the quality of the solutions for the various systems in small graphs. All systems were tested with an annealing time of 20 μs (matching the annealing time of D-Wave). We obtained the best result out of 50 runs for each graph. Using these graphs, we verified that QuBRIM, OIM, and ASA are able to reach the ground state. D-Wave did not reach the ground state, and its best solution was at distance 6. Both ASA and QuBRIM are often able to achieve the ground state, but QuBRIM achieves the ground state with a higher probability (68%) than ASA (25%). Note that systems such as D-Wave and ASA are not all-to-all connected machines. Therefore, to fit a graph in these systems, it is necessary to preprocess the graph using a minor embedding algorithm. Preprocessing takes a significant amount of time, but we ignored this time when making the comparison.

[0128] Finally, to test scalability, we simulated the machine with an even larger graph. Again, we adopted a behavioral model due to the significant time it takes to simulate large graphs at the circuit level. We used the original Gset graphs from Stanford Ye, https: / / web.stanford.edu / ~yyye / yyye / Gset. These graphs have between 800 and 20,000 nodes. The edges and their weights are generated probabilistically, sometimes between +1 and -1, and sometimes all +1. QuBRIM was compared to ASA, which has unlimited nodes for mapping the problem, as well as classical Simulated Annealing (SA) algorithms. The entire test was run on a 2.9GHz Intel Xeon Platinum 8268 CPU with 371GB RAM and server cluster nodes. Table 2 below summarizes the benchmark results for Gsets with 1000 nodes or less. For QuBRIM, the distances ranged from 0 to 16, with an average of 5.45 and a median of 4. In contrast, ASA (1 ms) distances ranged from 0 to 42, with a mean of 15.1 and a median of 14. Furthermore, SA (2 seconds) distances ranged from 0 to 2, with a mean of 0.3 and a median of 0. Note that SA performed slightly better, but took six orders of magnitude longer than QuBRIM. Increasing the annealing time for QuBRIM improves quality, but is very costly to simulate. [Table 2]

[0129] Herein, we disclose a bistable resistively coupled Ising machine with quantized node interactions. Simulation results indeed demonstrate its ability to solve challenging computational problems such as the maximum cut problem. By using only simple building blocks, the disclosed topology becomes more scalable and cheaper compared to other desk-sized (or room-sized) Ising machines. With the help of spin-fix annealing, the performance of the disclosed machine is further improved. Not only is the probability of reaching the maximum cut increased by a factor of 2.6, but the quality of the solution is also significantly improved even when the global minimum is not reached.

[0130] The disclosures of each and every patent, patent application, and publication cited herein are incorporated herein by reference in their entirety. Although the present invention has been disclosed with reference to specific embodiments, it is apparent that other embodiments and variations of the present invention may be devised by those skilled in the art without departing from the true spirit and scope of the present invention. It is intended that the appended claims be construed to include all such embodiments and equivalent variations.

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Claims

1. A computing node, Input, Output, a bistable node having an input and an output, the output configured to have at least two balanced output voltages; a first buffer circuit having an input and an output, a buffer input coupled to the output of the bistable node and a buffer output coupled to the output of the computational node, the buffer circuit configured to provide a first output voltage when a voltage at the buffer input is below a threshold and to provide a second output voltage when the voltage at the buffer input is above the threshold; a current conveyor node having an input connected to the input of the computational node and an output connected to the input of the bistable node, the current conveyor configured to hold its input at a constant voltage and to mirror a current received at said input to the input of the bistable node; The computing node.

2. The computational node of claim 1 , wherein the first buffer circuit comprises an inverter.

3. The computing node, a second inverting output; and 2. The computational node of claim 1, further comprising: a second buffer circuit having an input connected to an inverting output of the bistable node, the inverting output of the bistable node being configured to have an inverse value of the output of the bistable node, the second buffer circuit further comprising an output connected to the second inverting output of the computational node.

4. The computational node of claim 3 , wherein the first buffer circuit and the second buffer circuit each include an inverter.

5. a second inverting input; and 2. The computational node of claim 1, further comprising: a second current conveyor node having an input connected to the second inverting input of the computational node and an output connected to a second input of the bistable node, the current conveyor configured to hold its input at a constant voltage and to mirror a current received at the input to the second input of the bistable node.

6. 2. The network of claim 1, further comprising a combining node connecting said output of said first computing node to said input of said second computing node.

7. The network of claim 6 , wherein the coupling nodes include resistors.

8. The network of claim 6 , wherein the coupling nodes include pseudo resistors.

9. A network of resistively coupled computational nodes, comprising: at least one computing node, each computing node comprising: Input, Output, a bistable node having an input and an output, the output configured to have at least two balanced output voltages; a first inverter having an input and an output, the input of the inverter being connected to the output of the bistable node and the output of the inverter being connected to the output of the computational node; a current conveyor node having an input connected to the input of the computational node and an output connected to the input of the bistable node; the at least one computing node comprising: a resistive coupling connected to the output of the computational node; The network comprising:

10. the at least one computing node includes a first and a second computing node; the input of the second computing node is connected to the input of the first computing node; The network of claim 9.

11. 11. The network of claim 10, wherein the output of the first computational node and the output of the second computational node are connected to a multiplication node configured to multiply the outputs and provide the multiplied output as a multiplication node output.

12. The network of claim 11 , wherein the multiplication nodes comprise exclusive NOR gates.

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