Integration of stacked nanosheets with FINFETs

Abstract

Integration of stacked nanosheets with FINFETs A semiconductor device including a first spacer positioned over a substrate, the first spacer having a first width in a first axis of the nanodevice, and at least one fin positioned over the first spacer, the at least one fin having a second width in the first axis of the nanodevice, where the second width is greater than the first width.

Description

[Technical field]

[0001] The present invention relates generally to the field of nanodevices, and more particularly to forming contacts and preventing shorting of contacts.

[0002] Nanosheets are the leading device architecture in continued CMOS scaling. However, nanosheet technology has proven problematic in fabricating contacts to buried power rails without shorting adjacent contacts. Summary of the Invention

[0003] Additional aspects and / or advantages will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

[0004] According to one aspect of the invention, a semiconductor device is provided, comprising: a first spacer located over a substrate and having a first width in a first axis of the nanodevice; and at least one fin located over the first spacer and having a second width in the first axis of the nanodevice, the second width being greater than the first width.

[0005] According to another aspect of the present invention, there is provided a semiconductor device comprising: a first nanodevice comprising a plurality of nanosheets located on a substrate, each of the plurality of nanosheets having a first width along a first axis; and a second nanodevice comprising at least one fin located on the substrate, the at least one fin having a second width along the first axis, the second width being greater than the first width.

[0006] According to another aspect of the invention, there is provided a method including forming alternating layers of sacrificial material and channel material overlying a substrate, a first sacrificial layer overlying the substrate; removing the first sacrificial layer to form a lower spacer overlying the substrate and below the alternating layers; etching the alternating layers and the lower spacer to a first width along a first axis; removing the alternating layers of sacrificial material; and epitaxially growing each layer of the alternating layers of channel material to merge the layers of the alternating layers of channel material to form a merged fin, the fin having a second width along the first axis, the second width being greater than the first width.

[0007] The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0008] [Figure 1] 1A and 1B are top views of one location including nano devices on a common substrate according to an embodiment of the present invention; [Diagram 2] FIG. 2 shows cross section A of a nanodevice according to an embodiment of the present invention. [Diagram 3] 3A and 3B show cross sections B1 and B2 of a nanodevice according to an embodiment of the present invention. [Figure 4] 1A and 1B show cross sections C1 and C2 of a nanodevice according to an embodiment of the present invention. [Diagram 5] FIG. 2A shows cross section A of a nanodevice after formation of a top spacer according to an embodiment of the present invention. [Figure 6] 3A and 3B show cross sections B1 and B2 of a nanodevice after formation of a bottom spacer according to an embodiment of the present invention. [Figure 7] 13A and 13B show cross sections C1 and C2 of a nanodevice after formation of top and bottom spacers according to an embodiment of the present invention. [Figure 8] 13A-13C show cross sections C1 and C2 of a nano device after patterning the nano-stacks and forming inner spacers according to an embodiment of the present invention. [Figure 9] FIG. 2A shows cross section A of a nano device after source / drain formation according to an embodiment of the present invention. [Figure 10] 3A and 3B show cross sections B1 and B2 of a nano-device after source / drain formation according to an embodiment of the present invention. [Figure 11] 13A and 13B show cross sections C1 and C2 of a nano-device after source / drain formation according to an embodiment of the present invention. [Figure 12] FIG. 2 shows a cross section B1 of a nanosheet device according to an embodiment of the present invention. [Figure 13] FIG. 2 shows a cross section C1 of a nanosheet device according to an embodiment of the present invention. [Figure 14] FIG. 2 shows cross section B2 of a Fin device after removing some layers according to an embodiment of the present invention. [Figure 15] FIG. 2 shows a cross section C2 of a Fin device after removing some layers according to an embodiment of the present invention. [Figure 16] FIG. 2 illustrates a cross section B2 of a Fin device after each layer has been epitaxially grown to form a layer in accordance with an embodiment of the present invention. [Figure 17] FIG. 2 shows a cross section C2 of a Fin device after each layer has been epitaxially grown to form a layer in accordance with an embodiment of the present invention. [Figure 18] FIG. 2 illustrates cross section B2 of a Fin device after formation of a gate according to an embodiment of the present invention. [Figure 19] FIG. 2 shows a cross section C2 of a Fin device after formation of a gate according to an embodiment of the present invention. [Figure 20] FIG. 2 shows a cross section B1 of a nanosheet device after formation of a gate according to an embodiment of the present invention. [Figure 21]FIG. 13 shows a cross section C1 of a nanosheet device after formation of a gate according to an embodiment of the present invention. [Figure 22] FIG. 2 illustrates cross section B2 of a Fin device after formation of a gate according to an embodiment of the present invention. [Diagram 23] FIG. 2 shows a cross section C2 of a Fin device after formation of a gate according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The following description, which refers to the accompanying drawings, is provided to aid in a comprehensive understanding of exemplary embodiments of the present invention defined by the claims and their equivalents. The following description includes various specific details to aid in its understanding, but these should be considered as merely exemplary. Thus, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of the present invention. In addition, descriptions of well-known functions or configurations may be omitted for clarity and conciseness.

[0010] The terms and words used in the following description and claims are not limited to their bibliographical meanings, but are merely used to enable a clear and consistent understanding of the present invention. Therefore, it should be clear to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustrative purposes only, and is not intended to limit the present invention defined by the appended claims and their equivalents.

[0011] The singular forms "a," "an," and "the" are understood to include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component surface" includes reference to one or more of such surfaces unless the context clearly dictates otherwise.

[0012] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it should be understood that the disclosed embodiments are merely examples of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0013] References herein to "one embodiment," "embodiment," "exemplary embodiment," and the like indicate that the embodiment being described may include a particular feature, structure, or characteristic, but that all embodiments may not include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0014] For purposes of the following description, the terms "above," "below," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, shall refer to the disclosed structures and methods as oriented in the drawing figures. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is on a second element, such as a second structure, and that an intervening element, such as an interface structure, may be between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0015] In order not to obscure the presentation of the embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for the purpose of presentation and illustration, and in some cases may not be described in detail. In other cases, some process steps or operations known in the art may not be described at all. It should be understood that the following description instead focuses on the distinctive features or elements of various embodiments of the present invention.

[0016] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternative embodiments may be devised without departing from the scope of the present invention. It should be noted that in the following description and drawings, various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are described. These connections and / or positional relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, the coupling of entities may refer to either direct or indirect coupling, and the positional relationship between entities may be a direct or indirect positional relationship. As an example of an indirect positional relationship, reference herein to forming layer "A" on layer "B" includes the situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", so long as the relevant properties and functionality of layer "A" and layer "B" are not substantially changed by the intermediate layer.

[0017] The following definitions and abbreviations are used for interpretation of the claims and the specification. As used herein, the terms "comprise," "comprising," "include," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements and can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or device.

[0018] Moreover, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" can be understood to include any integer number greater than or equal to one, i.e., 1, 2, 3, 4, etc. The term "multiple" can be understood to include any integer number greater than or equal to two, i.e., 2, 3, 4, 5, etc. The term "connected" can include both indirect and direct "connections."

[0019] As used herein, the term "about" to modify the amount of an ingredient, component, or reactant of the invention used refers to the variation in the numerical amount that may occur due to, for example, typical measuring procedures and liquid handling procedures used to make concentrates or solutions. Additionally, variation may result from inadvertent error in measuring procedures, differences in manufacture, source, or purity of ingredients used to make the composition or carry out the method, and the like. The term "about" or "substantially" is intended to include the degree of error associated with the measurement of a particular quantity based on equipment available at the time of filing of this application. For example, about can include a range of ±8% or 5% or 2% of a given value. In another embodiment, the term "about" means within 5% of the reported numerical value. In another embodiment, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

[0020] The various processes used to form microchips that are packaged into integrated circuits (ICs) fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from the wafer. Examples include etching processes (either wet or dry), reactive ion etching (RIE), and chemical mechanical planarization (CMP). Semiconductor doping is the modification of electrical properties, for example by doping the source and drain of a transistor, typically by diffusion or ion implantation or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate electrical components. By selectively doping various regions of a semiconductor substrate, the electrical conductivity of the substrate can be altered by the application of a voltage.

[0021] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, like reference numerals refer to like elements throughout. Stacked nanowires have been proposed for CMOS scaling due to their superior current capability. However, stacked nanowires are not beneficial for I / O devices such as thick oxides, as the oxide thickness is limited by the gap between the stacked nanowires. There are advantages to having both nanosheet devices and FIN devices on the same wafer, for example, FINFETs can be used as thick oxide devices. The present invention is directed to forming nanosheet devices and FINFETs on the same wafer, where the nanosheet devices and FINFETs are formed from a common set of starting layers. Fins are fabricated from nanosheets after sacrificial layers separating the nanosheets are removed. The spaces between the nanosheets are filled by epitaxially adding material to the nanosheets to form solid fins from the separate nanosheets. The width of the fin is greater than the width of the nanosheet. The height of the fin is greater than the height of the stacked nanosheets. The present invention allows for the formation of fins and nanosheets on a common substrate from a common starting layer. Additionally, the present invention allows for the formation of fins without removing layers, allowing for the deposition of new layers to form the fins.

[0022] 1A and 1B show top views of two locations containing nanodevices on a common substrate according to an embodiment of the present invention. FIG. 1A shows a completed nanosheet device and FIG. 1B shows a completed Fin device, where the nanosheet device and the Fin device are located on a common substrate 105. The Fin device and the nanosheet device are located at different points on the common substrate 105. The devices can be adjacent to each other, spaced apart, or with different devices located between them, or a combination thereof. Cross-section B of a nanodevice 1 and B. 2 is along the Y axis of the device. 1 and C 2is along the device's X axis.

[0023] FIG. 2 shows a cross section A of a nano device according to an embodiment of the present invention. Each of the nano devices (nanosheets / fins) has a common starting point including a substrate 105, a shallow trench insulating layer 110, a dummy gate 140, and a hard mask 145. The substrate 105 can be, for example, but not necessarily limited to, a material including silicon (Si), silicon germanium (SiGe), Si:C (carbon doped silicon), carbon doped silicon germanium (SiGe:C), III-V, II-V compound semiconductors, or another similar semiconductor. In addition, multiple layers of semiconductor material can be used as the semiconductor material of the substrate 105. In some embodiments, the substrate 105 includes both semiconductor and dielectric materials. The semiconductor substrate 105 can also include an organic semiconductor or a layered semiconductor, for example, Si / SiGe, silicon-on-insulator, or SiGe-on-insulator. A portion or the entirety of the semiconductor substrate 105 may be comprised of amorphous, polycrystalline, or single crystal. The semiconductor substrate 105 may be doped or undoped, or the semiconductor substrate may include doped and undoped regions. A shallow trench isolation layer 110 is located over the substrate 105. A dummy gate 140 is located over the shallow trench isolation layer 110. The dummy gate 140 may be comprised of, for example, amorphous Si or SiGe. A hard mask 145 is located over the dummy gate 140. The dummy gate 140 is etched into a desired pattern.

[0024] FIG. 3 is a cross-sectional view of a nanodevice according to an embodiment of the present invention. 1 and B. 2 FIG. 4 shows a cross-section of a nanodevice according to an embodiment of the present invention. 1 and C 21 shows a schematic diagram of a semiconductor device according to the present invention. Each of the nanodevices (nanosheets / fins) has a common starting point including a substrate 105, a shallow trench insulating layer 110, a nanostack 112, a dummy gate 140, and a hard mask 145. The nanostack 112 is comprised of multiple layers. The nanostack 112 includes a first sacrificial layer 115, a second layer 120, a third layer 125, a fourth layer 130, and a fifth layer 135. The number of layers shown is for illustrative purposes only. The first sacrificial layer 115 can be comprised of SiGe, for example, with Ge in the range of about 45%-70%. A second group of sacrificial layers includes the second layer 120 and the fourth layer 130. Each layer of the second group of sacrificial layers can be comprised of SiGe, for example, with Ge in the range of about 15%-35%. The third layer 125 and the fifth layer 135 are nanosheets made of, for example, Si. The nanostacks 112 are formed in a plurality of columns. The dummy gates 140 are located around the columns of the nanostacks 112 and are located on the shallow trench insulating layer 110. The hard mask 145 is located on the dummy gates 140.

[0025] 5 illustrates cross section A of a nano device after forming a top spacer 152 according to an embodiment of the present invention. The top spacer 152 is formed on the exposed surfaces of the shallow trench insulation layer 110, the dummy gate 140, and the hard mask 145. The top spacer 152 is etched back such that portions of the top spacer 152 remain along the sidewalls of the dummy gate 140 and the sidewalls of the hard mask 145.

[0026] FIG. 6 is a cross-section B of a nanodevice after formation of a bottom spacer according to an embodiment of the present invention. 1 and B. 2 7 shows the first sacrificial layer 115 selectively removed and replaced with a bottom spacer 150. FIG. 7 shows the top and bottom spacers 152, 154, 156, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 189, 190, 191, 192, 193, 194, 195 Cross section of the nanodevice after forming 150C 1 and C 27 illustrates another view showing the bottom spacer 150 of the nano-stack 112 and the top spacer 152 located adjacent the dummy gate 140 and the hard mask 145.

[0027] FIG. 8 shows a cross-section C of a nanodevice after patterning the nanostacks and forming inner spacers 155 according to an embodiment of the present invention. 1 and C 2 1 shows a cross-sectional view of a semiconductor device according to the present invention. The second layer 120, the third layer 125, the fourth layer 130, and the fifth layer 135 are etched based on the patterns of the top spacer 152, the dummy gate 140, and the hard mask 145. The second layer 120 and the fourth layer 130 are etched back to form a recess. The recess is filled with an inner spacer 155.

[0028] FIG. 9 shows cross section A of the nano device after formation of the source / drain 160 according to an embodiment of the present invention. The source / drain 160 is epitaxially grown on the shallow trench insulating layer 110 adjacent to the top spacer 152. The source / drain 160 can be, for example, n-type epitaxy or p-type epitaxy. For n-type epitaxy, an n-type dopant selected from the group of phosphorus (P), arsenic (As), or antimony (Sb), or a combination thereof, can be used. For p-type epitaxy, a p-type dopant selected from the group of boron (B), gallium (Ga), indium (In), or thallium (Tl), or a combination thereof, can be used. Other doping techniques can be used, such as ion implantation, gas phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid phase doping, solid phase doping, or any suitable combination of these techniques, or a combination thereof. In some embodiments, the dopants are activated by thermal annealing, such as laser annealing, flash annealing, rapid thermal annealing (RTA), or any suitable combination of these techniques.

[0029] FIG. 10 is a cross-section of a nanodevice after source / drain formation according to an embodiment of the present invention. 1 and B. 2 FIG. 11 shows a cross-section of a nanodevice after source / drain formation according to an embodiment of the present invention. 1 and C 2 1. The source / drain 160 is located above the lower spacer 150 and is adjacent to the sidewalls of the inner spacer 155, the third layer 125, and the fifth layer 135.

[0030] FIG. 12 is a cross-sectional view of a nanosheet device according to an embodiment of the present invention. 1 FIG. 13 shows a cross-section of a nanosheet device according to an embodiment of the present invention. 1 At this point, the processing of the nanosheet and fin devices diverges from the common processing steps. A first dielectric layer 165 is located above the source / drain 160. The first dielectric layer 165 is located adjacent to the top spacer 152.

[0031] FIG. 14 is a cross-sectional view of a Fin device after removing some layers in accordance with an embodiment of the present invention. 2 The second layer 120, the fourth layer 130, the dummy gate 140, and the hard mask 145 have been removed. FIG. 15 shows a cross section B of a Fin device after removing some layers according to an embodiment of the present invention. 2 The third layer 125 and the fifth layer 135 have a width W 1 At this stage, the width W of the fin section and the nanosheet section on the substrate 105 1 is the same. Height H 1 is the distance between the upper surface of the lower spacer 150 and the upper surface of the fifth layer 135. At this stage, the height H of the fin section and the nanosheet section on the substrate 105 1 At this point in the process, the nanosheet section has not undergone removal of the second layer 120, the fourth layer 130, the dummy gate 140, or the hard mask 145.

[0032] FIG. 16 shows a cross-sectional view of a Fin device after epitaxially growing each layer to form a layer in accordance with an embodiment of the present invention. 2 1 shows a top view of a semiconductor device according to the present invention. The third layer 125 and the fifth layer 135 are composed of, for example, Si. The third layer 125 and the fifth layer 135 are epitaxially grown to combine / merge the layers into a combined fin 170. The shape of the combined fin 170 is affected by the inner spacer 155, so if the inner spacer 155 is not removed, the combined fin 170 has a puzzle-piece shape. The puzzle-piece shape of the combined fin 170 has protruding and recessed regions, as highlighted by the dashed circle 172. If the inner spacer 155 is removed before the epitaxial growth step, the combined fin 170 does not have a puzzle shape (not shown). However, in both scenarios, the height of the top surface of the combined fin 170 is higher than the top surface of the fifth layer 135.

[0033] FIG. 17 shows a cross-section B of a Fin device after each layer has been epitaxially grown to form a layer in accordance with an embodiment of the present invention. 2 1. The materials of the third layer 125 and the fifth layer 135 are epitaxially grown to combine / merge the layers into a combined fin 170. The combined fin 170 has a width W 2 and height H 2 It has a width W 2 and height H 2 are the width W 1 and height H 1 Larger than width W 2 and height H 2 The reason why W becomes larger is because material is added to the width and height by epitaxially growing each layer. The width W of the nanosheet (i.e., the third layer 125 and the fifth layer 135) 1 is equal to the width of the lower spacer 150. The width W of the merged fin 170 2is greater than the width of the lower spacer 150. Thus, the merged fin 170 creates a gap or space between the bottom surface of the merged fin 170 and the top surface of the shallow trench isolation layer 110, as shown by dashed circle 177. This gap or space, i.e., dashed circle 177, allows material to be deposited under a portion of the merged fin 170 and adjacent to the lower spacer 150. Furthermore, the merged fin 170 does not have uniform / flat sidewalls. The epitaxial growth of the third layer 125 and the fifth layer 135 leaves a dip or recess in the sidewall after the layers are merged. Because the third layer 125 and the fifth layer 135 become wider as material is added and the layers are merged, a dip or recess as shown by dashed circle 175 is formed at the edges of the layers.

[0034] FIG. 18 is a cross-sectional view of a Fin device after formation of a gate 185 in accordance with an embodiment of the present invention. 2 1 shows a gate oxide liner 180 formed on the exposed surface of the coalesced fin 170. A gate 185 is formed on the gate oxide liner 180 between sections of the top spacer 152. The gate 185 may be formed of, for example, HfO 2 , ZrO 2 , HfL a O x The gate dielectric liner, such as a high-κ dielectric such as TiN, TiAlC, TiC, a work function layer, such as TiN, TiAlC, TiC, and a conductive metal filler, such as W. A gate cap 190 is formed on the gate 185 between the sections of the top spacer 152. In this embodiment, the gate 185 is formed on the fin section first and not on the nanosheet section. The gate 185 can be formed of different materials in the fin section and the nanosheet section because the gate 185 is not formed on the fin section and the nanosheet section at the same time. FIG. 18 shows that the merged fin 170 has a first shape along the X-axis of the fin nanodevice. It is also possible to form the gate 185 on the FINFET and the nanosheet at the same time, in which case the gate 185 will be the same between the FINFET and the nanosheet devices.

[0035] FIG. 19 illustrates a cross-section B of a Fin device after formation of a gate 185 in accordance with an embodiment of the present invention. 2 19 shows a schematic diagram of a semiconductor device according to the present invention. A gate oxide liner 180 is formed on the exposed surfaces (i.e., top, sidewall, and bottom) of the coalesced fins 170. A gate 185 is formed around the entire periphery of the gate oxide liner 180 to surround each of the coalesced fins 170. The gate 185 is in direct contact with the shallow trench insulation layer 110, the bottom spacer 150, and the gate oxide liner 180. The gate 185 is located below the bottom surface of the coalesced fins 170 at the location of the dashed circle 177. FIG. 19 shows that the coalesced fins 170 have a second shape along the Y-axis of the fin nanodevice. The first shape of the coalesced fins 170 as shown in FIG. 18 is different from the second shape of the coalesced fins 170 as shown in FIG. 19.

[0036] FIG. 20 is a cross-sectional view of a nanosheet device after formation of a gate 205 according to an embodiment of the present invention. 1 1 shows a gate 205 formed on the nanosheet device after the fin device according to one embodiment. The gate 205 is different from the gate 185 in this embodiment, but may be the same if the gates on the nanosheet and FINFET are formed simultaneously. The dummy gate 140, the hard mask 145, the second layer 120, and the fourth layer 130 are removed. A gate oxide liner 200 is formed on the exposed surfaces of the inner spacer 155, the bottom spacer 150, the third layer 125, the fifth layer 135, and the top spacer 152. The gate oxide liner 200 for the nanosheets is typically thinner than the gate oxide liner 180 for the FINFET. The gate 205 is formed of, for example, HfO 2 , ZrO 2 , HfL a O xThe gate dielectric liner, such as a high-κ dielectric such as ZnO, a work function layer such as TiN, TiAlC, TiC, and a conductive metal filler such as W. A gate cap 210 is formed on top of the gate 205 between sections of the top spacer 152. FIG. 21 shows a cross-section B of a nanosheet device after formation of the gate 205, according to an embodiment of the present invention. 1 1 shows a gate oxide liner 200 formed on the exposed surfaces of the shallow trench insulation layer 110, the bottom spacer 150, the third layer 125, and the fifth layer 135. A gate 205 is formed all around the perimeter of the nanosheet (third layer 125, fifth layer 135).

[0037] FIG. 22 is a cross-sectional view of a Fin device after formation of a gate 205, in accordance with an embodiment of the present invention. 2 18 and 22. A gate oxide liner 180 is formed on top of the merged fin 170 and along the sidewalls of the top spacer 152. A gate 205 is formed on top of the gate oxide liner 180, and a gate cap 210 is formed on top of the gate 205. The difference between the fin device shown by FIG. 18 and the fin device shown by FIG. 22 is that the gate 205 is located on top of the merged fin 170. The gate 205 can be composed of the same material in the nanosheet device and the fin device.

[0038] FIG. 23 is a cross-section B of a Fin device after formation of a gate in accordance with an embodiment of the present invention. 2 2 shows a schematic diagram of a gate oxide liner 180 formed on the exposed surfaces (i.e., top, sidewalls, and bottom) of the coalesced fins 170, the lower spacers 150, and the shallow trench isolation layer 110. A gate 205 is formed around the entire periphery of the gate oxide liner 180 to surround each of the coalesced fins 170. The gate 205 is located below the bottom surface of the coalesced fins 170 at the location of the dashed square 216.

[0039] Although the present invention has been shown and described with reference to specific exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail can be made therein without departing from the scope of the invention as defined by the appended claims and their equivalents.

[0040] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of one or more embodiments, practical applications or technical improvements to the technology found in the market, or to allow those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A semiconductor device comprising: a first spacer overlying the substrate and having a first width in a first axis of the nanodevice; at least one fin located on the first spacer and having a second width at the first axis of the nanodevice, the second width being greater than the first width; Semiconductor device.

2. a gate overlying the substrate and positioned around at least four surfaces of the at least one fin; The semiconductor device of claim 1 further comprising:

3. a gate overlying the substrate and below a bottom surface of the at least one fin; The semiconductor device of claim 1 , further comprising:

4. a liner positioned around the at least one fin in the first axis of the nanodevice; The semiconductor device of claim 3 , further comprising:

5. 5. The semiconductor device of claim 4, wherein the liner is in direct contact with the bottom surface of the at least one fin, and the gate is in direct contact with the liner underlying the bottom surface of the at least one fin.

6. The semiconductor device of claim 1 , wherein a sidewall surface of a sidewall of the at least one fin in the first axis of the nano-device is not uniform.

7. The semiconductor device of claim 5 , wherein the sidewall surface of the at least one fin includes a plurality of recesses.

8. 2. The semiconductor device of claim 1 , wherein the at least one fin has a first shape in the first axis of the nano device and the at least one fin has a second shape in a second axis of the nano device, the first shape and the second shape being different.

9. an internal spacer located within a recess of the at least one fin; The semiconductor device of claim 1 , further comprising:

10. a source / drain located along a second axis of the nanodevice adjacent a sidewall of the at least one fin and adjacent the inner spacer; 10. The semiconductor device of claim 9, further comprising:

11. 1. A semiconductor device comprising: a first nanodevice including a plurality of nanosheets located on a substrate, each of the plurality of nanosheets having a first width along a first axis; a second nanodevice including at least one fin located on the substrate, the at least one fin having a second width along the first axis, the second width being greater than the first width; Semiconductor device.

12. a first spacer overlying the substrate, the first spacer having a third width along a first axis, the second width being greater than the third width and the third width being substantially equal to the first width; The semiconductor device of claim 11 further comprising:

13. a first gate overlying the substrate, the first gate being positioned around at least four surfaces of the at least one fin and constructed from a first material; a second gate overlying the substrate, the second gate being disposed around the plurality of nanosheets and constructed from a second material; The semiconductor device of claim 11 further comprising:

14. a liner positioned about the at least one fin in the first axis; The semiconductor device of claim 12 further comprising:

15. 15. The semiconductor device of claim 14, wherein the liner is in direct contact with a bottom surface of the at least one fin, and the first gate is in direct contact with the liner underlying the bottom surface of the at least one fin.

16. 12. The semiconductor device of claim 11, wherein a sidewall surface of a sidewall of the at least one fin in the first axis is not uniform, the sidewall surface of the at least one fin including a plurality of recesses.

17. 12. The semiconductor device of claim 11, wherein the at least one fin has a first shape in the first axis and the at least one fin has a second shape in a second axis, the first shape and the second shape being different.

18. 1. A method comprising: forming alternating layers of sacrificial material and channel material overlying a substrate, a first sacrificial layer overlying the substrate; removing the first sacrificial layer to form a bottom spacer above the substrate and below the alternating layers; Etching the alternating layers and the bottom spacer to a first width along a first axis; removing the alternating layers of the sacrificial material; and epitaxially growing each layer of the alternating layers of the channel material to merge the layers of the alternating layers of the channel material to form a merged fin, the fin having a second width along the first axis, the second width being greater than the first width; A method comprising:

19. forming a liner positioned about the merged fin at the first axis; 20. The method of claim 18, further comprising:

20. forming a gate around the liner, the liner in direct contact with a bottom surface of the at least one fin, the gate in direct contact with the liner underlying the bottom surface of the at least one fin; 20. The method of claim 19, further comprising:

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