Datapath circuits and methods

Abstract

In one embodiment, a memory circuit includes a memory, N latch circuits coupled in parallel, a data multiplexer, a logic circuit, and a data path. The memory array is configured to provide read data to a first data bus, and each latch circuit is configured to store the read data from the first data bus. The data multiplexer has N data inputs respectively coupled to data outputs of the N latch circuits, and is configured to select one data input of the N data inputs of the data multiplexer to connect to a data output of the data multiplexer based on a select input of the data multiplexer. The data path is configured to cause propagation of data from the data output of the data multiplexer to the data input of the logic circuit.

Description

Technical Field

[0001] Cross-Reference to Related Applications This application claims the benefit of U.S. Patent Application No. 17 / 833,562, filed June 6, 2022, which claims the priority benefit of U.S. Provisional Application No. 63 / 311,596, filed February 18, 2022, all of which are hereby incorporated by reference into the present specification.

[0002] The present disclosure generally relates to electronic systems and methods, and in certain embodiments, to data path circuits and methods.

Background Art

[0003] FIG. 1 is a schematic diagram of an exemplary memory circuit 100. The memory circuit 100 includes a memory controller 102, a read control circuit 104, a memory array 106, a latch control circuit 108, a latch circuit 110, a data path 112, and a logic circuit 114.

[0004] Conventional memory read operations are initiated by read commands and executed synchronously. For example, FIG. 2 shows an exemplary waveform 200 associated with the memory circuit 100 during a burst read operation. FIG. 1 and FIG. 2 can be understood in conjunction with each other.

[0005] When the memory controller 102 receives a read command, a read operation is initiated to read data from the memory array 106 and output such data at the output of the logic circuit 114. For example, as shown in FIG. 2, in response to receiving a first read command, the signal RD_EN is pulsed, whereby the signal RD_CR initiates an analog data sensing process from the memory array 106 based on the cell address decoded from the received read command. After the analog data sensing process is completed, the sensed data is latched into the latch circuit 110 in response to the assertion of the signal RD_LAT. After the sensed data is latched into the latch circuit 110, the sensed data is transmitted as data D 110becomes available as, and propagates to logic circuit 114 through data path 112. Data D 110 is captured (e.g., latched) by the logic circuit 114 in response to assertion of signal RDB_LATCH, and then outputs the latched data as output data D out to an external circuit.

[0006] Since the propagation delay of data path 112 may not be negligible, data D 110 is synchronously captured (e.g., latched) by the logic circuit 114 after a certain number of clock pulses from the start of a read command, and the certain number of clock pulses is sufficient to accommodate the propagation delay of data path 112 when the memory circuit 100 operates at the maximum rated frequency. In the example shown in Figure 2, the signal RDB_LATCH is asserted 16 clock pulses after the start of reception of an associated read command. Summary of the Invention Means for Solving the Problems

[0007] According to one embodiment, the memory circuit includes a memory array configured to provide read data to a first data bus; N latch circuits coupled in parallel, each of the N latch circuits having a data input and a latch input, where N is a positive integer of 2 or more, and each latch circuit is configured to be coupled to the first data bus and to store read data from the first data bus; a data multiplexer having a data output, N data inputs coupled to the data outputs of the N latch circuits, and a selection input, configured to select one of the N data inputs of the data multiplexer and connect it to the data output of the data multiplexer based on the selection input of the data multiplexer; a logic circuit having a data input and a data output; and a data path coupled between the data output of the data multiplexer and the data input of the logic circuit, configured to cause the propagation of data from the data output of the data multiplexer to the data input of the logic circuit.

[0008] According to one embodiment, the method is to receive a first read command, to detect first data from a memory array based on the first read command, to provide the detected first data to a first data bus, to assert a first latch signal a certain period after receiving the first read command, and to latch the detected first data from the first data bus to one of N latch circuits in response to the assertion of the first latch signal, wherein the N latch circuits are connected in parallel, each of the N latch circuits has a data input connected to the first data bus, N is a positive integer of 2 or more, and the output of one latch circuit is connected to the data input of a logic circuit via a data path. This includes propagating a force, asserting an output latch signal a first time after receiving a first read command to latch the detected first data from one latch circuit to a logic circuit, receiving a second read command, detecting second data from a memory array based on the second read command, selecting the next latch circuit from N latch circuits, latching the detected second data to the next latch circuit, propagating the output of the next latch circuit to the data input of a logic circuit via a data path, and asserting an output latch signal a second time after receiving a second read command to latch the detected second data from the next latch circuit to a logic circuit.

[0009] According to one embodiment, the memory circuit includes a memory array configured to provide read data to a first data bus, a controller configured to receive read commands and clock signals and to assert an output latch signal after a predetermined number of clock pulses of the clock signal from the reception of the read command, and further configured to provide a memory address to the memory array based on the read command, a read control circuit configured to assert a first read signal in response to a read command to cause the memory array to provide read data to the first data bus based on the memory address, and to assert a first latch signal a certain period of time after asserting the first read signal, wherein the certain period of time is asynchronous with respect to the clock signal, and N latch circuits coupled in parallel, each of the N latch circuits having a data input and a latch input coupled to the first data bus, and N being a positive integer of 2 or more, and from the read control circuit A latch control circuit configured to receive a latch signal 1 and provide the respective latch signal to the latch input of each of the N latch circuits, wherein the latch control circuit is configured to cause data to latch in one of the N latch circuits in response to the assertion of a first latch signal by asserting each output latch signal; a data multiplexer having a data output, N data inputs coupled to the data outputs of the N latch circuits, and a selection input, wherein the data multiplexer is configured to select one of the N data inputs of the data multiplexer based on the selection input of the data multiplexer and connect it to the data output of the data multiplexer; a data path having a data input coupled to the data output of the data multiplexer; and a logic circuit having a data output and a data input coupled to the data output of the data path, wherein the logic circuit is configured to latch data at the data input of the logic circuit when an output latch signal is asserted.

[0010] For a more complete understanding of the present invention and its advantages, please refer here to the following description in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0011] [Figure 1] A schematic diagram of an exemplary memory circuit is shown. [Figure 2] Figure 1 shows an example waveform related to the memory circuit. [Figure 3] Figure 1 shows an example waveform related to the memory circuit. [Figure 4] Figure 1 shows an example waveform related to the memory circuit at a clock frequency lower than that of Figure 3. [Figure 5] This is a schematic diagram of a memory circuit according to one embodiment of the present invention. [Figure 6] The waveforms related to the memory circuit in Figure 5 during burst read operation according to one embodiment of the present invention are shown. [Figure 7] The waveforms related to the memory circuit in Figure 5 during burst read operation according to one embodiment of the present invention are shown. [Figure 8] A schematic diagram of a memory circuit according to one embodiment of the present invention is shown. [Figure 9] A flowchart of one embodiment of a method for controlling a latch circuit and associated data multiplexer (MUX) according to one embodiment of the present invention is shown. [Modes for carrying out the invention]

[0012] Corresponding numbers and symbols in different figures generally refer to the corresponding parts unless otherwise specified. The drawings are drawn to clearly illustrate relevant aspects of preferred embodiments and are not necessarily drawn to scale.

[0013] The configuration and use of the disclosed embodiments are described in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific situations. The specific embodiments described are merely illustrative of specific ways of configuring and using the present invention and do not limit the scope of the invention.

[0014] The following description provides various specific details to give a detailed understanding of some exemplary embodiments described herein. Embodiments may be obtained without using one or more of the specific details, or by using other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so as not to obscure different aspects of the embodiments. References to “embodiments” in this specification indicate that a particular configuration, structure, or feature described in relation to an embodiment is included in at least one embodiment. Thus, phrases such as “in one embodiment,” which may appear in different parts of this specification, do not necessarily refer to the exact same embodiment. Furthermore, particular configurations, structures, or features may be combined in any suitable manner in one or more embodiments.

[0015] Embodiments of the present invention are described in a specific context, for example, a data path circuit with a wide frequency range using a multi-channel data multiplexer (MUX) in a flash memory device, and related methods for performing read operations within a flash memory device. Embodiments of the present invention may be used in other types of memory devices, such as other types of non-volatile memory devices and volatile memory devices. Some embodiments may be used in data paths of other types of devices (e.g., microcontrollers, processors, etc.) that include internal memory such as an internal data array. Some embodiments may be used for other types of operations, such as write operations.

[0016] In one embodiment of the present invention, the memory circuit comprises a plurality of parallel latch circuits used for temporarily holding data read from a memory array before propagation of such data via a data path towards an output terminal of the memory circuit. The latch circuits are updated in a round-robin manner by data read from the memory array. A MUX selects which latch circuit provides an output to the data path in the round-robin manner. By using parallel latch circuits to temporarily hold data, some embodiments advantageously achieve a lower minimum operating frequency without affecting the delay between the output of the memory array and the output terminal of the memory circuit, thereby advantageously achieving a wider operating frequency range without affecting the maximum operating frequency of the memory array.

[0017] Figure 3 shows an exemplary waveform 200 with additional labels. As shown in Figure 3, during a burst read operation, read commands are received periodically (e.g., every 8 clock pulses). A period T between assertion of the signal RD_CR and assertion of the signal RD_LAT RD is based on the sense time of a sense amplifier (not shown) associated with sensing or reading data from the memory array 106 to generate corresponding data D 106 . For example, the latch controller 108 can assert the signal RD_LAT after a fixed period T RD from assertion of the signal RD_CR, and the fixed period T RD is sufficiently long to allow the analog data sensing process to generate data D 106 from the memory array 106 based on the received read command.

[0018] Assuming that read commands are received sequentially during burst read operation, the contents of the latch circuit 110 are periodically updated in response to the periodic assertion of the signal RD_LAT. Therefore, as shown in Figure 3, the memory controller 102 asserts the signal RDB_LATCH after a certain number of clock pulses (e.g., 16) from the start of receiving the relevant read command, and this certain number of pulses is used to assert the data D associated with the corresponding read command. 110 However, it is designed to occur during a period in which it remains valid. For example, as shown in Figure 3, the signal RDB_LATCH is first asserted during clock pulse 17 (which occurs before the signal RD_LAT is asserted in response to the reception of a second read command), thereby enabling the data D associated with the first read command (received between clock pulses 1 and 4) to be asserted. 110 It will be imported correctly.

[0019] As shown in Figure 3, during burst read operation, output data D out This is the first D, which is the data associated with the first RD command. 110 , the second D is data associated with the second RD command 110 It correctly generates things like these.

[0020] When the frequency of the clock signal CLK of the memory circuit 100 is reduced, the output data D out This could be damaged. For example, Figure 4 shows an example waveform 400 at a clock frequency lower than waveform 200.

[0021] As shown in Figure 4, the clock signal CLK has a lower frequency in waveform 400 than in waveform 200, and during period T RD Since it is fixed, the first assertion of the signal RD_LAT in waveform 400 occurs asynchronously between clock pulses 6 and 7, in contrast to the asynchronous assertion around clock pulse 10 in waveform 200. The same behavior occurs each time the signal RD_LAT is asserted.

[0022] The assertion of the signal RDB_LATCH occurs at a fixed clock pulse interval (clock pulse 17 in the waveform 200 and 400 examples), therefore the data (first D 110 The first assertion of the signal RDB_LATCH, which attempts to capture the data (the first D 110 ) is no longer available, and incorrect data (the second D associated with the second RD command) 110 This occurs when ) is latched to logic circuit 114. As a result, output data D out This is the data associated with the first RD command (the first D 110 It is destroyed because it does not contain ).

[0023] As shown in Figures 3 and 4, the memory circuit 100 stores undamaged output data D out It has a relatively narrow operating frequency range for generating [the specified signal].

[0024] In one embodiment of the present invention, the memory circuit achieves a wide operating frequency by using multiple parallel latch circuits to temporarily hold data read from the memory array before it propagates through the data path. The latch circuits are updated in a round-robin manner by the data read from the memory array. The MUX selects which latch circuit provides output to the data path in a round-robin manner. When the signal RDB_LATCH is asserted, or thereafter, the MUX is updated to output data from the next latch circuit, thereby advantageously providing output D OUT The data is delivered in the same order in which it was read.

[0025] Figure 5 shows a schematic diagram of a memory circuit 500 according to one embodiment of the present invention. The memory circuit 500 includes a memory controller 502, a read control circuit 504, a memory array 506, a latch control circuit 508, a latch circuit 510, a MUX 511, a data path 512, and a logic circuit 514.

[0026] In some embodiments, the memory circuit 500 is a flash memory circuit, such as a NAND flash memory circuit or a NOR flash memory circuit. In some embodiments, the memory circuit 500 may be implemented using other non-volatile memory technologies. In some embodiments, the memory circuit 500 may be a volatile memory circuit.

[0027] In some embodiments, the memory circuit 500 is implemented within a single IC, which may include one die or multiple dies. In some embodiments, the memory circuit 500 may be implemented using multiple ICs.

[0028] In some embodiments, the memory circuit 500 is designed to operate over a wide frequency range. For example, in some embodiments, the operating frequency of the clock signal CLK may be in the range of 533MHz to 800MHz. Other frequency ranges can also be used, such as a maximum operating frequency higher than 800MHz (e.g., 820MHz, 900MHz, 2GHz or higher) or lower than 800MHz (e.g., 600MHz, 50MHz or lower), and a minimum operating frequency higher than 533MHz (e.g., 600MHz, 1GHz or higher) or lower than 533MHz (e.g., 200MHz, 10MHz or lower).

[0029] In some embodiments, the memory circuit 500 includes multiple modes with different frequency ranges. For example, in a first mode, the clock signal CLK may be in the range of 0MHz to 266MHz; in a second mode, the clock signal CLK may be in the range of 266MHz to 533MHz; in a third mode, the clock signal CLK may be in the range of 533MHz to 800MHz; and in a fourth mode, the clock signal CLK may be in the range of 533MHz to 820MHz. As another example, in some embodiments, in a first mode, the clock signal CLK may be in the range of 800MHz to 1066MHz; in a second mode, the clock signal CLK may be in the range of 1066MHz to 1333MHz; and in a third mode, the clock signal CLK may be in the range of 1333MHz to 1600MHz. Other implementations are also possible.

[0030] In some embodiments, the memory controller 502 is configured to cause the memory array 506 to perform memory operations (e.g., read, write) based on commands received, for example, from an external circuit. For example, in some embodiments, the memory controller 502 receives a read command (e.g., from an external controller), and in response reads the requested data from the memory array 506 and outputs the requested data to output D out It is provided as (for example, to an external controller).

[0031] In some embodiments, the memory controller 502 is compatible and operates according to known communication protocols such as the serial peripheral interface (SPI) and low power double data rate 4 (LPDDR4). In some embodiments, the memory controller 502 is not compliant with and / or incompatible with known communication protocols.

[0032] In some embodiments, the memory controller 502 includes an address control circuit (not shown) configured to generate a decoded memory cell address based on a received read command.

[0033] In some embodiments, the memory controller 502 may be implemented as a general-purpose or custom controller or processor configured to be coupled to memory and execute instructions from memory. In some embodiments, the memory controller 502 may include a finite state machine (FSM). Other implementations are also possible.

[0034] In some embodiments, the memory array 506 is configured to store data. In some embodiments, the memory array 506 may be implemented using flash memory, such as NOR flash or NAND flash. Other implementations are also possible, for example, using volatile memory or non-flash memory.

[0035] In some embodiments, a sense amplifier or sense circuit (not shown) associated with the memory array 506 detects the state of the memory cells of the memory array 506 and records such state as data on the data bus D 506 It is used to provide to the data bus D. In one embodiment, the sense circuit may be part of the memory array 506. In some embodiments, its output is to the data bus D. 506 Multiple latches (not shown) can be used at the output of the sense amplifier to temporarily store the sensed data, which can advantageously enable the sense amplifier to be multiplexed to sense the data. In some embodiments, the data bus D 506 This is a parallel bus containing tens or hundreds of lines, for example, more than 100 data lines, for example, 300 data lines.

[0036] In some embodiments, the read control circuit 504 is configured to trigger a read operation to read data from the memory array 506. For example, in some embodiments, the read control circuit 504 asserts the signal RD_CR (for example, in response to the assertion or pulsation of the signal RD_EN). When the signal RD_CR is asserted, the memory array initiates a read operation (for example, using a sense amplifier in a known way) to read a memory cell corresponding to a decoded memory cell address received from the memory controller 502. (For example, a predetermined constant) period (e.g., T) RD ) After that, the read control circuit 504 asserts the signal RD_LAT and uses the latch control circuit 508 to detect data D 506 This is latched into one of the latches 510.

[0037] In some embodiments, the read control circuit 504 includes digital circuitry and may be implemented using an FSM. Other implementations are also possible. In some embodiments, the read control circuit 504 is implemented as part of the memory controller 502.

[0038] In some embodiments, the latch 510 responds to the assertion of the signal RD_LAT to the data bus D 506 It is configured to store data from. As shown in Figure 5, in some embodiments, the latch 510 includes two latches 5101 and 5102. As will be described in more detail below, in some embodiments, the latch 510 may include three or more latches, for example, n latches, where n is an integer greater than 2, such as 3, 5, 10, or more.

[0039] In some embodiments, the latch control circuit 508 responds to an assertion of the signal RD_LAT by using signals LAT1 and LAT2 to either of the latches 510 (e.g., 5101 or 5102) on the data bus D 506It is configured to select which of the latches 510 to take data from. In some embodiments, the latch control circuit 508 also uses the signal SEL to select which of the latches 510 is on the data bus D. 511 Choose whether to propagate to [other locations].

[0040] In some embodiments, the latch control circuit 508 is implemented using digital circuits such as combinational logic.

[0041] In some embodiments, the MUX511 is configured to select which data is transferred to the data path 512 based on the signal SEL. The MUX511 may be implemented in any manner known in the art.

[0042] In some embodiments, the data path 512 includes circuits such as buffer circuits for routing data from the output of the MUX 511 (which may be physically located near the memory array 506) to the logic circuit 514 (which may be physically located near the output of the memory circuit 500, such as an I / O pin). The data path 512 may be implemented in any way known in the art.

[0043] In some embodiments, the memory circuit 500 includes, for example, multiple memory arrays 506 implemented in each memory bank, and bank selection can be controlled using a bank address bus (for example, read commands). In some such embodiments, a data path 512 can receive data from multiple memory banks (for example, via each MUX 511).

[0044] In some embodiments, the logic circuit 514 responds to the assertion of the signal RDB_LATCH to the data bus D 511 Data is imported from and such imported data is output to D out It is configured to be provided as such. In some embodiments, the logic circuit 514 is implemented using digital circuits such as combinational logic.

[0045] Figures 6 and 7 show waveforms 600 and 700, respectively, associated with the memory circuit 500 during burst read operation according to one embodiment of the present invention. Waveform 600 has the same clock frequency as waveform 200. Waveform 700 has the same clock frequency as waveform 400. Figures 5 to 7 can be understood together.

[0046] When the memory controller 502 receives a read command, it provides the memory array 506 with the decoded cell address (based on the received read command) and triggers the reading of data from the memory array 506 by asserting the signal RD_EN. The read control circuit 504 asserts the signal RD_CR in response to the pulsation of the signal RD_EN and for a period T RD An internal timer (not shown) designed to assert the signal RD_LAT afterwards is started.

[0047] In response to the assertion of signal RD_CR, data is conventionally read from the memory cells of the memory array 506 at an address based on the decoded cell address provided by the memory controller 502, using a sense amplifier (not shown). The read data is then sent to the data bus D once the data sensing process (performed by the sense amplifier) ​​is complete. 506 It is supplied to.

[0048] The readout control circuit 504 determines the period T from the assertion of the signal RD_CR. RD The signal RD_LAT is asserted when the internal timer expires, which occurs later. In some embodiments, period T RD This period is sufficient to allow the data detection process to terminate. As shown in Figures 6 and 7, in some embodiments, the period T is sufficient. RDThis is independent of the clock signal CLK. For example, at the first (faster) clock frequency of the clock signal CLK, the assertion of signal RD_LAT occurs approximately 7 clock pulses after the assertion of signal RD_CR, as shown in Figure 6. At the second (slower) clock frequency of the clock signal CLK, the assertion of signal RD_LAT occurs approximately 3 clock pulses after the assertion of signal RD_CR.

[0049] In response to the signal RD_LAT being asserted by the read control circuit 504 when the internal timer expires, the latch control circuit 508 asserts either signal LAT1 or LAT2 to access the data bus D 506 The data in is latched to either latch 5101 or 5102. For example, as shown in Figures 6 and 7, in response to the assertion of signal RD_LAT, the latch control circuit 508 asserts signal LAT1 to latch the data D corresponding to odd-numbered read commands (first RD command, third RD command, etc.). 506 The signal LAT2 is asserted by latching it to latch 5101, and data D corresponding to even-numbered read commands (second RD command, fourth RD command, etc.) is retrieved. 506 It latches into latch 5102.

[0050] As shown in Figures 6 and 7, the latch control circuit 508 also transitions the signal SEL (for example, in a round-robin manner) when asserting the signal RDB_LATCH or after asserting it, from the latch 510 to the data bus D 511 Propagation of read data to (for example, data bus D 506 This triggers (in the same order that data is latched).

[0051] After a certain number of clock pulses following the assertion of signal RD_EN (for example, 13 clock pulses after signal RD_EN is asserted, as shown in Figures 6 and 7), the memory controller 502 asserts signal RDB_LATCH to the logic circuit 514 and transmits data bus D 511The data from is latched. In some embodiments, a certain number of clock pulses (e.g., 13 in the embodiments of Figures 6 and 7) between the assertion of the signal RD_EN and the assertion of the signal RDB_LATCH are designed to allow sufficient time for the data to propagate from the output of the memory array 506 through the data path 512 to the logic circuit 514.

[0052] As shown in Figures 5 to 7, some embodiments are advantageous in that output data D out It is possible to operate at a low operating frequency while avoiding damage to the device. For example, in the examples in Figures 6 and 7, in response to the reception of a first read command (first RD), the first data (first D 506 ) is detected from memory array 506, data bus D 506 Provided to: When the latch signal RD_LAT is asserted, the latch signal LAT1 is asserted, and the first data (the first D 506 The first data (the first D) is latched into latch 5101. When signal SEL is low, the output of latch 5101 flows through MUX 511 and data path 512. When the output latch signal RDB_LATCH is asserted, the first data (the first D) is released from latch 5101. 506 ) is latched in logic circuit 514. In response to the reception of the second read command (second RD), the second data (second D 506 ) is detected from memory array 506, data bus D 506 It is then provided to the second data (second D). Subsequently, when the latch signal RD_LAT is asserted, the latch signal LAT2 is asserted, thereby providing the second data (second D 506 The second data (second D) is latched into latch 5102. When signal SEL is high, the output of latch 5102 flows through MUX 511 and data path 512. When the output latch signal RDB_LATCH is subsequently asserted, the second data (second D) is latched into latch 5102. 506 ) is latched into logic circuit 514.

[0053] As shown in Figures 6 and 7, by using multiple parallel latches (e.g., 510) that are selectively latched asynchronously with data from a memory array (e.g., 506), some embodiments advantageously achieve lower minimum operating frequencies without affecting the maximum operating frequency, thereby exhibiting a wider operating frequency range compared to solutions that rely on multiple serial latches, such as those implemented in conventional FIFO buffers.

[0054] In some embodiments, as shown in Figure 5, two parallel latches (5101 and 5102) are used, and the addition of the second latch halves the minimum operating frequency of the memory circuit 500 (thus doubling the operating frequency range of the memory circuit 500). In some embodiments, three or more parallel latches can be used to further reduce the minimum operating frequency. For example, Figure 8 shows a schematic diagram of a memory circuit 800 according to one embodiment of the present invention.

[0055] As shown in Figure 8, the memory circuit 800 includes N latches 510, where N is a positive integer greater than or equal to 2. The memory circuit 500 is a possible embodiment of the memory circuit 800 where N is equal to 2.

[0056] In some embodiments, when N is equal to 2, the memory circuit 800 operates as the memory circuit 500, the MUX 811 operates as the MUX 511, and the latch control circuit 808 operates as the latch control circuit 508.

[0057] More generally, (if N is 2 or greater,) the latch control circuit 808 is on the data bus D 506 The data in is latched from 5101 to 510 N To latch one of them, signal LAT1~LAT N It is configured to assert one of the signals LAT1 to LAT. For example, in some embodiments, in response to the assertion of the signal RD_LAT, the latch control circuit 808 asserts the signals LAT1 to LAT N Assert one of the following (for example, selected using a round-robin method) and select Data D 506This is latched into the corresponding latch 5101.

[0058] The latch control circuit 808 also transitions the signal SEL (for example, in a round-robin manner) when asserting the signal RDB_LATCH or after asserting it, from the latch 510 to the data bus D 811 Propagation of read data to (for example, data bus D 506 This triggers (in the same order that data is latched) from the signal RDB_LATCH. For example, in some embodiments, the latch control circuit 808 asserts the signal RDB_LATCH and the signal LAT i Assertion and home of Whichever is newer According to the event, signal SEL transitions to the next latch 510. i Select i, where i is a number between 1 and N (i=1 corresponds to latch 5101, i=2 corresponds to latch 5102, i=N corresponds to latch 510 N (corresponding to ). In some embodiments, i may be increased sequentially in a round-robin manner.

[0059] For example, when signal SEL is equal to 0 (selecting the output of latch circuit 5101), the next latch circuit to be selected is 5102, and i is equal to 2. Thus, in some embodiments, the transition of signal SEL from 0 to 1 is between the assertion of RDB_LATCH and the assertion of signal LAT2, as shown in Figures 6 and 7. home of Whichever is newer Occurs according to the event. Signal SEL is equal to N-1 (latch circuit 510) N When selecting the output of , the next latch circuit to be selected is 5101, where i is equal to 1. Thus, in some embodiments, the transition of signal SEL from N-1 to 0 is between the assertion of RDB_LATCH and the assertion of signal LAT1. home of Whichever is newer It occurs according to the event.

[0060] For example, in some embodiments, the signal SEL may be updated according to the following: If SEL=0, RDB_LATCH and LAT1 home of Whichever is newer This assertion causes SEL to transition to 1. If SEL=1, RDB_LATCH and LAT2 home of Whichever is newer With this assertion, SEL transitions to 2. If SEL=N-1, RDB_LATCH and LAT N to home of Whichever is newer This assertion causes SEL to transition to 0.

[0061] Therefore, in the case of N=2, in some embodiments, the signal SEL may be updated according to the following: If SEL=0, RDB_LATCH and LAT1 home of Whichever is newer This assertion causes SEL to transition to 1. If SEL=1, SEL is the relationship between RDB_LATCH and LAT2. home of Whichever is newer The assertion transitions to 0, and signals LAT1 and LAT2 are asserted alternately in response to the assertion of signal RD_LAT.

[0062] Figure 9 shows a flowchart of Method 900 of an embodiment for controlling the latch circuit 510 and MUX811 according to one embodiment of the present invention. Method 900 includes steps 901 and 911. Step 901 responds to the assertion of the signal RD_LAT to determine which signal LAT j Step 900 is performed to determine whether to assert and includes steps 902, 904, 906, and 908. Step 911 is performed to determine when to update the signal SEL and includes steps 912, 914, 916, 918, and 920. Method 900 can be implemented by the latch control circuit 808.

[0063] As shown in steps 902, 904 and 906, j is updated in a round-robin manner, and the signal LAT jDuring step 908, for example, the assertion of signal RD_CR is performed from T RD It will be asserted after the specified period (using a round-robin method).

[0064] As shown by steps 912, 914 and 916, i is updated in a round-robin manner and determined during step 918, so that the signal LAT i When both RDB_LATCH and RDB_LATCH are asserted in the current round-robin cycle, the signal SEL is updated (in a round-robin manner) during step 920.

[0065] Signal LAT i Assertion and RDB_LATCH home of Whichever is newer In some embodiments, by updating the signal SEL in the event, the signal LAT i Before the transition, the power consumption and noise that may arise from the transition of the signal SEL are advantageously reduced. However, in some embodiments, step 918 is (for example, the signal LAT i Regardless of the state, the RDB_LATCH signal may be modified to output "yes" when asserted, which may, advantageously, result in a simpler implementation.

[0066] In some embodiments, the use of a multi-channel data MUX (e.g., 511, 811) is advantageous in that it enables the use of asynchronous data paths in memory systems with a wide dynamic frequency range, and the number of channels in the multi-channel data MUX is not limited, allowing the memory system requirements to be determined. Further advantages of some embodiments include achieving a wide operating frequency range through low-power designs with low design complexity and small silicon area. In some embodiments, the design of the memory circuit (e.g., 500, 800) can be easily transferred between different manufacturing technologies.

[0067] Exemplary embodiments of the present invention are summarized herein. Other embodiments can also be understood from the entirety of this specification and the claims filed herein.

[0068] Embodiment 1 A memory circuit comprising: a memory array configured to provide read data to a first data bus; N latch circuits coupled in parallel, each of the N latch circuits having a data input and a latch input, where N is a positive integer of 2 or more, and each latch circuit is configured to be coupled to the first data bus and to store read data from the first data bus; a data multiplexer having a data output, N data inputs coupled to the data outputs of the N latch circuits, and a selection input, configured to select one of the N data inputs of the data multiplexer and connect it to the data output of the data multiplexer based on the selection input of the data multiplexer; a logic circuit having a data input and a data output; and a data path coupled between the data output of the data multiplexer and the data input of the logic circuit, configured to cause the propagation of data from the data output of the data multiplexer to the data input of the logic circuit.

[0069] Embodiment 2 The memory circuit according to Embodiment 1, further comprising: a read control circuit configured to assert a first read signal in response to a read command to cause the memory array to provide read data to a first data bus, and to assert a first latch signal after asserting the first read signal; and a latch control circuit configured to provide a selection signal to the selection input of a data multiplexer, receive a first latch signal from the read control circuit, and provide the respective latch signals to the latch input of each of the N latch circuits, and configured to assert one of the latch signals in response to the assertion of the first latch signal.

[0070] The memory circuit according to either Example 1 or 2, further comprising a controller configured to receive a read command and assert an output latch signal a period of time after the receipt of the read command, wherein the logic circuit is configured to latch data at the data input of the logic circuit when the output latch signal is asserted.

[0071] The memory circuit according to any one of Examples 1 to 3, wherein the controller is configured to assert a read enable signal in response to the reception of a read command, and the read control circuit is configured to assert a first read signal in response to the assertion of the read enable signal.

[0072] Example 5: The memory circuit according to any one of Examples 1 to 4, wherein the controller is configured to receive a clock signal, the read command is synchronized with the clock signal, and the controller is configured to assert an output latch signal a certain number of clock pulses of the clock signal after receiving the read command.

[0073] The memory circuit according to any one of Examples 1 to 5, wherein the latch control circuit is configured to control a selection signal based on an output latch signal.

[0074] The memory circuit according to any one of Examples 1 to 6, wherein the latch control circuit of Example 7 is configured to trigger a transition of the selection signal in a round-robin manner when the output latch signal is asserted.

[0075] Example 8: The latch control circuit asserts the output latch signal and the latch signal provided to the next latch circuit. home of Whichever is newer A memory circuit according to any one of Examples 1 to 7, configured to cause the selection signal to transition to the next value that selects the next latch circuit among N latch circuits in the event of a certain event.

[0076] Example 9 A memory circuit according to any one of Examples 1 to 8, wherein N is equal to 2 such that the N latch circuits include first and second latch circuits, and the latch control circuit is configured to alternately assert a first latch signal provided to a first latch circuit and a second latch signal provided to a second latch circuit in response to an assertion of a first latch signal.

[0077] The memory circuit according to any one of Examples 1 to 9, wherein the read control circuit of Example 10 is configured to assert a first latch signal a certain period of time after asserting a first read signal.

[0078] The memory circuit according to any one of Examples 1 to 8 or 10, wherein N is equal to 4, and the latch control circuit is configured to assert the first, second, third and fourth latch signals provided to the first, second, third and fourth latch circuits in a round-robin manner in response to the assertion of the first latch signal.

[0079] Example 12: A memory circuit according to any one of Examples 1 to 11, wherein the memory array comprises flash memory.

[0080] Example 13: A memory circuit according to any one of Examples 1 to 12, wherein the first data bus includes more than 100 data lines.

[0081] Embodiment 14: Receiving a first read command; detecting first data from a memory array based on the first read command; providing the detected first data to a first data bus; asserting a first latch signal a certain period after receiving the first read command; and, in response to the assertion of the first latch signal, latching the detected first data from the first data bus to one of N latch circuits, wherein the N latch circuits are connected in parallel, each of the N latch circuits has a data input connected to the first data bus, N is a positive integer greater than or equal to 2, and the output of one latch circuit is propagated to the data input of a logic circuit via a data path. A method comprising: asserting an output latch signal a first time period after receiving a first read command in order to latch the detected first data from one latch circuit to a logic circuit; receiving a second read command; detecting second data from a memory array based on the second read command; selecting the next latch circuit from N latch circuits; latching the detected second data to the next latch circuit; propagating the output of the next latch circuit to the data input of a logic circuit via a data path; and asserting an output latch signal a second time period after receiving a second read command in order to latch the detected second data from the next latch circuit to a logic circuit.

[0082] Example 15: The method according to Example 14, wherein selecting the next latch circuit from N latch circuits is performed in a round-robin manner.

[0083] The method according to either Example 14 or 15, further comprising receiving a clock signal, wherein the first read command is synchronized with the clock signal, and asserting an output latch signal includes asserting the output latch signal after a certain number of clock pulses of the clock signal have been received from the first read command.

[0084] Example 17: The method according to any one of Examples 14 to 16, wherein the frequency of the clock signal is 533MHz to 820MHz.

[0085] Example 18 Selecting the next latch circuit from N latch circuits, asserting the output latch signal, and latching the detected second data to the next latch circuit, home of Whichever is newer The method according to any one of Examples 14 to 17, comprising selecting the next latch circuit in response to the event.

[0086] The method according to any one of Examples 14 to 18, wherein asserting the first latch signal is performed after a certain period of time has elapsed since receiving the first read command.

[0087] Example 20 A memory array configured to provide read data to a first data bus; a controller configured to receive read commands and clock signals, and to assert an output latch signal after a predetermined number of clock pulses of the clock signal from the reception of a read command, and further configured to provide a memory address to the memory array based on a read command; a read control circuit configured to assert a first read signal in response to a read command, causing the memory array to provide read data to the first data bus based on a memory address, and to assert a first latch signal a certain period of time after asserting the first read signal, wherein the certain period of time is asynchronous with respect to the clock signal; N latch circuits coupled in parallel, each of the N latch circuits having a data input and a latch input coupled to the first data bus, where N is a positive integer of 2 or more; and a first latch signal from the read control circuit. A latch control circuit configured to receive a latch signal and provide a latch signal to the latch input of each of N latch circuits, wherein the latch control circuit is configured to cause data to latch in one of the N latch circuits in response to the assertion of a first latch signal by asserting each output latch signal; a data multiplexer having a data output, N data inputs coupled to the data outputs of the N latch circuits, and a selection input, wherein the data multiplexer is configured to select one of the N data inputs of the data multiplexer based on the selection input of the data multiplexer and connect it to the data output of the data multiplexer; a data path having a data input coupled to the data output of the data multiplexer; and a logic circuit having a data output and a data input coupled to the data output of the data path, wherein the logic circuit is configured to latch data at the data input of the logic circuit when an output latch signal is asserted.

[0088] Example 21: The memory circuit according to Example 20, wherein the latch control circuit is configured to provide a selection signal to the selection input of a data multiplexer and to control the transition of the selection signal based on an assertion of the output latch signal.

[0089] While the present invention has been described with reference to exemplary embodiments, this description is not intended to be constrained. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the invention, will be obvious to those skilled in the art by reference to the description. Accordingly, the appended claims are intended to encompass such modifications or embodiments.

Claims

1. a memory array configured to provide read data to a first data bus; N latch circuits coupled in parallel; a data multiplexer having a data output, N data inputs respectively coupled to the data outputs of said N latch circuits, and a select input; a logic circuit having a data input and a data output; a data path coupled between the data output of the data multiplexer and the data input of the logic circuit; A memory circuit comprising: each latch circuit of the N latch circuits has a data input and a latch input coupled to the first data bus and configured to store read data from the first data bus, N being a positive integer greater than or equal to 2; the data multiplexer is configured to select one of the N data inputs of the data multiplexer to connect to the data output of the data multiplexer based on the selection input of the data multiplexer; the data path is configured to cause propagation of data from the data output of the data multiplexer to the data input of the logic circuit; Memory circuit.

2. The memory circuit includes: a read control circuit configured to, in response to a read command, assert a first read signal to cause the memory array to provide the read data on the first data bus, and to assert a first latch signal after asserting the first read signal; a latch control circuit configured to provide a select signal to the select input of the data multiplexer, to receive the first latch signal from the read control circuit, and to provide a respective latch signal to the latch input of each latch circuit of the N latch circuits, the latch control circuit configured to assert one of the latch signals in response to assertion of the first latch signal; Further comprising:

2. The memory circuit of claim 1.

3. the memory circuit further comprises a controller configured to receive the read command and assert an output latch signal a period of time after receiving the read command, the logic circuit being configured to latch data at the data input of the logic circuit when the output latch signal is asserted. The memory circuit of claim 2 .

4. the controller is configured to assert a read enable signal in response to receiving the read command, and the read control circuit is configured to assert the first read signal in response to the assertion of the read enable signal.

4. The memory circuit of claim 3.

5. the controller is configured to receive a clock signal, the read command is synchronized with the clock signal, and the controller is configured to assert the output latch signal a certain number of clock pulses of the clock signal from receiving the read command.

4. The memory circuit of claim 3.

6. the latch control circuit is configured to control the selection signal based on the output latch signal.

4. The memory circuit of claim 3.

7. the latch control circuit is configured to cause the transition of the select signal in a round robin fashion when the output latch signal is asserted; The memory circuit of claim 6.

8. the latch control circuit is configured to transition the select signal to a next value that selects the next one of the N latch circuits on the most recent event between the assertion of the output latch signal and the assertion of the latch signal provided to a next latch circuit. The memory circuit of claim 6.

9. wherein N is equal to 2, such that the N latch circuits comprise first and second latch circuits; the latch control circuit is configured to alternate between asserting a first latch signal provided to the first latch circuit and asserting a second latch signal provided to the second latch circuit in response to the assertion of the first latch signal. The memory circuit of claim 2 .

10. the read control circuit is configured to assert the first latch signal a certain period after asserting the first read signal; The memory circuit of claim 2 .

11. N is equal to 4, such that the N latch circuits comprise first, second, third and fourth latch circuits; the latch control circuit is configured to assert, in a round robin manner in response to assertion of the first latch signal, first, second, third and fourth latch signals provided to the first, second, third and fourth latch circuits, respectively; The memory circuit of claim 2 .

12. the memory array comprises flash memory; 2. The memory circuit of claim 1.

13. the first data bus includes more than 100 data lines; 2. The memory circuit of claim 1.

14. Receiving a first read command; sensing first data from a memory array based on the first read command; providing the sensed first data to a first data bus; asserting a first latch signal a period of time after receiving the first read command; latching the sensed first data from the first data bus into one latch circuit of N latch circuits in response to assertion of the first latch signal, the N latch circuits being coupled in parallel, each latch circuit of the N latch circuits having a data input coupled to the first data bus, N being a positive integer greater than or equal to two; Propagating the output of said one latch circuit through a data path to a data input of a logic circuit; asserting an output latch signal a first time period after receiving the first read command to latch the sensed first data from the one latch circuit into the logic circuit; Receiving a second read command; sensing second data from the memory array based on the second read command; selecting a next latch circuit from the N latch circuits; latching the sensed second data into the next latch circuit; propagating the output of the next latch circuit through the data path to the data input of the logic circuit; asserting the output latch signal a second time period after receiving the second read command to latch the sensed second data from the next latch circuit into the logic circuit; The method includes:

15. selecting the next latch circuit from the N latch circuits includes selecting the next latch circuit in a round robin manner. The method of claim 14.

16. The method further includes receiving a clock signal, the first read command being synchronous with the clock signal, and asserting the output latch signal includes asserting the output latch signal a certain number of clock pulses of the clock signal after receiving the first read command. The method of claim 14.

17. The frequency of the clock signal is 533 MHz to 820 MHz.

17. The method of claim 16.

18. selecting the next latch circuit from the N latch circuits includes selecting the next latch circuit in response to a most recent event between the assertion of the output latch signal and the latching of the sensed second data into the next latch circuit. The method of claim 14.

19. asserting the first latch signal includes asserting the first latch signal a certain period after receiving the first read command. The method of claim 14.

20. a memory array configured to provide read data to a first data bus; A controller; A read control circuit; N latch circuits coupled in parallel; A latch control circuit; a data multiplexer having a data output, N data inputs respectively coupled to the data outputs of said N latch circuits, and a select input; a data path having a data input coupled to the data output of the data multiplexer; A logic circuit; A memory circuit comprising: the controller is configured to receive a read command and a clock signal, and to assert an output latch signal a predetermined number of clock pulses of the clock signal from receiving the read command, and is further configured to provide a memory address to the memory array based on the read command; The read control circuit responds to the read command by asserting a first read signal to cause the memory array to provide read data to the first data bus based on the memory address; a first latch signal is asserted a fixed period of time after the first read signal is asserted, the fixed period of time being asynchronous with respect to the clock signal; each latch circuit of the N latch circuits has a data input coupled to the first data bus and a latch input, N being a positive integer greater than or equal to 2; the latch control circuit is configured to receive the first latch signal from the read control circuit and provide a respective latch signal to the latch input of each of the N latch circuits, and is configured to cause one of the N latch circuits to latch data in response to assertion of the first latch signal by asserting a respective output latch signal; the data multiplexer is configured to select one of the N data inputs of the data multiplexer to connect to the data output of the data multiplexer based on the selection input of the data multiplexer; the logic circuit has a data output and a data input coupled to the data output of the data path and is configured to latch data at the data input of the logic circuit when the output latch signal is asserted; Memory circuit.

21. the latch control circuit is configured to provide a select signal to the select input of the data multiplexer and to control a transition of the select signal based on the assertion of the output latch signal.

21. The memory circuit of claim 20.

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