Process for forming an electronic device including a component structure adjacent to a trench

Abstract

The process of forming an electronic device can form an accumulation channel or an integral diode by selective doping of components of a workpiece. In one embodiment, the doped region (644) can be formed by implanting into the sidewalls of the body region (780). In another embodiment, the doped region can correspond to the remaining portion (1844) of the semiconductor layer (310) after forming another doped region by implanting into the contact opening (1816). The accumulation channel or integral diode can lower the barrier for body diode turn-on. The stored charge and Q RR A reduction in the switching losses can be achieved.

Description

[Technical field]

[0001] The present disclosure relates to electronic devices and processes for forming them, and more particularly to electronic devices that include component structures adjacent to trenches, and processes for forming them. [Background technology]

[0002] The power transistor may be an insulated gate field effect transistor and may include a body diode. The body diode conducts current in a direction that is opposite to the current flow when the transistor is in the on state. The conduction of the body diode causes the injection and accumulation of minority carriers that must be removed before the transistor can be switched off. The reverse recovery charge (Q RR ) causes switching losses. RR Reducing θ is beneficial for increasing efficiency, but requires that other transistor parameters remain within acceptable limits. [Brief description of the drawings]

[0003] Embodiments are illustrated by way of example and not limitation in the accompanying figures. [Figure 1] Included are schematic diagrams of circuits including transistors and components. [Diagram 2] Included are illustrations of cross-sectional views of portions of a workpiece that include a substrate. [Diagram 3] Included is an illustration of a cross-sectional view of the workpiece of FIG. 2 after patterning the substrate to define trenches. [Figure 4] Included is an illustration of a cross-sectional view of the workpiece of FIG. 3 after forming an insulating layer along the sidewalls and bottom of the trench, a shield electrode, an insulating layer over the shield electrode, and a gate dielectric layer. [Diagram 5] 5 includes an illustration of a cross-sectional view of the workpiece of FIG. 4 during formation of a doped region in the component portion. [Figure 6]6 includes an illustration of a cross-sectional view of the workpiece of FIG. 5 after forming electrodes in the trenches and source regions. [Figure 7] 7 includes an illustration of a cross-sectional view of the workpiece of FIG. 6 after forming a substantially completed electronic device according to one embodiment. [Figure 8] 1 includes an illustration of a top view of an electronic device including a transistor portion and a component portion, according to one embodiment. [Figure 9] Included is an illustration of a top view of an electronic device including a transistor portion and a component portion according to another embodiment. [Figure 10] Included is an illustration of a top view of an electronic device including a transistor portion and a component portion according to yet another embodiment. [Figure 11] 1 includes an illustration of a top view of an electronic device including a transistor portion and a component portion according to a further embodiment. [Figure 12] 2 includes an illustration of a cross-sectional view of a workpiece corresponding to the component shown in FIG. 1 . [Figure 13] 2 includes an illustration of a cross-sectional view of a workpiece corresponding to the component shown in FIG. 1 according to another embodiment. [Figure 14] 2 includes an illustration of a cross-sectional view of a workpiece corresponding to the component shown in FIG. 1 . [Figure 15] Included are plots of conduction band energy as a function of distance from a major surface for transistor and component structures. [Figure 16] Included are plots of hole density as a function of distance from a major surface for transistor structures and component structures.

[0004] Those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale - for example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] The following description in combination with the drawings is provided to aid in understanding the teachings disclosed herein. The following description focuses on specific implementations and embodiments of the teachings. This focus is provided to aid in the explanation of the teachings and should not be construed as a limitation on the scope or applicability of the teachings. However, other teachings may of course also be utilized in the present application.

[0006] The term "electrically coupled" is intended to mean the connection, coupling, or association of two or more electronic components, circuits, systems, or any combination of (1) at least one electronic component, (2) at least one circuit, or (3) at least one system, in such a way that a signal (e.g., a current, voltage, or optical signal) can be transferred partially or completely from one to the other. A subset of "electrically coupled" can include an electrical connection between two electronic components. In a circuit diagram, a node corresponds to an electrical connection between electronic components. Thus, an electrical connection is a specific type of electrical coupling. However, not all electrical couplings are electrical connections. Other types of electrical couplings include capacitive coupling, resistive coupling, and inductive coupling.

[0007] Unless expressly stated otherwise, the terms "horizontal," "lateral," and variations thereof refer to a direction along or parallel to a major surface of a substrate or semiconductor layer or region, and the term "vertical" and variations thereof refer to a direction perpendicular to a major surface of a substrate or semiconductor layer or region. For example, two features may be laterally offset and may or may not be at different heights. Thus, a lateral offset may be seen in a top view of a plan view of an electronic device.

[0008] With respect to dimensions, length is measured in a direction along or parallel to the direction corresponding to the flow of primary current through the component, region, or layer, and width is measured in a direction perpendicular to the length.

[0009] The terms "normal operation" and "normal operating state" refer to the conditions under which an electronic component or device is designed to operate. The conditions may be obtained from a data sheet or other information regarding voltage, current, capacitance, resistance, or other electrical conditions. Normal operation therefore does not include operating an electrical component or device well beyond its design limits.

[0010] The term "power transistor" refers to the drain-source voltage (V DS ) times the drain current when the transistor is on (I D ) and is at least 11 W. For example, the transistor may have a V DS When in the on state, the I D Such a transistor is a power transistor, since the product of 40V x 12A is 480W.

[0011] The group numbers correspond to columns in the Periodic Table of the Elements based on the IUPAC Periodic Table of the Elements, version dated December 1, 2018.

[0012] The terms "on," "overlying," and "over" may be used to indicate that two or more elements are in direct physical contact with each other. However, "over" may also mean that two or more elements are not in direct contact with each other. For example, "over" may mean that one element is above another element, but the elements do not contact each other and may have another element or elements between the two elements.

[0013] The terms "comprises," "comprising," "includes," "including," "has," "having," or any other variations thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that includes a list of features is not necessarily limited to only those features and may include other features not expressly listed or inherent to such method, article, or apparatus. Furthermore, unless expressly stated to the contrary, "or" refers to an inclusive or, not an exclusive or. For example, a condition A or B is satisfied by any one of A being true (or present) and B being false (or absent), A being false (or absent) and B being true (or present), and both A and B being true (or present).

[0014] Also, the use of "a" or "an" is employed to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. This description should be read to include one, at least one, or the singular, and vice versa, unless otherwise clearly meant. For example, where a single item is described herein, two or more items may be used in place of the single item. Similarly, where two or more items are described herein, the two or more items may be replaced with a single item.

[0015] Use of the words "about," "approximately," or "substantially" is intended to mean that the value of a parameter is close to the stated value or location. However, slight variations may result in the value or location not being exactly as stated. Thus, variations of up to ten percent (10%) for the values ​​(and up to twenty percent (20%) for semiconductor doping concentrations) are reasonable variations from the precisely stated ideal target.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. The materials, methods, and examples are illustrative only and are not intended to be limiting. To the extent not described herein, many details regarding specific materials and processing operations are conventional and can be found in textbooks and other sources within the semiconductor and electronics arts.

[0017] The process of forming an electronic device may form an accumulation channel or an integral diode by selective doping of components of a workpiece. In one embodiment, the doped region may be formed by implanting into the sidewall of the body region. In another embodiment, the doped region may correspond to the remaining portion of the semiconductor layer after forming another doped region by implanting into a contact or other similar opening. The accumulation channel or integral diode may lower the barrier for body diode turn-on. The stored charge and Q RR A reduction in the switching losses can be achieved.

[0018] 1 includes a schematic diagram of a circuit 100 that includes a power transistor 120 and a component 140. The component 140 is a Q RR1. A source terminal 106 is electrically coupled to a source of power transistor 120 and to a terminal of component 140, and a drain terminal 102 is electrically coupled to a drain of power transistor 120 and to another terminal of component 140. A control terminal 104 is electrically coupled to a gate of power transistor 120. One or more other electrical connections may be made to component 140 but are not shown in FIG.

[0019] The power transistor 120 can be an insulated-gate field-effect transistor (IGFET). The power transistor 120 can include one or more transistor structures. In one embodiment, the power transistor 120 includes tens, hundreds, or even thousands of transistor structures, where drain regions of the transistor structures are electrically connected to each other, source regions of the transistor structures are electrically connected to each other, and gate electrodes of the transistor structures are electrically connected to each other. The component 140 can be implemented using a variety of different circuit components. Further details regarding some options for the component 140 are described in more detail below. Such options are intended to illustrate possible designs for the component 140, but are not intended to limit them.

[0020] In one embodiment, component 140 may be in the form of an accumulation-channel field-effect transistor (ACCUFET). The ACCUFET may have some characteristics that are substantially similar and other characteristics that are significantly different than power transistor 120. For example, power transistor 120 and the ACCUFET may have approximately the same threshold voltage, and power transistor 120 may have a slightly steeper subthreshold slope than the ACCUFET. The ACCUFET reduces the Q associated with electronic devices. RRallows component 140 to be dissipated much more quickly than if it were not present in circuit 100. The value of the resistance associated with the accumulation channel of ACCUFET can be determined by running simulations that result in a leakage current that is acceptable (not too high) for a particular application.

[0021] 2 includes an illustration of a cross-sectional view of a power transistor portion 320 and a component portion 340 of a workpiece 300. The power transistor portion 320 corresponds to the power transistor 120, and the component portion 340 corresponds to the component 140. The workpiece 300 includes a substrate 310 having a major surface 312. The substrate 310 includes a base region 330 and a semiconductor layer 350. The base region 330 may be in the form of a semiconductor wafer. In one embodiment, the base region 330 may include one or more Group 14 elements, such as Si or SiC, and may be heavily doped with an n-type or p-type dopant. For purposes of this specification, heavily doped means at least 1×10 19 atoms / cm 3 "Average or peak dopant concentration" is intended to mean the average or peak dopant concentration of

[0022] The semiconductor layer 350 may be epitaxially grown from the base region 330. The semiconductor layer 350 may have a dopant having the same conductivity type as the base region 330. In one embodiment, the semiconductor layer 350 is a 1×10 15 atoms / cm 3 ~9x10 17 atoms / cm 3For purposes of this specification, the semiconductor layer 350 is a type of doped region. The thickness of the semiconductor layer 350 may depend on the voltage rating of the power transistor 120 (the voltage difference between the drain and source of the power transistor 120 when in the off state), as well as the average dopant concentration (or dopant concentration profile) of the semiconductor layer 350. In one embodiment, the thickness of the semiconductor layer 350 may be in the range of 2 microns to 9 microns. In other embodiments, other dopant concentrations and thicknesses for the semiconductor layer 350 may be used without departing from the concepts described herein. The semiconductor layer 350 may or may not have a higher dopant concentration adjacent to the base region 330.

[0023] In another embodiment, the semiconductor layer 350 may be replaced by multiple epitaxially grown semiconductor layers. In a particular embodiment, a relatively thinner semiconductor bottom layer and a relatively thicker top semiconductor layer may be used. The relatively thinner semiconductor layer may help control the electric field near the base region 330. When initially formed, the relatively thinner bottom semiconductor layer may have an average dopant concentration that is between the dopant concentration of the base region 330 and the average dopant concentration of the relatively thicker semiconductor layer. In another particular embodiment, a relatively thinner semiconductor layer may be used near the major surface 312. In this embodiment, when initially formed, the relatively thinner semiconductor layer may be undoped or may have an average dopant concentration that is significantly lower than the average dopant concentration of the subsequently formed body region. In a further particular embodiment, a bottom semiconductor layer, a middle semiconductor layer, and a top semiconductor layer may be used. The middle semiconductor layer may be thicker than each of the bottom semiconductor layers. The top semiconductor layer and the bottom semiconductor layer may be thicker than each of the bottom semiconductor layers to provide a desired on-state resistance (R DSON) The lower semiconductor layer may be used to control the electric field near the base region 330 as described above, and the upper semiconductor layer may be used to allow for greater control of the average dopant concentration of the subsequently formed body region. After reading this specification, one of ordinary skill in the art will be able to determine the number and dopant concentrations of semiconductor layers to be formed above the base region 330.

[0024] 3, portions of substrate 310 are removed to define trench 420 in power transistor portion 320 and trench 440 in component portion 340. Semiconductor pillar 422 is immediately adjacent trench 420 and semiconductor pillar 442 is immediately adjacent trench 440. One or more other trenches and semiconductor pillars are also formed but are not shown in FIG. 3. Within power transistor portion 320, the other trenches and semiconductor pillars are substantially identical to trench 420 and semiconductor pillar 422, and within component portion 340, the one or more other trenches and semiconductor pillars, if present, are substantially identical to trench 440 and semiconductor pillar 442.

[0025] At least one electrode will then be formed within each of trenches 420 and 440. The width of trenches 420 and 440 as measured at the top of trenches 420 and 440 must allow for the subsequent formation of an insulating layer and electrode(s). However, as the width increases, the effective channel width of power transistor 120 may decrease. In one embodiment, the width of the trenches may be in the range of 0.3 microns to 8.0 microns, 0.6 microns to 6.0 microns, or 0.9 microns to 4.0 microns.

[0026] The trenches 420 and 440 extend into and at least partially through the semiconductor layer 350. In one embodiment, the trenches 420 and 440 do not extend to the base region 330, but are spaced from the base region 330 by at least a portion of the semiconductor layer 350. In one embodiment, the trenches 420 and 440 extend to a depth of 9 microns or less, 7 microns or less, or 5 microns or less, as measured from the main surface 312. In the same or a different embodiment, the trenches 420 and 440 extend to a depth of at least 0.7 microns. The depth of the trenches 420 and 440 may depend on the voltage rating of the device, and therefore the depth of the trenches 420 and 440 may be outside of the values ​​stated above.

[0027] FIG. 4 includes an illustration of a cross-sectional view of workpiece 300 after forming insulating layer 522, shield electrode 524, insulating layer 526, and gate dielectric layer 544. Insulating layer 522 is formed along exposed portions of semiconductor layer 350. Insulating layer 522 partially fills trenches 420 and 440, but does not completely fill them. Insulating layer 522 may include an oxide, a nitride, an oxynitride, or any combination thereof. In one embodiment, insulating layer 522 may include a single insulating film, and in another embodiment, insulating layer 522 may include multiple insulating films. Insulating layer 522 has a thickness in the range of approximately 70 nm to approximately 1000 nm. Insulating layer 522 may be grown, deposited, or a combination of growing and depositing.

[0028] A conductive layer is formed over the insulating layer 522 and within the trenches 420 and 440. The conductive layer substantially fills the remaining portions of the trenches 420 and 440. The conductive layer may include a metal-containing or semiconductor-containing material. In one embodiment, the conductive layer may include a highly doped semiconductor material, such as amorphous silicon or polysilicon. In another embodiment, the conductive layer includes multiple films, such as an adhesion film, a barrier film, and a conductive fill material. In a particular embodiment, the adhesion film may include a refractory metal, such as titanium, tantalum, or the like; the barrier film may include a refractory metal nitride, such as titanium nitride, tantalum nitride, or the like; a refractory silicide, such as tungsten silicide, titanium silicide, or the like; or a refractory metal semiconductor nitride, such as TaSiN; and the conductive fill material may include tungsten. In a further particular embodiment, the conductive layer may include Ti / TiN / W. The selection of the number of films and the composition(s) of those film(s) depends on the electrical performance, the temperature of the subsequent thermal cycle, another criterion, or any combination thereof. Refractory metals and refractory metal-containing compounds can withstand high temperatures (e.g., the melting point of such materials can be at least 1400° C.), can be conformally deposited, and can have a lower bulk resistivity than heavily doped n-type silicon. After reading this specification, those skilled in the art will be able to determine the composition of the conductive layer to meet their needs and desires for a particular application.

[0029] The portions of the conductive layer overlying the insulating layer 522 outside of the trenches 420 and 440 are removed. The removal can be performed using chemical mechanical polishing or blanket etching techniques. The insulating layer 522 can be used as a polish stop or an etch stop layer.

[0030] The exposed portions of the conductive structures are recessed to form shield electrodes 524 in trenches 420 and 440. Removal may be performed using wet or dry etching techniques. The highest height of shield electrodes 524 is below the lowest height of the subsequently formed body regions. Although not yet formed, the dashed lines in FIG. 4 are used as reference points to indicate the depth of the body regions in the completed device. The highest height of shield electrodes 524 may be within a range of approximately 0.4 microns to 3.0 microns below major surface 312.

[0031] The portions of insulating layer 522 overlying major surface 312 and within trenches 420 and 440 at an elevation above the shield electrode are removed. An insulating layer 526 is formed along the exposed portions of workpiece 300. Insulating layer 526 partially fills, but does not completely fill, trenches 420 and 440. Insulating layer 526 may include an oxide, a nitride, an oxynitride, or any combination thereof. In one embodiment, insulating layer 526 may include a single insulating film, and in another embodiment, insulating layer 526 may include multiple insulating films. Insulating layer 526 has a thickness in the range of approximately 70 nm to approximately 500 nm. Insulating layer 526 may be grown or deposited.

[0032] In one embodiment, a subsequently formed gate electrode will be formed over insulating layer 526. The top surfaces of insulating layer 526 in trenches 420 and 440 are at an elevation below the lowest elevation of their corresponding subsequently formed body regions. Therefore, the amount of recessing of the conductive structures in forming shield electrode 524 and the thickness of insulating lays 526 are selected to achieve the required or desired site for the bottom surface of the subsequently formed gate electrode.

[0033] Portions of insulating layer 526 overlying major surface 312 and within trenches 420 and 440 at a height above the top surface of the insulating layer in the center of trenches 420 and 440 are removed. A gate dielectric layer 544 is formed along the surfaces of workpiece 300 not covered by insulating layers 522 and 526. Gate dielectric layer 544 may include an oxide, a nitride, an oxynitride, or any combination thereof. Gate dielectric layer 544 is significantly thinner than each of insulating layers 522 and 526. Gate dielectric layer 544 has a thickness in the range of 2 nm to 150 nm. Gate dielectric layer 544 may be grown, deposited, or a combination of grown and deposited. FIG. 5 illustrates the workpiece during a doping step to form a doped region 644 in component portion 340. Doped region 644 may be an accumulation channel for the component structure shown. Doped region 644 has the same conductivity type as semiconductor layer 350. Doped regions 644 may be present along the conductive path between semiconductor layer 350 and a later formed contact, allowing the ACCUFET to D -V DS When operating in the third quadrant of the curve, current can flow through doped region 644 .

[0034] The doped region 644 in the ACCUFET causes the component 140 to have a higher leakage current when the ACCUFET is in the off state compared to the power transistor 120 when in the off state. RR is desirable, and a lower resistance, Q RR However, if the resistance of ACCUFET is too low when it is in the off state, the leakage current for component 140 may become too high. Simulations can be performed to determine a resistance or range of resistance that can be used for ACCUFET.

[0035] After the resistance is determined, the properties of the doped region 644 to achieve the resistance can be determined. In one embodiment, the doped region 644 is a 1×10 15atoms / cm 3 ~1x10 19 atoms / cm 3 and in more particular embodiments, 1x10 16 atoms / cm 3 ~9x10 17 The doped region 644 may have a higher average dopant concentration than the semiconductor layer 350 near the top of the semiconductor pillar.

[0036] The thickness of each doped region 644 is measured as the distance from the sidewall of the corresponding trench 440 to its corresponding pn junction with the subsequently formed body region. The thickness can be in the range of 5 nm to 200 nm, and in embodiments, in the range of 11 nm to 95 nm.

[0037] The lengths of doped regions 644 are measured in a direction of current flow through doped regions 644, which is substantially perpendicular to major surface 312. When formed, each length of doped regions 644 may extend from major surface 312 into semiconductor layer 350 to a height below the lowest height of the subsequently formed body region of the ACCUFET (corresponding to the dashed line). The length of doped regions 644 may be in the range of 0.2 microns to 1.5 microns, and in one embodiment, in the range of 0.3 microns to 0.9 microns.

[0038] Attention is now directed to the process used to form the doped region 644. The resist member 620 covers the power transistor portion 320 such that the semiconductor layer 350 in the power transistor portion 320 is not doped when forming the doped region 644 in the component portion 340. The doping to form the doped region 644 can be formed using tilt angle implantation, as indicated by the arrows in FIG. 5. The angle for the tilt angle is specified as the angle from vertical, perpendicular to the major surface 312. Thus, when ions are directed at the workpiece in a direction perpendicular to the major surface 312, there is no tilt angle (0°). In one embodiment, the tilt angle can be in the range of 7.5° to 45°. The workpiece 300 can be rotated during implantation to ensure that all surfaces not covered by the resist member 620 are implanted.

[0039] The energy for the implantation may be selected such that the desired thickness of the doped region 644 (distance from the sidewall of the corresponding trench 440) may be achieved when considering the tilt angle and thickness of the gate dielectric layer 544. To determine the required or desired combination of tilt angle and energy for the implantation, the projected range (R P ) and straggle (ΔR P ) may be consulted, or alternatively, simulations or empirical data may be collected. In one embodiment, the energy may be in the range of 5 keV to 200 keV, and in one embodiment, in the range of 11 keV to 95 keV. A dose is selected to achieve a desired dopant concentration for the doped region 644. After formation, the doped region 644 is formed and the resist member 620 over the power transistor portion 320 is removed.

[0040] In another embodiment, an implant shielding layer (not shown) may be used, such that the implant is performed through the implant shielding layer and not through the gate dielectric layer 544. The implant shielding layer may include an oxide, nitride, or oxynitride. The implant shielding layer may have a thickness in the range of 2 nm to 50 nm. The implant shielding layer may be grown or deposited. Doping to form the doped region 644 may then be performed. As with the gate dielectric layer 544 as described above, the thickness of the implant shielding layer may be considered when determining the energy for the implant used to form the doped region 644. After implantation, the implant shielding layer is removed and the gate dielectric layer 544 is formed as described above. In this embodiment, the implant shielding layer receives any implant damage that may occur during doping instead of the gate dielectric layer 544, and the implant shielding layer is removed before forming the gate dielectric layer 544.

[0041] 6 includes an illustration of the workpiece 300 after forming the gate electrode 724, the electrode 744, and the source region 726. A conductive layer is formed over the workpiece 300 and within the trenches 420 and 440. The conductive layer substantially fills the remaining portions of the trenches 420 and 440. Because the conductive layer will form the gate electrode, the material in contact with the gate dielectric layer 544 may be selected for a particular work function to help achieve a desired threshold voltage for the power transistor 120. The conductive layer for the gate electrode 724 and the electrode 744 may include any of the materials and number of films as described above with respect to the shield electrode 524. The gate electrode 724 and the electrode 744 may have the same composition (materials and number of films) or a different composition compared to the shield electrode 724.

[0042] The portions of the conductive layer outside of the trenches 420 and 440 are removed. The removal can be performed using chemical mechanical polishing or blanket etching techniques. The portions of the conductive layer within the trenches can be recessed to reduce source-to-gate capacitance. The highest portions of the gate electrodes 724 and 744 can be at a higher height than the lowest portions of their corresponding adjacent source regions 726.

[0043] Body regions 770 and 780 are formed for power transistor 120 and ACCUFET, respectively. In this embodiment, body regions 770 and 780 are formed after forming gate electrodes 724 and 744. In another embodiment, body regions 770 and 780 may be formed prior to forming gate electrodes 724 and 744. In a further embodiment, body regions 770 and 780 may be formed prior to forming doped region 644, which corresponds to the accumulation channel of the ACCUFET. After reading this specification, one of ordinary skill in the art will be able to determine when body regions 770 and 780 are formed relative to other features of an electronic device to meet the needs and desires for a particular application.

[0044] The body region 770 has an opposite conductivity type compared to the base region 330 and the semiconductor layer 350. For example, when the base region 330 and the semiconductor layer 350 are doped n-type, the body region 770 may be doped p-type. At least a portion of the body region 770 will comprise a channel region for the illustrated transistor structure. The average dopant concentration for the body region 770 can affect the threshold voltage of the power transistor 120. Thus, the selection of a particular average dopant concentration may be determined based on the desired threshold voltage, and possibly other transistor characteristics. In one embodiment, the average dopant concentration of the body region 770 is about 1×10 15 atoms / cm 3 ~5x10 17 atoms / cm 3The average dopant concentration for the body region 770 can be in the range of 0.99 microns or less. The average dopant concentration for the body region 770 can be higher, lower, or the same as the average dopant concentration for the semiconductor layer 350. The thickness of the body region 770 is selected to achieve a desired channel length for the power transistor 120. Portions of the body region 770 are counterdoped for later formed current carrying regions, such as source regions. Thus, when initially formed, the body region 770 can have a thickness that is typically 0.99 microns or less, 0.90 microns or less, or 0.8 microns or less. In the same or different embodiments, the thickness can be at least 0.11 microns. Other dopant concentrations and thicknesses of the body region 770 can also be used to achieve the necessary or desired characteristics for the power transistor 120.

[0045] Referring to component portion 340, body region 780 has an opposite conductivity type compared to base region 330 and semiconductor layer 350. For example, when base region 330 and semiconductor layer 350 are doped n-type, body region 780 may be doped p-type. Body region 780 may be formed during the same process operation in forming body region 770. Thus, body region 780 may have the same conductivity type and substantially the same average dopant concentration and thickness as body region 770. In another embodiment, the process of forming body region 780 may have at least some difference from the process of forming body region 770. Thus, the average dopant concentration of body region 780 may be higher or lower compared to body region 770, and the thickness of body region 780 may be higher or lower compared to body region 770.

[0046] Compared to body region 770, body region 780 may have a wider range of average dopant concentration, thickness, or both concentration and thickness. For example, the average dopant concentration for body region 780 may be greater than 1×10 15 atoms / cm 3 ~1x10 19 atoms / cm 3In the same or a different embodiment, the thickness for body region 780 can be 2.0 microns or less, 1.2 microns or less, or 0.8 microns or less. In the same or a different embodiment, the thickness can be at least 0.11 microns.

[0047] Although not shown, a portion of the body region 780 may extend to the sidewall of one of the trenches 440. Thus, the doped region 644 may be discontinuous along such sidewall.

[0048] The source region 726 can have the same conductivity type as the doped region 644 and the semiconductor layer 350. The source region 726 can have a peak dopant concentration sufficient to allow an ohmic contact to be made to a subsequently formed contact. In one embodiment, the peak dopant concentration of the source region 726 is at least 5×10 18 atoms / cm 3 Or at least 1x10 19 atoms / cm 3 It can be.

[0049] FIG. 7 includes an illustration of the workpiece after forming a substantially completed electrode device. An interlevel dielectric ("ILD") layer 800 is formed over the workpiece 300 and may include an oxide, nitride, oxynitride, or any combination thereof. The ILD layer 800 may include a single film or multiple individual films. An etch stop film, an anti-reflective film, or a combination may be used within the ILD layer 800 to aid in processing. In one embodiment, the ILD layer 800 has a thickness in the range of approximately 100 nm to approximately 1000 nm. The ILD layer 800 may be planarized using etch-back or polishing techniques.

[0050] The ILD layer 800 may be patterned to define a contact opening 816, and the workpiece 300 is implanted to form a body contact region 826. The contact opening 816 extends through the source region 726 and exposes portions of the body regions 770 and 780. The body contact region 826 has the same conductivity type as the body regions 770 and 780, which are the body regions for the structure being formed. The body contact region 826 may have a peak dopant concentration sufficient to allow an ohmic contact to the conductive plug 836 to be made. In one embodiment, the peak dopant concentration of the body contact region 826 is at least 5×10 18 atoms / cm 3 Or at least 1x10 19 atoms / cm 3 Although not shown, contact openings to shield electrode 524, gate electrode 724, and electrode 744 may be formed in locations not shown in FIG.

[0051] A conductive plug 836 is formed by forming a conductive layer over the workpiece and within the contact opening 816, and the portion of the conductive layer outside the contact opening 816 is removed by an etch-back or polishing technique. The conductive layer can include any of the materials described above internal to the shield electrode 524. In an embodiment, the conductive layer can include an adhesion layer, a barrier layer, and a bulk conductive layer. In a particular embodiment, the adhesion layer can include Ti, the barrier layer can include TiN, and the bulk conductive layer can be W. The portion of Ti in contact with the source region 726 and the body contact region 826 may or may not be reacted to form TiSi2. Other conductive plugs 836 will also contact the shield electrode 524, the gate electrode 724, and the electrode 744, but are not shown in FIG. 7.

[0052] Interconnects, including source interconnect 846, are formed over the ILD layer 800 and conductive plugs 836. The interconnects are formed from a conductive layer by patterning the conductive layer. The conductive layer can include a single film or multiple films. In one embodiment, the conductive layer can include a bottom film, a bulk conductive film, and a top film.

[0053] The underlayer may include an adhesion film, a barrier film, or both. The underlayer may include a refractory metal, such as titanium, tantalum, or the like, and the barrier film may include a refractory metal nitride, such as titanium nitride, tantalum nitride, or the like, a refractory silicide, such as tungsten silicide, titanium silicide, or the like, or a refractory metal semiconductor nitride, such as TaSiN. The underlayer may have a thickness in the range of 5 nm to 100 nm.

[0054] The bulk conductive film serves to provide low resistivity in the interconnect. In another embodiment, the bulk conductive film is typically at least 70% by weight aluminum, copper, or a noble metal. In one embodiment, the bulk conductive film can include at least 90% by weight Al or Cu. The bulk conductive film can have a thickness that is in the range of 50% to 95% of the total thickness of the interconnect. In one embodiment, the thickness of the bulk conductive film can be in the range of 0.1 microns to 4.0 microns.

[0055] The top film can be an anti-reflective or barrier film on top of the bulk conductive film. Thus, the top film can help reduce reflection during patterning of a subsequently formed resist layer. The top film can include a metal nitride. The thickness of the top film can depend on the particular material of the top film and the wavelength of the radiation used to expose the resist layer. The thickness can be selected such that the radiation is sufficiently attenuated before reaching the bulk conductive film when exposing the resist layer, in cases where the bulk conductive film can be highly reflective compared to other materials in the electronic device. In one embodiment, the thickness of the top film has a thickness in the range of 11 nm to 500 nm.

[0056] Other thicknesses for either the lower bulk conductive film and the top film may be used without departing from the concept as described herein. After patterning the conductive layer, the source interconnects and gate interconnects are formed. The source interconnects, including source interconnect 846, are electrically coupled to the source region 726, the body contact region 826, and the shield electrode 524. The gate interconnects are electrically coupled to the gate electrode 724 and the electrode 744. In another embodiment, the electrode 744 in the component portion 340 may be electrically coupled to the source interconnect rather than the gate interconnect.

[0057] One or more other interconnect levels and passivation layers may be formed on the workpiece. Each interconnect level may include an interlevel dielectric layer and an interconnect. A conductive layer may be used in each interconnect level. The conductive layer may be the same as or different from other conductive layers previously described herein. After forming the interconnect level, an anneal may be performed.

[0058] The substrate 310 may be thinned during a backgrinding operation and metal wiring 852 may be formed along the back side of the substrate and electrically coupled to the base region 330. The metal wiring 852 may be part of or electrically coupled to the drain terminal 102. The source terminal 106 may be electrically coupled to source interconnects, including source interconnect 846. The control terminal 104 may be electrically coupled to a gate interconnect, which is electrically coupled to the gate electrode 724 and the electrode 744. The control terminal 104 may be electrically coupled to a gate driver or logic used to turn on and off the power transistor 120 and the ACCUFET corresponding to the component 140.

[0059] At this point in the process, the transistor structures that make up power transistor 120 are formed in power transistor portion 320. The transistor structures have their source regions 726 electrically coupled to each other and their gate electrodes 724 electrically coupled to each other. The portion of the semiconductor region between trench 420 and the underlying base region 330 is a semiconductor pillar and contains the drift region for the transistor structure of power transistor 120. The component structures that make up ACCUFET are formed in component 140. The component structures have their source regions 726 electrically coupled to each other and their electrodes 744 electrically coupled to each other.

[0060] The layout of the electronic device may be adjusted to achieve the required or desired electronic performance. The amount of area occupied by each of the power transistor portion 320 corresponding to the power transistor 120 and the component portion 340 corresponding to the component 140 may be varied. As used herein, the percentage of the area occupied by the component portion 340 is the area occupied by the component region 340 divided by the combined area occupied by the portions 320 and 340 times 100%. The component portion 340 may occupy an area of ​​more than 0% and up to 100%, meaning that the power transistor portion 320 is not present. In practical applications, the component portion 340 will occupy significantly less than 100% because the leakage current increases with the percentage of the area occupied by the component portion 340. In one embodiment, the component portion 340 may occupy an area in the range of 5% to 30% of the combined area. In another embodiment, the percentage may be less than 5% or more than 30%.

[0061] 8-11 include some exemplary layouts that may be used for the electronic device. FIG. 8 includes a layout in which only selected semiconductor pillars are within the component portion 340. The other semiconductor pillars are within the power transistor region 320. FIG. 9 includes a layout in which the pitch (combination of power transistor portion 320 and component portion 340) along one or more semiconductor pillars is substantially constant. FIG. 10 includes a layout in which the areas of the power transistor portion 320 and component portion 340 along one or more semiconductor pillars may vary. Thus, a power transistor portion 320 may have a different size compared to another power transistor portion 320 along such semiconductor pillar(s), or a component portion 340 may have a different size compared to another component portion 340 along such semiconductor pillar(s). FIG. 11 includes a layout in which portions of the component portion 340 may have different sizes and are located within different semiconductor pillars. The portions may be selected to enable performance advantages.

[0062] Any of the layouts described with respect to Figures 8-11 may be used for any of the above and following embodiments. After reading this specification, one of ordinary skill in the art will understand that other layouts may be used to achieve the needs and desires of a particular application without departing from the concepts described herein.

[0063] Other embodiments may also be used for component 140. Figures 12-15 focus on alternative embodiments for component 140. Power transistor 120 and its corresponding structures in power transistor portion 320 as shown in Figure 7 may or may not be present in component 140 and its structures and equivalent corresponding circuits for such structures. Previous figures will be frequently referenced. After reading this entire specification, one skilled in the art will be able to correlate features described below with the same or similar features described and illustrated above.

[0064] 12 includes an illustration of a cross-sectional view of a component portion 1540 of a workpiece 1500. Although not shown, the workpiece 1500 includes a power transistor portion 320, as described above, which corresponds to the power transistor 120. The component portion 1540 corresponds to the component 140 shown in FIG. 1. Many of the features shown in the embodiment of FIG. 12 have been described above, and therefore, the formation of the component structure in the component portion 1540 is similar to the component structure in the component portion 340 as shown in FIG. 7. Therefore, the structural and process differences between the component structures in the component portions 340 and 1540 are noted. With reference to the embodiment shown in FIG. 12, no source region is formed near the top of the semiconductor pillar adjacent to the trench 440.

[0065] The Schottky layer 1536 is formed on the semiconductor pillar in FIG. 12 to form a Schottky contact between the Schottky layer 1536 and the doped region 644. Under reverse bias, the Schottky junction between the Schottky layer 1536 and the doped region 644 is shielded from high electric fields by depletion from the body region 780 and depletion from the MOS effect of the source electrode 744. The dopant concentration of the doped region 644 is low enough to allow a Schottky contact to be formed, rather than an ohmic contact. The Schottky layer 1536 may include a metal-containing conductive layer, such as Ti, TiSi2, TiN, Ta, TaSi, TaN, Co, Pt, W, TiW, Ni, Cr, or the like. The thickness of the Schottky layer 1536 is sufficient to allow a Schottky diode to be formed at the Schottky contact, but is not so thick as to cause excessive resistive losses across the Schottky layer 1536. In one embodiment, the Schottky layer 1536 has a thickness in the range of 11 nm to 99 nm.

[0066] After reading this specification, one of ordinary skill in the art will understand that the timing at which to form Schottky layer 1536, and whether or not a silicide mask should be used (in forming Schottky layer 1536 when Schottky layer 1536 is a metal silicide), can be tailored for a particular application. Schottky layer 1536 is formed after forming doped regions 644 and body regions 780, and can be formed before forming source interconnect 836, or can be formed as part of source interconnect 836. Thus, the formation of Schottky layer 1536 can be tailored to meet the desires or needs for a particular application.

[0067] After forming the ILD layer 800, contact openings are formed for the component portion 1540, including contact opening 1516. Contact opening 1516 may have the same width or may be wider than contact opening 816 in the power transistor portion 320. The component portion 1540 is not doped in forming the body contact region 826 for the transistor structure in the power transistor portion 320. Although not shown in FIG. 12, another contact opening extends to electrode 744 in the component portion 1540. The patterning of the ILD layer 800 to form contact openings for portions 320 and 1540 may be performed during the same etch sequence or during different etch sequences.

[0068] The source and gate interconnects may be formed as described above. The electrode 744 is electrically coupled to the source terminal 106, not the control terminal 104. The source interconnect 846 contacts the Schottky layer 1536 and the electrode 744. However, the contact between the source interconnect 846 and the electrode 744 is not shown in FIG. 12. Thus, the source interconnect 846 may be electrically connected to the source region 726 and the body contact region 826 in the power transistor portion 320, electrically connected to the electrode 744, and electrically coupled to the doped region 644 and the body region 780 through the Schottky layer 1536 in the component portion 1540. The gate interconnect (not shown in FIG. 12) for the power transistor 120 of the power transistor portion 320 is electrically connected to the gate electrode 724 and is not electrically connected to the electrode 744 in the component portion 1540.

[0069] The embodiment as shown in Figure 12 can use the same process flow as described above for the embodiment as shown in Figure 7. Changes in mask design to achieve structures in component portion 1540 can be implemented. No new masks or processing operations may be required. Any of the layouts as described above, such as those shown in Figures 8-11, can be used with the embodiment shown in Figure 12.

[0070] In another embodiment, doping of portions of semiconductor layer 350 may be performed after forming contact openings to the semiconductor pillars, rather than doping the sidewalls of the semiconductor pillars. Figure 13 includes an illustration of a cross-sectional view of a component portion 1840 of workpiece 1800. Although not shown, workpiece 1800 includes power transistor portion 320, as described above, which corresponds to power transistor 120. Component portion 1840 corresponds to component 140 shown in Figure 1.

[0071] Many of the features shown in the embodiment of Figure 13 have been described above, and therefore, the formation of the component structure in component portion 1840 is similar to the component structure in component portion 340 as shown in Figure 7. Therefore, note the structural and process differences between the component structures in component portions 340 and 1840. With reference to the embodiment shown in Figure 7, doped region 644 and body region 780 are not formed near the top of the semiconductor pillar adjacent trench 440. Therefore, a masking layer overlies component portion 1840 when forming body region 770 in power transistor portion 320 for power transistor 120.

[0072] 13, after forming the contact opening 1816, a doped region 1880 may be formed adjacent to the contact opening 1816. The power transistor portion 320 may be masked to prevent a doped region similar to the doped region 1880 from being formed along the sidewalls of the contact opening 1816. If necessary or desired, the width of the semiconductor pillar in the component portion 1840, the width of the contact opening 1816, or both may be changed. The semiconductor pillar in the component portion 1840 may have the same, narrower, or wider width as the semiconductor pillar in the power transistor portion 320. The contact opening 1816 may have the same, narrower, or wider width as the contact opening 816.

[0073] Formation of doped region 1880 may be performed using any of the techniques described with respect to doped region 644, except that the conductivity type of the dopant used to form doped region 1880 is opposite that of doped region 644. The implantation parameters for doped region 1880 affect the width of portion 1844 of semiconductor layer 350 that remains between doped region 1880 and the corresponding sidewall of trench 440. Portion 1844 corresponds to the accumulation channel of the ACCUFET and is similar to doped region 644 described above. The average dopant concentration of semiconductor layer 350 near the top of the semiconductor pillar, the length of portion 1844 of semiconductor layer 350 between source region 726 and the lowest height of doped region 1880, and the above-mentioned widths for portion 1844 of semiconductor layer 350 are selected to achieve the required or desired resistance for resistor 144.

[0074] The doping to form the body contact region 826 may be performed before or after forming the doped region 1880. In another embodiment, both the doped region 1880 in the component portion 1840 and the body contact region 826 may be replaced by doped regions of the same conductivity type and formed using a single doping operation. Processing may continue with the formation of the conductive plug 836 and the source interconnect 846 as described above with respect to the embodiment of FIG.

[0075] Any of the layouts as described above, such as those shown in FIGS. 8-11, may be used in the embodiment shown in FIG.

[0076] 14 includes an illustration of a cross-sectional view of a component portion 2040 of workpiece 2000. Component portion 2040 corresponds to component 140 in FIG. 1. Although not shown, workpiece 2000 can include power transistor portion 320, as described above, which corresponds to power transistor 120.

[0077] Many of the features shown in the embodiment of FIG. 14 have been described above, and therefore the formation of the component structure in component portion 2040 is similar to the component structure in component portion 1840 as shown in FIG. 13. Therefore, the structural and process differences between the component structures in component portions 1840 and 2040 are noted. Electrode 2044 includes portions 2054 and 2064. With reference to the embodiment shown in FIG. 14, insulating layer 526 is not formed as shown in the previous figures. Within trench 440 of component portion 340, the combination of shield electrode 524, insulating layer 526, and gate electrode 724 is replaced by electrode 2044 in component portion 2040 of workpiece 2000 in FIG. 14.

[0078] Attention is now directed to the process of forming the structure as shown in Fig. 14. A shield electrode 524 is formed in the trench 420 of the power transistor portion 320, and a portion 2054 of the electrode 2044 is formed in the trench 440 of the component portion 2040. Thus, the portion 2054 provides substantially the same electrical function as the shield electrode 524 in the trench 440 as described above with respect to the other embodiments. An insulating layer 526 is formed in the trenches 420 and 440 in the portions 320 and 2040, respectively. The insulating layer 526 is removed from the sidewalls of the trenches 420 and 440. After removing the mask, a gate dielectric layer 544 is formed in the trenches 420 and 440 of the portions 320 and 2040. A mask (not shown) is formed over the power transistor portion 320 to protect the insulating layer 526 in the trench 420 of the power transistor portion 320, and the insulating layer 526 and the gate dielectric layer 544 are removed from the trench 440 in the component portion 2040. The gate electrode 724 is formed in the trench 420 of the power transistor portion 320, and the portion 2064 of the electrode 2044 is formed in the trench 440 of the component portion 2040. The gate electrode 724 and the portion 2064 of the electrode may be formed during the same processing sequence. The electrode 2044 includes a combination of the portions 2054 and 2064 as shown in FIG. 14 . Later in the process sequence, the ILD layer 800 may be patterned to define a contact opening 1816, and a conductive plug 1836 is formed in the opening 1816. The contact opening 1816 and the conductive plug 1836 may be formed during the same process sequence to form the contact opening 816 and the conductive plug 836, respectively. The source interconnect 846 contacts the conductive plug 1836 .

[0079] Although not shown, a portion of the doped region 1880 may extend to a sidewall of one of the trenches 440. Thus, a portion of the semiconductor layer 350 may be discontinuous along a sidewall of one of the trenches 440.

[0080] Any of the layouts as described above, such as those shown in FIGS. 8-11, may be used in the embodiment shown in FIG.

[0081] The above-described embodiment is RR 15 includes a plot of the conduction band energy as a function of distance from a major surface of the workpiece. The portion from 0.0 microns to 0.2 microns corresponds to source region 726, and the portion from 0.2 microns to approximately 0.55 microns represents body regions 770 and 780. As indicated by the dashed line corresponding to ACCUFET(channel), doped region 644 allows the conduction band energy to be reduced by 0.25 eV to 0.35 eV compared to a transistor structure without doped region 644 (power transistor(channel) in FIG. 15).

[0082] FIG. 16 includes a plot of hole density as a function of distance from the major surface when the power transistor 120 is in an on-state. The drift region corresponds to the portion of the semiconductor layer 350 between the base region 330 and each of the body regions 770 and 780. The drift region is approximately 0.55 microns to 4.5 microns from the major surface 312. As can be seen in the plot, the hole density corresponding to the component structure of the component 140 is within 30% to 40% lower than the hole density corresponding to the transistor structure of the power transistor 120. The actual reduction in hole density may depend on the dopant concentration and the device geometry. Therefore, the actual reduction in hole density may have a value higher or lower than the ranges described above.

[0083] For example, other embodiments having doped region 1880 and remaining portion 1844 of semiconductor layer 350 will have similar properties to those shown in FIGS.

[0084] Therefore, the embodiments allow the accumulation channel to lower the barrier for body diode turn-on. As a result, in the third quadrant, current flows through the accumulation channel region as majority carriers. Therefore, the stored minority carrier charge is reduced, which reduces Q RR Therefore, the stored charge and Q RR is reduced, resulting in lower switching losses.

[0085] Much of the above description has dealt with power transistor 120 being an IGFET. In further embodiments, power transistor 120 may be replaced with an insulated-gate bipolar transistor (IGBT).

[0086] Many different aspects and embodiments are possible, some of which are described below, and after reading this specification, those skilled in the art will understand that these aspects and embodiments are merely illustrative and do not limit the scope of the invention.

[0087] Embodiment 1. A process for forming an electronic device can include patterning a substrate including a first doped region having a first conductivity type to define a first trench, the first trench extending at least partially through the first doped region; forming a second doped region in the first semiconductor pillar and along a sidewall of the first trench, the second doped region having the first conductivity type; forming a third doped region in the first semiconductor pillar, the third doped region having a second conductivity type opposite the first conductivity type; and forming a first contact to the third doped region. In the completed device, the second doped region and the third doped region can overlie the first doped region, at least a portion of the third doped region can be spaced from a sidewall of the first semiconductor pillar by the second doped region, and the second doped region can be along a current path between the first doped region and the first contact.

[0088] Embodiment 2. The process described in embodiment 1 may further include forming an insulating layer along a sidewall and a bottom of the first trench, and forming a shield electrode in the first trench, the insulating layer being disposed between the substrate and the shield electrode.

[0089] Embodiment 3. The process of embodiment 2, wherein forming an insulating layer and forming a shield electrode are performed before forming the second doped region.

[0090] Embodiment 4. The process of embodiment 1, wherein the second doped region is discontinuous along the sidewall of the first trench.

[0091] Embodiment 5. The process of embodiment 1, wherein forming the second doped region is performed using oblique angle implantation.

[0092] Embodiment 6. The process described in any one of embodiments 1 to 5 may further include forming a dielectric layer along a sidewall of the first trench before forming the second doped region, and forming a first electrode in the first trench after forming the second doped region.

[0093] Embodiment 7. The process of embodiment 6, wherein in the completed device, the second doped region, the third doped region, the dielectric layer, and the first electrode are part of a component structure.

[0094] Embodiment 8. The process of embodiment 7 may further include forming a current carrying region overlying the third doped region and in contact with the second doped region, forming a first contact opening extending into the third doped region, and forming a doped contact region in the third doped region and along a surface of the first contact opening. Forming the first contact may be performed such that an ohmic contact is formed to the third doped region and to the current carrying region.

[0095] Embodiment 9. The process of embodiment 6, wherein in the completed device, a Schottky contact is made to the second doped region.

[0096] Embodiment 10. Forming the second doped region comprises forming the second doped region at a concentration of 1x10 in the completed device. 16 atoms / cm 3 ~9x10 17 atoms / cm 3 10. The process of embodiment 9, wherein the process is carried out so as to have an average dopant concentration in the range of

[0097] Embodiment 11. The process of any one of embodiments 1, 4, and 5, wherein patterning the substrate includes patterning the substrate to define a second trench, the second trench having a sidewall and extending at least partially through the first doped region, and during forming the second doped region, substantially no dopant is introduced into the second semiconductor pillar immediately adjacent to the second trench. The process may further include forming a gate dielectric layer along a sidewall of the second trench, forming a gate electrode in the second trench, the gate dielectric layer being disposed between the gate electrode and the sidewall of the second trench, forming a body region overlying the first doped region and along a sidewall of the second trench, forming a current carrying region adjacent to the second trench, and forming a second contact to the body region and the current carrying region. In the completed device, the body region may extend to the sidewalls of the second trench, and the body region, gate dielectric layer, gate electrode, and current carrying region may be part of a transistor structure.

[0098] Embodiment 12. The process of embodiment 11 may further include forming a first insulating layer along the sidewalls and bottom of the first trench and along the sidewalls and bottom of the second trench, forming a first shield electrode in the first trench and a second shield electrode in the second trench, forming a second insulating layer on the first shield electrode and forming a third insulating layer on the second shield electrode, where forming the second insulating layer and forming the third insulating layer are performed before forming the gate dielectric layer. In the completed device, the first contact, the second contact, the first shield electrode, the second shield electrode, and the current carrying region may be electrically connected to each other, the second doped region and the third doped region are part of a component structure, the component structure may be at least a portion of a component, the transistor structure may be at least a portion of a power transistor, and the area occupied by the component may be in the range of 5% to 30% of the combined area occupied by the component and the power transistor.

[0099] Embodiment 13. The process of embodiment 11, wherein the second doped region and the third doped region are part of a component structure, the component structure is at least a portion of a component, the transistor structure is at least a portion of a transistor, and the area occupied by the component is within the range of 5% to 30% of the combined area occupied by the component and the transistor.

[0100] Embodiment 14. A process for forming an electronic device may include: patterning a substrate, the substrate including a first doped region having a first conductivity type, to define a first trench having a first trench depth, the first trench having sidewalls and extending at least partially through the first doped region; and patterning the substrate to define an opening having an opening depth. The opening may have sidewalls and extend into the first doped region, the opening may overlie a first portion of the first doped region, and the opening may be spaced from the first trench by a second portion of the first doped region. The process may further include forming a second doped region adjacent a sidewall of the opening, the second doped region having a second conductivity type opposite the first conductivity type, and forming a first contact to the second doped region. In the completed device, the third portion of the first doped region can be disposed along a sidewall of the first trench at an elevation above the lowest point of the second doped region, and the third portion of the first doped region can be along a current path between the first portion of the first doped region and the first contact.

[0101] Embodiment 15. The process of embodiment 14, wherein forming the second doped region is performed using an oblique angle implant.

[0102] Embodiment 16 The process of embodiment 14, wherein the second doped region contacts a sidewall of the first trench.

[0103] Embodiment 17. The process of any one of embodiments 14 to 16 may further include forming an insulating layer in the first trench; forming a first portion of a first electrode in the first trench, the insulating layer being disposed between a sidewall of the first trench and the first portion of the first electrode; forming a dielectric layer in the first trench, the dielectric layer being thinner than the insulating layer; and forming a second portion of the first electrode in the first trench, the dielectric layer being disposed between a sidewall of the first trench and the second portion of the first electrode, the second portion of the first electrode being in contact with the first portion of the first electrode.

[0104] Embodiment 18. The process described in embodiment 17 may further include forming a first current carrying region adjacent to the first trench and electrically connected to the first contact, and in the completed device, the second doped region, the dielectric layer, and the first current carrying region may be part of a component structure.

[0105] Embodiment 19. The process of embodiment 18, wherein patterning the substrate includes patterning the substrate to define a second trench, the second trench having sidewalls and extending at least partially through the first doped region. The process may further include forming a gate dielectric layer along the sidewalls of the second trench, forming a gate electrode in the second trench, the gate dielectric layer being disposed between the gate electrode and the sidewalls of the second trench, forming a body region in the semiconductor pillar immediately adjacent to the second trench, the body region extending to the sidewalls of the second trench, the body region having a second conductivity type, forming a second current carrying region adjacent to the second trench, and forming a second contact to the body region and the second current carrying region. In the completed device, the body region, the gate dielectric layer, the gate electrode, and the second current carrying region may be part of a transistor structure.

[0106] Embodiment 20. The process of embodiment 19, wherein the first current carrying region is at least a portion of a first terminal of a component structure, the second current carrying region is at least a portion of a source of a transistor structure, the first terminal of the component structure, the first electrode of the component structure, and the source of the transistor structure are electrically connected to each other, the gate electrode of the transistor structure is electrically connected to a control terminal of the transistor structure, and the second terminal of the component structure and the drain of the transistor structure are electrically connected to each other.

[0107] It should be noted that not all of the operations described above in the general description or in the examples may be required, some of the specific operations may not be required, and one or more additional operations may be performed in addition to those described. Furthermore, the order in which the operations are listed is not necessarily the order in which they are performed.

[0108] Benefits, other advantages, and solutions to problems have been described above with respect to certain embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may give rise to or make more prominent any benefit, advantage, or solution should not be construed as a critical, required, or essential feature of any or all of the claims.

[0109] The detailed descriptions and illustrations of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. The detailed descriptions and illustrations are not intended to serve as an exhaustive and comprehensive description of all of the elements and features of the apparatus and systems that use the structures or methods described herein. Separate embodiments may be provided in combination in a single embodiment, and conversely, various features that are described for brevity in the context of a single embodiment may be provided separately or in any subcombination. Furthermore, references to values ​​described in ranges include each and every value within that range. Many other embodiments may become apparent to those skilled in the art only after reading this specification. Other embodiments may be used and derived from this disclosure, such that structural substitutions, logical substitutions, or other changes may be made without departing from the scope of this disclosure. Thus, this disclosure should be considered as illustrative and not limiting.

Claims

1. 1. A process for forming an electronic device, comprising: patterning a substrate (310), the substrate including a first doped region (350) having a first conductivity type, to define a first trench (440), the first trench extending at least partially through the first doped region; forming a second doped region (644, 1884) within the first semiconductor pillar (442) and along a sidewall of the first trench, the second doped region (644, 1884) having the first conductivity type; forming a third doped region (780, 1880) in the first semiconductor pillar, the third doped region (780, 1880) having a second conductivity type opposite the first conductivity type; forming a first contact (836, 1536, 1836) to the third doped region; Including, In the completed device, the second doped region and the third doped region overlie the first doped region; at least a portion of the third doped region is spaced from the sidewall of the first semiconductor pillar by the second doped region; The process wherein the second doped region is along a current path between the first doped region and the first contact.

2. forming an insulating layer (522) along the sidewalls and bottom of the first trench; forming a shield electrode (524, 2054) in the first trench, the insulating layer being disposed between the substrate and the shield electrode; The process of claim 1 further comprising:

3. The process of claim 2 , wherein forming the insulating layer and forming the shield electrode are performed before forming the second doped region.

4. The process of claim 1 , wherein the second doped region is discontinuous along the sidewall of the first trench.

5. The process of claim 1 , wherein forming the second doped region is performed using an oblique angle implant.

6. forming a dielectric layer (544) along the sidewalls of the first trench prior to forming the second doped region; forming a first electrode (744, 2054) in the first trench after forming the second doped region; The process of claim 1 , further comprising:

7. The process of claim 6 , wherein in the completed device, the second doped region, the third doped region, the dielectric layer, and the first electrode are part of a component structure.

8. forming a current carrying region (726) overlying the third doped region and in contact with the second doped region; forming a first contact opening (816, 1816) extending into the third doped region; forming a doped contact region (826, 1880) in the third doped region and along a surface of the first contact opening; Further comprising: forming the first contact is performed such that an ohmic contact is formed to the third doped region and to the current carrying region.

8. The process of claim 7.

9. 7. The process of claim 6, wherein in the completed device, a Schottky contact (1536) is made to the second doped region.

10. Forming the second doped region may be such that in the completed device, the second doped region has a dopant density of 1×10 １６ atoms / cm ３ ~9x10 １７ atoms / cm ３ 10. The process of claim 9, wherein the process is carried out to have an average dopant concentration in the range of:

11. patterning the substrate includes patterning the substrate to define a second trench (420), the second trench having sidewalls and extending at least partially through the first doped region; during formation of the second doped region, substantially no dopant is introduced into a second semiconductor pillar (422) immediately adjacent the second trench; The process comprising: forming a gate dielectric layer (544) along the sidewalls of the second trench; forming a gate electrode (724) in the second trench, the gate dielectric layer being disposed between the gate electrode and the sidewall of the second trench; forming a body region (770) overlying the first doped region and along a sidewall of the second trench; forming a current carrying region (726) adjacent the second trench; forming a second contact (836) to the body region and to the current carrying region (726); Further comprising: In the completed device, the body region extends to the sidewall of the second trench; the body region, the gate dielectric layer, the gate electrode, and the current carrying region are part of a transistor structure; 6. The process of any one of claims 1, 4 and 5.

12. forming a first insulating layer (522) along the sidewalls and bottom of the first trench and along the sidewalls and bottom of the second trench; forming a first shield electrode (524) in the first trench and a second shield electrode in the second trench; forming a second insulating layer (526) on the first shield electrode and a third insulating layer (526) on the second shield electrode, wherein forming the second insulating layer and forming the third insulating layer are performed before forming the gate dielectric layer; Further comprising: In the completed device, the first contact, the second contact, the first shield electrode, the second shield electrode, and the current carrying region are electrically connected to each other; the second doped region and the third doped region are part of a component structure; the component structure being at least a portion of a component (140); the transistor structure being at least part of a power transistor (120); the area occupied by the component is in the range of 5% to 30% of the combined area occupied by the component and the power transistor; 12. The process of claim 11.

13. the second doped region and the third doped region are part of a component structure; the component structure being at least a portion of a component (140); the transistor structure being at least a portion of a transistor (120); the area occupied by the component is within the range of 5% to 30% of the combined area occupied by the component and the transistor; 12. The process of claim 11.

14. 1. A process for forming an electronic device, comprising: patterning a substrate (310), the substrate including a first doped region (350) having a first conductivity type, to define a first trench (440) having a first trench depth, the first trench having sidewalls and extending at least partially through the first doped region; patterning the substrate to form an opening (1816) having an opening depth; the opening has a sidewall and extends into the first doped region; the opening overlies a first portion of the first doped region; the opening is spaced from the first trench by a second portion of the first doped region. Defining an opening (1816); forming a second doped region (1880) adjacent the sidewall of the opening, the second doped region having a second conductivity type opposite the first conductivity type; forming a first contact (1836) to the second doped region; Including, In the completed device, a third portion (1844) of the first doped region is disposed along the sidewall of the first trench at an elevation above a lowest point of the second doped region; the third portion of the first doped region is along a current path between the first portion of the first doped region and the first contact.

15. The process of claim 14 , wherein forming the second doped region is performed using an oblique angle implant.

16. The process of claim 14 , wherein the second doped region contacts the sidewall of the first trench.

17. forming an insulating layer (522) in the first trench; forming a first portion (2054) of a first electrode (2044) in the first trench, the insulating layer being disposed between the sidewall of the first trench and the first portion of the first electrode; forming a dielectric layer (544) in the first trench, the dielectric layer being thinner than the insulating layer; forming a second portion (2064) of the first electrode in the first trench, the dielectric layer being disposed between the sidewall of the first trench and the second portion of the first electrode, the second portion of the first electrode being in contact with the first portion of the first electrode; 17. The process of any one of claims 14 to 16, further comprising:

18. forming a first current carrying region (726) adjacent the first trench and electrically connected to the first contact; 20. The process of claim 17, wherein in the completed device, the second doped region, the dielectric layer, and the first current carrying region are part of a component structure.

19. patterning the substrate includes patterning the substrate to define a second trench (420), the second trench having sidewalls and extending at least partially through the first doped region; The process comprising: forming a gate dielectric layer (544) along the sidewalls of the second trench; forming a gate electrode (724) in the second trench, the gate dielectric layer being disposed between the gate electrode and the sidewall of the second trench; forming a body region (770) in the semiconductor pillar (422) immediately adjacent to the second trench, the body region extending to a sidewall of the second trench, the body region having the second conductivity type; forming a second current carrying region (726) adjacent the second trench; forming a second contact (836) to the body region and to the second current carrying region; Further comprising:

20. The process of claim 18, wherein in the completed device, the body region, the gate dielectric layer, the gate electrode, and the second current carrying region are part of a transistor structure.

20. the first current carrying region being at least a portion of a first terminal of the component structure; the second current carrying region being at least a portion of a source of the transistor structure; the first terminal of the component structure, the first electrode of the component structure, and the source of the transistor structure are electrically connected to each other; the gate electrode of the transistor structure is electrically connected to a control terminal (104) of the transistor structure; 20. The process of claim 19, wherein the second terminal of the component structure and the drain of the transistor structure are electrically connected to each other.

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