Trench channel semiconductor device and related methods

Abstract

An implementation of a semiconductor device can include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material. The device can include a trench channel adjacent the trench and two doped pillars of a second conductivity type extending on either side of the first conductivity type doped pillar, and a ratio of a depth of each of the two second conductivity type doped pillars to a depth of the trench into the substrate material can be at least 1.6 to 1.

Description

[Technical field]

[0001] Aspects of the present specification relate generally to semiconductor devices, such as transistor devices. More specific implementations include power semiconductor devices. [Background technology]

[0002] Semiconductor devices are formed within the material of a semiconductor substrate and are designed to control the flow of electricity in the form of current and / or flux through the semiconductor substrate. A wide variety of semiconductor devices have been devised to control the flow of electricity in a variety of ways and using a variety of control structures. Summary of the Invention

[0003] An implementation of a semiconductor device can include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material. The device can include a trench channel adjacent the trench and two doped pillars of a second conductivity type extending on either side of the first conductivity type doped pillar, and a ratio of a depth of each of the two second conductivity type doped pillars to a depth of the trench into the substrate material can be at least 1.6 to 1.

[0004] Semiconductor device implementations may include one, all or any of the following:

[0005] The first conductivity type doped pillar may be n-type doped with nitrogen, and the second conductivity type doped pillar may be p-type doped with aluminum.

[0006] The depth of each of the two p-type doped pillars may extend from 0.5 microns to more than 2 microns into the substrate material beyond the depth of the trench into the substrate material.

[0007] The substrate material may be silicon carbide.

[0008] The device may include p+ doped regions and n+ doped regions on either side of the trench adjacent to the trench channel.

[0009] The device may be comprised in two or more epitaxial layers of silicon carbide.

[0010] An implementation of a semiconductor device can include a trench including a gate and a gate oxide formed therein, the trench extending into an n-type doped pillar formed in a substrate material. The device may include a trench channel adjacent the trench and two p-type doped pillars extending into the substrate material on either side of the n-type doped pillar, each of the two p-type doped pillars including a first region adjacent the trench channel and a second region that may be wider than the first region.

[0011] Semiconductor device implementations may include one, all, or any of the following:

[0012] The n-type doped pillar may be doped with nitrogen and the two p-type doped pillars may be doped with aluminum.

[0013] The substrate material may be silicon carbide.

[0014] The device may include p+ doped regions and n+ doped regions on either side of the trench adjacent to the trench channel.

[0015] The device may be contained in two epitaxial layers of silicon carbide.

[0016] An implementation of a semiconductor device can include a trench including a gate and a gate oxide formed therein, the trench extending into an n-doped pillar formed in a substrate material, a trench channel adjacent the trench, and two p-doped pillars extending on either side of the n-doped pillar. The n-doped pillar can have a higher concentration of n-dopant than the concentration of n-dopant in the substrate material.

[0017] Semiconductor device implementations may include one, all, or any of the following:

[0018] The n-type doped pillar may be doped with nitrogen and the two p-type doped pillars may be doped with aluminum.

[0019] The substrate material may be silicon carbide.

[0020] The device may include where the n-type dopant concentration of the n-type doped pillars can be configured to tune the capacitance curve of the device.

[0021] The device may include p+ doped regions and n+ doped regions on either side of the trench adjacent to the trench channel.

[0022] The device may be contained in two epitaxial layers of silicon carbide.

[0023] An implementation of a semiconductor device can include a trench including a gate and a gate oxide formed therein, the trench extending into an n-type doped pillar formed in a substrate material. The device can include a trench channel adjacent the trench and two p-type doped pillars extending on either side of the n-type doped pillar. The n-type doped pillar can have a varying concentration of n-type dopant from a first portion adjacent the gate oxide to a second portion adjacent the substrate material.

[0024] Semiconductor device implementations may include one, all or any of the following:

[0025] The n-type doped pillar may be doped with nitrogen and the two p-type doped pillars may be doped with aluminum.

[0026] The substrate material may be silicon carbide.

[0027] The device may include where an n-type dopant concentration gradient increases from the first portion to the second portion.

[0028] The device may include a case where the n-type doping has a decreasing n-type dopant concentration from the first portion to the second portion.

[0029] The device may include p+ doped regions and n+ doped regions on either side of the trench adjacent to the trench channel.

[0030] The device may be contained in two epitaxial layers of silicon carbide.

[0031] An implementation of a method for forming a semiconductor device can include injecting a silicon carbide substrate with a p-type dopant to form a plurality of p-type doped regions in the silicon carbide substrate, injecting the silicon carbide substrate with an n-type dopant to form a plurality of n-type doped regions in the silicon carbide substrate, growing an epitaxial silicon carbide layer on the silicon carbide substrate after injecting the n-type dopant into the silicon carbide substrate, and injecting a p-type dopant to form a plurality of p-type doped pillars in the silicon carbide substrate after growing the epitaxial silicon carbide layer. The method can include injecting an n-type dopant to form a plurality of n-type doped pillars in the silicon carbide substrate, forming a plurality of trenches in the plurality of n-type doped pillars, depositing a gate oxide in the plurality of trenches, depositing a polysilicon oxide material in the plurality of trenches, and forming a plurality of contacts coupled to the polysilicon oxide material and the gate oxide.

[0032] Implementations of the method of forming a semiconductor device may include one, all, or any of the following.

[0033] Injecting a p-type dopant into the silicon carbide substrate to form a plurality of p-type doped regions in the silicon carbide substrate may further include first forming a hard mask pattern having a plurality of first openings with a first opening width before injecting the p-type dopant to form the plurality of p-type doped regions, and first forming a hard mask pattern having a plurality of second openings with a second opening width after growing the epitaxial silicon carbide layer and before injecting the p-type dopant to form the plurality of p-type doped pillars. The second opening width may be smaller than the first opening width.

[0034] Injecting the silicon carbide substrate with an n-type dopant to form a plurality of n-type doped regions in the silicon carbide substrate may further include implanting the n-type dopant a first predetermined number of times, and injecting the n-type dopant to form a plurality of n-type doped pillars in the silicon carbide substrate may further include implanting the n-type dopant a second predetermined number of times, where the first predetermined number of times may be greater than the second predetermined number of times.

[0035] Injecting the silicon carbide substrate with an n-type dopant to form a plurality of n-type doped regions in the silicon carbide substrate may further include implanting the n-type dopant a first predetermined number of times, and injecting the n-type dopant to form a plurality of n-type doped pillars in the silicon carbide substrate may further include implanting the n-type dopant a second predetermined number of times, where the first predetermined number of times may be less than the second predetermined number of times.

[0036] Injecting the silicon carbide substrate with an n-type dopant to form a plurality of n-type doped regions in the silicon carbide substrate may further include implanting the n-type dopant a first predetermined number of times, and injecting the n-type dopant to form a plurality of n-type doped pillars in the silicon carbide substrate may further include implanting the n-type dopant a second predetermined number of times, and the first predetermined number of times may be the same as the second predetermined number of times.

[0037] The method can include varying the capacitance curve using the n-type dopant concentration of the n-type doped pillars.

[0038] An implementation of a semiconductor device can include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material, a trench channel adjacent the trench, and two doped pillars of a second conductivity type extending on either side of the first conductivity type doped pillar, the depth of each of the two second conductivity type doped pillars extending 0.5 to 2 microns into the substrate material beyond the depth of the trench into the substrate material.

[0039] Semiconductor device implementations may include one, all, or any of the following:

[0040] The first conductivity type doped pillar may be n-type doped with nitrogen, and the two second conductivity type doped pillars may be p-type doped with aluminum.

[0041] The substrate material may be silicon carbide.

[0042] The device may include p+ doped regions and n+ doped regions on either side of the trench adjacent to the trench channel.

[0043] The device may be comprised in two or more epitaxial layers of silicon carbide.

[0044] These and other aspects, features, and advantages will be apparent to those skilled in the art from the detailed description and drawings, and from the claims. [Brief description of the drawings]

[0045] Implementations are described below in conjunction with the accompanying drawings, in which like numbers refer to like elements, and in which: [Figure 1]FIG. 1 is a cross-sectional view of one implementation of trench metal oxide semiconductor field effect transistors (MOSFETs). [Diagram 2] FIG. 2 is a detailed diagram of the trench MOSFET of FIG. 1. [Diagram 3] 2 is a cross-sectional view of a simulation of the electric field of the trench MOSFET of FIG. 1. [Figure 4] 4 is a one-dimensional electric field profile taken along section line HH in FIG. 3. [Diagram 5] FIG. 1 is a cross-sectional view of another implementation of a trench MOSFET. [Figure 6] FIG. 6 is a detailed cross-sectional view of the trench MOSFET shown in FIG. 5, showing section lines AA and BB. [Figure 7] 7 is a one-dimensional graph of dopant concentration with depth into the substrate at cross-sectional lines AA and BB of FIG. 6. [Figure 8] FIG. 1 is a flow diagram of one implementation of a method of forming an implementation of a trench MOSFET. [Figure 9] FIG. 2 is a detailed cross-sectional view of one implementation of a trench MOSFET as shown in FIG. [Figure 10] FIG. 6 is a detailed cross-sectional view of one implementation of a trench MOSFET as shown in FIG. [Figure 11] 11 is a detailed cross-sectional view of a simulation of an electric field of the trench MOSFET of FIG. 10 showing section line CC. [Figure 12] FIG. 12 is a detailed cross-sectional view of a simulation of the electric field of the trench MOSFET of FIG. 11 showing cross section DD. [Figure 13] FIG. 13 is a graph of absolute electric field with depth into the substrate for the trench MOSFET implementation shown in FIGS. 11 and 12, with a detailed view showing the electric field voltage at the corners of the oxide region. [Figure 14] FIG. 2 is a detailed cross-sectional view of one implementation of a trench MOSFET showing a p-type doping profile. [Figure 15]FIG. 13 is a detailed cross-sectional view of another implementation of a trench MOSFET showing an alternative p-type doping profile having a wider second portion. [Figure 16] FIG. 15 is a detailed cross-sectional view of a simulation of an electric field of the trench MOSFET of FIG. 14 showing section line II. [Figure 17] FIG. 16 is a detailed cross-sectional view of a simulation of an electric field of the trench MOSFET of FIG. 15 showing section line JJ. [Figure 18] 18 is a graph of absolute electric field at cross-sectional lines II and JJ with respect to depth into the substrate for the trench MOSFET implementations shown in FIGS. 16 and 17. [Figure 19] 18 is a graph of absolute electric field with drain voltage for the trench MOSFET implementations of FIGS. 16 and 17. [Figure 20] FIG. 2 is a detailed cross-sectional view of an implementation of a trench MOSFET having a first concentration of n-type doped pillars showing cross-section line EE. [Figure 21] FIG. 2 is a detailed cross-sectional view of an implementation of a trench MOSFET having a second concentration n-type doped pillar, showing section line FF. [Figure 22] FIG. 13 is a detailed cross-sectional view of an implementation of a trench MOSFET having a third concentration of n-type doped pillars, showing section line GG. [Diagram 23] 24 is a graph of one-dimensional dopant concentration for the trench MOSFET implementations of FIGS. 21-23 along cross-sectional lines EE, FF, and GG. [Figure 24] 24 is a graph of absolute electric field versus drain voltage for the three trench MOSFET implementations of FIGS. 21-23. [Diagram 25] 1 is a graphical representation of a detailed view of an implementation of a trench MOSFET having a substantially constant n-type dopant concentration in the n-type doped pillars showing cross-section line KK. [Figure 26] 1 is a graph of a detailed view of an implementation of a trench MOSFET having an increasing n-type dopant profile into the substrate showing the cross-section line LL. [Figure 27]FIG. 1 is a graphical representation of a detailed view of an implementation of a trench MOSFET with a decreasing n-type dopant profile into the substrate showing cross section MM. [Figure 28] 29 is a graph of one-dimensional n-type dopant concentration as a function of depth into the substrate for the trench MOSFET implementations of FIGS. 26-28 at cross-sectional lines KK, LL, and MM. [Figure 29] FIG. 2 is a three-dimensional cross-sectional view of one implementation of a trench MOSFET after gate oxide growth. [Diagram 30] FIG. 30 is a three-dimensional cross-sectional view of an implementation of the trench MOSFET of FIG. 29 showing only the silicon carbide portion. [Diagram 31] FIG. 30 is a detailed view of the three-dimensional cross-section of FIG. 29. [Diagram 32] FIG. 31 is a detailed view of the three-dimensional cross section of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] The present disclosure, its aspects and implementations are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and / or method elements known in the art consistent with the intended trench channel semiconductor devices for use with specific implementations from the present disclosure will become apparent. Thus, for example, although specific implementations are disclosed, such implementations and implementation components can include any shape, size, style, type, model, version, dimension, concentration, material, amount, method element, step, etc., as known in the art for such trench channel semiconductor devices and implementation components and methods consistent with the intended operation and method.

[0047] Referring to FIG. 1, a cross-sectional view of one implementation of a trench channel semiconductor device 2 is shown. As shown, the device 2 is formed on a substrate (substrate material) 4, which in this case is a silicon carbide substrate. An epitaxial layer 6 of silicon carbide is grown on the substrate 4. In a particular implementation, the epitaxial layer is a single layer and is grown to a height / thickness of about 10 microns on the substrate 4 doped with a dopant of a first conductivity type. In this implementation, the first conductivity type is 9.5×10 15 / cm 3 A trench 8 is formed in the epitaxial layer 6 material. Referring to FIG. 2, a detailed view of the device implementation of FIG. 1, a gate oxide 10 is deposited over the trench and a polysilicon gate material 12 is deposited within the trench. The device 2 is designed to be a trench metal oxide semiconductor field effect transistor (trench MOSFET) and, in the implementation shown, is designed as a power semiconductor device capable of handling 1200V. The advantage of using a trench channel MOSFET design in power semiconductor device applications is that such devices can have lower Rdson and less switching losses due to better channel mobility coupled with a smaller cell pitch compared to a planar channel MOSFET design. However, the trench design creates an operating condition where the corner oxide 14 experiences a very large electric field when the device is operated in reverse bias mode using silicon carbide due to the higher critical electric field value that silicon carbide has. Due to the electric field crowding on the corner oxide, the breakdown voltage of the trench MOSFET may not be sufficient to meet the 1200V design requirement without the aid of other device protection due to corner oxide breakdown.

[0048] Referring to Figure 3, a cross-sectional view of a simulation of the electric field profile in the structure shown in Figure 2 with section line HH is shown, showing the circled area with the maximum magnitude of the absolute electric field. Figure 4 shows the one-dimensional electric field along section line HH with depth into the substrate material, showing a spike in the absolute electric field corresponding to the top surface of corner oxide 14. Due to the strength of the spike, the breakdown voltage of the device shown in Figures 1 and 2 is only 754V, which means that a secondary protection needs to be provided for this device during operation at 1200V to prevent destruction of the device in reverse bias mode.

[0049] Referring to FIG. 5, another implementation of a trench MOSFET 16 designed to also operate at 1200V is shown. Similar to the device of FIG. 1, the device 16 is formed on a silicon carbide substrate 18 on which an epitaxial layer 20 is grown that is about 10 microns thick. However, referring to FIG. 6, an additional / second epitaxial layer 22 (regrowth layer) is grown on the epitaxial layer 20 that is about 1 micron thick, as shown by the indicator line 24 in FIG. 6. In various implementations, this layer may be thicker or thinner than a micron, depending on the electrical properties of the device to be formed. In some implementations, the layer may be 2 microns, 3 microns, or more microns thick. In various method implementations, multiple regrown layers can be formed on top of each other to reach the desired second epitaxial layer thickness (and the desired pillar depth of the second conductivity type into the material of the substrate, as will be further described).

[0050] Pillars of a first conductivity type material are represented by pillars of a second conductivity type material. In the implementation shown in FIG. 5, the first conductivity type is an n-type doped material (n-type doped pillar) 26 surrounded on either side by pillars of a second conductivity type, p-type doped material (p-type doped pillar) 28, both formed using ion implantation during processing, as described below. However, in various implementations, the first conductivity type may be an n-type doped material and the second conductivity type may be a p-type doped material. As used herein, the term "pillar" is used for simplicity of description to describe the cross-sectional appearance of the implanted structure. However, in reality, the pillar structure appears as alternating n-type and p-type doped protrusion- or trench-shaped doped regions 30, 32, respectively, in the material of the substrate, as shown in the three-dimensional views of the structures in FIGS. 29-32. However, for ease of reference to cross-sectional views, the structures are referred to herein as "pillars" with the understanding that the three-dimensional structures appear as protrusions (for n-type) or trenches (for p-type).

[0051] 6, a trench 34 is formed in the material of the second epitaxial layer 22 into which a gate oxide 36 and a gate material 38 are deposited. In the implementation shown in FIG. 6, the trench 34 extends only into the material of the second epitaxial layer 22, although in other implementations the trench 34 may extend into the material of the first epitaxial layer 20. The trench 34 extends into the material of the n-doped pillar 26 to form p-doped trench channels 40 on either side of the trench 34. In the implementation shown in FIG. 6, an additional p + Doped region 42 and n + A doped region 44 is also included above the trench channel 40, although in other implementations one or both of these regions may not be included.

[0052] As used herein, the depth of a pillar of material of a given conductivity type into a material is defined as the point (or line of points) into the material where the last peak of concentration of the dopant material concentration is observed. Note that in this implementation, the difference between the lowest point of the depth of the trench 34 and the depth of the p-doped pillar 28 into the material of the first and second epitaxial layers may be about 0.5 microns to about 2 microns or more. In some implementations, the ratio between the depth of the p-doped pillar and the depth of the trench may be about 1.6:1 to 2:1. In other implementations, the ratio between the depth of the p-doped pillar and the depth of the trench may be greater than 2:1. In various implementations, there may be no theoretical upper limit to this ratio, since the described methods of forming one or more regrown layers essentially allow for the formation of a desired number of doped regrown layers. This can be a distinct advantage of this technique when used with silicon carbide substrates, since the difficulties observed in doping silicon carbide material to a desired depth can be substantially reduced simply by using multiple doped regrown layers. In the implementation shown in Figures 5 and 6, the n-type dopant is nitrogen and the p-type dopant is aluminum. Both the first and second epitaxial layers 1 and 2 are doped with approximately 9 x 10 15 / cm 3 The doping levels of both epitaxial layers are the same in the illustrated implementation, but in other implementations the doping levels may be different for each layer.

[0053] 6 and 7, the one-dimensional (in-plane) n-type dopant concentration along cross-sectional line AA and the p-type dopant concentration along cross-sectional line BB are shown. As shown, the concentration of n-type dopant is substantially constant at a first distance into the material of the substrate until the last peak of dopant concentration is observed (at about 2.1 microns for n-type dopant), and the concentration of p-type dopant is substantially constant at a second distance into the material of the substrate until the last peak of dopant concentration is observed (at about 1.95 microns). FIG. 7 is a graph showing a particular dopant concentration (represented using a logarithmic scale on the Y-axis) versus depth for a particular implementation. Other dopant concentration profiles are possible depending on the desired depth of each dopant into the material of the substrate. As can be observed from the lines in FIG. 7, the concentration of n-type dopant in the n-type doped pillar and in the p-type doped pillar is substantially constant in the implementation shown in FIG. 5.

[0054] Referring to Figure 9, a detailed cross-sectional view of one implementation of a trench MOSFET without pillar structures (such as that shown in Figure 1) is shown. Figure 10 shows a detailed cross-sectional view of another implementation of a trench MOSFET with pillar structures (n-type doped 46 and p-type doped 48). Figure 11 is a corresponding electric field simulation of the implementation of Figure 10 at a breakdown voltage condition with depth into the material, showing a section line CC located across a corner oxide region 50 where the maximum electric field is experienced. Figure 12 is a corresponding electric field simulation of the implementation of Figure 11 also at a breakdown voltage condition, with a section line DD located across a corner oxide region 52 showing the circled location of the maximum electric field.

[0055] Figure 13 is a graph of absolute electric field with depth into the substrate along section lines CC and DD. The breakdown voltage of the implementation of Figure 9 is 754V, or more than twice as high, as compared to the breakdown voltage of the implementation of Figure 10, which is 1566V. The detailed graph at the top right shows an enlarged version of the larger graph, which illustrates how the maximum electric field experienced at the corner oxide region 52 for the pillar version of the device is nearly 50% less than the field experienced by the corner oxide region 50 of the non-pillar device, and thus may be a strong factor contributing to the over 50% increase in the breakdown voltage of the pillar device.

[0056] Referring to FIG. 14, a detailed cross-sectional view of a trench MOSFET device 54 similar to the implementation shown in FIG. 10 is shown. As with other previously disclosed pillar-containing implementations disclosed herein, the concentration of p-type dopants in the p-type doped pillar 56 is substantially constant. Referring to FIG. 15, another implementation of a trench MOSFET device 58 is shown having a p-type doped pillar 68 with a first / top portion 60 and a second / bottom portion 62. As shown, the top portion 60 has a first width 64 into the material adjacent the trench channel of the first two epitaxial layers, and the bottom portion 62 has a second width 66 that is wider than the first width 64 into the material of the first two epitaxial layers when viewed in cross section. In FIG. 15, the detail view approximately bisects the full width of the pillar, so that the dopant profile on the left side of the p-type doped pillar 68 is substantially a mirror image of the dopant profile on the right side. 16 and 17 are electric field simulation graphs at the breakdown condition for the trench MOSFET devices of FIGS. 14 and 15, respectively, showing cross-section lines II and JJ and the circled regions of highest electric field.

[0057] Referring to FIG. 18, a graph of absolute electric field with depth into the substrate is shown, illustrating the electric field experienced by the corner oxide regions 70, 72 (see FIGS. 16-17) at breakdown along section lines II and JJ. The breakdown voltage of device 54 of FIG. 14 is 1566V, and the breakdown voltage of device 58 of FIG. 15 is 1570V. As the detailed view shows, the use of a wider bottom p-pillar design allows the maximum electric field experienced by corner oxide 72 to be approximately 33% less than the maximum electric field experienced by corner oxide 70. Thus, a wider bottom p-pillar design can be used to further reduce the maximum oxide field during stable operation in reverse blocking mode. Additionally, the use of different implant aperture widths during fabrication of the p-doped pillars (described later in this specification) can be used to control the shape of the capacitance curve of the trench MOSFET device, thereby controlling the switching performance of the device. The effect of the wider bottom p-type doped pillar on the capacitance curves plotted on a logarithmic scale for both absolute electric field and drain voltage (both in V) for device implementations 54 and 58 is shown in the simulated absolute electric field versus drain voltage graph shown in FIG. 19, which shows the effect on the input capacitance (Ciss), reverse transfer capacitance (Crss), and output capacitance (Coss) curves.

[0058] 20-22, three implementations of trench MOSFETs 74, 76, 78 are shown having different but substantially constant n-type doping of their respective n-type doped pillars 80, 82, 84. As shown, the n-type doping of the n-type doped pillars 80, 82, 84 are each a first dopant level, a second dopant level higher than the first dopant level, and a third dopant level higher than the first and second dopant levels. By way of non-limiting example, the n-type doping of the pillars 80, 82, 84 is approximately 1×10 16 ~Approx. 5×10 17 / cm 3Various n-dopant concentrations, such as 1000 n-doped pillars 80, 82, 84, ...

[0059] In various trench MOSFET implementations, the concentration of n-type dopant in the n-type doped pillar can vary along the length / distance / direction of the pillar into the material of the first and second epitaxial layers. With reference to FIG. 25, an implementation of a trench MOSFET implementation 86 is shown with an n-doped pillar 88 having a substantially constant concentration of n-type dopant showing the cross-section line KK. With reference to FIG. 26, an implementation of a trench MOSFET implementation 90 is shown with an n-doped pillar 92 having an increasing profile or concentration gradient of n-type dopant that increases as the pillar extends into the material of the first and second epitaxial layers (substrate). FIG. 27 shows an implementation of a trench MOSFET 94 having an n-doped pillar 96 having a decreasing profile or concentration gradient of n-type dopant that decreases as the pillar extends into the material of the first and second epitaxial layers (substrate). 28 shows the one-dimensional (in-plane) logarithm of the concentration gradient of the n-type dopant within each n-doped pillar 88, 92, 96, showing constant, increasing, and decreasing profiles within the depth of the material, respectively. The ability to create a concentration gradient of the n-type dopant within the n-doped pillars within the material can allow for tuning the trench MOSFET to operate more stably in reverse blocking mode and / or tailoring the capacitance curve to improve switching performance.

[0060] The various trench MOSFET device implementations illustrated herein can be fabricated using various methods of forming trench MOSFET devices. One of the main challenges of implanting dopants into silicon carbide is that the implants tend to be shallow compared to single crystal silicon, which requires high implantation energies (about 1.1 megaelectronvolts [MeV] required to implant to a depth of about 1 micron). In addition, dopants do not substantially diffuse into silicon carbide, so the use of drive-in and other techniques to move the dopants further in is not useful. Thus, it is very difficult to implant p-type dopants into silicon carbide beyond 2 microns. To do so, if the p-type dopant is aluminum, energies in excess of 2-3 MeV are required to form implants beyond 2 microns into the silicon carbide substrate. When doing this, a thick hardmask oxide (greater than 4 microns thick) is also required to protect the undoped regions, and the thickness of the oxide acts to limit the pitch of the transistor cells that can be fabricated and successfully doped, given the aspect ratio of the features that need to be doped. An angled channeling implant at 4 degrees from the plane of the substrate can be used, but because the c-face of the silicon carbide in most substrates is at a 4 degree angle from the plane of the silicon carbide substrate (as well as in many epitaxial silicon carbide layers grown), the ability to use angled implants to increase the depth of implantation is generally not significant enough to avoid having to use high implant energies.

[0061] Instead of using very high implant energies, implementations of the various methods disclosed herein use an intermediate epitaxial growth / regrowth process followed by another round of implantation to build implants into the silicon carbide that can exceed 2 microns in depth for both n-type and p-type dopants. The use of multiple regrowth layers also allows for the construction of successively implanted regions at any desired depth within the silicon carbide.

[0062] Referring to FIG. 8, a flow chart of a first implementation of a method for forming a trench MOSFET is shown. As shown, following the formation of an implant blocking pattern 98, a first p-type implant is performed to form a p-type doped region 100. The blocking pattern 98 may be formed from a photoresist material using a lithographic processing step and a photoresist, or may be formed from a hardmask material (oxide, nitride) formed from one or more layers designed to protect the masked regions from the implant (using corresponding additional photolithographic steps to pattern and etch the hardmask). In a particular implementation, the p-type dopant is aluminum.

[0063] Following completion of the first p-type implant, the blocking pattern 98 is removed and then a first n-type implant is performed to form an n-type doped region 104 in the material of the substrate, in this case the first epitaxial layer 106. In a particular implementation, the n-type dopant is nitrogen.

[0064] Following the first p-type implant and the first n-type implant, a second silicon carbide epitaxial growth process is performed to form a second epitaxial layer 108 over the first epitaxial layer 106 and over the p-type doped region 100 and the n-type doped region 104. In a particular implementation, the second epitaxial layer has a dopant concentration of 9.5×10 when the n-type dopant is nitrogen. 15 / cm 3 The second epitaxial layer can be grown to a thickness of about 1 micron with an n-type dopant concentration of 10 ...

[0065] Following the growth of the second epitaxial layer 108, a second blocking layer 110 is formed over the n-type doped region 104, and a second p-type implant is performed into the p-type doped region 100 to form p-type doped pillars 112 in the second epitaxial layer 108 and the first epitaxial layer 106. In a particular implementation, the second p-type implant is performed when aluminum is the dopant. Following the second p-type implant, the second blocking layer 110 is removed and a second n-type implant is performed into the n-type doped region to form the n-type doped pillars 116, as shown in FIG. 8. In a particular implementation, the second n-type implant can use nitrogen as a dopant. The effect of performing an n-type implant is that the n-type doped pillars 116 have a higher concentration of n-type dopants than the materials of the first epitaxial layer 106, the second epitaxial layer 108, and / or the substrate itself in various implementations. Multiple epitaxial regrowth steps followed by additional n-type and p-type doping steps to form variously doped pillars can be used in various method implementations.

[0066] Following the second n-type implant, a p-type implant 118 is performed across the surface of the substrate to establish the depth that will become the trench channel. + An implant is performed to establish the upper boundary of the trench channel structure. + Region 120 is formed, followed by the formation of third blocking layer 122. Next, p + The injection is performed and p + Region 124 is formed, followed by removal of third blocking layer 122.

[0067] A trench patterning layer 126 is then formed using any of the patterning materials using any of the patterning techniques disclosed herein. A trench 130 is then formed using an etching process (wet, dry, etc.) down to the material of the n-type doped pillar 116, forming a trench channel 132 on either side of the trench 130. Following removal of the trench patterning layer 126, a gate oxide 134 is formed on the surface of the substrate down into the trench 130. In a particular implementation, the gate oxide is silicon dioxide. Next, most of each trench is filled with a gate material 136, which in a particular implementation is polysilicon. The polysilicon can be grown using a chemical vapor deposition process followed by an etch-back or chemical mechanical planarization (CMP) polishing / grinding process to remove excess polysilicon from the surface of the substrate, in various implementations. Additional oxide is then grown over and into the trench 130, and an etching process is used to form contact regions 140 between the oxides 138. Following the formation of the oxide, metal 142 is then deposited over the oxide and formed into the desired pattern (using additional photolithography and etching steps as necessary) to allow the gates of the various trench MOSFETs to be electrically connected and routed as desired.

[0068] The above method can be modified using more or fewer successive n-type dopant implants to increase or decrease the amount of n-type dopant in the n-type doped pillars 116. The method can also be modified by changing the dopant dose received during one or more of the successively applied n-type dopant implants to produce n-type doped pillars with different constant n-type dopant concentrations or increasing or decreasing dopant profiles. The same principles can be used to control the p-type doping of the p-type doped pillars to produce a constant varying concentration in the pillar or an increasing or decreasing p-type dopant concentration along the length of the p-type doped pillars 112.

[0069] The implementation of the method described above can be modified in various implementations. For example, the initial process of growing the second epitaxial layer 148 after forming the p-type doped region 144 and the n-type doped region 146 may be the same as the implementation of the method of FIG. 8, except that the first spacing between the patterned elements of the first blocking layer is wider than the spacing between the patterned elements of the second blocking layer. The narrower spacing results in the formation of a second region in the p-type doped pillar in the material of the substrate that is wider than the width of the first region. As shown, the remaining processing steps in the method are the same as those previously described in the implementation of the method of FIG. 8, resulting in the formation of a trench MOSFET device having a wider bottom portion for the p-type doped pillar. Those skilled in the art will be able to readily apply the principles disclosed herein to form various methods of forming trench MOSFET devices such as those disclosed herein.

[0070] Figures 29-32 show three-dimensional versions of a trench MOSFET device at two intermediate steps in its fabrication. Figures 29 and 31 show the case where a gate oxide 162 has been applied. Figures 30 and 32 show the case where no oxide is present, with the p +The location of the pattern of regions 166 is shown. The particular device shown in Figures 29-32 is a striped cell. However, the principles herein can be readily applied by one skilled in the art to other trench MOSFET device types, including, by way of non-limiting example, rectangular designs, hexagonal designs, and any other MOSFET device arrangements / configurations. Also, while the trench MOSFET device structures disclosed herein focus on those in which the trenches are formed in n-type doped pillars and the epitaxial layer is n-type doped, the same principles can be applied to devices in which the trenches are formed in p-type doped pillars and the epitaxial layer is p-type doped.

[0071] Where the above description refers to particular implementations and implementation components, sub-components, methods and sub-methods of trench channel devices, it will be readily apparent that certain modifications may be made without departing from the spirit thereof, and that these implementations, implementation components, sub-components, methods and sub-methods may be applied to other trench channel devices.

Claims

1. a trench having a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material; a trench channel adjacent to the trench; two doped pillars of a second conductivity type extending on either side of the first conductivity type doped pillar, the ratio of the depth of each of the two second conductivity type doped pillars to the depth of the trench into the substrate material being at least 1.6 to 1; A semiconductor device comprising:

2. 2. The device of claim 1, wherein the first conductivity type doped pillar is n-type doped with nitrogen and the second conductivity type doped pillar is p-type doped with aluminum.

3. 3. The device of claim 2, wherein the depth of each of the two p-type doped pillars extends from 0.5 microns to more than 2 microns into the substrate material beyond the depth of the trench into the substrate material.

4. The device of claim 1 , wherein the substrate material is silicon carbide.

5. p on both sides of the trench adjacent to the trench channel ＋ Doped regions and n ＋ The device of claim 1 further comprising a doped region.

6. The device of claim 1 , wherein the device is comprised in two or more epitaxial layers of silicon carbide.

7. a trench having a gate and a gate oxide formed therein, the trench extending into an n-type doped pillar formed in a substrate material; a trench channel adjacent to the trench; two p-type doped pillars extending into the substrate material on either side of the n-type doped pillar, each of the two p-type doped pillars comprising a first region adjacent the trench channel and a second region wider than the first region; A semiconductor device comprising:

8. 8. The device of claim 7, wherein the n-type doped pillar is doped with nitrogen and the two p-type doped pillars are doped with aluminum.

9. The device of claim 7 , wherein the substrate material is silicon carbide.

10. p on both sides of the trench adjacent to the trench channel ＋ Doped regions and n ＋ The device of claim 7 further comprising a doped region.

11. The device of claim 7 , wherein the device is comprised in two epitaxial layers of silicon carbide.

12. a trench having a gate and a gate oxide formed therein, the trench extending into an n-type doped pillar formed in a substrate material; a trench channel adjacent to the trench; two p-doped pillars extending on either side of the n-doped pillar; Equipped with the n-type doped pillars have a concentration of n-type dopant that is greater than a concentration of n-type dopant in the substrate material; Semiconductor device.

13. The device of claim 12 , wherein the n-type doped pillar is doped with nitrogen and the two p-type doped pillars are doped with aluminum.

14. The device of claim 12 , wherein the substrate material is silicon carbide.

15. The device of claim 12 , wherein an n-type dopant concentration of the n-type doped pillars is configured to tune a capacitance curve of the device.

16. p on both sides of the trench adjacent to the trench channel ＋ Doped regions and n ＋ The device of claim 12 further comprising a doped region.

17. The device of claim 12 , wherein the device is comprised in two epitaxial layers of silicon carbide.

18. a trench having a gate and a gate oxide formed therein, the trench extending into an n-type doped pillar formed in a substrate material; a trench channel adjacent to the trench; two p-doped pillars extending on either side of the n-doped pillar; Equipped with the n-type doped pillar having a varying concentration of n-type dopant from a first portion adjacent the gate oxide to a second portion adjacent the substrate material. Semiconductor device.

19. 20. The device of claim 18, wherein the n-type doped pillar is doped with nitrogen and the two p-type doped pillars are doped with aluminum.

20. The device of claim 18 , wherein the substrate material is silicon carbide.

21. 20. The device of claim 18, wherein an n-type dopant concentration gradient increases from the first portion to the second portion.

22. 20. The device of claim 18, wherein the n-type doping has an n-type dopant concentration that decreases from the first portion to the second portion.

23. p on both sides of the trench adjacent to the trench channel ＋ Doped regions and n ＋ 20. The device of claim 18 further comprising a doped region.

24. The device of claim 18 , wherein the device is comprised in two epitaxial layers of silicon carbide.

25. 1. A method of forming a semiconductor device, comprising: implanting a silicon carbide substrate with p-type dopants to form a plurality of p-type doped regions within the silicon carbide substrate; implanting the silicon carbide with an n-type dopant to form a plurality of n-type doped regions in the silicon carbide substrate; growing an epitaxial silicon carbide layer on the silicon carbide substrate after implanting the silicon carbide substrate with the n-type dopant; implanting a p-type dopant after growing the epitaxial silicon carbide layer to form a plurality of p-type doped pillars in the silicon carbide substrate; implanting an n-type dopant to form a plurality of n-type doped pillars in the silicon carbide substrate; forming a plurality of trenches within the plurality of n-type doped pillars; depositing a gate oxide in the plurality of trenches; depositing a polysilicon oxide material into the plurality of trenches; forming a plurality of contacts coupled to the polysilicon oxide material and to the gate oxide; A method comprising:

26. implanting the silicon carbide substrate with the p-type dopants to form the plurality of p-type doped regions in the silicon carbide substrate; prior to implanting the p-type dopant to form the plurality of p-type doped regions, first forming a hard mask pattern having a plurality of first openings with a first opening width; after growing the epitaxial silicon carbide layer and before implanting the p-type dopant to form a plurality of p-type doped pillars, first forming a hard mask pattern having a plurality of second openings with a second opening width; Further comprising: The second opening width is smaller than the first opening width.

26. The method of claim 25.

27. implanting the silicon carbide substrate with the n-type dopant to form the plurality of n-type doped regions in the silicon carbide substrate further comprises implanting the n-type dopant a first predetermined number of times; implanting the n-type dopant to form the plurality of n-type doped pillars in the silicon carbide substrate further comprises implanting the n-type dopant a second predetermined number of times; The first predetermined number of times is greater than the second predetermined number of times.

26. The method of claim 25.

28. implanting the silicon carbide substrate with the n-type dopant to form the plurality of n-type doped regions in the silicon carbide substrate further comprises implanting the n-type dopant a first predetermined number of times; implanting the n-type dopant to form the plurality of n-type doped pillars in the silicon carbide substrate further comprises implanting the n-type dopant a second predetermined number of times; The first predetermined number of times is less than the second predetermined number of times.

26. The method of claim 25.

29. implanting the silicon carbide substrate with the n-type dopant to form the plurality of n-type doped regions in the silicon carbide substrate further comprises implanting the n-type dopant a first predetermined number of times; implanting the n-type dopant to form the plurality of n-type doped pillars in the silicon carbide substrate further comprises implanting the n-type dopant a second predetermined number of times; The first predetermined number of times is the same as the second predetermined number of times.

26. The method of claim 25.

30. 26. The method of claim 25, further comprising using the n-type dopant concentration of the n-type doped pillar to vary a capacitance curve.

31. a trench having a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material; a trench channel adjacent to the trench; two doped pillars of a second conductivity type extending on either side of the first conductivity type doped pillar, the depth of each of the two second conductivity type doped pillars extending 0.5 to 2 microns into the substrate material beyond the depth of the trench into the substrate material; A semiconductor device comprising:

32. 32. The device of claim 31 , wherein the first conductivity type doped pillar is n-type doped with nitrogen and the two second conductivity type doped pillars are p-type doped with aluminum.

33. 32. The device of claim 31 , wherein the substrate material is silicon carbide.

34. p on both sides of the trench adjacent to the trench channel ＋ Doped regions and n ＋ 32. The device of claim 31 further comprising a doped region.

35. 32. The device of claim 31 , wherein the device is comprised in two or more epitaxial layers of silicon carbide.

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