Method for forming a semiconductor device with air gaps for low capacitance wiring - Patents.com
JP2025507101APending Publication Date: 2025-03-13TOKYO ELECTRON LTD +1
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Patent Information
- Application Number
- JP2024553461
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-03-08
- Filing Date
- 2023-03-07
- Publication Date
- 2025-03-13
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Figure 2025507101000001_ABST
Abstract
A method for forming a semiconductor device with air gaps for low capacitance wiring is provided. The method includes providing a substrate including raised metal features having upper regions and sidewalls and voids between the raised metal features, filling the voids with a sacrificial fill material, and selectively depositing a blocking layer over the sacrificial fill material. The method further includes depositing a cap layer over the upper regions of the raised metal features, the cap layer having an overhang that extends beyond the sidewalls, removing the blocking layer and the sacrificial fill material between the raised metal features, and depositing a dielectric film, the dielectric film forming an air gap between the raised metal features below the overhang.
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