Methods for forming devices having planar split-gate non-volatile memory cells, planar HV devices, and FINFET logic devices on a substrate - Patents.com

Abstract

A method of forming a device in a silicon substrate having first, second, and third areas includes recessing an upper substrate surface in the first and third areas; forming an upwardly extending silicon fin in the second area; forming a first source, drain, and channel region in the first area; forming a second source, drain, and channel region in the fin; forming a third source, drain, and channel region in the third area; forming a floating gate over a first portion of the first channel region using a first polysilicon deposition; forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition; and forming a wordline gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.

Description

[Technical field]

[0001] (Related Applications) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 317,810, filed March 8, 2022, and U.S. Patent Application No. 17 / 824,812, filed May 25, 2022.

[0002] FIELD OF THEINVENTION The present disclosure relates to non-volatile flash memory and methods for integrating high voltage transistors with low voltage FinFET transistors. [Background technology]

[0003] Split-gate non-volatile flash memory cells having a select gate, a floating gate, a control gate, and an erase gate are well known in the art. See, for example, U.S. Patent Nos. 6,747,310 and 7,868,375. It is also known to form logic devices (i.e., low-voltage and high-voltage logic devices) on the same silicon chip as memory cells, and to share some processing steps to form parts of both memory cells and logic devices (e.g., using the same polysilicon deposition process to form gates for both memory cells and logic devices). However, it can often be difficult and complicated to form both types of devices on the same wafer, since other processing steps to form memory cells can adversely affect previously fabricated logic devices, and vice versa.

[0004] To solve the problems associated with reducing the channel width by shrinking the size of lithography, FinFET type structures have been proposed for memory cell structures. In FinFET type structures, a fin-shaped member of semiconductor material connects the source region to the drain region. The fin-shaped member has a top surface and two side surfaces. The current from the source region to the drain region can then flow along the top surface and the two side surfaces of the fin-shaped member. Thus, the effective width of the channel region is increased, thereby increasing the current flow. However, by "folding" the channel region to the two sides, the effective width of the channel region is increased without sacrificing more semiconductor area, thereby reducing the "footprint" of the channel region. Non-volatile memory cells using such FinFETs have been disclosed. Some examples of prior art FinFET non-volatile memory structures include U.S. Patent Nos. 7,423,310, 7,410,913, and 8,461,640, the entire contents of each of which are incorporated herein by reference. What these prior art references do not contemplate is a FinFET configuration for logic devices formed on the same wafer substrate as both the non-volatile memory cells and the high voltage transistor devices, both of which are non-FinFET configurations.

[0005] U.S. Patent Nos. 9,972,630 and 10,249,631 disclose memory devices having FinFET logic devices and non-FinFET memory cells, the entire contents of each of which are incorporated herein by reference, but these patents do not contemplate the simultaneous formation of high voltage transistor devices in non-FinFET configurations. Summary of the Invention

[0006] The above problems and needs are addressed by a method of forming a device, comprising: providing a substrate of silicon having first, second and third areas; recessing an upper surface of the substrate in the first area and an upper surface of the substrate in the third area relative to an upper surface of the substrate in the second area; removing a portion of the substrate in a second area to form an upwardly extending silicon fin having a pair of upwardly extending side surfaces terminating at a top surface; forming a first source region and a first drain region in a first area, the first source region and the first drain region defining a first channel region in the substrate extending between the first source region and the first drain region; forming a second source region and a second drain region in the silicon fin to define a second channel region in the substrate extending between the second source region and the second drain region along a pair of top and side surfaces of the silicon fin; forming a third source region and a third drain region in the third area, the third source region and the third drain region defining a third channel region in the substrate extending between the third source region and the third drain region; forming a floating gate disposed above and insulated from a first portion of a first channel region of the substrate using a first polysilicon deposition; forming an erase gate disposed above and insulated from the first source region and a device gate disposed above and insulated from a third channel region of the substrate using a second polysilicon deposition different from the first polysilicon deposition; and using metal deposition to form a word line gate disposed above and insulated from the second portion of the first channel region, a control gate disposed above and insulated from the floating gate, and a logic gate disposed above and insulated from the second channel region of the substrate.

[0007] A device, comprising: a substrate of silicon having first, second and third areas, The upper surface in the first area is flat, The upper surface in the third area is flat, the upper surface in the second area includes an upwardly extending silicon fin including a pair of side surfaces extending upwardly and terminating at a top surface; a silicon substrate, the top surface of which in the first area and the top surface of which in the third area are recessed below a top surface of the silicon fin; A memory cell in the first area, a first source region and a first drain region formed in the first area, and a first channel region in the substrate extending between the first source region and the first drain region; a polysilicon floating gate disposed above and insulated from a first portion of the first channel region; a metal wordline gate disposed above and insulated from the second portion of the first channel region; a metal control gate disposed vertically above and insulated from a top surface of the floating gate, the metal control gate disposed laterally adjacent and insulated from a pair of side surfaces of the floating gate such that the metal control gate wraps around the top surface and pair of side surfaces of the floating gate; a polysilicon erase gate disposed above and insulated from the first source region; a high voltage device in a third area, a third source region and a third drain region formed in the third area, and a third channel region in the substrate extending between the third source region and the third drain region; a polysilicon device gate disposed above and insulated from the third channel region; and a logic device in the second area, a second source region and a second drain region formed in the silicon fin, the second channel region of the substrate extending between the second source region and the second drain region along a pair of top and side surfaces of the silicon fin; a logic gate disposed vertically above and insulated from a top surface of the silicon fin, the logic gate disposed laterally adjacent and insulated from a pair of side surfaces of the silicon fin such that the logic gate wraps around the top surface and the pair of side surfaces of the silicon fin.

[0008] Other objects and features of the present disclosure will become apparent from a review of the specification, claims, and accompanying drawings.

[0009]

[0010]

[0011] [Brief description of the drawings]

[0012] [Figure 1A] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1B] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1C] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1D] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1E] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1F] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1G] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1H] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1I] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1J] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1K] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1L] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1M] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1N] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1O] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1P] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1Q]1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Figure 1R] 1A to 1C are perspective cross-sectional views showing steps of forming non-volatile memory cells, HV devices, and logic devices in a semiconductor substrate according to the present embodiment. [Diagram 2] 1 is a side cross-sectional view of a memory cell in a memory cell area, a logic device in a logic device area, and an HV device in an HV device area of ​​a semiconductor substrate. [Diagram 3] 2 is a side cross-sectional view of a memory cell in a memory cell area of ​​a semiconductor substrate. [Figure 4] 1 is a side cross-sectional view of a logic device in a logic device area of ​​a semiconductor substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] 1A-1R, perspective cross-sectional views are shown of steps in a process of fabricating multiple pairs of memory cells in a memory cell area (also referred to as an MC area or a first area) 2 of a semiconductor wafer substrate (also referred to as a substrate) 10, multiple logic devices in a logic device area (also referred to as a logic area or a second area) 4 of the substrate 10, and multiple high voltage transistor devices in an HV device area (also referred to as an HV area or a third area) 6 of the substrate 10.

[0014] The process begins by recessing the top surface of the substrate by forming a layer of silicon dioxide (also called oxide) 12 on the substrate 10, which may be formed of P-type single crystal silicon. The oxide layer 12 may be formed by deposition or by thermal oxidation. A silicon nitride layer 14 (also called nitride) is then formed on the oxide layer 12. A photolithographic masking process is then used to pattern the nitride layer 14 and the oxide layer 12 (i.e., selectively remove some parts of the layer but not others). The photolithographic masking process includes coating the nitride layer 14 with a photoresist material, which is then exposed and developed to remove the photoresist material from the memory cell area 2 and the HV device area 6 while maintaining the photoresist in the logic device area 4. Nitride and oxide etches are used to remove the exposed nitride layer 14 and oxide layer 12 from the memory cell area 2 and HV device area 6, respectively, leaving the substrate 10 exposed (the photoresist protects these layers from etching in the logic device area 4). After the remaining photoresist is removed from the logic device area 4, silicon oxidation alone or silicon oxidation combined with silicon etching is used to recess the exposed top surface of the substrate 10 in the memory cell area 2 and HV device area 6. The oxide layer 12 and nitride layer 14 protect the logic device area 4 from this oxidation / etch. The resulting structure after silicon oxide removal in the memory cell area 2 and HV device area 6 is shown in FIG. 1A, where the top surface of the substrate 10 in the memory cell area 2 and HV device area 6 is recessed below the surface of the substrate 10 in the logic device area 4 by a recession amount R. A non-limiting example of the recession amount R can include approximately 50 nm.

[0015] The nitride layer 14 and the oxide layer 12 are removed (e.g., by one or more etchings) from the logic device area 4, leaving the surface of the substrate 10 exposed. The top surface of the substrate 10 at this point is stepped, with the portions of the top surface of the substrate 10 in the memory cell area 2 and the HV device area 6 being recessed (i.e., lower) by a recess R relative to the portions of the top surface of the substrate 10 in the logic device area 4. An oxide layer 16 is then formed on the surface of the substrate 10 in all three areas 2 / 4 / 6, followed by a polysilicon (also called poly) layer 18 formed by a first polysilicon deposition on the oxide layer 16. The polysilicon layer 18 is then removed from the logic device area 4 by chemical mechanical polishing (or by chemical etching with a photoresist mask operation protecting the memory cell area 2 and the HV device area 6), while preserving the polysilicon layer 18 in the memory cell area 2 and the HV device area 6, as illustrated in FIG. 1B. This polysilicon layer 18 is finally used to form the floating gates of the memory cells in the memory cell area 2.

[0016] An oxide layer 20 is formed over the structure, and a nitride layer 22 is formed in the oxide layer 20. The structure is then covered with photoresist, which is exposed and developed to selectively remove the photoresist from portions of the memory cell area 2 and the HV device area 6, leaving selected portions of the nitride layer 22 exposed. One or more etches are performed to form trenches through the exposed portions of the nitride layer 22, through the oxide layer 20, the polysilicon layer 18, the underlying portions of the oxide layer 16, and into the substrate 10 (the trenches divide the polysilicon layer 18 into strips of polysilicon in the memory cell area 2 and the HV device area 6), leaving trenches 10b extending into the substrate 10 in both the memory cell area 2 and the HV device area 6. After removing the photoresist, the structure is covered with a thick layer 24 of insulating material such as oxide (i.e., STI oxide) (filling the trenches 10b with oxide), and then planarized (e.g., by chemical mechanical polishing-CMP) to expose the top surface of the nitride layer 22 in the logic area 4. The resulting structure is shown in FIG. 1C.

[0017] As shown in FIG. 1D, oxide spacers 26 are formed in the nitride layer 22 in the logic device area 4. The oxide spacers 26 can be formed by depositing a layer of material (e.g., amorphous carbon) on the structure. The layer of material is patterned by forming a photoresist and selectively removing strips of the photoresist in the logic device area 4 to remove exposed portions of the layer of material below and form trenches in the layer of logic device area 4 that extend down to and expose the underlying nitride layer 22. The oxide spacers 26 are then formed in the trenches. The formation of spacers is well known in the art and involves depositing material above the contours of the structure, followed by an anisotropic etching process, whereby material is removed from horizontal surfaces of the structure, while material remains largely intact on the vertically oriented surfaces of the structure (which often have rounded top surfaces). In this case, the oxide spacers 26 are formed along the sidewalls of the trenches in the layer of material. The remaining portions of the layer of material are then etched away to obtain the structure shown in FIG. 1D.

[0018] The structure is then covered with photoresist, exposed and developed, and the photoresist is removed from the logic device area 4. A nitride etch is then used to remove the exposed portions of nitride layer 22, followed by an oxide etch to remove the exposed portions of oxide layer 16 / 20 in the logic device area 4. A silicon etch is then used to recess the exposed surface of substrate 10 in the logic device area 4 to form upwardly extending silicon fins 10a of silicon substrate 10. The resulting structure is shown in FIG. 1E.

[0019] The structure is covered with a thick layer 30 of insulating material such as oxide (i.e., STI oxide) and then planarized (e.g., by chemical mechanical polishing-CMP) to expose the top surface of the nitride layer 22. Etching is then used to remove the nitride layer 22, as shown in FIG. 1F. One or more etches can be performed to remove the oxide layer 20 from the memory cell area 2 (exposing the polysilicon layer 18) and selectively recess the oxide layers 24 and 30 in the memory cell area 2, the logic device area 4, and the HV device area 6 (including recessing the oxide 24 between the strips of the polysilicon layer 18 in the memory cell area 2). An insulating layer 32, which can include three sublayers of a first oxide, a nitride, and a second oxide (e.g., an ONO layer), is formed above the structure. A polysilicon layer 34 is formed in the insulating layer 32 by a second polysilicon deposition (i.e., a polysilicon deposition different from the first polysilicon deposition). An oxide layer 35 is formed on polysilicon layer 34, and a hard mask layer (eg, nitride) 36 is formed on oxide layer 35. The resulting structure is shown in Figure 1G.

[0020] Photoresist is formed over the structure and partially removed to expose portions of the HV device area 6 and memory cell area 2, leaving portions of the hard mask layer 36 exposed. A nitride etch is used to remove the exposed portions of the hard mask layer 36, exposing portions of the oxide layer 35, which is then etched away to expose portions of the polysilicon layer 34. A polysilicon etch is used to remove the exposed portions of the polysilicon layer 34, exposing portions of the insulating layer 32. An etch is used to remove the exposed portions of the insulating layer 32, exposing portions of the polysilicon layer 18. Oxide spacers 38 are then formed by oxide deposition and anisotropic etching. A polysilicon etch is then used to remove the exposed portions of the polysilicon layer 18. The resulting structure is shown in FIG. 1H, with strips of the polysilicon layer 18 remaining in the memory cell area 2.

[0021] A photoresist is formed over the structure and partially removed to expose portions of the memory cell area 2 (adjacent the ends of the polysilicon layer strips 18). An implant is then performed to form source regions 40 (also referred to herein as first source regions) in the memory cell area 2 of the substrate below where the photoresist was removed. After removal of the photoresist, a layer of oxide (tunnel oxide) 42 is formed (e.g., by high temperature oxidation - HTO) on the exposed ends of the polysilicon layer strips 18. A polysilicon layer 44 is then formed over the structure by a third polysilicon deposition (i.e., a polysilicon deposition different from the first and second polysilicon depositions). The polysilicon layer 44 is planarized by CMP and further etched using polysilicon etchback to leave blocks of the polysilicon layer 44 extending over the source regions 40 and along the oxide layer 42 in the memory cell area 2 and blocks of the polysilicon layer 44 in the HV device area 6. After removing the hard mask layer 36 by etching, the structure is covered with a layer of oxide 46. The resulting structure is shown in FIG. 1I.

[0022] Photoresist is formed over the structure and partially removed to expose portions of oxide layer 46 in memory cell area 2 (i.e., above the central portions of polysilicon strips 18). An oxide etch is then used to remove the exposed portions of oxide layer 46 and expose portions of polysilicon layer 34. A polysilicon etch is used to remove the exposed portions of polysilicon layer 34 and expose portions of insulating layer 32. An etch (e.g., oxide, nitride, oxide etch) is used to remove the exposed portions of insulating layer 32 and expose the central portions of polysilicon strips 18. A polysilicon etch is used to remove the central portions of polysilicon strips 18. The resulting structure (after photoresist removal) is shown in FIG. 1J.

[0023] Oxide spacers 47 are formed on the exposed sidewalls of polysilicon layers 18 and 34 in memory cell area 2 by oxide deposition and anisotropic etching. Photoresist is formed over the structure and partially removed to expose logic area 4. Etching is used to remove oxide layer 46, polysilicon layer 34, insulating layer 32, and upper portions of oxide 30 to expose the upper portions of fins 10a (i.e., so that silicon fins 10a protrude from the recessed top surface of oxide layer 30). The resulting structure (after photoresist removal) is shown in FIG. 1K.

[0024] An oxide layer 49 is formed on the structure including the fin 10a and the substrate surface between the source regions 40. A dummy polysilicon layer 50 is formed on the oxide layer 49 by a fourth polysilicon deposition (i.e., a polysilicon deposition different from the first, second, and third polysilicon depositions). The dummy polysilicon layer 50 is then planarized using CMP to remove portions of the dummy polysilicon layer 50 above the oxide 46, leaving portions of the dummy polysilicon layer 50 in the memory cell area 2 and the logic device area 4, as shown in FIG. 1L.

[0025] One or more hard mask layers are then formed on the structure. For example, an amorphous carbon layer 52 is formed on the structure and an oxide layer 54 is formed on the amorphous carbon layer 52. Photoresist is formed on the oxide layer 54 and partially removed to expose portions of the oxide layer 54 in the memory cell area 2 and the logic device area 4. An oxide etch is then used to remove the exposed portions of the oxide layer 54 and expose portions of the amorphous carbon layer 52. A carbon etch is used to remove the exposed portions of the amorphous carbon layer 52 and expose portions of the dummy polysilicon layer 50. A polysilicon etch is used to remove the exposed portions of the dummy polysilicon layer 50. This sequence of etches results in the formation of trenches 56 extending through the dummy polysilicon layer 50 in the memory cell area 2 and leaves strips of the dummy polysilicon layer 50 extending over and between the silicon fins 10a in the logic device area 4. The resulting structure is shown in FIG. 1M (after removal of the photoresist).

[0026] Photoresist is again applied to the structure and partially removed, exposing portions of oxide layer 54 in HV device area 6 (while memory cell area 2 and logic device area 4 remain covered). An oxide etch is used to remove the exposed portions of oxide layer 54 (in HV device area 6) and expose portions of amorphous carbon layer 52. A carbon etch is used to remove the exposed portions of amorphous carbon layer 52 and expose portions of oxide layer 46. An oxide etch is then used to remove the exposed portions of oxide layer 46 and expose portions of polysilicon layer 44. A polysilicon etch is used to remove the exposed portions of polysilicon layer 44. As a result of this sequence of etches, blocks of polysilicon layer 44 remain in HV device area 6. The resulting structure (after photoresist removal) is shown in FIG. 1N.

[0027] Photoresist is formed on the structure and partially removed to expose the oxide 49 on the substrate surface adjacent to the blocks of dummy polysilicon layer 50 (at the bottom of trench 56 in FIG. 1N) in the memory cell area 2. An LDD (lightly doped drain) implant is performed to initiate the formation of drain regions 60 in the substrate 10 at the bottom of trench 56 (i.e., between the blocks of dummy polysilicon layer 50) in the memory cell area 2. After removal of the photoresist, nitride spacers 58 are formed on the exposed sidewalls of dummy polysilicon layer 50 and polysilicon layer 44 by nitride deposition and anisotropic etching, as shown in FIG. 1O.

[0028] Photoresist is formed on the structure and partially removed to expose the oxide 49 on the substrate surface adjacent the blocks of dummy polysilicon layer 50 in the memory cell area 2 (at the bottom of trench 56 in FIG. 1M) and adjacent the blocks of polysilicon layer 44 in the HV device area 6. An n-type implant is then used to further form an n-type drain region 60 (also referred to herein as the first drain region) in the substrate 10 at the bottom of trench 56 in the memory cell area 2 (i.e., between the blocks of dummy polysilicon layer 50), and n-type source-drain regions 62 / 64 (also referred to herein as the third source region and the third drain region) in the substrate 10 on either side of the blocks of polysilicon layer 44 in the HV device area 6. For simplicity, only n-type transistors are shown, but p-type transistors can also be formed in the same substrate at the same time. Thus, after removing the photoresist, a similar photoresist patterning / p-type implant / photoresist strip sequence is performed to form p-type source-drain regions 62 / 64 (also referred to herein as the third source region and the third drain region) in the HV device area 6. The oxide in the fin 10a in the logic device area 4 is removed by etching, and epitaxial growth followed by n-type implant is performed to form n-type epitaxial source / drain regions 66 / 68 (also referred to herein as the second source region and the second drain region) in the fin 10a on either side of the remaining strip of the dummy polysilicon layer 50 for the n-type logic devices in the logic device area 4. A similar photoresist patterning / hardmask etch / photoresist strip / epitaxial growth / p-type implant sequence is used to form p-type epitaxial source-drain regions 66 / 68 (also referred to herein as the second source region and the second drain region) for the p-type devices in the logic device area 4. The resulting structure is shown in FIG. 1P.

[0029] Next, the exposed portions of oxide layer 49, oxide layer 54, and amorphous carbon layer 52 are removed by etching. A nitride layer 70 is formed on the structure, and an oxide layer 72 is formed into thick nitride layer 70. Chemical mechanical polishing is used to planarize oxide layer 72 using nitride layer 70 as a polishing stop. Next, the nitride layer 70 above the strips of dummy polysilicon layer 50 / 34 in memory cell area 2 and logic device area 4 is selectively removed by chemical mechanical polishing using oxide layers 46 and 72 as etch stops. A selective poly etch is used to remove the exposed strips of dummy polysilicon layer 50 in memory cell area 2 (also referred to herein as the first polysilicon block) and logic device area 4 (also referred to herein as the second polysilicon block), and the strips of polysilicon layer 34 in memory cell area 2 (also referred to herein as the third polysilicon block). An oxide layer 74 is formed on the silicon substrate 10 from which the strips of dummy polysilicon layer 50 have been removed. A layer 76 of high-K material (i.e., having a dielectric constant K greater than that of an oxide such as HfO2, ZrO2, TiO2, Ta2O5, or other suitable material) is formed on the structure. One or more metal layers are then formed on the structure. For example, as shown in FIG. 1Q, a TiN layer 77 is formed on the structure, followed by a thick layer 78 of tungsten, followed by CMP, leaving strips of metal 77 / 78 in the high-K material 76 in the memory cell area 2 and logic device area 4 (effectively replacing the previously removed dummy polysilicon strips 50 and polysilicon layer strips 34).

[0030] A nitride layer 80 is formed over the structure, and an oxide layer 82 is formed on the nitride layer 80. Photoresist is formed over the structure and portions are removed above the source regions 60 in the memory cell area 2, above the source / drain regions 66 / 68 in the logic device area 4, and above the source / drain regions 62 / 64 in the HV device area 6, leaving openings exposing portions of the oxide layer 82. One or more etches are used to form contact holes through the openings that extend down to and expose the source regions 60, the source / drain regions 66 / 68, and the source / drain regions 62 / 64. The contact holes are filled with a conductive material (e.g., TiN / tungsten) to form conductive contacts 84. The resulting structure is shown in FIG. 1R (after removal of the photoresist).

[0031] 2 and 3 are cross-sectional views of memory cells 100 formed in the memory cell area 2. Each memory cell 100 includes a respective source region 40 and drain region 60 that define a planar channel region 86 (also referred to herein as a first channel region) in the substrate between the source region 40 and the drain region 60. A floating gate 18a is polysilicon and is disposed above a first portion of the channel region 86 to control the conductivity of the first portion of the channel region 86, and a metal word line (select) gate 78a (also referred to herein as a first metal block) is disposed above a second portion of the channel region 86 to control the conductivity of the second portion of the channel region 86. A metal control gate 78b is disposed above the floating gate 18a, and a polysilicon erase gate 44a is disposed above the source region 40. The erase gate 44a may have a notch or recess facing the edge of the floating gate 18a to enhance tunneling through the intervening tunnel oxide layer 42. The memory cells 100 are formed in pairs end-to-end, with each pair of memory cells sharing a common drain region 60, and adjacent pairs of memory cells sharing a common erase gate 44a and source region 40.

[0032] 2 and 4 are cross-sectional views of logic devices 102 formed in logic device area 4. Each logic device 102 includes a source region 66 and a drain region 68 that define a channel region 88 (also referred to herein as a second channel region) in the substrate fin 10a between the source region 66 and the drain region 68. Each silicon fin 10a includes a pair of side surfaces that extend upward and terminate at a top surface. As best shown in FIG. 2, the channel region 88 includes a top surface portion 88a that extends along the top of the fin structure 10a and a side surface portion 88b that extends along the side of the fin structure 10a. A logic gate 78c (also referred to herein as a block of a second metal) is disposed above a top portion of channel region 88a and laterally adjacent a side portion of channel region 88b (i.e., logic gate 78c wraps around top portion 88a and side portion 88b of fin 10a) to control the conductivity of channel region 88.

[0033] 2 includes a cross-sectional view of HV devices 104 (also referred to herein as high voltage devices) formed in the HV device area 6. For purposes of this disclosure, a high voltage device is one that has an operating voltage higher than that of the logic device 102. Each HV device includes a source region 62 and a drain region 64 that define a planar channel region 90 (also referred to herein as a third channel region) in the substrate between the source region 62 and the drain region 64. An HV gate 44b (also referred to herein as a device gate) is disposed above the channel region 90 and controls the conductivity of the channel region 90.

[0034] Although only two memory cells 100, four logic devices 102, and one HV device 104 are shown in FIG. 2, those skilled in the art will appreciate that many devices of each type may be formed simultaneously in each of areas 2 / 4 / 6.

[0035] The memory device methods and resulting structures described above provide many advantages including the advantages of high operational performance and ease of manufacture of planar memory cells 100 (i.e., memory cells formed in planar regions of a substrate) and planar HV devices 104 (i.e., devices formed in planar regions of a substrate) with the advantages of an advanced combination of embedded logic and memory devices where logic device 102 is a condensed non-planar logic device (i.e., a logic device formed in and surrounding a silicon fin structure). The FinFET transistor architecture of logic device 102 provides enhanced channel control using a tri-gate configuration, allowing further scaling of transistor dimensions.

[0036] Another advantage is that the top surface of the substrate 10 is recessed in the memory cell area 2 and the HV device area 6 relative to the logic device area 4. Specifically, the planar surface of the substrate 10 constituting the channel region in the memory cell area 2 and the HV device area 6 has a height that is recessed below the top of the fin 10a in the logic device area 4 by a recess amount R, as shown in Figure 2, which corresponds to a higher gate stack thickness and topology of the memory cells 100 and the HV devices 104 relative to the logic devices 102. In addition, common processing in the logic device area 4 and the memory cell area 2 and the HV device area 6 is facilitated. For example, having the fin 10a of the logic device area 4 raised above the level of the substrate surface of the memory cell area 2 simplifies the common formation steps of the dummy polysilicon layer 50, the oxide layer 74, the high-K layer 76, the block of TiN layer 77 and the block of tungsten 78 in both areas, and the resulting metal gate 78a with a planar bottom surface is formed for the memory cell using the same formation steps used to form the metal gate 78c with a bottom surface that wraps around the fin 10a for the logic device 102. Similarly, a common implantation operation forms the memory cell drain region 60 and the HV device source / drain regions 62 / 64. Furthermore, the erase gate 44a and the HV gate 44b are formed using the same polysilicon deposition process, and the word line gate 78a, the control gate 78b and the logic gate 78c are formed using the same metal deposition process. The control gate 78b can be made thinner without compromising its low resistivity considering the highly conductive metal composition of the control gate 78b. The control gate 78b is formed as a continuous line extending across multiple active areas and has a bottom portion 79 that extends downward between adjacent floating gates 18 for better capacitive coupling (e.g., as best shown in FIG. 2, the control gate 78b has a first portion vertically above the floating gate 18 and a second portion 79 laterally adjacent the floating gate 18 that results from recessing the STI oxide 24 between the floating gates 18 before the insulating layer 32 and polysilicon layer 34 are formed).

[0037] Yet another advantage is the combination of polysilicon material for the HV gate 44b, floating gate 18a, and erase gate 44a (to facilitate fabrication and better control tunneling between the floating gate 18a and the erase gate 44a) and metal material (to enhance conductivity and performance) insulated by high-K material for the word line gate 78a, control gate 78b, and logic gate 78c. The dummy polysilicon layer 50 is used to form dummy gates in the memory cell area 2 and logic area 4, which are then removed and replaced with metal word line gates 78a and control gates 78b for the memory cells and logic gates 78c for the logic devices. Most of the process fabrication for the memory cells and HV devices (including the formation of all polysilicon gates for the memory cells and HV devices) is done before the formation of the logic gates, which reduces the processing impact on the CMOS baseline. Finally, an improved combination of insulation between the various components is achieved. Specifically, the word line gate is insulated from the second portion of the first channel region by at least a layer of high-K material, the logic gate is insulated from the second channel region by at least a layer of high-K material, and the control gate is insulated from the floating gate by at least a layer of high-K material. In addition, the word line gate is further insulated from the second portion of the first channel region by an oxide layer, and the logic gate is further insulated from the second channel region by an oxide layer. Finally, the control gate is further insulated from the floating gate by an insulating layer that includes a first oxide sublayer, a nitride sublayer, and a second oxide sublayer.

[0038] It should be understood that the present disclosure is not limited to the embodiments described above and illustrated herein. For example, any reference herein to the present disclosure or invention or examples is not intended to limit the scope of any claim or claim term, but instead merely refers to one or more features that may be covered by one or more claims. The material, process, and numerical examples described above are merely illustrative and should not be considered as limiting the scope of the claims. Furthermore, as will be apparent from the claims and the specification, it is not necessary that all method steps be performed in the exact order illustrated or claimed, but rather in any order (unless there is an expressly recited limitation in any order) that allows for the proper formation of memory cells and logic devices as described herein. Finally, a single layer of material can be formed as multiple layers of such or similar materials, and vice versa.

[0039] It should be noted that, as used herein, the terms "over" and "on" both inclusively include "directly on" (with no intermediate material, element, or gap disposed therebetween) and "indirectly on" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween), "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached to" (with an intermediate material, element, or gap disposed therebetween), and "electrically coupled" includes "directly electrically coupled" (without an intermediate material, element, or gap disposed therebetween) and "indirectly electrically coupled" (with an intermediate material, element, or gap disposed therebetween). For example, forming an element "above a substrate" can include forming the element directly on the substrate without any intermediate materials / elements, or forming the element indirectly on the substrate through one or more intermediate materials / elements.

Claims

1. 1. A method of forming a device, comprising: providing a substrate of silicon having first, second and third areas; recessing an upper surface of the substrate in the first area and an upper surface of the substrate in a third area relative to an upper surface of the substrate in the second area; removing portions of the substrate in the second area to form an upwardly extending silicon fin having a pair of upwardly extending side surfaces terminating at a top surface; forming a first source region and a first drain region in the first area, the first source region and the first drain region defining a first channel region in the substrate extending between the first source region and the first drain region; forming a second source region and a second drain region in the silicon fin to define a second channel region in the substrate extending between the second source region and the second drain region along the pair of top and side surfaces of the silicon fin; forming a third source region and a third drain region in the third area, the third source region and the third drain region defining a third channel region in the substrate extending between the third source region and the third drain region; forming a floating gate disposed over and insulated from a first portion of the first channel region of the substrate using a first polysilicon deposition; forming an erase gate disposed above and insulated from the first source region and a device gate disposed above and insulated from the third channel region of the substrate using a second polysilicon deposition different from the first polysilicon deposition; and using metal deposition to form a word line gate disposed over and insulated from a second portion of the first channel region, a control gate disposed over and insulated from the floating gate, and a logic gate disposed over and insulated from the second channel region of the substrate.

2. 2. The method of claim 1, wherein the control gate has a first portion disposed vertically above the floating gate and a second portion disposed laterally adjacent to the floating gate.

3. 2. The method of claim 1, wherein the control gate is disposed vertically above and insulated from a top surface of the floating gate and disposed laterally adjacent and insulated from a pair of side surfaces of the floating gate such that the control gate wraps around the top surface and the pair of side surfaces of the floating gate.

4. The method of claim 1 , wherein the removing of the portions of the substrate to form the silicon fins is performed after the recessing step.

5. After the recessing step and before the removing step, the method further comprises: forming trenches extending into the substrate in the first and third areas; forming an insulating material in the first and third areas; and planarizing the top surface of the insulating material. The method of claim 4 , wherein the trench is filled with the insulating material after the planarizing step.

6. 2. The method of claim 1 , wherein the step of removing the portions of the substrate to form the silicon fins is performed before the steps of forming the control gates, the erase gates, the device gates, the word line gates, and the logic gates.

7. The step of removing the portion of the substrate in the second area to form the silicon fin comprises: forming a layer of a first material over the second area; forming a trench in the first material; forming spacers of a second material along sidewalls of the trench of the first material; removing the second material; and performing an etch of the substrate around the spacers of the first material to form the silicon fins of silicon.

8. 2. The method of claim 1 , wherein the logic gate is disposed vertically above and insulated from the top surface of the silicon fin and disposed laterally adjacent and insulated from the pair of side surfaces of the silicon fin such that the logic gate wraps around the top surface and the pair of side surfaces of the silicon fin.

9. 2. The method of claim 1 , wherein the word line gate is insulated from the second portion of the first channel region by at least a layer of high-K material, the logic gate is insulated from the second channel region by at least the layer of high-K material, and the control gate is insulated from the floating gate by at least the layer of high-K material.

10. 10. The method of claim 9, wherein the word line gate is further insulated from the second portion of the first channel region by an oxide layer, and the logic gate is further insulated from the second channel region by the oxide layer.

11. 10. The method of claim 9, wherein the control gate is further insulated from the floating gate by an insulating layer comprising a first oxide sublayer, a nitride sublayer, and a second oxide sublayer.

12. The step of forming the word line gates and the logic gates comprises: performing a third polysilicon deposition different from the first and second polysilicon depositions to form a first block of polysilicon material over and insulated from the second portion of the first channel region, and a second block of polysilicon material over and insulated from the second channel region; replacing the first polysilicon block with a first metal block using a polysilicon etch and the metal deposition; and replacing said block of second polysilicon with a block of second metal using said polysilicon etch and said metal deposition.

13. the step of replacing the first polysilicon block includes forming a layer of high-K material under the first metal block; 13. The method of claim 12, wherein the step of replacing the block of second polysilicon comprises forming a layer of the high-K material under the block of second metal.

14. The step of forming the control gate comprises: performing a fourth polysilicon deposition different from the first, second, and third polysilicon depositions to form a third block of polysilicon disposed above and insulated from the floating gate; and replacing the third block of polysilicon with a third block of metal using the polysilicon etch and the metal deposition.

15. 15. The method of claim 14, wherein the step of replacing the third block of polysilicon comprises forming a layer of high-K material under the third block of metal.

16. A device, comprising: a substrate of silicon having first, second and third areas, The upper surface in the first area is flat, The upper surface in the third area is flat, the upper surface in the second area includes an upwardly extending silicon fin including a pair of upwardly extending side surfaces terminating at a top surface; a silicon substrate, the top surface in the first area and the top surface in the third area being recessed below the top surface of the silicon fin; A memory cell in the first area, a first source region and a first drain region formed in the first area, and a first channel region in the substrate extending between the first source region and the first drain region; a polysilicon floating gate disposed above and insulated from a first portion of the first channel region; a metal word line gate disposed over and insulated from a second portion of the first channel region; a metal control gate disposed vertically above and insulated from a top surface of the floating gate, the metal control gate disposed laterally adjacent and insulated from a pair of side surfaces of the floating gate such that the metal control gate wraps around the top surface and the pair of side surfaces of the floating gate; a polysilicon erase gate disposed above and insulated from the first source region; a high voltage device in the third area, a third source region and a third drain region formed in the third area, and a third channel region in the substrate extending between the third source region and the third drain region; a polysilicon device gate disposed above and insulated from the third channel region; and A logic device in the second area, a second source region and a second drain region formed in the silicon fin, and a second channel region in the substrate extending between the second source region and the second drain region along the pair of top and side surfaces of the silicon fin; a logic gate disposed vertically above and insulated from the top surface of the silicon fin, the logic gate disposed laterally adjacent and insulated from the pair of side surfaces of the silicon fin such that the logic gate wraps around the top surface and the pair of side surfaces of the silicon fin.

17. 17. The device of claim 16, wherein the word line gate is insulated from the second portion of the first channel region by at least a layer of high-K material, the logic gate is insulated from the second channel region by at least the layer of high-K material, and the control gate is insulated from the floating gate by at least the layer of high-K material.

18. 20. The device of claim 17, wherein the word line gate is further insulated from the second portion of the first channel region by an oxide layer, and the logic gate is further insulated from the second channel region by the oxide layer.

19. 20. The device of claim 17, wherein the control gate is further insulated from the floating gate by an insulating layer comprising a first oxide sublayer, a nitride sublayer, and a second oxide sublayer.

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