Three-dimensional memory and method

Abstract

The present disclosure provides a three-dimensional memory and its manufacturing method, a memory system, and an electronic device, and relates to the technical field of semiconductor chips. The three-dimensional memory includes a stack structure, an etching stop layer, a protection layer, and a plurality of connection pillars. The stack structure includes gate layers and dielectric layers arranged alternately, and a plurality of steps. The etching stop layer is disposed on the steps. The protection layer covers the stack structure and the etching stop layer. The connection pillars penetrate the protection layer and the etching stop layer on the corresponding steps, and are electrically connected to the gate layers of the corresponding steps.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This disclosure is based on and claims priority to Chinese Patent Application No. 202210270254.X, filed on March 18, 2022, and is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to the technical field of semiconductor chips, and in particular to a three-dimensional memory and its manufacturing method, a memory system, and an electronic device. [Background technology]

[0003] As memory cell feature sizes approach the lower process limits, planar processes and manufacturing techniques become difficult and expensive, and the storage density of 2D or planar NAND flash approaches the upper limit. To overcome the limitations caused by 2D or planar NAND flash, the industry has developed memories with three-dimensional structures (3D NAND) in which memory cells are arranged three-dimensionally on a substrate to increase storage density.

[0004] In 3D NAND, the memory array device comprises an array region and a step region. During the fabrication of the memory array device, contact holes are formed in each step of the step region by etching and filled with a conductive material to form a connecting pillar, thereby transferring electrical signals to and from the gate layer.

[0005] However, during etching to form the contact hole, the gate layer is etched so that the contact hole passes through the dielectric layer between two adjacent gate layers, which may result in a short circuit between different gate layers, i.e., a short circuit between word lines in different layers, thereby generating a control error for the memory cell and causing a memory failure. Summary of the Invention

[0006] Examples of the present disclosure provide a three-dimensional memory and a method for manufacturing the same, a memory system, and an electronic device.

[0007] The examples of the present disclosure adopt the following technical solutions.

[0008] In one aspect, a three-dimensional memory is provided. The three-dimensional memory includes a stack structure, an etch stop layer, a protective layer, and a plurality of connection pillars. The stack structure includes gate layers and dielectric layers arranged alternately. The stack structure includes a plurality of steps. The etch stop layer is disposed on the steps. The protective layer covers the stack structure and the etch stop layer. Each step corresponds to at least one connection pillar, and the connection pillar penetrates the protective layer and the etch stop layer on the corresponding step and is electrically connected to the gate layer of the corresponding step.

[0009] In some examples, the etch stop layer includes a plurality of etch stops, one for each step, and the plurality of etch stops are spaced apart from one another.

[0010] In some cases, the etch stop layer is a continuous film layer that covers multiple steps.

[0011] In some cases, the etch stop layer material comprises an insulating material.

[0012] In some examples, the three dimensional memory further comprises a first dielectric layer and a second dielectric layer, the first dielectric layer disposed around the gate layer and the second dielectric layer disposed around the etch stop layer.

[0013] In some examples, the three dimensional memory further includes an isolation structure, the isolation structure extending through the stack structure and the protective layer and comprising a first insulating layer, the material of the first insulating layer being different from the material of the etch stop layer.

[0014] In some examples, the isolation structure further includes a filler layer, and the first insulating layer is located between the filler layer and the laminate structure.

[0015] In some examples, the etch stop layer material includes silicon nitride or polysilicon.

[0016] In some examples, the three dimensional memory further comprises an isolation structure penetrating the stack structure and the protective layer and comprising a second insulating layer, the material of the second insulating layer being the same as the material of the etch stop layer.

[0017] In some examples, the isolation structure further includes a filler layer, and the second insulating layer is located between the filler layer and the laminate structure.

[0018] In some examples, the isolation structure further comprises a third insulating layer located between the fill layer and the second insulating layer.

[0019] In some examples, the material of the first insulating layer and the etch stop layer includes silicon nitride.

[0020] In some cases, the thickness of the etch stop layer is greater than the thickness of the gate layer.

[0021] In another aspect, a method for manufacturing a three-dimensional memory is provided, the method includes forming an initial stack structure including a plurality of initial steps including alternating first sacrificial layers and dielectric layers, forming a second sacrificial layer on the initial stack structure, forming a gate line slit through the second sacrificial layer and the initial stack structure, removing the first sacrificial layer to form a first cavity, removing the second sacrificial layer to form a second cavity through the gate line slit, forming a gate layer in the first cavity, forming an etching stop layer in the second cavity, and forming an isolation structure in the gate line slit.

[0022] In some examples, after forming a second sacrificial layer on the initial laminated structure, the manufacturing method further includes patterning the second sacrificial layer to form a plurality of sacrificial portions, one of the sacrificial portions being provided on each of the initial stages, and the plurality of sacrificial portions being spaced apart from one another.

[0023] In some examples, forming a gate layer in the first cavity and forming an etch stop layer in the second cavity includes filling the first cavity with a gate material and partially filling the second cavity with the gate material through the gate line slits, removing the gate material in the second cavity, and forming an etch stop layer in the second cavity.

[0024] In some examples, forming the etch stop layer in the second cavity includes filling the second cavity with a dielectric material through the gate line slits, the dielectric material in the second cavity forming the etch stop layer.

[0025] In some examples, forming the etch stop layer in the second cavity includes filling the second cavity with a semiconductor material through the gate line slits and removing the semiconductor material covering the sidewalls of the gate line slits to form the etch stop layer.

[0026] In some examples, prior to forming the gate layer in the first cavity and the etch stop layer in the second cavity, the manufacturing method further includes forming a first dielectric layer in the first cavity and a second dielectric layer in the second cavity, the first dielectric layer covering a sidewall of the first cavity and the second dielectric layer covering a sidewall of the second cavity.

[0027] In some examples, the manufacturing method further includes forming a protective layer covering the initial stack structure and the second sacrificial layer, with the gate line slit also passing through the protective layer.

[0028] In some examples, the manufacturing method further includes forming a plurality of initial contact holes through the protective layer, etching the etch stop layer exposed by the initial contact holes to form contact holes, and filling the contact holes with a conductive material to form connection pillars, the connection pillars being electrically connected to the gate layer of a corresponding stage.

[0029] In yet another aspect, a memory system is provided, the memory system comprising: a controller and a three-dimensional memory, the three-dimensional memory being the three-dimensional memory according to any one of the above examples or being manufactured by the method for manufacturing the three-dimensional memory according to any one of the above examples, the controller being coupled to the three-dimensional memory for controlling the three-dimensional memory to store data.

[0030] In yet another aspect, an electronic device is provided, the electronic device comprising a memory system according to any of the examples above. [Brief description of the drawings]

[0031] In order to more clearly describe the technical solutions in the present disclosure, the drawings used in some examples of the present disclosure are briefly introduced below. Obviously, the drawings in the following description are only drawings of some examples of the present disclosure. Those skilled in the art can also obtain other drawings according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, without limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc., contained in the examples of the present disclosure. [Figure 1] 1 is a perspective view of a three-dimensional memory structure provided by some examples; [Diagram 2] 1 illustrates a top view of a three-dimensional memory provided by some examples. [Diagram 3] 3 is a cross-sectional view taken along the line AA' of the three-dimensional memory shown in FIG. 2. [Figure 4] 2 is an equivalent circuit diagram of a memory cell string of the three-dimensional memory of FIG. 1. [Diagram 5] 1 is a cross-sectional view along a first direction of a step region of a three-dimensional memory provided by some examples. [Figure 6] 1 is a cross-sectional view along a first direction of a step region of another three-dimensional memory provided by some examples. [Figure 7] 13 is a cross-sectional view along a second direction of a step region of a three-dimensional memory provided by some examples. [Figure 8]13 is a cross-sectional view along a second direction of a step region of another three-dimensional memory provided by some examples. [Figure 9] 1 is a flow diagram of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 10] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 11] FIG. 1 is a flow diagram of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 12] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 13] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 14] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 15] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 16] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 17] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 18] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 19] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 20] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 21] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 22] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 23] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 24] FIG. 1 is a flow diagram of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Diagram 25] FIG. 1 is a flow diagram of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 26]1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 27] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 28] FIG. 1 is a flow diagram of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Figure 29] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Diagram 30] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Diagram 31] FIG. 1 is a flow diagram of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Diagram 32] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Diagram 33] 1 is a diagram of a manufacturing operation of a method for manufacturing a three-dimensional memory, in accordance with some examples. [Diagram 34] FIG. 1 is a structural diagram of a three-dimensional memory according to some examples. [Diagram 35] 1 is a block diagram of a memory system, in accordance with some examples. [Diagram 36] FIG. 11 is a block diagram of a memory system according to some other examples. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] The technical solutions in some examples of the present disclosure are described below clearly and completely in conjunction with drawings. Obviously, the described examples are only some, but not all, of the examples of the present disclosure. All other examples obtained by those skilled in the art based on the examples provided by the present disclosure should fall within the scope of protection of the present disclosure.

[0033] In describing the present disclosure, it should be understood that terms such as "middle," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inside," "outside," and the like, indicate an orientation or positional relationship based on an orientation or positional relationship depicted in the drawings, do not indicate or imply that the depicted devices or elements have a particular orientation or must be constructed and operated in a particular orientation, but are merely intended to facilitate and simplify the description of the present disclosure, and therefore cannot be understood as limiting the present disclosure.

[0034] Unless otherwise specified in the context, throughout this specification and claims, the term "comprises" is to be interpreted in an open and inclusive sense, e.g., "including but not limited to." In the description herein, terms such as "one implementation," "some implementations," "one implementation," "one example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that implementation or example is included in at least one implementation or example of the present disclosure. Schematic illustrations of the above terms do not necessarily refer to the same implementation or example. Moreover, a particular feature, structure, material, or characteristic may be included in any one or more implementations or examples in any suitable manner.

[0035] Hereinafter, the terms "first" and "second" are merely descriptive and cannot be construed as indicating or implying a relative importance or number of the technical features indicated. Thus, features defined by "first" and "second" can explicitly or implicitly include one or more of such features. In the description of the examples of the present disclosure, "plurality" means two or more, unless otherwise specified.

[0036] In describing some examples, the expression "connected" and its derivatives may be used. For example, the term "connected" may be used in describing some examples to indicate that two or more components are in direct physical or electrical contact with each other. The examples disclosed herein are not necessarily limited to the contents of the present specification.

[0037] "At least one of A, B, and C" and "at least one of A, B, or C" have the same meaning and both include the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0038] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0039] The meanings of "on," "above," and "over" in the context of this disclosure should be interpreted in the broadest possible manner, such that "on" not only means "directly on something," but also includes the meaning "on something" with an intermediate feature or layer in between, and "above" or "over" not only means "above" or "over" something, but also includes the meaning "above" or "over" something without an intermediate feature or layer in between (e.g., directly on top of something).

[0040] Exemplary implementations are described herein with reference to at least one of cross-sectional or plan views used as idealized exemplary drawings. In the drawings, thicknesses of layers and regions are exaggerated for clarity. As such, variations in shape relative to the drawings due, for example, to manufacturing techniques and / or tolerances are possible. Thus, the exemplary implementations should not be construed as limited to the shapes of regions shown herein, including shape deviations caused, for example, by manufacturing. For example, an etched region shown as a rectangle typically has curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to represent the actual shape of a region of a device, nor are they intended to limit the scope of the exemplary implementations.

[0041] Fig. 1 is a perspective view of a structure of a three-dimensional memory 100 provided by some examples. Fig. 2 is a top view of the three-dimensional memory 100 provided by some examples. Fig. 3 is a cross-sectional view along AA' of the three-dimensional memory 100 shown in Fig. 2. Fig. 2 shows a top view of only a portion of the three-dimensional memory 100.

[0042] 1 and 2, the three-dimensional memory 100 includes an array region A and a step region B. The step region B may be located between the array regions A or may be located around the array region A. In one example, along a first direction X, the three-dimensional memory 100 comprises array regions A and step regions B arranged side-by-side and consecutively, where the array region A is configured to form memory cells and the step regions B are configured to provide contacts for connecting with word line connecting lines (WL1-WL4 are used as examples for illustration in FIG. 1).

[0043] Referring to Figures 1 and 3, the three-dimensional memory 100 comprises a stacked structure 2 and a protective layer 3 covering the stacked structure 2, and the stacked structure 2 comprises alternating gate layers 21 and dielectric layers 22 (not shown in Figure 1).

[0044] It should be noted that the number of gate layers 21 and dielectric layers 22 in the stacked structure 2 may be set according to actual needs, and the present disclosure does not impose any detailed limitations here.

[0045] In some examples, as shown in FIGS. 1 and 3, the three-dimensional memory 100 further includes a substrate 1, and the laminated structure 2 is disposed on the substrate 1.

[0046] In some examples, the substrate 1 is configured to support the stacked structure 2 and may include a doped region 11, and the material of the substrate 1 includes at least one of monocrystalline silicon (Si), monocrystalline germanium (Ge), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor material known in the art.

[0047] In some other examples, the substrate 1 does not function to support the stacked structure 2 and may be a source layer, and the material of the source layer includes a semiconductor material. The semiconductor material may be, for example, single crystal silicon, polysilicon, single crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer may be partially or fully doped. In one example, the source layer may include a doped region doped with a p-type dopant.

[0048] In some examples, the material of the dielectric layer 22 includes an insulating material. In one example, the material of the dielectric layer 22 includes silicon oxide or silicon nitride. For example, the material of the dielectric layer 22 includes silicon dioxide, although the present disclosure is not limited thereto.

[0049] In some examples, the material of the gate layer 21 includes a conductive material. In one example, the material of the gate layer 21 includes a metal or doped polysilicon. For example, the material of the gate layer 21 includes at least one of tungsten, cobalt, copper, aluminum, and doped crystalline silicon, and the present disclosure is not limited thereto.

[0050] In some examples, the material of the protective layer 3 includes an insulating material. The material of the protective layer 3 may be the same as the material of the dielectric layer 22. In one example, the material of the protective layer 3 includes silicon oxide or silicon nitride. For example, the material of the protective layer 3 includes silicon dioxide, and the present disclosure is not limited thereto.

[0051] As shown in Figures 1, 2, and 3, there are multiple memory cell strings 4 in the array region A, and the multiple memory cell strings 4 may penetrate the stacked structure 2 along the third direction Z, and the multiple memory cell strings 4 may be arranged in a matrix in the first direction X and the second direction Y.

[0052] It should be noted that the substrate 1 extends on an XY plane, and the first direction X and the second direction Y may be two orthogonal directions on the plane of the substrate 1. For example, the first direction X is the extension direction of the word lines WL, the second direction Y is the extension direction of the bit lines BL, and the third direction Z is perpendicular to the substrate 1, i.e., perpendicular to the XY plane.

[0053] Fig. 4 is an equivalent circuit diagram of the memory cell string 4 of the three-dimensional memory 100 of Fig. 1. As shown in Fig. 1 and Fig. 4, one memory cell string 4 corresponds to the storage capacity of a plurality of planar memory cells. Therefore, the three-dimensional memory 100 can provide a large storage capacity.

[0054] 1 and 4, a first end of the memory cell string 4 is connected to a bit line BL, and a second end is connected to a source line SL. That is, the memory cell string 4 includes a plurality of transistors connected in series between the first end and the second end, and the plurality of transistors includes at least one top select transistor Q1, at least one storage transistor M, and at least one bottom select transistor Q2. FIG. 4 illustrates a plurality of transistors including one top select transistor Q1, four storage transistors M, and one bottom select transistor Q2.

[0055] In a write operation, data is written to a selected one of the memory transistors M (one of M1 to M4 in FIG. 4) in the memory cell string 4 by utilizing the FN (Fowler-Nordheim) tunnel effect.

[0056] In a read operation, the amount of stored charge is determined for the memory cell string 4 according to the on state of a selected storage transistor (any of M1 to M4 in FIG. 4) in the storage transistor M, thereby obtaining data represented by that amount of charge.

[0057] 5 is a cross-sectional view along a first direction X of a step region B of a three-dimensional memory 100 provided according to some examples. As shown in FIGS. 2 and 5, a portion of the stacked structure 2 in the step region B includes a plurality of steps 23, and each gate layer 21 of the stacked structure 2 is electrically connected to a corresponding signal line connection line via a connection pillar 5.

[0058] In one example, referring to FIG. 1, along the third direction Z, at least one bottom gate layer 21 of the multiple gate layers 21 is configured as a ground selection line layer SGS, and at least one top gate layer 21 of the multiple gate layers 21 is configured as a string selection line layer SGD. A middle gate layer 21 of the multiple gate layers 21 is configured as a word line layer WL. In FIG. 1, as an example, one gate layer 21 configured as a ground selection line layer SGS (gate of bottom selection transistor Q2), one gate layer 21 configured as a string selection line layer SGD (gate of top selection transistor Q1), and four gate layers configured as word line layers WL (gate of storage transistor M) are shown.

[0059] The string selection line layer SGD is electrically connected to a corresponding selection line connecting line (any of SSL1 to SSL4) via a connection pillar 5, the ground selection line layer SGS is electrically connected to a ground selection line GSL via a connection pillar 5, and the word line layer WL is electrically connected to a corresponding word line connecting line (any of WL1 to WL4) via a connection pillar 5.

[0060] In the process of forming the connection pillar 5, first, the protective layer 3 covering the stacked structure 2 is etched to form a contact hole 6 (see FIG. 33). However, during the etching of the protective layer 3 to form the contact hole 6, due to the different thicknesses of the protective layer 3 across different stages 23, the gate layer 21 of the stage 23 corresponding to the thin protective layer 3 tends to be etched, so that the contact hole 6 (see FIG. 33) passes through the dielectric layer 22 between two adjacent ones of the gate layers 21, resulting in a short circuit between different gate layers 21, thereby generating a control error for the memory cell and causing a memory failure.

[0061] Based on this, and referring to Figures 3 and 5, some examples of the present disclosure provide a three-dimensional memory 100 comprising a stacked structure 2, an etching stop layer 7, a protective layer 3, and a number of connecting pillars 5.

[0062] An etch stop layer 7 is disposed on the steps 23, and a protective layer 3 covers the stack 2 and the etch stop layer 7. Each step 23 corresponds to at least one connection pillar 5 that penetrates the protective layer 3 and the etch stop layer 7 on the corresponding step 23 and is electrically connected to the gate layer 21 of the corresponding step 23.

[0063] It should be noted that the protective layer 3 has a high etching selectivity with respect to the etching stop layer 7, and during the subsequent removal of the protective layer 3 to form the contact hole 6 (see FIG. 32), the initial contact hole 61 (see FIG. 33) can be reliably stopped on the etching stop layer 7. It should be understood that the initial contact hole 61 (see FIG. 32) may also extend through the protective layer 3 and stop in the etching stop layer 7. In one example, the material of the protective layer 3 includes silicon oxide, and the material of the etching stop layer 7 includes silicon nitride. The process of removing the protective layer 3 to form the contact hole 6 (see FIG. 33) can refer to the fabrication method of the three-dimensional memory 100 described later, and will not be repeated here.

[0064] In the three-dimensional memory 100 provided in the above examples of the present disclosure, the etching stop layer 7 is disposed on the step 23. In this case, in the step of forming the contact hole 6 (see FIG. 33), the initial contact hole 61 may be formed (see FIG. 32) by stopping the via formed by etching the protective layer 3 at the etching stop layer 7. Then, the etching stop layer 7 exposed by the initial contact hole 61 (see FIG. 32) is etched, and the etching is stopped at the gate layer 21 of the corresponding step 23 to form the contact hole 6 (see FIG. 33).

[0065] Based on this, in the three-dimensional memory 100 provided in the above example of the present disclosure, during etching to form the contact holes 6, the contact holes 6 (see FIG. 33 ) for forming the connection pillars 5 can be stopped at the corresponding gate layers 21 by two-step etching, thereby solving the problem of short circuits between different gate layers 21 caused by etching the contact holes 6 penetrating the gate layers 21, and thereby improving the product yield.

[0066] In some examples, as shown in Fig. 5, the thickness of the etching stop layer 7 is greater than the thickness of the gate layer 21. The thickness of the etching stop layer 7 may be designed according to the thickness of the stacked structure 2, and the present disclosure does not impose detailed limitations thereon.

[0067] In some examples, the three-dimensional memory 100 further includes a first dielectric layer and a second dielectric layer, the first dielectric layer being disposed between the gate layer 21 and the dielectric layer 22, and the second dielectric layer being disposed between the etch stop layer 7 and the dielectric layer 22, to reduce the risk of leakage current of the memory cell. The material of the first dielectric layer and the second dielectric layer is a high dielectric constant material. For example, the material of the first dielectric layer and the second dielectric layer includes at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

[0068] In some examples, the three-dimensional memory 100 further includes an adhesion layer disposed between the second dielectric layer and the gate layer 21 to enhance adhesion between the gate layer 21 and the second dielectric layer. The material of the adhesion layer includes at least one of tantalum, tantalum nitride, titanium, and titanium nitride.

[0069] 5, the etching stop layer 7 includes a plurality of etching stop portions 71, one of which is provided on each step 23, and the plurality of etching stop portions 71 are spaced apart from one another. That is, of two adjacent steps 23, the step 23 relatively farther from the substrate 1 is the first step, and the step 23 relatively closer to the substrate 1 is the second step, and the etching stop portion 71 on the first step is spaced apart from the etching stop portion 71 on the second step. That is, the etching stop portions 71 on different steps 23 are separated from one another, thereby reducing structural stress and improving reliability.

[0070] As shown in Fig. 5, the etch stop 71 of the second stage is also spaced apart from the first stage. That is, there is a gap between the etch stop 71 on the second stage and the gate layer 21 included in the first stage, for example, the etch stop 71 is electrically insulated from the gate layer 21 included in the first stage. In this case, the material of the etch stop 71 may further include a conductive material, and the connecting pillar 5 is electrically connected only to the gate layer 21 of the stage 23 below it, and there is no short circuit between different gate layers 21, which does not cause memory failure.

[0071] It should be noted that the material of the etch stop 71 may include an insulating material or a conductive material. In one example, the material of the etch stop 71 includes any of silicon nitride, polysilicon, and metal, but the present disclosure is not limited thereto.

[0072] 6 is a cross-sectional view along the first direction X of a step region B of another three-dimensional memory 100 provided by some examples. In some other examples, as shown in FIG. 6, the etch stop layer 7 is a continuous film layer covering the steps 23.

[0073] In order to avoid short circuits between gate layers due to electrically connecting different gate layers 21 through the etching stop layer 7, the material of the etching stop layer 7 is an insulating material. In this way, the connecting pillar 5 is electrically connected only to the gate layer 21 of the step 23 below it by direct contact, and there is no short circuit between different gate layers 21, which does not cause memory failure.

[0074] It should be noted that if a second dielectric layer is placed between the etch stop layer 7 and the dielectric layer 22, the second dielectric layer is also an insulating material, such as aluminum oxide, to avoid short circuits between the different gate layers 21 caused by electrically connecting the different gate layers 21 through the etch stop layer 7. In this case, the continuous etch stop layer 7 may also be a conductive material.

[0075] 7 is a cross-sectional view along the second direction Y of the step region B of the provided three-dimensional memory 100 according to some examples. As shown in FIGS. 1, 2, and 7, the three-dimensional memory 100 further includes an isolation structure 8 penetrating the stacked structure 2 and the protective layer 3 to divide the three-dimensional memory 100 into multiple memory blocks.

[0076] 7 and 23, in some examples, the stacked structure 2 has a gate line slit GLS, and the isolation structure 8 is located in the gate line slit GLS. The isolation structure 8 includes a first insulating layer 81 filling the gate line slit GLS to prevent short-circuiting between different gate layers 21 in the gate line slit GLS or to prevent oxidation of the gate layer 21. The material of the first insulating layer 81 is different from the material of the etching stop layer 7, for example, the first insulating layer 81 and the etching stop layer 7 are formed in different process operations.

[0077] In some other examples, as shown in FIG. 7 and FIG. 23, the isolation structure 8 includes a first insulating layer 81 and a filling layer 82, and the first insulating layer 81 covers the sidewall of the gate line slit GLS to prevent short circuits between different gate layers 21 in the gate line slit GLS or to prevent oxidation of the gate layer 21. The filling layer 82 fills the gate line slit GLS to provide a mechanical support function and prevent the stacked structure 2 from collapsing. The material of the first insulating layer 81 is different from the material of the etching stop layer 7, for example, the first insulating layer 81 and the etching stop layer 7 are formed by different process operations. That is, there is a clear interface distinction between the first insulating layer 81 and the etching stop layer 7.

[0078] It should be noted that the etch stop layer 7 may be an insulating material or a conductive material if the etch stop layer 7 includes a plurality of spaced apart etch stops 71. If the etch stop layer 7 is a continuous film layer, the etch stop layer 7 may be an insulating material. In one example, the etch stop layer 7 includes silicon nitride.

[0079] Furthermore, the material of the first insulating layer 81 includes an insulating material. In one example, the material of the first insulating layer 81 includes silicon oxide, and the present disclosure is not limited thereto. The material of the filling layer 82 may be a conductive material or an insulating material. In one example, the material of the filling layer 82 includes polysilicon, and the present disclosure is not limited thereto. When an array common source doped region is formed in the substrate 1 exposed by the gate line slit GLS, the material of the filling layer 82 may be a conductive material, and a source signal may be derived through the filling layer 82 arranged in the gate line slit GLS.

[0080] 8 is a cross-sectional view along the second direction Y of the step region B of another three-dimensional memory 100 provided by some examples. As shown in FIGS. 1, 2, and 8, the semiconductor structure 100 further includes an isolation structure 8 penetrating the stack structure 2 and the protective layer 3 to divide the semiconductor structure 100 into a plurality of memory blocks.

[0081] 8 and 29, the isolation structure 8 includes a second insulating layer 83 filling the gate line slit GLS to prevent short circuits between different gate layers 21 in the gate line slit GLS or to prevent oxidation of the gate layer 21. The material of the second insulating layer 83 is the same as the material of the etching stop layer 7, and for example, the second insulating layer 83 and the etching stop layer 7 may be formed together in the same process operation. That is, there is no clear interface distinction between the second insulating layer 83 and the etching stop layer 7.

[0082] In some other examples, as shown in FIG. 8 and FIG. 29, the isolation structure 8 includes a second insulating layer 83, a third insulating layer 84, and a filling layer 82, and the second insulating layer 83 covers the sidewall of the gate line slit GLS to prevent short-circuiting between different gate layers 21 in the gate line slit GLS or to prevent oxidation of the gate layer 21. The third insulating layer 84 is located on the side of the second insulating layer 83 farther from the stacked structure 2, between the filling layer 82 and the second insulating layer 83. The filling layer 82 is located on the side of the third insulating layer 84 farther from the second insulating layer 83, and fills the gate line slit GLS to provide a mechanical support function and prevent the stacked structure 2 from collapsing.

[0083] The material of the second insulating layer 83 is the same as the material of the etching stop layer 7, for example, the second insulating layer 83 and the etching stop layer 7 may be formed together in the same process operation. That is, there is no clear interface distinction between the second insulating layer 83 and the etching stop layer 7. In one example, the material of the second insulating layer 83 includes silicon nitride, and the present disclosure is not limited thereto. The material of the third insulating layer 84 includes an insulating material. In one example, the material of the third insulating layer 84 includes silicon oxide, and the present disclosure is not limited thereto. The material of the filling layer 82 may be referred to above and will not be repeated here any more.

[0084] It should be noted that when the second insulating layer 83 and the etch stop layer 7 are formed together in the same process operation, the etch stop layer 7 is an insulating material, regardless of whether the etch stop layer 7 includes a plurality of spaced apart etch stops 71 or whether the etch stop layer 7 is a continuous film layer. In one example, the etch stop layer 7 includes silicon nitride.

[0085] As shown in FIG. 9, some examples of the present disclosure further provide a manufacturing method of a three-dimensional memory 100 (see FIG. 3) including S1 to S6.

[0086] S1: Referring to Figures 9 and 10, an initial laminate structure 200 is formed.

[0087] In the above operation, the initial laminated structure 200 includes a first sacrificial layer 211 and a dielectric layer 22, which are alternately arranged. The initial laminated structure 200 includes a plurality of initial stages 23, and the top layer of the initial stages 23 is the dielectric layer 22.

[0088] The initial laminated structure 200 can be formed by any of the thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). In one example, a CVD thin film deposition process is used to sequentially form a plurality of initial film layer pairs 210 on the substrate 1, and each initial film layer pair 210 includes a first sacrificial layer 211 and a dielectric layer 22 arranged in sequence.

[0089] It should be noted that the multiple initial steps 23 of the initial laminate structure 200 may be formed by performing multiple "trim etch" cycles. The region in which the multiple initial steps 23 are located may be referred to as step region B (see FIG. 2).

[0090] The material of the dielectric layer 22 is different from the material of the first sacrificial layer 211. The material of the dielectric layer 22 includes an insulating material. In one example, the material of the dielectric layer 22 includes silicon oxide or silicon nitride. For example, the material of the dielectric layer 22 includes silicon dioxide, and the present disclosure is not limited thereto. The material of the first sacrificial layer 211 includes at least one of polysilicon, silicon nitride, and polycrystalline germanium, and the present disclosure is not limited thereto.

[0091] S2: Referring to FIGS. 9, 12 and 13, a second sacrificial layer 710 is formed on the initial laminate structure 200.

[0092] In the above operations, a second sacrificial layer 710 is disposed on the initial stages 23. The second sacrificial layer 710 may be formed by any thin film deposition process such as CVD, PVD, ALD, etc. In one example, the second sacrificial layer 710 is formed on the plurality of initial stages 23 using a PVD thin film deposition process.

[0093] It should be noted that the material of the second sacrificial layer 710 is the same as the material of the first sacrificial layer 211 and includes at least one of polysilicon, silicon nitride, polycrystalline germanium, and the present disclosure is not limited in this respect. It should be understood that the material of the dielectric layer 22 is also different from the material of the second sacrificial layer 710. In one example, the material of the dielectric layer 22 includes silicon dioxide and the material of the second sacrificial layer 710 includes silicon nitride.

[0094] S3: Referring to FIG. 9, FIG. 17, and FIG. 18, a gate line slit GLS penetrating the second sacrificial layer 710 and the initial stacked structure 200 is formed.

[0095] In the above operation, the gate line slit GLS may be formed by dry etching or may be formed by a combination of dry etching and wet etching processes. In one example, the gate line slit GLS is formed using an anisotropic etching process (any of dry etching such as ion milling etching, plasma etching, reactive ion etching, and laser ablation) and the etching duration is controlled so that the etching penetrates the initial stacked structure 200.

[0096] S4: Referring to Figures 9, 17 and 18, the first sacrificial layer 211 is removed through the gate line slit GLS to form a first cavity C1, and the second sacrificial layer 710 is removed to form a second cavity C2.

[0097] In the above operation, referring to FIG. 15, when the first cavity C1 and the second cavity C2 are formed, the first sacrificial layer 211 is removed by isotropic etching using the gate line slit GLS as an etchant channel to form the first cavity C1. The second sacrificial layer 710 is removed by isotropic etching using the gate line slit GLS as an etchant channel to form the second cavity C2. The isotropic etching can be selective wet etching or steam etching. In the wet etching, an etching solution is used as an etchant. In the steam etching, an etching gas is used as an etchant.

[0098] When the material of the protective layer 3 and the dielectric layer 22 is silicon oxide, and the material of the first sacrificial layer 211 and the second sacrificial layer 710 is silicon nitride, a phosphoric acid solution may be used as an etchant during wet etching. It is noted that at least one of C4F8, C4F6, and CH2F2 may be used as an etching gas during steam etching.

[0099] S5: Referring to Figures 9, 17 and 19, a gate layer 21 is formed in a first cavity C1. An etch stop layer 7 is formed in a second cavity C2.

[0100] In the above operations, as shown in Figures 21 and 22, when the inner wall of the second cavity C2 is covered by the gate material and a gap is maintained in the second cavity C2, another process is required to form an etching stop layer 7, and exemplary processes can refer to the following and are not repeated here any more.

[0101] S6: Referring to Figs. 7, 9 and 23, an isolation structure 8 is formed in the gate line slit GLS.

[0102] Through the above operations, the isolation structure 8 is formed in the gate line slit GSL, which prevents short circuits between different gate layers 21 in the gate line slit GLS, prevents oxidation of the gate layer 21, and provides a mechanical support function. The isolation structure 8 may be formed in the gate line slit GLS by any of thin film deposition processes such as CVD, PVD, and ALD.

[0103] 7 and 23, the isolation structure 8 includes a first insulating layer 81 and a filling layer 82, in which the first insulating layer 81 covers the sidewall of the gate line slit GLS and is located between the filling layer 82 and the isolation structure 8 to prevent short-circuiting between different gate layers 21 in the gate line slit GLS and to prevent oxidation of the gate layer 21. The filling layer 82 fills the gate line slit GLS to provide a mechanical support function and prevent the stacked structure 2 from collapsing.

[0104] It should be noted that the material of the first insulating layer 81 includes an insulating material. In one example, the material of the first insulating layer 81 includes silicon oxide, and the present disclosure is not limited thereto. The material of the filling layer 82 may be a conductive material or an insulating material. In one example, the material of the filling layer 82 is a conductive material and includes polysilicon, and the present disclosure is not limited thereto. When an array common source doped region is formed in the substrate 1 exposed by the gate line slit GLS, the material of the filling layer 82 may be a conductive material to draw out the source signal through the filling layer 82.

[0105] In some other examples, as shown in FIG. 8 and FIG. 29, the isolation structure 8 includes a second insulating layer 83, a third insulating layer 84, and a filling layer 82. The second insulating layer 83 covers the sidewall of the gate line slit GLS. The third insulating layer 84 is located on the side of the second insulating layer 83 farther from the stacked structure 2, between the filling layer 82 and the second insulating layer 83. The filling layer 82 is located on the side of the third insulating layer 84 farther from the second insulating layer 83, and fills the gate line slit GLS. It should be noted that the material of the second insulating layer 83 includes silicon nitride, and the present disclosure is not limited thereto. The material of the third insulating layer 84 includes silicon oxide, and the present disclosure is not limited thereto.

[0106] In some examples, before S5, the method for manufacturing the semiconductor structure 100 further includes S10.

[0107] S10: A first dielectric layer is formed in the first cavity C1, and a second dielectric layer is formed in the second cavity C2.

[0108] In the above operation, the first dielectric layer covers the sidewall of the first cavity C1, and the second dielectric layer covers the sidewall of the second cavity C2 to reduce leakage current of the gate layer 21. The material of the first dielectric layer and the second dielectric layer is a high dielectric constant material. For example, the material of the first dielectric layer and the second dielectric layer includes at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

[0109] In some examples, between S10 and S5, the method for manufacturing semiconductor structure 100 further includes S11.

[0110] S11: An adhesive layer is formed in the first cavity C1.

[0111] In the above operation, the adhesion layer is disposed between the second dielectric layer and the gate layer 21 to enhance adhesion between the gate layer 21 and the second dielectric layer. The material of the adhesion layer includes at least one of tantalum, tantalum nitride, titanium, and titanium nitride.

[0112] It should be noted that the etch rate of the adhesive layer may be close to the etch rate of the gate material, and the adhesive layer may be etched away during a subsequent etching step to remove the gate material in the second cavity C2.

[0113] In some examples, referring to FIG. 25, after S2, the method for manufacturing the three-dimensional memory 100 further includes S21.

[0114] S21: Referring to FIG. 12, FIG. 14, and FIG. 25, the second sacrificial layer 710 is etched to form a plurality of sacrificial portions 711.

[0115] In the above operation, a sacrificial portion 711 is provided on each initial stage 23, and the multiple sacrificial portions 711 are spaced apart from each other, i.e., the sacrificial portions 711 on different initial stages 23 are separated from each other, reducing structural stress and thus improving reliability.

[0116] During patterning of the second sacrificial layer 710, a photoresist layer can be applied onto the second sacrificial layer 710, then a patterned photoresist layer is formed by process operations such as exposure and development, the second sacrificial layer 710 is etched using the patterned photoresist layer as a mask, and finally the photoresist layer is removed to form multiple sacrificial portions 711.

[0117] In some examples, referring to FIGS. 17, 21, and 24, S5 includes S51 to S53.

[0118] S51: Due to the gate line slit GLS, the first cavity C1 is filled with the gate material and the second cavity C2 is partially filled with the gate material.

[0119] In the above operation, the first cavity C1 is filled with the gate material, and a part of the gate material in the first cavity C1 forms the gate layer 21. A gap is maintained in the second cavity C2. The thickness of the second cavity C2 is greater than the thickness of the first cavity C1. At this time, when the first cavity C1 is completely filled with the gate material to form the gate layer 21, the filling of the gate material is stopped, and the filling time of the gate material may be controlled so that the inner wall of the second cavity C2 is covered with the gate material and a gap is maintained in the second cavity C2.

[0120] S52: The gate material in the second cavity C2 is removed.

[0121] In the above operation, in the process of removing the gate material covering the sidewall of the gate line slit GLS, the gate material covering the sidewall of the gate line slit GLS is also removed. That is, the removal of the gate material covering the sidewall of the gate line slit GLS and the removal of the gate material in the second cavity C2 may be performed in the same process. For example, the gate material on the sidewall of the gate line slit GLS and the gate material in the second cavity C2 are removed by a single etching process.

[0122] Since the gate material in the second cavity C2 maintains a gap, in the process of removing the gate material on the sidewall of the gate line slit GLS, the etchant enters the gap in the second cavity C2 and comes into contact with the gate material in the second cavity C2 over a wide area for etching, and after the gate material on the sidewall of the gate line slit GLS is removed, the gate material in the second cavity C2 is also removed. Here, the etching time may be controlled so that both the gate material covering the sidewall of the gate line slit GLS and the gate material in the second cavity C2 are completely removed.

[0123] S53: An etch stop layer 7 is formed in the second cavity C2.

[0124] In some examples, S53 includes S531.

[0125] S531: Referring to FIG. 19 and FIG. 29, the second cavity C2 is filled with a dielectric material through the gate line slit GLS.

[0126] In the above operations, referring to Figures 19 and 20, the dielectric material fills the second cavity C2 to form the etching stop layer 7. The dielectric material covers the sidewall of the gate line slit GLS to form the second insulating layer 83 of the isolation structure 8 (refer to Figure 8). The dielectric material is an insulating material.

[0127] During filling the second cavity C2 with the dielectric material, the second cavity C2 can be filled with the dielectric material by using the gate line slit GLS as a deposition channel by any one of thin film deposition processes such as CVD, PVD, and ALD. In the process of filling the second cavity C2 with the dielectric material by using the gate line slit GLS as a deposition channel, the dielectric material is also formed on the sidewall of the gate line slit GLS.

[0128] It should be noted that the material of the protective layer 3 has a high etching selectivity with respect to the dielectric material, which ensures that during the subsequent removal of the protective layer 3 to form the contact holes 6 (see FIG. 32), the initial contact holes 61 (see FIG. 33) can be stopped on the etching stop layer 7 formed by the dielectric material, thereby ensuring that very little of the etching stop layer 7 is removed. It should be understood that the above-mentioned initial contact holes 61 (see FIG. 32) may also extend through the protective layer 3 and stop in the etching stop layer 7 formed by the dielectric material.

[0129] In some other examples, referring to FIG. 28, S53 includes S532 and S533.

[0130] S532: Referring to FIG. 19, FIG. 28 and FIG. 29, a semiconductor material is filled into the second cavity C2 through the gate line slit GLS.

[0131] 19 and 20, in the above operation, when filling the second cavity C2 with a semiconductor material, the gate line slit GLS may be used as a deposition channel for filling the second cavity C2 with a semiconductor material by any of thin film deposition processes such as CVD, PVD, and ALD. In the process of filling the second cavity C2 with a semiconductor material using the gate line slit GLS as a deposition channel, a semiconductor material is also formed on the sidewall of the gate line slit GLS.

[0132] S533: Referring to FIG. 28 and FIG. 30, the semiconductor material covering the sidewalls of the gate line slits GSL is removed.

[0133] In the above operation, the semiconductor material on the sidewall of the gate line slit GLS may be etched away using an etchant, and the etching time may be controlled so as to stop the etching after the semiconductor material on the sidewall of the gate line slit GLS is etched away. At this time, the semiconductor material may be a material different from the material of the protective layer 3, since the material of the protective layer 3 has a high etching selectivity with respect to the semiconductor material. In one example, the semiconductor material includes at least one of polysilicon or metal, and the present disclosure is not limited thereto.

[0134] In some examples, the method further includes S22.

[0135] S22: Referring to FIGS. 11, 15 and 16, a protective layer 3 is formed on the second sacrificial layer 710 and the initial laminated structure 200.

[0136] In the above operation, the protective layer 3 covers the initial laminated structure 200 and the second sacrificial layer 710. The protective layer 3 may also be formed by filling the step region B by any of thin film deposition processes such as CVD, PVD, ALD (see FIG. 3), and then by a planarization process. The planarization process includes a chemical mechanical planarization (CMP) process or a recess etching process (REP), and the present disclosure is not limited thereto.

[0137] It should be noted that the material of the protective layer 3 is different from the material of both the first sacrificial layer 211 and the second sacrificial layer 710. The material of the protective layer 3 includes an insulating material and may be the same as the material of the dielectric layer 22. In one example, the material of the protective layer 3 includes silicon oxide. For example, the material of the protective layer 3 includes silicon dioxide, and the present disclosure is not limited thereto.

[0138] In some examples, after the etch stop layer 7 is formed, referring to FIG. 31, the method for manufacturing the semiconductor structure 100 further includes S7 to S9.

[0139] S7: Referring to Figures 31 and 32, a plurality of initial contact holes 61 penetrating the protective layer 3 are formed.

[0140] In the above operation, each initial contact hole 61 corresponds to one step 23, and the initial contact hole 61 is located on the corresponding step 23. Here, the step 23 includes a gate layer 21 and a dielectric layer 22.

[0141] The initial contact hole 61 may be formed by dry etching or a combination of dry etching and wet etching steps. In one example, the initial contact hole 61 is formed using an anisotropic etching (either dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation, etc.) step, and the etching time is controlled such that the etching stops at the etch stop layer 7 after penetrating the protective layer 3. It is noted that the initial contact hole 61 may extend until it stops in the etch stop layer 7.

[0142] S8: Referring to FIGS. 31, 32 and 33, the etching stop layer 7 exposed in the initial contact hole 61 is etched to form the contact hole 6.

[0143] In the above operation, each contact hole 6 corresponds to one step 23 , and the orthogonal projection of the contact hole 6 on the substrate 1 lies within the orthogonal projection of the corresponding step 23 on the substrate 1 .

[0144] It should be noted that the shape of the contact hole 6 may be cylindrical. For example, the shape of the contact hole 6 is a columnar or prismatic shape, but the present disclosure is not limited thereto.

[0145] S9: Referring to FIG. 5, FIG. 31 and FIG. 33, the contact holes 6 are filled with a conductive material to form connection pillars 5.

[0146] In the above operation, the connection pillars 5 are electrically connected to the gate layers 21 of the corresponding stages 23. Here, the contact holes 6 are filled with a conductive material by any thin film deposition process such as CVD, PVD, ALD, etc. The gate layers 21 are electrically connected to corresponding signal lines through the connection pillars 5. The signal lines include at least one of a string select line (one of SSL1 to SSL4), a ground select line GSL, and a word line (one of WL1 to WL4).

[0147] It should be noted that the shape of the connecting pillars 5 may be cylindrical, for example, the shape of the connecting pillars 5 may be cylindrical or prismatic, and the present disclosure is not limited thereto.

[0148] Referring to FIG. 34, the three dimensional memory 100 further comprises an array interconnect layer 110, a peripheral interconnect layer 120, and a peripheral circuit 130.

[0149] The array interconnect layer 110 may be coupled to the memory cell string 4. The array interconnect layer 110 may include one or more first interlayer insulating layers 111 and may further include a plurality of contacts insulated from each other through the first interlayer insulating layers 111, for example, a bit line contact coupled to the bit line and a drain select gate contact coupled to the drain select gate. The array interconnect layer 110 may further include one or more first interconnect conductor layers 112. The first interconnect conductor layer 112 may include a plurality of connection lines, for example, a bit line and a word line connection line coupled to the word line. The material of the first interconnect conductor layer 112 and the contacts may be a conductive material, for example, one or some combination of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable material. The material of the first interlayer insulating layer 111 is an insulating material, for example, one or more combinations of silicon oxide, silicon nitride, high-k insulating material, or other suitable material.

[0150] The peripheral circuits 130 are configured to control and sense the array devices. The peripheral circuits 130 may be any suitable digital, analog, and / or hybrid signal control and sensing circuitry configured to support the operation (or operation) of the array devices, including, but not limited to, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may further comprise any other circuitry compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs)) or memory circuits (e.g., static random access memories (SRAMs)).

[0151] The peripheral interconnect layer 120 is coupled with the peripheral circuit 130 to achieve the transmission of electrical signals between the peripheral circuit 130 and the peripheral interconnect layer 120. The peripheral interconnect layer 120 may include one or more second interlayer insulating layers 121 and may further include one or more second interconnect conductor layers 122. Different second interconnect conductor layers 122 may be coupled through contacts. The materials of the second interconnect conductor layers 122 and the contacts may be conductive materials, such as one or some combination of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials. The material of the second interlayer insulating layer 121 is an insulating material, such as one or more combinations of silicon oxide, silicon nitride, high-k insulating materials, or other suitable materials.

[0152] The peripheral interconnect layer 120 may be coupled with the array interconnect layer 110 such that the memory cell strings 4 may be coupled with the peripheral circuitry. In one example, since the peripheral interconnect layer 120 is coupled with the array interconnect layer 110, the peripheral circuitry 130 may be coupled with the memory cell strings 4, and transmission of electrical signals between the peripheral circuitry 130 and the memory cell strings 4 may be achieved. An adhesive interface may be disposed between the peripheral interconnect layer 120 and the array interconnect layer 110, and the peripheral interconnect layer 120 and the array interconnect layer 110 may be adhered and coupled to each other via the adhesive interface.

[0153] Fig. 35 is a block diagram of the memory system 10 according to some examples. Fig. 36 is a block diagram of the memory system 10 according to other some examples. As shown in Figs. 35 and 36, some examples of the present disclosure further provide a memory system 10. The memory system 10 includes a controller 300 and the three-dimensional memory 100 of some examples above, and the controller 300 is coupled to the three-dimensional memory 100 to control the three-dimensional memory 100 to store data.

[0154] Memory system 10 may be integrated into various types of storage devices, for example, included in the same package (such as a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package), that is, memory system 10 may be applied and packaged in different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having a storage device therein.

[0155] In some examples, referring to FIG. 35, the memory system 10 may include a controller 300 and one three-dimensional memory 100, and may be integrated into a memory card.

[0156] The memory card comprises any one of a PC (PCMCIA, Personal Computer Memory Card International Association) card, a CompactFlash (registered trademark) (CF) card, a SmartMedia (SM) card, a memory stick, a MultiMedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

[0157] In some other examples, referring to FIG. 36, a memory system 10 includes a controller 300 and multiple 3D memories 100 and is integrated into a solid-state drive (SSD).

[0158] Some examples of the present disclosure further provide an electronic device, which may be any one of a mobile communication terminal, a tablet, a game console, a digital multimedia player, a smart wearable device (such as a smart watch, a smart bracelet, or a smart glass), etc.

[0159] An electronic device may include the memory system 10 described above, and may further include at least one of a central processing unit (CPU) and a cache, etc.

[0160] It will be understood that the beneficial effects that can be achieved by the three-dimensional memory 100, memory system 10, and electronic device manufacturing method provided by the above examples of the present disclosure can refer to the beneficial effects of the three-dimensional memory 100 described above and will not be repeated further here.

[0161] The above description is merely an exemplary implementation of the present disclosure, and the protection scope of the present disclosure is not limited thereto. Any variation or replacement that can be easily understood by a person skilled in the art within the technical scope disclosed by the present disclosure shall be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the protection scope of the claims.

Claims

1. a stacked structure including a plurality of stages, the stacked structure including alternating gate layers and dielectric layers; an etch stop layer disposed on the steps; a protective layer covering the laminate structure and the etching stop layer; a plurality of connection pillars, each of the connection pillars penetrating the protection layer and the etch stop layer on a corresponding step and connected to the gate layer of the corresponding step.

2. The three dimensional memory of claim 1 , wherein the etch stop layer comprises a plurality of etch stops, one at each of the steps, and the plurality of etch stops are spaced apart from one another.

3. The three dimensional memory of claim 1 , wherein the etch stop layer is a continuous film layer covering the steps.

4. The three dimensional memory of claim 3 , wherein the etch stop layer comprises an insulating material.

5. 3. The three dimensional memory of claim 2, further comprising an isolation structure penetrating the stack structure and the protective layer and comprising a first insulating layer, the material of the first insulating layer being different from the material of the etch stop layer.

6. The three dimensional memory of claim 5 , wherein the isolation structure further comprises a fill layer, and the first insulating layer is located between the fill layer and the stack structure.

7. The three dimensional memory of claim 5 , wherein the material of the etch stop layer comprises silicon nitride or polysilicon.

8. 3. The three dimensional memory of claim 2, further comprising an isolation structure penetrating the stack structure and the protective layer and comprising a second insulating layer, the material of the second insulating layer being the same as the material of the etch stop layer.

9. The three dimensional memory of claim 8 , wherein the isolation structure further comprises a fill layer, and the second insulating layer is located between the fill layer and the stack structure.

10. 10. The three dimensional memory of claim 9, wherein the isolation structure further comprises a third insulating layer located between the fill layer and the second insulating layer.

11. 9. The three dimensional memory of claim 8, wherein said material of said second insulating layer and said etch stop layer comprises silicon nitride.

12. The three-dimensional memory of any one of claims 1 to 11, wherein a thickness of the etch stop layer is greater than a thickness of the gate layer.

13. a stacked structure including a plurality of stages, the stacked structure including alternating gate layers and dielectric layers; an insulating layer disposed on the steps; a protective layer covering the laminated structure and the insulating layer; a plurality of connection pillars, each of the connection pillars penetrating the protective layer and the insulating layer on a corresponding stage and connected to the gate layer of the corresponding stage.

14. The three dimensional memory of claim 13 , wherein the insulating layer is a continuous film layer covering the steps.

15. The three-dimensional memory of claim 13 , wherein a material of the insulating layer comprises silicon nitride.

16. The three-dimensional memory according to any one of claims 13 to 15, wherein a thickness of the insulating layer is greater than a thickness of the gate layer.

17. A method for manufacturing a three-dimensional memory, comprising the steps of: forming an initial stack structure including a plurality of initial stages, the initial stages including alternating first sacrificial layers and dielectric layers; forming a second sacrificial layer on the initial laminate structure; forming a gate line slit penetrating the second sacrificial layer and the initial stack structure, removing the first sacrificial layer to form a first cavity, and removing the second sacrificial layer to form a second cavity penetrating the gate line slit; forming a gate layer in the first cavity; forming an etch stop layer in the second cavity; forming an isolation structure in the gate line slit.

18. 20. The method of claim 17, further comprising forming the second sacrificial layer on the initial laminate structure, and then etching the second sacrificial layer to form a plurality of sacrificial portions, one of the sacrificial portions being provided on each of the initial stages, and the plurality of sacrificial portions being spaced apart from one another.

19. forming the gate layer in the first cavity and the etch stop layer in the second cavity, filling the first cavity with a gate material and partially filling the second cavity with the gate material through the gate line slit; removing the gate material in the second cavity; and and forming the etch stop layer in the second cavity.

20. 20. The method of claim 19, wherein forming the etch stop layer in the second cavity comprises filling the second cavity with a dielectric material through the gate line slits, the dielectric material in the second cavity forming the etch stop layer.

21. Forming the etch stop layer in the second cavity includes: filling the second cavity with a semiconductor material through the gate line slit; and removing the semiconductor material covering a sidewall of the gate line slit to form the etch stop layer.

22. 20. The method of claim 19, further comprising, prior to forming the gate layer in the first cavity and forming the etch stop layer in the second cavity, forming a first dielectric layer in the first cavity and a second dielectric layer in the second cavity, wherein the first dielectric layer covers a sidewall of the first cavity and the second dielectric layer covers a sidewall of the second cavity.

23. The method of claim 17 , further comprising forming a protective layer covering the initial stack structure and the second sacrificial layer, the gate line slit also passing through the protective layer.

24. forming a plurality of initial contact holes penetrating the protective layer; Etching the etch stop layer exposed by the initial contact hole to form a contact hole; 24. The method of claim 23, further comprising: filling the contact holes with a conductive material to form connection pillars, the connection pillars being electrically connected to the gate layer of the corresponding step.

25. A controller; A three-dimensional memory, A memory system, wherein the three-dimensional memory is the three-dimensional memory according to any one of claims 1 to 16, and the controller is coupled to the three-dimensional memory for controlling the three-dimensional memory to store data.

26. 26. An electronic device comprising the memory system of claim 25.

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