High performance devices with double-sided contacts

Abstract

A transistor is disclosed in the device having double-sided contacts, where at least the drain contact is on the opposite side of the gate, which allows for reduced gate resistance without increasing the parasitic capacitance between the gate and drain.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0001] The present disclosure relates generally to high performance devices, and more particularly, but not by way of limitation, to devices having double sided contacts and techniques for their fabrication. [Background technology]

[0002]

[0002] Integrated circuit technology has achieved great advances in increasing computing power by miniaturizing active and passive components. Packaged devices are used in many electronic devices, including processors, servers, radio frequency integrated circuits, etc.

[0003]

[0003] Noise figure is a key parameter in devices such as low noise amplifiers. However, this parameter is constrained by the gate resistance of the transistor. Traditional approaches can improve the gate resistance. However, such approaches can also increase undesirable parasitic capacitance.

[0004]

[0004] Therefore, there is a need for systems, apparatus, and methods that overcome the shortcomings of conventional devices, including the methods, systems, and apparatus provided herein. Summary of the Invention

[0005]

[0005] The following presents a simplified summary of one or more aspects and / or examples related to the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview of all contemplated aspects and / or examples, nor should the following summary be considered to identify key or critical elements of all contemplated aspects and / or examples or to delineate the scope related to any particular aspect and / or example. As such, the following summary is intended solely to present certain concepts related to one or more aspects and / or examples related to the apparatus and methods disclosed herein in a simplified form prior to the detailed description presented below.

[0006]

[0006] An exemplary transistor is disclosed. The transistor may comprise a silicon (Si) layer including a source region, a drain region, and a channel region therebetween. The transistor may also comprise a gate oxide on the channel region at a first side of the Si layer. The transistor may further comprise a gate on the gate oxide. The transistor may further comprise a source contact electrically coupled to the source region. The transistor may still further comprise a drain contact on a second side of the Si layer opposite the first side of the Si layer. The drain contact may be electrically coupled to the drain region. The first gate length may be shorter than the second gate length. The first gate length may be the length of a portion of the gate closer to the gate oxide, and the second gate length may be the length of a portion of the gate farther from the gate oxide.

[0007]

[0007] Another exemplary transistor is disclosed. The transistor may comprise a silicon (Si) layer including a source region, a drain region, and a channel region therebetween. The transistor may also comprise a gate oxide on the channel region at a first side of the Si layer. The transistor may further comprise a gate on the gate oxide. The transistor may further comprise a source contact electrically coupled to the source region. The transistor may still further comprise a drain contact on a second side of the Si layer opposite the first side of the Si layer. The drain contact may be electrically coupled to the drain region. A center of the gate may be closer to the source region than the drain region.

[0008]

[0008] A method of fabricating a transistor is disclosed. The method may include forming a silicon (Si) layer including a source region, a drain region, and a channel region therebetween. The method may also include forming a gate oxide on the channel region at a first side of the Si layer. The method may further include a gate on the gate oxide. The method may further include forming a source contact electrically coupled to the source region. The method may still further include forming a drain contact on a second side of the Si layer opposite the first side of the Si layer. The drain contact may be electrically coupled to the drain region. The first gate length may be shorter than the second gate length. The first gate length may be the length of a portion of the gate closer to the gate oxide, and the second gate length may be the length of a portion of the gate farther from the gate oxide.

[0009]

[0009] Another method of fabricating a transistor is disclosed. The method may include forming a silicon (Si) layer including a source region, a drain region, and a channel region therebetween. The method may also include forming a gate oxide on the channel region at a first side of the Si layer. The method may further include a gate on the gate oxide. The method may further include forming a source contact electrically coupled to the source region. The method may still further include forming a drain contact on a second side of the Si layer opposite the first side of the Si layer. The drain contact may be electrically coupled to the drain region. A center of the gate may be closer to the source region than the drain region.

[0010]

[0010] Other features and advantages associated with the apparatus and methods disclosed herein will become apparent to one of ordinary skill in the art based on the accompanying drawings and detailed description. [Brief description of the drawings]

[0011]

[0011] A more complete understanding of many of the aspects and attendant advantages of the present disclosure will be readily obtained by reference to the following detailed description, taken in conjunction with the accompanying drawings, which are presented merely to illustrate and not to limit the disclosure, and in which: [Figure 1A]

[0012] The limitations of optimizing the gate resistance under conventional approaches to designing device transistors are demonstrated. [Figure 1B] The limitations of optimizing the gate resistance under conventional approaches to designing device transistors are demonstrated. [Figure 2A]

[0013] 1 illustrates a cross-sectional view of an exemplary transistor in accordance with one or more aspects of the present disclosure. [Figure 2B] 1 illustrates a cross-sectional view of an exemplary transistor in accordance with one or more aspects of the present disclosure. [Figure 3A] 1 illustrates a cross-sectional view of an exemplary transistor in accordance with one or more aspects of the present disclosure. [Figure 3B] 1 illustrates a cross-sectional view of an exemplary transistor in accordance with one or more aspects of the present disclosure. [Figure 4A] 1 illustrates a cross-sectional view of an exemplary transistor in accordance with one or more aspects of the present disclosure. [Figure 4B] 1 illustrates a cross-sectional view of an exemplary transistor in accordance with one or more aspects of the present disclosure. [Figure 5A] 1 illustrates a cross-sectional view of an exemplary transistor in accordance with one or more aspects of the present disclosure. [Figure 5B] 1 illustrates a cross-sectional view of an exemplary transistor in accordance with one or more aspects of the present disclosure. [Figure 6A]

[0014] 1 illustrates example stages for fabricating a transistor according to one or more embodiments of the present disclosure. [Figure 6B] 1 illustrates example stages for fabricating a transistor according to one or more embodiments of the present disclosure. [Figure 6C] 1 illustrates example stages for fabricating a transistor according to one or more embodiments of the present disclosure. [Figure 6D] 1 illustrates example stages for fabricating a transistor according to one or more embodiments of the present disclosure. [Figure 6E] 1 illustrates example stages for fabricating a transistor according to one or more embodiments of the present disclosure. [Figure 6F] 1 illustrates example stages for fabricating a transistor according to one or more embodiments of the present disclosure. [Figure 7A]

[0015] 1 illustrates an example of alternative steps for fabricating a transistor according to one or more embodiments of the present disclosure. [Figure 7B] 1 illustrates an example of alternative steps for fabricating a transistor according to one or more embodiments of the present disclosure. [Figure 7C] 1 illustrates an example of alternative steps for fabricating a transistor according to one or more embodiments of the present disclosure. [Figure 7D] 1 illustrates an example of alternative steps for fabricating a transistor according to one or more embodiments of the present disclosure. [Figure 8]

[0016] 1 is a flowchart of an exemplary method for fabricating a transistor in accordance with one or more aspects of the present disclosure. [Figure 9] 1 is a flowchart of an exemplary method for fabricating a transistor in accordance with one or more aspects of the present disclosure. [Figure 10] 1 is a flowchart of an exemplary method for fabricating a transistor in accordance with one or more aspects of the present disclosure. [Figure 11]

[0017] 1 illustrates various electronic devices in which one or more aspects of the present disclosure may be utilized.

[0012]

[0018] Other objects and advantages associated with the aspects disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. In accordance with common practice, features depicted by the drawings may not be drawn to scale. Thus, dimensions of depicted features may be arbitrarily increased or decreased for clarity. In accordance with common practice, some of the drawings have been simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Moreover, like reference numerals refer to like features throughout the specification and figures. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013]

[0019] Aspects of the present disclosure are illustrated in the following description and related drawings directed to specific embodiments. Alternative aspects or embodiments may be devised without departing from the scope of the teachings herein. In addition, well-known elements of the exemplary embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

[0014]

[0020] In some described exemplary implementations, instances are identified where portions of the structure and operation of various components may be derived from known conventional techniques and then configured in accordance with one or more exemplary embodiments. In such instances, some internal details of the structure and / or operation of the known conventional components may be omitted to help avoid potentially obscuring the concepts illustrated in the exemplary embodiments disclosed herein.

[0015]

[0021] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates otherwise. It is further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0016]

[0022] In the above, it has been shown that noise figure (F) is a key performance parameter in devices such as radio frequency (RF) low noise amplifier (LNA) devices. However, the parameter F is constrained by the gate resistance (Rg) of the transistors in the LNA device. Both the minimum noise figure and noise impedance (Rn) are strongly dependent on Rg. That is, generally, a lower Rg leads to a better minimum noise figure Fmin and noise figure F.

[0017]

[0023] The traditional approach can improve Rg, but it can also increase undesirable parasitic capacitances, including gate-source capacitance (Cgs) and gate-drain capacitance (Cgd). That is, under the traditional approach, there is a trade-off of improving some parameters at the expense of decreasing others.

[0018]

[0024] 1A shows a cross-section of a conventional silicon-on-insulator (SOI) transistor 100A. Transistor 100A includes a silicon (Si) layer 115 on a buried oxide (BOX) layer 110. Si layer 115 includes a source region 120, a drain region 130, and a channel region 140. In this example, transistor 100A is shown as an NMOS transistor. A gate oxide 150 is formed on channel region 140, and a gate 180A is formed on gate oxide 150. A source contact 160 is formed on source region 120, and a drain contact 170 is formed on drain region 130.

[0019]

[0025] As mentioned above, the gate resistance Rg has a large effect on the noise figure F and therefore on the performance of the transistor. Therefore, it is desirable to improve Rg to improve the performance of the transistor. Generally, Rg is inversely proportional to the gate length Lg. In FIG. 1A, Lg is represented by a double-headed arrow in the gate 180A.

[0020]

[0026] Therefore, one way to improve Rg is to increase the effective length of the gate. This can be seen in FIG. 1B, which shows a transistor 100B that illustrates a traditional approach to improving Rg. Transistor 100B of FIG. 1B includes similar components to those of transistor 100A of FIG. 1A. The difference is in gate 180B, which has a mushroom-shaped or T-shaped cross section. Although the mushroom shape of gate 180B does improve Rg of transistor 100B, it also increases the undesirable parasitic capacitances Cgs and Cgd.

[0021]

[0027] To address these and other challenges with designing devices with conventional transistors, it is proposed to provide a transistor in which the gate and at least the drain contact are on opposite sides of a silicon layer. In one or more embodiments, the source contact may also be on the opposite side of the silicon layer from the gate. In one or more other embodiments, the source contact may be on the same side of the silicon layer as the gate. The proposed transistor may be used in applications such as low noise amplifiers (LNAs) in radio frequency (RF) transceivers.

[0022]

[0028] FIG. 2A illustrates a cross-sectional view of a transistor 200A according to one or more embodiments of the present disclosure. The transistor 200A may be a silicon-on-insulator (SOI) field effect transistor (FET). As can be seen, the transistor 200A may comprise a buried oxide (BOX) layer 210 and a silicon (Si) layer 215 on the BOX layer 210. Specifically, the Si layer 215 may be on the top surface of the BOX layer 210. It should be noted that terms or phrases such as "lower", "upper", "left", "right", "below", "above", "horizontal", "vertical", etc. are used for convenience. Unless otherwise specified, such terms / phrases are not intended to indicate absolute orientations or directions.

[0023]

[0029] The Si layer 215 may include a source region 220, a drain region 230, and a channel region 240 between the source region 220 and the drain region 230. The Si layer 215 may be doped with impurities to form the source, drain, and channel regions 220, 230, 240. The transistor 200A is shown to be an NMOS transistor with the source and drain regions 220, 230 heavily doped with n-type impurities. This is for illustrative purposes only and should not be considered limiting; that is, PMOS transistor counterparts are fully contemplated. It is noted that other examples of NMOS transistors will also be illustrated and described. However, it is understood that PMOS counterparts are also contemplated.

[0024]

[0030] 2A , the transistor 200A may comprise a gate oxide 250 on a first side or surface (e.g., top side / surface) of the Si layer 215 and on the channel region 240. In one embodiment, the gate oxide 250 may overlap the channel region 240 and be in direct contact with the Si layer 215. The gate oxide 250 may at least partially overlap the channel region 240. In other embodiments, the gate oxide 250 may also overlap at least a portion of the source region 220 and / or at least a portion of the drain region 230.

[0025]

[0031] A gate 280 may be formed on the gate oxide 250. Thus, the gate 280 may also be on the first side of the Si layer 215. In one embodiment, the gate 280 may be in direct contact with the gate oxide 250. The gate 280 may be formed from an electrically conductive material such as polysilicon, a metal, or the like.

[0026]

[0032] A source contact 260A may be formed on a second side or surface (e.g., underside / surface) of the Si layer 215 opposite the first side. The source contact 260A may be formed through the BOX layer 210. The source contact 260A may be electrically coupled to the source region 220. For example, the source contact 260A may be in direct contact with the source region 220 on the second side of the Si layer 215. Metals such as copper (Cu) and aluminum (Al) may be used to form the source contact 260A.

[0027]

[0033] A drain contact 270 may also be formed on the second side of the Si layer 215. Similar to the source contact 260A, the drain contact 270 may be formed through the BOX layer 210. The drain contact 270 may be electrically coupled to the drain region 230. For example, the drain contact 270 may directly contact the drain region 230 on the second side of the Si layer 215. Metals such as copper (Cu) and aluminum (Al) may be used to form the drain contact 270.

[0028]

[0034] Note that by having source and drain contacts 260A, 270 on opposite sides of the gate 280, this means that the gate 280 can be sized to improve the gate resistance Rg without increasing the undesirable parasitic capacitances Cgs and Cgd. That is, with double-sided contacts, there is much more freedom to optimize the gate shape, and therefore the gate resistance Rg, without degrading the parasitic capacitances Cgs and Cgd. Also, the transistor 200A (and other transistors described below) can be fabricated using technology that is fully compatible with advanced CMOS processes.

[0029]

[0035] A gate contact 290 may be formed to be electrically coupled to the gate 280. For example, the gate contact 290 may be formed directly on the gate 280. In this manner, the gate resistance Rg may be improved. The gate contact 290 may be formed of a conductive metal (e.g., Cu, Al, etc.).

[0030]

[0036] A gate connection 295 may be formed to be electrically coupled to the gate contact 290 (and thus to the gate 280). For example, the gate connection 295 may be formed directly on the gate contact 290. The gate connection 295 may allow for electrical connection to other devices. The gate connection 295 may be formed from a conductive metal (e.g., Cu, Al, etc.).

[0031]

[0037] Transistor 200A may further include a source connection 265A and a drain connection 275 electrically coupled to source contact 260A and drain contact 270, respectively. For example, source connection 265A may be in direct contact with source contact 260A and / or drain connection 275 may be in direct contact with drain contact 270. Source connection 265A and drain connection 275 may be to enable electrical connection with other devices. Source connection 265A and / or drain connection 275 may be formed from a conductive metal (e.g., Cu, Al, etc.).

[0032]

[0038] 2B illustrates a cross-sectional view of transistor 200B according to one or more embodiments of the present disclosure. Transistor 200B can be similar to transistor 200A (of FIG. 2A), except that source contact 260B is on a first side of Si layer 215, i.e., on the same side as gate 280.

[0033]

[0039] This is due to at least the following factors: First, the parasitic capacitance Cgs between the gate and source is not as critical as the parasitic capacitance Cgd between the gate and drain. Therefore, it may be acceptable to have the source contact 260B on the same side of the Si layer 215 as the gate 280. Second, in some cases, the designer may want a higher Cgs to have a closer input match to the source resistance. That is, having the source contact 260B on the same side as the gate 280 may be beneficial in some respects. However, in either case, it is desirable to have the drain contact 270 on the opposite side.

[0034]

[0040] The transistor 200B may further include a source connect 265B electrically coupled to the source contact 260B. For example, the source connect 265B may be in direct contact with the source contact 260B. The source connect 265B may serve a similar role to that of the source connect 265A. That is, the source connect 265B may be to enable electrical connection with other devices. The source connect 265B may be formed from a conductive metal (e.g., Cu, Al, etc.).

[0035]

[0041] 3A illustrates a cross-sectional view of a transistor 300A according to one or more embodiments of the present disclosure. The transistor 300A may be a SOI field effect transistor. As can be seen, the transistor 300A may include a BOX layer 310 and a Si layer 315 on the BOX layer 310.

[0036]

[0042] The Si layer 315 may include a source region 320, a drain region 330, and a channel region 340 between the source region 320 and the drain region 330. The Si layer 315 including the source, drain, and channel regions 320, 330, 340 may be similar to the Si layer 215 including the source, drain, and channel regions 220, 230, 240 of Figures 2A and 2B described above, and therefore a detailed description thereof will be omitted for the sake of brevity.

[0037]

[0043] The transistor 300A may also include a gate oxide 350 on the channel region 340 on the first side of the Si layer 315. The gate oxide 350 may be similar to the gate oxide 250 of Figures 2A and 2B described above, and therefore a detailed description thereof is omitted for the sake of brevity.

[0038]

[0044] A gate 380 may be formed on the gate oxide 350. Therefore, the gate 380 may also be on the first side of the Si layer 315. In this case, the gate 380 may be mushroom-shaped or T-shaped to improve the gate resistance Rg. In one embodiment, the gate 380 may be in direct contact with the gate oxide 350. The gate 380 may be formed from an electrically conductive material such as polysilicon, metal, etc.

[0039]

[0045] A source contact 360A may be formed on a second side of the Si layer 315. The source contact 360A may be similar to the source contact 260A of Figure 2A described above, and therefore a detailed description thereof is omitted for the sake of brevity.

[0040]

[0046] A drain contact 370 may also be formed on the second side of the Si layer 315. The drain contact 370 may be similar to the drain contact 270 of Figures 2A and 2B described above, and therefore a detailed description thereof is omitted for the sake of brevity.

[0041]

[0047] Note, for emphasis, that the source and drain contacts 360A, 370 are on opposite sides of the gate 380, which means that the gate 380 can be sized to improve the gate resistance Rg without increasing the undesirable parasitic capacitances Cgs and Cgd. That is, the use of double-sided contacts allows much more freedom to optimize the gate shape and thus improve the gate resistance Rg without degrading the parasitic capacitances Cgs and Cgd.

[0042]

[0048] Gate 380 is an example of a shape setting to improve Rg. The shape of gate 380 may be described as follows. Gate 380 may have a first and a second gate length. The first gate length may represent the length of a portion of gate 380 closer to gate oxide 350 (e.g., a lower portion of gate 380), and the second gate length may represent the length of a portion of gate 380 farther from gate oxide 350 (e.g., an upper portion of gate 380). As can be seen, the first gate length may be shorter than the second gate length.

[0043]

[0049] Although not specifically shown, a gate contact and gate connection may be formed on the gate 380, which may be similar to the gate contact 290 and gate connection 295. The transistor 300A may further include a source connection 365A and a drain connection 375 for enabling electrical connection to other devices. The source connection 365A and the drain connection 375 may be similar to the source connection 265A and the drain connection 275 of FIG. 2A described above, and therefore a detailed description thereof will be omitted for the sake of brevity.

[0044]

[0050] 3B illustrates a cross-sectional view of transistor 300B according to one or more embodiments of the present disclosure. Transistor 300B may be similar to transistor 300A (of FIG. 3A), except that source contact 360B is on a first side of Si layer 315, i.e., on the same side as gate 380. The reasons for having source contact 360B on the same side as gate 380 may be similar to those discussed above with respect to source contact 260B, and therefore will not be repeated for brevity.

[0045]

[0051] The transistor 300B may further include a source connection portion 365B electrically coupled to the source contact 360B. For example, the source connection portion 365B may be in direct contact with the source contact 360B. The source connection portion 365B may be similar to the source connection portion 265B of FIG. 2B, and therefore, a description thereof will be omitted.

[0046]

[0052] 4A illustrates a cross-sectional view of a transistor 400A according to one or more embodiments of the present disclosure. The transistor 400A may be a SOI field effect transistor. As can be seen, the transistor 400A may include a BOX layer 410 and a Si layer 415 on the BOX layer 410.

[0047]

[0053] The Si layer 415 may include a source region 420, a drain region 430, and a channel region 440 between the source region 420 and the drain region 430. The Si layer 415 including the source, drain, and channel regions 420, 430, 440 may be similar to the Si layer 215 including the source, drain, and channel regions 220, 230, 240 of Figures 2A and 2B described above, and therefore a detailed description thereof will be omitted for the sake of brevity.

[0048]

[0054] The transistor 400A may include a gate oxide 450 on the channel region 440 on a first side of the Si layer 415. The gate oxide 450 may be similar to the gate oxide 250 of Figures 2A and 2B described above, and therefore a detailed description thereof is omitted for the sake of brevity.

[0049]

[0055] A gate 480 may be formed on the gate oxide 450. Therefore, the gate 480 may also be on the first side of the Si layer 415. In this case, the gate 480 may be trapezoidal in shape to improve the gate resistance Rg. In one embodiment, the gate 480 may be in direct contact with the gate oxide 450. The gate 480 may be formed from an electrically conductive material such as polysilicon, metal, etc.

[0050]

[0056] A source contact 460A may be formed on a second side of the Si layer 415. The source contact 460A may be similar to the source contact 260A of Figure 2A described above, and therefore a detailed description thereof is omitted for the sake of brevity.

[0051]

[0057] A drain contact 470 may also be formed on the second side of the Si layer 415. The drain contact 470 may be similar to the drain contact 270 of Figures 2A and 2B described above, and therefore a detailed description thereof is omitted for the sake of brevity.

[0052]

[0058] Note again that the source and drain contacts 460A, 470 are on opposite sides of the gate 480, which means that the gate 480 can be sized to improve the gate resistance Rg without increasing the undesirable parasitic capacitances Cgs and Cgd. That is, the use of double-sided contacts allows much more freedom to optimize the gate shape and thus improve the gate resistance Rg without degrading the parasitic capacitances Cgs and Cgd.

[0053]

[0059] The shape of the gate 480 may be another form of the shape of the gate 380 of Figures 3A and 3B. That is, the shape of the gate 480 may be described as follows. The gate 480 may have a first and a second gate length. The first gate length may represent the length of a portion of the gate 480 closer to the gate oxide 450 (e.g., a lower portion of the gate 480), and the second gate length may represent the length of a portion of the gate 480 farther from the gate oxide 450 (e.g., an upper portion of the gate 480). As can be seen, the first gate length may be shorter than the second gate length.

[0054]

[0060] Although not specifically shown, a gate contact and gate connection may be formed on gate 480, which may be similar to gate contact 290 and gate connection 295. Transistor 400A may further include source connection 465A and drain connection 475 to allow electrical connection to other devices. Source connection 465A and drain connection 475 may be similar to source connection 265A and drain connection 275 of FIG. 2A.

[0055]

[0061] 4B illustrates a cross-sectional view of transistor 400B according to one or more embodiments of the present disclosure. Transistor 400B may be similar to transistor 400A (of FIG. 4A), except that source contact 460B is on a first side of Si layer 415, i.e., on the same side as gate 480. The reasons for having source contact 460B on the same side as gate 480 may be similar to those discussed above with respect to source contact 260B, and therefore will not be repeated for brevity.

[0056]

[0062] The transistor 400B may further include a source connection 465B electrically coupled to the source contact 460B. For example, the source connection 465B may be in direct contact with the source contact 460B. The source connection 465B may be similar to the source connection 265B of FIG. 2B, and therefore, a description thereof will be omitted.

[0057]

[0063] 5A illustrates a cross-sectional view of a transistor 500A according to one or more embodiments of the present disclosure. The transistor 500A may be a SOI field effect transistor. As can be seen, the transistor 500A may include a BOX layer 510 and a Si layer 515 on the BOX layer 510.

[0058]

[0064] The Si layer 515 may include a source region 520, a drain region 530, and a channel region 540 between the source region 520 and the drain region 530. The Si layer 515 including the source, drain, and channel regions 520, 530, 540 may be similar to the Si layer 215 including the source, drain, and channel regions 220, 230, 240 of Figures 2A and 2B described above, and therefore a detailed description thereof will be omitted for the sake of brevity.

[0059]

[0065] The transistor 500A may comprise a gate oxide 550 on the channel region 540 on a first side of the Si layer 515. The gate oxide 550 may be similar to the gate oxide 250 of Figures 2A and 2B at least in the materials forming the gate oxides 250, 550. However, the gate oxide 550 may extend over a portion of the source region 520. That is, the gate oxide 550 may overlap at least a portion of the source region 520.

[0060]

[0066] In general, the gate oxide (e.g., gate oxide 250, 350, 450, 550, etc.) may overlap at least a portion of the channel region (e.g., channel region 240, 340, 440, 540, etc.). In some embodiments, the gate oxide (e.g., gate oxide 250, 350, 450, 550, etc.) may also overlap at least a portion of the drain region (e.g., drain region 230, 330, 430, 530). However, in this case, even if the gate oxide 550 overlaps the drain region 530, the portion of the source region 520 overlapped by the gate oxide 550 may be larger than the portion of the drain region 530 overlapped by the gate oxide 550.

[0061]

[0067] A gate 580 may be formed on the gate oxide 550. Therefore, the gate 580 may also be on the first side of the Si layer 515. The gate 580 may be in direct contact with the gate oxide 550. The gate 580 may be formed from an electrically conductive material such as polysilicon, metal, etc. In one embodiment, the gate 580 may be formed to be aligned with the gate oxide 550. In this case, it can be said that the portion of the source region 520 overlapped by the gate oxide 550 and the gate 580 may be larger than the portion of the drain region 530 overlapped by the gate oxide 550 and the gate 580. More generally, the gate 580 and / or the gate oxide 550 may be centered between the source and drain regions 520, 530, but they do not have to be centered. For example, the center of the gate 580 and / or the center of the gate oxide 550 may be closer to the source region 520 than the drain region 530.

[0062]

[0068] Although not shown, gates of various shapes can have a larger extension over the source region than over the drain region. For example, a mushroom shaped gate 380 can be formed in the gate oxide 350 to overlap a portion of the source region 320 that is larger than the drain region 330. As another example, a trapezoid shaped gate 480 can be formed in the gate oxide 350 to overlap a portion of the source region 420 that is larger than the drain region 430.

[0063]

[0069] Also, although not specifically shown, a gate contact and gate connection may be formed on gate 580, which may be similar to gate contact 290 and gate connection 295. Transistor 500A may further include source connection 565A and drain connection 575 to enable electrical connection with other devices. Source connection 565A and / or drain connection 575 may be formed from a conductive metal (e.g., Cu, Al, etc.).

[0064]

[0070] A source contact 560A may be formed on a second side of the Si layer 515. The source contact 560A may be similar to the source contact 260A of Figure 2A described above, and therefore a detailed description thereof is omitted for the sake of brevity.

[0065]

[0071] A drain contact 570 may also be formed on the second side of the Si layer 515. The drain contact 570 may be similar to the drain contact 270 of Figures 2A and 2B described above, and therefore a detailed description thereof is omitted for the sake of brevity.

[0066]

[0072] The source and drain contacts 560A, 570 are on opposite sides of the gate 580, which means that the gate 580 can be sized to improve the gate resistance Rg without increasing the undesirable parasitic capacitances Cgs and Cgd. That is, using double-sided contacts allows much more freedom to optimize the gate shape and thus improve the gate resistance Rg without degrading the parasitic capacitances Cgs and Cgd.

[0067]

[0073] Although not specifically shown, a gate contact and gate connection may be formed on gate 580, which may be similar to gate contact 290 and gate connection 295. Transistor 500A may further include source connection 565A and drain connection 575 to enable electrical connection with other devices. Source connection 565A and drain connection 575 may be similar to source connection 265A and drain connection 275 of FIG. 2A.

[0068]

[0074] 5B illustrates a cross-sectional view of transistor 500B according to one or more embodiments of the present disclosure. Transistor 500B may be similar to transistor 500A (of FIG. 5A), except that source contact 560B is on a first side of Si layer 515, i.e., on the same side as gate 580. The reasons for having source contact 560B on the same side as gate 580 may be similar to those discussed above with respect to source contact 260B, and therefore will not be repeated for brevity.

[0069]

[0075] The transistor 500B may further include a source connection 565B electrically coupled to the source contact 560B. For example, the source connection 565B may be in direct contact with the source contact 560B. The source connection 565B may be similar to the source connection 265B of FIG. 2B, and therefore, a description thereof will be omitted.

[0070]

[0076] 6A-6F show example stages of fabricating a gate of a transistor according to one or more aspects of the present disclosure. In this case, exemplary stages of fabricating a mushroom-shaped gate (e.g., gate 380) are shown.

[0071]

[0077] 6A shows the steps of providing the following layers from bottom to top: an oxide layer 610 (e.g., a BOX layer), a silicon (Si) layer 615 (e.g., an SOI layer), a gate oxide layer 651, and a lower gate layer 681. The lower gate layer 681 may be formed of a conductive material (e.g., polysilicon, metal, etc.).

[0072]

[0078] FIG. 6B shows the step in which gate oxide layer 651 and bottom gate layer 681 are etched to form gate oxide 650 and bottom gate portion 682 .

[0073]

[0079] FIG. 6C shows a stage where a first dielectric layer 625 is deposited over the Si layer 615 and over the bottom gate portion 682 and planarized to expose the bottom gate portion 682 .

[0074]

[0080] FIG. 6D shows a step in which a second dielectric layer 635 is deposited over the first dielectric layer 625 and the bottom gate portion 682 .

[0075]

[0081] 6E shows that a step in the second dielectric layer 635 is etched (e.g., through a photoresist (PR) process) to form a gate window 685 that exposes the lower gate portion 682. Note that the gate window 685 is longer than the lower gate portion 682.

[0076]

[0082] 6F shows that a top gate layer is deposited and planarized to fill the gate window 685 and form the gate 680. The top gate layer may be conductive and may be the same material as the bottom gate portion 682.

[0077]

[0083] 7A-7D show example stages for fabricating a gate of a transistor according to one or more aspects of the present disclosure. In this case, exemplary stages for fabricating a trapezoidal gate (e.g., gate 480) are shown.

[0078]

[0084] FIG. 7A shows that from bottom to top, the following layers are provided: an oxide layer 710 (eg, a BOX layer), a silicon (Si) layer 715 (eg, a SOI layer), and a dielectric layer 725.

[0079]

[0085] FIG. 7B shows the stage where the dielectric layer 725 is etched to form a gate window 785 .

[0080]

[0086] FIG. 7C shows the step in which a dielectric material (the same or different material as the dielectric layer 725 ) is deposited in the gate window 785 to form a spacer 737 .

[0081]

[0087] FIG. 7D shows that oxide and conductive material are deposited and planarized in gate window 785 to form gate oxide 750 and gate 780 .

[0082]

[0088] 8 illustrates a flowchart of an example method 800 of fabricating a transistor (e.g., transistors 200A, 200B, 300A, 300B, 400A, 400B, 400A, 400B, etc.) in accordance with one or more aspects of the present disclosure. In block 805, a buried oxide (BOX) layer (e.g., BOX layer 210, 310, 410, 510, etc.) may be formed.

[0083]

[0089] In block 810, a silicon (Si) layer (e.g., Si layer 215, 315, 415, 515, etc.) may be formed on the BOX layer. The Si layer may include a source region (e.g., source region 220, 320, 420, 520, etc.), a drain region (e.g., drain region 230, 330, 430, 530, etc.), and a channel region (channel region 240, 340, 440, 540, etc.) between the source and drain regions. In one aspect, the Si layer may be formed in direct contact with the BOX layer.

[0084]

[0090] In block 820, a gate oxide (e.g., gate oxide 250, 350, 450, 550, etc.) may be formed on the channel region on a first side of the Si layer. The gate oxide may at least partially overlap the channel region and directly contact the Si layer. The gate oxide may also overlap at least a portion of the source region and / or at least a portion of the drain region.

[0085]

[0091] At block 830, a gate (e.g., gate 280, 380, 480, 580, etc.) may be formed on the gate oxide. The gate may be in direct contact with the gate oxide and may be formed from an electrically conductive material such as polysilicon, a metal, etc.

[0086]

[0092] 9 illustrates a flowchart of an example process for implementing blocks 820 and 830 according to one or more aspects of the present disclosure. The flowchart in FIG. 9 may relate to forming a mushroom-shaped gate (e.g., gate 380) (see also FIGS. 6A-6F).

[0087]

[0093] In block 910, a gate oxide layer (e.g., gate oxide layer 651) may be deposited on a first side of a Si layer (e.g., Si layer 615), and a bottom gate layer (e.g., bottom gate layer 681) may be deposited on the gate oxide layer. Block 910 may correspond to the stage shown in FIG. 6A.

[0088]

[0094] In block 920, the gate oxide layer and the lower gate layer may be etched to form a gate oxide (e.g., gate oxide 650) and a lower gate portion (e.g., lower gate portion 682). Block 920 may correspond to the step shown in FIG.

[0089]

[0095] In block 930, a first dielectric layer (eg, the first dielectric layer 625) may be deposited on the Si layer and the bottom gate portion.

[0090]

[0096] The first dielectric layer may be planarized to expose the lower gate portion in block 940. Blocks 930 and 940 may correspond to the steps shown in Figure 6C.

[0091]

[0097] A second dielectric layer (e.g., second dielectric layer 635) may be deposited on the first dielectric layer and the lower gate portion in block 950. Block 950 may correspond to the stage shown in FIG.

[0092]

[0098] In block 960, the second dielectric layer may be etched to form a gate window (e.g., gate window 685) to expose the lower gate portion. The gate window may be longer than the lower gate portion 682. Block 960 may correspond to the stage shown in FIG.

[0093]

[0099] In block 970, the gate window can be filled with a conductive top gate layer, which can be the same material as the bottom gate portion.

[0094]

[0100] In block 980, the upper gate layer may be planarized to form a gate, such as gate 680. Blocks 970 and 980 may correspond to the step shown in Figure 6F.

[0095]

[0101] 10 illustrates a flowchart of another example process for implementing blocks 820 and 830 according to one or more aspects of the present disclosure. The flowchart in FIG. 10 may relate to forming a trapezoidal gate (e.g., gate 480) (see also FIGS. 7A-7D).

[0096]

[0102] In block 1010, a dielectric layer (e.g., dielectric layer 725) may be deposited on a first side of a Si layer (e.g., Si layer 715). Block 1010 may correspond to the stage shown in FIG. 7A.

[0097]

[0103] In block 1020, the dielectric layer may be etched to form a gate window (e.g., gate window 785) to expose a portion of the Si layer. Block 1020 may correspond to the step shown in FIG. 7B.

[0098]

[0104] In block 1030, a spacer (e.g., spacer 737) may be formed in the gate window to form a trapezoidal opening. Block 1030 may correspond to the step shown in FIG. 7C.

[0099]

[0105] In block 1040, a gate oxide layer (eg, gate oxide layer 750) may be formed in the gate window.

[0100]

[0106] In block 1050, a conductive gate material may be deposited over the gate material in the gate window.

[0101]

[0107] In block 1060, the gate material may be planarized to form a gate, such as gate 780. Blocks 1040, 1050, and 1060 may correspond to the steps shown in Figure 7D.

[0102]

[0108] 8, in block 832, a gate contact (e.g., gate contact 290) may be formed directly on the gate. More broadly, the gate contact may be formed to be electrically coupled to the gate.

[0103]

[0109] In block 834, a gate connection (e.g., gate connection 295) may be formed directly on the gate contact. More broadly, the gate connection may be formed to be electrically coupled to the gate contact. Blocks 832 and 834 are shown with dashed lines to indicate that the blocks are optional in one or more aspects.

[0104]

[0110] In block 840, a source contact (e.g., source contact 260A, 260B, 360A, 360B, 460A, 460B, 560A, 560B, etc.) may be formed on and electrically coupled to the source region. For example, the source contact may be in direct contact with the source region. In one or more embodiments, the source contact may be on a second side of the Si layer, opposite the first side. In this case, the source contact may be formed through the BOX layer. In one or more other embodiments, the source contact may be on a first side of the Si layer, i.e., on the same side of the Si layer as the gate.

[0105]

[0111] In block 850, a drain contact (e.g., drain contact 270, 370, 470, 570, etc.) may be formed on a second side of the Si layer. The drain contact may be electrically coupled to the drain region. For example, the drain contact may be in direct contact with the source region. The drain contact may be formed through the BOX layer.

[0106]

[0112] It will be understood that the foregoing fabrication process and related description are provided merely as general illustrations of some of the aspects of the present disclosure, and are not intended to limit the scope of the present disclosure or the appended claims. Furthermore, many details in the fabrication process known to those skilled in the art may be omitted or combined in a summary process section to facilitate understanding of the various aspects disclosed without detailed description of each detail and / or all possible process variations. Furthermore, it will be understood that the illustrated configurations and descriptions are provided merely to aid in the explanation of the various aspects disclosed herein. For example, the number and location of inductors, metallization structures may have more or fewer conductive and insulating layers, cavity orientation, size, whether formed of multiple cavities, closed or open, and other aspects may have variations driven by specific application design features such as the number of antennas, antenna type, frequency range, power, etc. Thus, the foregoing illustrative examples and related figures should not be construed as limiting the various aspects disclosed and claimed herein.

[0107]

[0113] 11 illustrates various electronic devices 1100 that may be integrated with any of the aforementioned devices according to various aspects of the disclosure. For example, a mobile phone device 1102, a laptop computer device 1104, and a stationary terminal device 1106 may each be generally considered user equipment (UE) and may include one or more transistors (e.g., 200A, 200B, 300A, 300B, 400A, 400B, 500A, 500B) as described herein. The devices 1102, 1104, 1106 illustrated in FIG. 11 are merely illustrative. Other electronic devices may also include RF filters including groups of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communications system (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented within automotive vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0108]

[0114] The devices and functions disclosed above may be designed and configured into computer files (e.g., RTL, GDSII, GERBER, etc.) stored on a computer readable medium. Some or all of such files may be provided to a fabricator who fabricates devices based on such files. The resulting product may include a semiconductor wafer that is then cut into semiconductor dies and packaged with an antenna on a glass device. The antenna on the glass device may then be used in the devices described herein.

[0109]

[0115] The following numbered clauses describe example implementations.

[0110]

[0116] Clause 1: A transistor comprising: a silicon (Si) layer including a source region, a drain region, and a channel region therebetween; a gate oxide on the channel region on a first side of the Si layer; a gate on the gate oxide; a source contact electrically coupled to the source region; and a drain contact on a second side of the Si layer opposite the first side of the Si layer, the drain contact electrically coupled to the drain region, wherein the first gate length is shorter than a second gate length, the first gate length being a length of a portion of the gate closer to the gate oxide and the second gate length being a length of a portion of the gate farther from the gate oxide.

[0111]

[0117] Clause 2: The transistor of clause 1, further comprising a buried oxide (BOX) layer on a second side of the Si layer, the drain contact being formed through the BOX layer.

[0112]

[0118] Clause 3: The transistor of clause 1 or 2, wherein the source contact is on the first side of the Si layer.

[0113]

[0119] Clause 4: The transistor of clause 1 or 2, wherein a source contact is on a second side of the Si layer.

[0114]

[0120] Clause 5. The transistor of clause 4, further comprising a buried oxide (BOX) layer on the second side of the Si layer, the source contact being formed through the BOX layer.

[0115]

[0121] Clause 6: The transistor of any one of clauses 1 to 5, wherein the gate is mushroom shaped.

[0116]

[0122] Clause 7: The transistor of any one of clauses 1 to 5, wherein the gate is trapezoidal.

[0117]

[0123] Clause 8: The transistor of any one of clauses 1 to 7, wherein the transistor is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

[0118]

[0124] Clause 9: A transistor comprising: a silicon (Si) layer including a source region, a drain region, and a channel region therebetween; a gate oxide on the channel region on a first side of the Si layer; a gate on the gate oxide; a source contact electrically coupled to the source region; and a drain contact on a second side of the Si layer opposite the first side of the Si layer, the drain contact being electrically coupled to the drain region, wherein a center of the gate is closer to the source region than the drain region.

[0119]

[0125] Clause 10: The transistor of clause 9, wherein the gate oxide and the gate overlap at least a portion of the source region.

[0120]

[0126] Clause 11: The transistor of clause 10, wherein the gate oxide and a portion of the source region overlapped by the gate are larger than the gate oxide and a portion of the drain region overlapped by the gate.

[0121]

[0127] Clause 12. The transistor of any one of clauses 9-11, further comprising a buried oxide (BOX) layer on the second side of the Si layer, the drain contact being formed through the BOX layer.

[0122]

[0128] Clause 13: The transistor of any one of clauses 9-12, wherein a source contact is on the first side of the Si layer.

[0123]

[0129] Clause 14: The transistor of any one of clauses 9-12, wherein a source contact is on a second side of the Si layer.

[0124]

[0130] Clause 15: The transistor of any one of clauses 9 to 14, wherein the transistor is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

[0125]

[0131] Clause 16: A method of making a transistor, comprising: forming a silicon (Si) layer including a source region, a drain region, and a channel region therebetween; forming a gate oxide on a first side of the Si layer over the channel region; forming a gate on the gate oxide; forming a source contact electrically coupled to the source region; and forming a drain contact on a second side of the Si layer opposite the first side of the Si layer, the drain contact electrically coupled to the drain region, wherein the first gate length is shorter than a second gate length, the first gate length being a length of a portion of the gate closer to the gate oxide and the second gate length being a length of a portion of the gate farther from the gate oxide.

[0126]

[0132] Clause 17: The method of clause 16, further comprising forming a buried oxide (BOX) layer on the second side of the Si layer, the drain contact being formed through the BOX layer.

[0127]

[0133] Clause 18: The method of clause 16 or 17, wherein a source contact is formed on the first side of the Si layer.

[0128]

[0134] Clause 19: The method of clause 16 or 17, wherein a source contact is formed on a second side of the Si layer.

[0129]

[0135] Clause 20. The method of clause 19, further comprising forming a buried oxide (BOX) layer on the second side of the Si layer, the source contact being formed through the BOX layer.

[0130]

[0136] Clause 21: The method of any one of clauses 16 to 20, wherein the gate is mushroom shaped.

[0131]

[0137] Clause 22: The method of clause 21, wherein forming a gate oxide and forming a gate includes depositing a gate oxide layer on a first side of the Si layer and a lower gate layer on the gate oxide layer, etching the gate oxide layer and the lower gate layer to form a gate oxide and a lower gate portion, depositing a first dielectric layer on the Si layer and on the lower gate portion, planarizing the first dielectric layer to expose the lower gate portion, depositing a second dielectric layer on the first dielectric layer and on the lower gate portion, etching the second dielectric layer to form a gate window to expose the lower gate portion, the gate window being longer than the lower gate portion, filling the gate window with an upper gate layer, and planarizing the upper gate layer to form a gate.

[0132]

[0138] Clause 23: The method of any one of clauses 16 to 20, wherein the gate is trapezoidal.

[0133]

[0139] Clause 24: The method of clause 23, wherein forming a gate oxide and forming a gate includes depositing a dielectric layer on a first side of the Si layer, etching the dielectric layer to form a gate window to expose a portion of the Si layer, forming a spacer in the gate window to form a trapezoidal opening, forming a gate oxide layer on the Si layer in the gate window, depositing a gate material on the gate oxide layer in the gate window, and planarizing the gate material to form a gate.

[0134]

[0140] Clause 25: A method of making a transistor, comprising: forming a silicon (Si) layer including a source region, a drain region, and a channel region therebetween; forming a gate oxide on a first side of the Si layer over the channel region; forming a gate on the gate oxide; forming a source contact electrically coupled to the source region; and forming a drain contact on a second side of the Si layer opposite the first side of the Si layer, the drain contact electrically coupled to the drain region, wherein a center of the gate is closer to the source region than the drain region.

[0135]

[0141] Clause 26: The method of clause 25, wherein the gate oxide and the gate overlap at least a portion of the source region.

[0136]

[0142] Clause 27: The method of clause 26, wherein the gate oxide and a portion of the source region overlapped by the gate are larger than the portion of the drain region overlapped by the gate oxide and the gate.

[0137]

[0143] Clause 28. The method of any one of clauses 25-27, further comprising forming a buried oxide (BOX) layer on the second side of the Si layer, the drain contact being formed through the BOX layer.

[0138]

[0144] Clause 29. The method of any one of clauses 25-28, wherein a source contact is formed on a first side of the Si layer.

[0139]

[0145] Clause 30. The method of any one of clauses 25-28, wherein a source contact is formed on a second side of the Si layer.

[0140]

[0146] As used herein, terms such as "user equipment" (or "UE"), "user device", "user terminal", "client device", "communication device", "wireless device", "wireless communication device", "handheld device", "mobile device", "mobile terminal", "mobile station", "handset", "access terminal", "subscriber device", "subscriber terminal", "subscriber station", "terminal", and variations thereof may interchangeably refer to any suitable mobile or fixed device capable of receiving wireless communication and / or navigation signals. These terms include, but are not limited to, music players, video players, entertainment units, navigation devices, communication devices, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, automotive devices in automotive vehicles, and / or other types of portable electronic devices that are typically carried by a person and / or have communication capabilities (e.g., wireless, cellular, infrared, short range radio, etc.). These terms are also intended to include a device that communicates with another device capable of receiving wireless communication and / or navigation signals, such as by a short-range wireless connection, an infrared connection, a wired connection, or other connection, regardless of whether the satellite signal reception, assistance data reception, and / or location-related processing is performed on that device or on another device. Furthermore, these terms are intended to include all devices, including wireless and wired communication devices, that can communicate with a core network via a radio access network (RAN), through which the UE can connect to external networks, such as the Internet, and to other UEs. Of course, other mechanisms for connecting to a core network and / or the Internet are also possible for a UE, such as via a wired access network, a wireless local area network (WLAN) (e.g., based on IEEE 802.11, etc.), etc.A UE may be embodied by any of several types of devices, including, but not limited to, a printed circuit (PC) card, a compact flash device, an external or internal modem, a wireless or wired phone, a smart phone, a tablet, a tracking device, an asset tag, etc. A communication link through which a UE can transmit signals to a RAN is called an uplink channel (e.g., a reverse traffic channel, a reverse control channel, an access channel, etc.). A communication link through which a RAN can send signals to a UE is called a downlink channel or a forward link channel (e.g., a paging channel, a control channel, a broadcast channel, a forward traffic channel, etc.). As used herein, the term traffic channel (TCH) may refer to either an uplink / reverse traffic channel or a downlink / forward traffic channel.

[0141]

[0147] Wireless communication between electronic devices can be based on various technologies such as Code Division Multiple Access (CDMA), W-CDMA, Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE), 5G New Radio, Bluetooth (BT), Bluetooth Low Energy (BLE), IEEE 802.11 (WiFi), and IEEE 802.15.4 (Zigbee / Thread) or other protocols that may be used in wireless or data communication networks. Bluetooth Low Energy (also known as Bluetooth LE, BLE, and Bluetooth Smart) is a wireless personal area network technology designed and marketed by the Bluetooth Special Interest Group that aims to significantly reduce power consumption and cost while maintaining a similar communication range. BLE was integrated into the main Bluetooth standard in 2010 by adopting the Bluetooth Core Specification Version 4.0 and was updated in Bluetooth 5.

[0142]

[0148] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any detail described herein as "exemplary" should not be construed as advantageous over other examples. Likewise, the term "example" does not imply that all examples include the discussed features, advantages, or modes of operation. Furthermore, particular features and / or structures may be combined with one or more other features and / or structures. Moreover, at least a portion of the apparatus described herein may be configured to perform at least a portion of the methods described herein.

[0143]

[0149] It should be noted that the terms "connected" and "coupled," or any variation thereof, mean any direct or indirect connection or coupling between elements, unless the connection is expressly disclosed as being directly connected, and may encompass the presence of intermediate elements between two elements that are "connected" or "coupled" together through intermediary elements.

[0144]

[0150] Any reference herein to an element using a designation such as "first," "second," etc. is not intended to limit the quantity and / or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and / or instances of an element. Also, unless otherwise stated, a set of elements can comprise one or more elements.

[0145]

[0151] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0146]

[0152] Nothing described or illustrated in this application is intended to publicly disclose any element, act, feature, benefit, advantage, or equivalent, whether or not that element, act, feature, benefit, advantage, or equivalent is recited in a claim.

[0147]

[0153] In the above detailed description, it can be seen that in each example, various features are grouped together. This method of disclosure should not be understood as the claimed examples having more features than are expressly recited in each claim. Rather, the disclosure may include fewer features than all of the individual examples disclosed. Thus, the following claims are hereby considered incorporated into this description, and each claim can stand alone as a separate example. Although each claim can stand alone as a separate example, it should be noted that a dependent claim can refer to a specific combination with one or more claims within the scope of the claim, while other examples can include or include a combination of the dependent claim with the subject matter of any other dependent claim, or a combination of any feature with other dependent claims and independent claims. Such combinations are suggested herein unless it is expressly stated that a specific combination is not intended. It is further intended that a feature of a claim can be included in any other independent claim, even if the claim is not directly dependent on the independent claim.

[0148]

[0154] It is further noted that the methods, systems and apparatus disclosed in the present description or claims may be implemented by a device comprising means for performing the respective acts and / or functions of the disclosed methods.

[0149]

[0155] Further, in some examples, an individual act may be subdivided into or include one or more sub-acts, and such sub-acts may be included in and be part of the disclosure of the individual act.

[0150]

[0156] Although the above disclosure illustrates exemplary examples of the present disclosure, it should be noted that various modifications and changes can be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions and / or acts of the method claims according to the examples of the present disclosure described herein need not be performed in any particular order. In addition, well-known elements may not be described in detail or may be omitted so as not to obscure the relevant details of the aspects and examples disclosed herein. Furthermore, although elements of the present disclosure may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Claims

1. A transistor, a silicon (Si) layer including a source region, a drain region, and a channel region therebetween; a gate oxide on the channel region on a first side of the Si layer; a gate on the gate oxide; a source contact electrically coupled to the source region; a drain contact on a second side of the Si layer opposite the first side of the Si layer, the drain contact being electrically coupled to the drain region; Equipped with 1. A transistor, comprising: a first gate length that is shorter than a second gate length, the first gate length being the length of a portion of the gate that is closer to the gate oxide and the second gate length being the length of a portion of the gate that is further from the gate oxide.

2. 2. The transistor of claim 1, further comprising a buried oxide (BOX) layer on the second side of the Si layer, the drain contact being formed through the BOX layer.

3. The transistor of claim 1 , wherein the source contact is on the first side of the Si layer.

4. The transistor of claim 1 , wherein the source contact is on the second side of the Si layer.

5. 5. The transistor of claim 4, further comprising a buried oxide (BOX) layer on the second side of the Si layer, the source contact being formed through the BOX layer.

6. The transistor of claim 1 , wherein the gate is mushroom shaped.

7. The transistor of claim 1 , wherein the gate is trapezoidal.

8. 10. The transistor of claim 1 , wherein the transistor is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

9. A transistor, a silicon (Si) layer including a source region, a drain region, and a channel region therebetween; a gate oxide on the channel region on a first side of the Si layer; a gate on the gate oxide; a source contact electrically coupled to the source region; a drain contact on a second side of the Si layer opposite the first side of the Si layer, the drain contact being electrically coupled to the drain region; Equipped with A transistor, wherein the center of the gate is closer to the source region than to the drain region.

10. The transistor of claim 9 , wherein the gate oxide and the gate overlap at least a portion of the source region.

11. 11. The transistor of claim 10, wherein the portion of the source region overlapped by the gate oxide and the gate is larger than the portion of the drain region overlapped by the gate oxide and the gate.

12. 10. The transistor of claim 9, further comprising a buried oxide (BOX) layer on the second side of the Si layer, the drain contact being formed through the BOX layer.

13. The transistor of claim 9 , wherein the source contact is on the first side of the Si layer.

14. The transistor of claim 9 , wherein the source contact is on the second side of the Si layer.

15. 10. The transistor of claim 9, wherein the transistor is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a stationary terminal, a tablet computer, a computer, a wearable device, an Internet of Things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

16. 1. A method of fabricating a transistor, comprising the steps of: forming a silicon (Si) layer including a source region, a drain region, and a channel region therebetween; forming a gate oxide on the channel region on a first side of the Si layer; forming a gate on the gate oxide; forming a source contact electrically coupled to the source region; forming a drain contact on a second side of the Si layer opposite the first side of the Si layer, the drain contact being electrically coupled to the drain region; Including, 1. A method according to claim 1, wherein a first gate length is shorter than a second gate length, the first gate length being the length of a portion of the gate closer to the gate oxide and the second gate length being the length of a portion of the gate farther from the gate oxide.

17. 17. The method of claim 16, further comprising forming a buried oxide (BOX) layer on the second side of the Si layer, the drain contact being formed through the BOX layer.

18. The method of claim 16 , wherein the source contact is formed on the first side of the Si layer.

19. The method of claim 16 , wherein the source contact is formed on the second side of the Si layer.

20. 20. The method of claim 19, further comprising forming a buried oxide (BOX) layer on the second side of the Si layer, the source contact being formed through the BOX layer.

21. The method of claim 16 , wherein the gate is mushroom shaped.

22. forming the gate oxide and forming the gate depositing a gate oxide layer on the first side of the Si layer and a bottom gate layer on the gate oxide layer; etching the gate oxide layer and the lower gate layer to form the gate oxide and lower gate portions; depositing a first dielectric layer over the Si layer and over the lower gate portion; planarizing the first dielectric layer to expose the lower gate portion; depositing a second dielectric layer over the first dielectric layer and over the lower gate portion; etching the second dielectric layer to form a gate window to expose the lower gate portion, the gate window being longer than the lower gate portion; filling the gate window with a top gate layer; planarizing the upper gate layer to form the gate; 22. The method of claim 21 , comprising:

23. The method of claim 16 , wherein the gate is trapezoidal in shape.

24. forming the gate oxide and forming the gate depositing a dielectric layer on the first side of the Si layer; Etching the dielectric layer to form a gate window to expose a portion of the Si layer; forming a spacer within the gate window to form a trapezoidal opening; forming a gate oxide layer on the Si layer in the gate window; depositing a gate material on the gate oxide layer in the gate window; planarizing the gate material to form the gate; 24. The method of claim 23, comprising:

25. 1. A method of fabricating a transistor, comprising the steps of: forming a silicon (Si) layer including a source region, a drain region, and a channel region therebetween; forming a gate oxide on the channel region on a first side of the Si layer; forming a gate on the gate oxide; forming a source contact electrically coupled to the source region; forming a drain contact on a second side of the Si layer opposite the first side of the Si layer, the drain contact being electrically coupled to the drain region; Including, The method of claim 1, wherein the center of the gate is closer to the source region than to the drain region.

26. 26. The method of claim 25, wherein the gate oxide and the gate overlap at least a portion of the source region.

27. 27. The method of claim 26, wherein the portion of the source region overlapped by the gate oxide and the gate is larger than the portion of the drain region overlapped by the gate oxide and the gate.

28. 26. The method of claim 25, further comprising forming a buried oxide (BOX) layer on the second side of the Si layer, the drain contact being formed through the BOX layer.

29. 26. The method of claim 25, wherein the source contact is formed on the first side of the Si layer.

30. 26. The method of claim 25, wherein the source contact is formed on the second side of the Si layer.

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