N-polar III-nitride device structures with P-type layers

Abstract

Reduction of gate leakage in N-polar III-N semiconductor devices. The N-polar III-N high electron mobility transistor device can include a III-N channel layer on the N-face of a III-N back barrier, where a compositional difference between the channel layer and the back barrier induces a 2DEG channel in the III-N channel layer adjacent the interface between the III-N channel layer and the back barrier. The device can further include a p-type III-N layer on the III-N channel layer and a thick III-N cap layer on the p-type III-N layer. The III-N cap layer can increase the charge density of the 2DEG channel directly below the cap layer, and the p-type III-N layer acts to prevent parasitic 2DEG formation in the III-N cap layer.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE This disclosure relates to semiconductor material structures and devices, particularly devices formed from N-polar Group III-nitride layers. [Background technology]

[0002] III-nitride semiconductor devices, such as III-N high electron mobility transistors (HEMTs), are typically formed from III-N material structures grown with a group-III polar orientation (i.e., [0 0 0 1] direction) on a substrate. FIG. 1 illustrates an example of a III-polar III-N HEMT device 100. In device 100, III-N layers 111, 112, and 113 are formed with a group-III polar orientation (i.e., [0 0 0 1] direction as shown) on a suitable substrate 110, such as silicon (Si), silicon carbide (SiC), sapphire, or GaN. III-N layer 111 is a buffer layer and can be formed from AlN, AlGaN, GaN, or combinations thereof. III-N layer 112 is a channel layer, such as GaN. III-N layer 113 is a barrier layer, such as AlGaN. The composition of the III-N layers 112, 113 is selected so that a two-dimensional electron gas (2DEG) channel 120 is induced in the III-N channel layer 112 extending from the source 121 to the drain 122. A gate insulator 132 is formed on the III-N barrier layer 113, and a gate 123 is formed on the gate insulator 132. A voltage applied to the gate 123 relative to the source 121 modulates the charge in the 2DEG 120 beneath the gate 123, thereby modulating the current flowing between the source 121 and the drain 122 during operation of the device.

[0003] A nitrogen-polar (N-polar) III-N HEMT device 200 (i.e., a device with III-N layers 211, 213, and 212 oriented in the [0 0 0 -1] direction on a substrate 210) is shown in FIG. 2. In device 200, III-N channel layer 212 (i.e., the layer that includes 2DEG channel 220) is formed on III-N barrier layer 213 (hence, in N-polar III-N HEMTs, the barrier layer is often referred to as a "back barrier"). Gate insulator 232 serves to reduce gate leakage, which may be more persistent in N-polar devices compared to III-polar devices, because in N-polar devices, there is no III-N barrier layer (e.g., layer 213) between gate 223 and the channel. In many cases, N-polar III-N devices such as device 200 can have lower contact resistance (e.g., the contact resistance at each of source contact 221 and drain contact 222) compared to III-polar III-N devices such as device 100. However, other challenges remain with N-polar III-N technology. Summary of the Invention

[0004] In a first aspect, a semiconductor device includes a III-N back barrier including one or more III-N layers, the one or more III-N layers of the III-N back barrier including a first III-N layer. The semiconductor device further includes a III-N channel layer on an N-face of the first III-N layer, a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer, a p-type III-N layer on an N-face of the III-N channel layer, and a III-N cap layer on an N-face of the p-type III-N layer. The III-N channel layer and the III-N cap layer each have a band gap smaller than the band gap of the first III-N layer.

[0005] In a second aspect, a semiconductor device includes a III-N back barrier including one or more III-N layers, the one or more III-N layers of the III-N back barrier including a first III-N layer. The semiconductor device further includes a III-N channel layer on an N-face of the first III-N layer, a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer, a p-type III-N layer on an N-face of the III-N channel layer, and a III-N cap layer on an N-face of the p-type III-N layer. The conduction band energy of the first III-N layer adjacent to the interface between the III-N channel layer and the first III-N layer is greater than the conduction band energy of the III-N channel layer.

[0006] In a third embodiment, a semiconductor device includes a III-N back barrier including one or more III-N layers, the one or more III-N layers of the III-N back barrier including a first III-N layer. The semiconductor device further includes a III-N channel layer on an N-face of the first III-N layer, the first III-N layer having a larger bandgap than the III-N channel layer. The semiconductor device further includes a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer, a p-type III-N layer on an N-face of the III-N channel layer, and an n-type III-N layer between the III-N channel layer and the p-type III-N layer.

[0007] In a fourth embodiment, a semiconductor device includes a III-N back barrier including one or more III-N layers, the one or more III-N layers of the III-N back barrier including a first III-N layer. The semiconductor device further includes a III-N channel layer on an N-face of the first III-N layer, the III-N channel layer including a gate region and a plurality of access regions opposite the gate region. The semiconductor device further includes a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer, a III-N barrier layer on an N-face of the III-N channel layer, a III-N cap layer on an N-face of the III-N barrier layer, and a p-type III-N layer. The III-N channel layer and the III-N cap layer each have a bandgap smaller than a bandgap of both the first III-N layer and the III-N barrier layer, and both the III-N barrier layer and the III-N cap layer are over an access region of the III-N channel layer but not over the gate region of the III-N channel layer.

[0008] Any of the devices described herein may each include one or more of the following features, either alone or in combination with each other: The band gap of the p-type III-N layer may be smaller than the band gap of the first III-N layer. The III-N channel layer may have a thickness larger than the thickness of the p-type III-N layer. The III-N cap layer may have a thickness larger than the thickness of the III-N channel layer. The device may further include a III-N barrier layer between the III-N channel layer and the p-type III-N layer, and the band gaps of the III-N channel layer and the p-type III-N layer may each be smaller than the band gap of the III-N barrier layer. The device may further include an n-type III-N layer between the III-N channel layer and the p-type III-N layer. The n-type III-N layer may have at least 10 16 cm -3The p-type III-N layer may be a first p-type III-N layer, and the semiconductor device may further include a second p-type III-N layer and a III-N barrier layer, and the III-N barrier layer may be between the first p-type layer and the second p-type layer. The band gaps of the III-N channel layer, the n-type III-N layer, the first and second p-type III-N layers, and the III-N cap layer may each be smaller than the band gap of the III-N barrier layer. The III-N channel layer may include a gate region and a plurality of access regions opposite the gate region, and the semiconductor device may further include a source contact, a drain contact, and a gate contact, and the gate contact may be on the gate region of the III-N channel layer. The III-N cap layer may be on the access region of the III-N channel layer but not on the gate region of the III-N channel layer. The device may further include a plurality of contacts on the N-face of the III-N channel layer, the plurality of contacts may include a source contact, a gate contact, and a drain contact. The III-N channel layer may include a gate region and a plurality of access regions opposite the gate region, the III-N cap layer may be on the access region of the III-N channel layer but not on the gate region of the III-N channel layer, and a gate contact may be on the gate region of the III-N channel layer. The device may further include a gate insulator between the gate contact and the III-N channel layer. The thickness of the p-type III-N layer is less than 8 nm, and the acceptor concentration in the p-type III-N layer is less than 10 18 cm -3 The acceptor concentration in the p-type III-N layer may be lower than the donor concentration in the n-type III-N layer. The donor concentration in the n-type III-N layer may be at least 10 16 cm -3The device may further include a gate contact on the gate region of the III-N channel layer, and the p-type III-N layer may be between the gate contact and the III-N channel layer. The p-type III-N layer may be in direct contact with the III-N channel layer, the III-N barrier layer, and the III-N cap layer.

[0009] In another aspect, a method for forming a semiconductor device includes forming a III-N back barrier on a substrate, the III-N back barrier having a group III face close to the substrate and an N face opposite the group III face, the III-N back barrier including one or more III-N layers, the one or more III-N layers of the III-N back barrier including a first III-N layer. The method further includes forming a III-N channel layer on the N face of the first III-N layer, forming a p-type III-N layer on the N face of the III-N channel layer, and forming a III-N cap layer on the N face of the p-type III-N layer. The III-N channel layer and the III-N cap layer can each have a band gap smaller than the band gap of the first III-N layer. Additionally, the semiconductor device can include a 2DEG channel in the III-N channel layer adjacent to an interface between the III-N channel layer and the first III-N layer.

[0010] Any of the methods described herein may each include one or more of the following features, either alone or in combination with each other: The method may include forming a recess through the full thickness of the III-N cap layer in a gate region of the semiconductor device and depositing a gate contact on the gate region of the semiconductor device. The recess may extend through the full thickness of the p-type III-N layer. The method may further include forming a III-N barrier layer between the III-N channel layer and the p-type III-N layer. The method may further include forming a gate insulator between the III-N barrier layer and the gate contact. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view of a group III-polarity III-N transistor device.

[0012] [Diagram 2] FIG. 1 is a cross-sectional view of an N-polarity III-N transistor device.

[0013] [Diagram 3] FIG. 1 illustrates a cross-sectional view of one embodiment of an N-polarity III-N transistor device. [Figure 4] FIG. 1 illustrates a cross-sectional view of one embodiment of an N-polarity III-N transistor device. [Diagram 5] FIG. 1 illustrates a cross-sectional view of one embodiment of an N-polarity III-N transistor device.

[0014] [Figure 6] FIG. 6 is a cross-sectional view of a portion of the N-polarity III-N transistor device of FIG.

[0015] [Figure 7] FIG. 1 is a cross-sectional view of another embodiment of an N-polarity III-N transistor device.

[0016] [Figure 8] 8A-8D illustrate a method of forming the transistor device of FIG. 7.

[0017] [Figure 9] FIG. 13 is a cross-sectional view illustrating another embodiment of an N-polarity III-N transistor device. [Figure 10] FIG. 13 is a cross-sectional view illustrating another embodiment of an N-polarity III-N transistor device. [Figure 11] FIG. 13 is a cross-sectional view illustrating another embodiment of an N-polarity III-N transistor device. [Figure 12] FIG. 13 is a cross-sectional view illustrating another embodiment of an N-polarity III-N transistor device.

[0018] [Figure 13A] 13A-13C illustrate a method of forming the transistor device of FIG. 12. [Figure 13B] 13A-13C illustrate a method of forming the transistor device of FIG. 12. [Figure 13C] 13A-13C illustrate a method of forming the transistor device of FIG. 12. [Figure 13D] 13A-13C illustrate a method of forming the transistor device of FIG. 12. [Figure 13E] 13A-13C illustrate a method of forming the transistor device of FIG. 12. [Figure 13F] 13A-13C illustrate a method of forming the transistor device of FIG. 12.

[0019] [Figure 14] FIG. 13 is a cross-sectional view illustrating another embodiment of an N-polarity III-N transistor device. [Figure 15] FIG. 13 is a cross-sectional view illustrating another embodiment of an N-polarity III-N transistor device.

[0020] Like numbers in the drawings represent like elements. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Detailed Description Described herein are N-polar III-nitride semiconductor devices suitable for a variety of applications, including RF electronics and power conversion. Each device includes a p-type III-N layer configured to address a variety of device performance issues that may otherwise arise. As used herein, the terms III-nitride or III-N materials, layers, devices, and the like refer to N-polar III-N semiconductor devices having the stoichiometric formula Sc v B w Al x In y Ga z N a (D) bIt refers to a material or device composed of a compound semiconductor material. Here, v + w + x + y + z is approximately 1, where 0 ≦ v ≦ 1, 0 ≦ w ≦ 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, a + b is approximately 1, 0.9 < a ≦ 1, 0 ≦ b < 0.1, and (D) is any Group V element other than nitrogen. In an III-N transistor device, the channel through which current flows can be included within one or more III-N layers of the device.

[0022] Figure 3 is a cross-sectional view of an example of an N-polarity III-N semiconductor device 300. The device 300 includes a substrate 310 and a plurality of III-N layers 311, 313, 312 formed on the substrate 310 with an N-polarity orientation (i.e., in the [0 0 0 -1] direction as shown). The substrate 310 can be any substrate suitable for epitaxially growing III-N layers thereon, for example, silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), or sapphire (Al2O3). The III-N layer 311 is a buffer layer and can be formed of AlN, AlGaN, GaN, or a combination thereof. The III-N layer 313 formed on the N surface of the III-N buffer layer 311 functions as a back barrier. The III-N layer 312 formed on the N surface of the III-N back barrier 313 functions as a channel layer.

[0023] The compositions of the III-N back barrier 313 and the III-N channel layer 312 are selected such that a two-dimensional electron gas (2DEG) channel 320 is induced in the III-N channel layer 312 adjacent to the interface between the III-N channel layer 312 and the III-N back barrier 313. To induce the 2DEG channel 320, the compositions of the III-N layers 312 and 313 may be selected such that the conduction band energy of the III-N back barrier 313 adjacent to the interface between the layers 312 and 313 is greater than the conduction band energy of the III-N channel layer 312. That is, at the interface between the III-N layers 312 and 313, there may be a conduction band energy discontinuity, with the conduction band energy on the back barrier side of the interface being greater than the conduction band energy on the channel layer side of the interface. Such a conduction band energy discontinuity can typically be achieved by selecting a material for the III-N channel layer 312 that has a band gap smaller than the band gap of the III-N back barrier 313. For example, the III-N channel layer 312 can be made of GaN, and the III-N back barrier can be made of Al x Ga 1-x N, and the aluminum fraction composition x may be in the range 0.2≦x≦0.4.

[0024] The III-N back barrier 313 can be formed as a single III-N layer or as multiple III-N layers. For example, as can be seen from FIG. 4, the III-N back barrier 313 can include a first III-N layer 441 and a second III-N layer 442. FIG. 4 shows an embodiment 300′ of the device of FIG. 3. In this embodiment, the back barrier 313 is implemented as multiple III-N layers. When the III-N back barrier 313 is formed as a single layer, the entire III-N back barrier 313 is implemented as a first III-N layer. When the III-N back barrier 313 is formed as multiple III-N layers, the first III-N layer 441 may be adjacent to the III-N channel layer 312 or may be in direct contact with the III-N channel layer 312. This results in the 2DEG channel 320 being adjacent to the interface between the III-N channel layer 312 and the first III-N layer 441 of the III-N back barrier 313. In this case, the first III-N layer 441 may have a larger bandgap than the III-N channel layer 312. In some embodiments, the first III-N layer 441 may be formed of AlN.

[0025] The device 300 further includes a III-N barrier layer 314 on the N-face of the III-N channel layer 312. The III-N barrier layer 314 can be formed of a material with a larger bandgap than the III-N channel layer 312. For example, if the III-N channel layer 312 is formed of GaN, the III-N barrier layer 314 can be formed of Al. y Ga 1-y The III-N barrier layer 314 may be formed of 0.1≦y≦0.6, where the aluminum fraction composition y may be in the range of 0.1≦y≦0.6. The III-N barrier layer 314 serves to reduce gate leakage in the device and increase the breakdown voltage of the device. However, the III-N barrier layer 314 may also reduce the charge density in the 2DEG channel 320 due to polarization of the layer. To minimize this charge density reduction, the thickness of the III-N barrier layer 314 may be thin, e.g., less than 10 nm, less than 8 nm, less than 5 nm, or less than 3 nm.

[0026] The device 300 further includes a source contact 321 and a drain contact 322, and a gate contact 323 between the source and drain contacts. An optional gate insulator 332 may be included between the gate contact 323 and the III-N material below to reduce gate leakage during operation of the device. A voltage applied to the gate contact 323 relative to the source contact 321 modulates the charge on the 2DEG 320 in the gate region of the device, thereby modulating the current flowing between the source contact 321 and the drain contact 322 during operation of the device. The source contact 321 and the drain contact 322 are each electrically connected to the 2DEG channel 320. As used herein, two or more contacts or other items such as conductive layers or components are said to be "electrically connected" when they are connected by a material that is sufficiently conductive so that the potential of each contact or other item is always the same, i.e., nearly identical, under any bias condition. As used herein, a "gate region" of a device or one or more layers of a device refers to the region that includes the portion of the 2DEG channel that is modulated by the gate contact, which is typically located directly beneath the gate contact. As used herein, a "contact region" of a device or one or more layers of a device is the region immediately beneath the source and drain contacts. As used herein, an "access region" of a device or one or more layers of a device is the region between the gate region and the contact region. The access region between the source contact and the gate region is typically referred to as the source access region, and the access region between the drain contact and the gate region is typically referred to as the gate access region.

[0027] 5 is a cross-sectional view of an N-polar III-N semiconductor device 500 according to another example. The device 500 includes a substrate 510, a III-N buffer layer 511, a III-N back barrier 513, a III-N channel layer 512, and a III-N barrier layer 514. The substrate 510 and the III-N layers 511, 513, 512, 514 may be similar or identical to the layers 310, 311, 313, 312, 314, respectively, of the device 300 of FIG. 3. As with other devices described herein, the compositions of the III-N back barrier 513 and the III-N channel layer 512 are selected such that a 2DEG channel 520 is induced in the III-N channel layer 512 adjacent to the interface between the III-N channel layer 512 and the III-N back barrier 513. Source and drain contacts 521 and 522, respectively, are formed on regrown III-N n-type region 516 that is sufficiently conductive to electrically connect the source and drain contacts to 2DEG channel 520, although alternatively, source and drain contacts 521 and 522, respectively, may be in direct contact with 2DEG channel 520, as in device 300.

[0028] The device 500 is similar to the device 300 of FIG. 3, but further includes a thick III-N cap layer 515 over the access regions of the III-N layers 511, 513, 512, and 514. The III-N cap layer 515 can be formed by first depositing the III-N cap layer material as a single layer and then etching the entire thickness of the III-N cap layer over the gate and contact regions of the device 500, leaving the III-N cap layer material only over the access regions. A gate insulator 532 is conformally deposited in a recess formed in the III-N cap layer 515 over the gate region of the device. The gate insulator 532 may optionally extend over the top surface of the III-N cap layer 515 as shown. A gate contact 523 is formed on the gate insulator 532 over the gate region of the device, in a recess formed through the III-N cap layer 515.

[0029] The III-N cap layer 515 may have a bandgap smaller than that of the III-N back barrier 513 or a bandgap smaller than that of the first III-N layer of the III-N back barrier 513. For example, if the III-N back barrier 513 (or the first III-N layer of the III-N back barrier 513) is Al x Ga 1-x If the III-N cap layer 515 is made of GaN (0.2≦x≦0.4), the III-N cap layer 515 may be made of GaN. The III-N cap layer 515 may have a bandgap smaller than the bandgap of the III-N barrier layer 514. For example, if the III-N barrier layer 514 is made of Al y Ga 1-y When the III-N cap layer 515 is made of GaN (0.1≦y≦0.6), the III-N cap layer 515 may be made of GaN. The III-N cap layer 515 may be undoped or may be unintentionally doped. The concentration of all dopants in the III-N cap layer is greater than 10 17 cm -3 Less than 10 16 cm -3 Less than or equal to 10 15 cm -3 It may be less than.

[0030] The III-N channel layer 512 may be thin, e.g., may have a thickness of less than 25 nm, less than 20 nm, less than 18 nm, less than 15 nm, or less than 13 nm. The thickness of the III-N cap layer 515 may be thicker than the thickness of the III-N channel layer 512. For example, the thickness of the III-N cap layer 515 may be greater than 25 nm, greater than 30 nm, greater than 35 nm, or greater than 40 nm.

[0031] The III-N cap layer 515 can increase the charge density of the 2DEG channel 520 directly below the cap layer, for example in the device access region, and can also reduce the effects of DC-RF dispersion in the device by moving surface states associated with the top surface of the III-N material away from the 2DEG channel 520. Thus, the thickness of the III-N cap layer 515 can be greater than the thickness of the III-N channel layer 512, for example, greater than 10 nm, greater than 20 nm, greater than 30 nm, or greater than 40 nm. In some embodiments, the reduction in 2DEG charge density due to the inclusion of the III-N barrier layer 514 can be at least partially offset in the device access region by the inclusion of the III-N cap layer 515. This reduces parasitic source and drain resistances in the device 500, improving device performance. However, as shown in Fig. 6, which is a close-up of a portion of device 500, the compositional difference between III-N barrier layer 514 and III-N cap layer 515 (described above) can also lead to the formation of a secondary parasitic 2DEG 530 in III-N cap layer 515. This typically occurs when the thickness of III-N cap layer 515 is greater than about 12 nm (the exact thickness at which the parasitic 2DEG is induced depends at least in part on the composition of III-N barrier layer 514 and III-N cap layer 515). This parasitic 2DEG 530 can reduce the lateral barrier between gate contact 523 and drain contact 522, respectively, and increase gate leakage in the device during operation.

[0032] FIG. 7 is a cross-sectional view of another N-polar III-N device 700 similar to the device 500 of FIG. 5, but further including a p-type III-N layer 717 in the device access region (but not in the gate region) between the III-N cap layer 515 and the III-N barrier layer 514. The p-type III-N layer 717 serves to prevent a parasitic 2DEG (e.g., 2DEG 530 shown in FIG. 6) from forming in the III-N cap layer 515. This reduces gate leakage of the device during operation, but may slightly reduce the 2DEG charge density in the device access region and increase the parasitic source and drain resistances. This reduction in 2DEG charge density can be minimized by making the thickness of the p-type III-N layer 717 very thin and the p-type doping level very high. For example, the thickness of the p-type III-N layer can be less than 10 nm, less than 8 nm, less than 6 nm, or less than 5 nm, and the concentration of acceptors can be less than 5×10 17 cm -3 Higher than 10 18 cm -3 Higher than 4×10 18 cm -3 Higher than or 8×10 18 cm -3 can be made higher than

[0033] The device 700 of FIG. 7 can be formed according to the method 800 shown in FIG. 8. First, a III-N buffer layer (e.g., layer 511) is formed (e.g., epitaxially grown) on a substrate (e.g., substrate 510) with the N-face of the III-N buffer layer facing away from the substrate and the group III face adjacent to the substrate (step 801). Next, a III-N back barrier (e.g., layer 513) is formed on the N-face of the III-N buffer layer (step 802). Next, a III-N channel layer (e.g., layer 512) is formed on the N-face of the III-N back barrier (step 803). If the III-N back barrier is formed of multiple III-N layers and includes a first III-N layer (e.g., layer 441 of FIG. 4), the III-N channel layer may be formed on the N-face of the first III-N layer. Next, a III-N barrier layer (e.g., layer 514) is formed on the N-face of the III-N channel layer (step 804). Next, a p-type III-N layer (e.g., layer 717) is formed on the N-face of the III-N barrier layer (step 805), and then a III-N cap layer (e.g., layer 515) is formed on the N-face of the p-type III-N layer (step 806). Next, an etch is performed to remove the III-N cap layer 515, the p-type III-N layer 717, and the III-N barrier layer in the contact region of the device (step 807), and selective area epitaxial growth is performed to form III-N n-type region 516 in the contact region of the device (step 808). Next, an etch is performed in the gate region of the device to form a recess that extends through the entire thickness of the III-N cap layer 515 and the p-type III-N layer 717 (step 809). To precisely control the depth of the recess, an etch that is selective between the III-N cap layer 515, the p-type III-N layer 717, and the III-N barrier layer 514 may be used.That is, the etching process used to form the recess can selectively etch the material of the III-N cap layer 515 (e.g., unintentionally doped or n-type GaN) and the p-type III-N layer 717 (e.g., p-type GaN) at a higher rate than the material of the III-N barrier layer 514 (e.g., AlyGa1-yN), thereby stopping the etch precisely at or near the top surface (i.e., the [0 0 0 -1] plane) of the III-N barrier layer 514. Finally, source and drain contacts (e.g., contacts 521 and 522, respectively) are deposited on the III-N n-type region 516, optionally a gate insulator 532 is deposited on the III-N material layer, and a gate contact 523 is deposited on the gate region of the device (step 810).

[0034] FIG. 9 is a cross-sectional view of another N-polar III-N device 900 similar to device 700 of FIG. 7, but also including a p-type III-N layer 717 under the gate contact 523 in the gate region of the device. Device 900 can be formed by adding the following modifications to method 800. When forming a recess in the gate region of the device (step 809 of method 800), the recess is formed to penetrate the III-N cap layer 515 but not the p-type III-N layer 717. To precisely control the depth of the recess, an etch that has selectivity between the III-N cap layer 515 and the p-type III-N layer 717 may be used. That is, the etch process used to form the recess can selectively etch the material of the III-N cap layer 515 (e.g., unintentionally doped or n-type GaN) at a higher rate than the material of the p-type III-N layer 717 (e.g., p-type GaN), thereby precisely stopping the etch at or near the top surface (i.e., the [0 0 0 -1] plane) of the p-type III-N layer 717. All other steps for forming device 900 are the same as those of method 800 .

[0035] FIG. 10 is a cross-sectional view of another N-polar III-N device 1000 similar to device 900 of FIG. 9, except that in device 1000, III-N barrier layer 514 is omitted and p-type III-N layer 717 is formed directly on III-N channel layer 512 (and on its N-face). Device 1000 can be formed by adding the following modifications to method 800: omitting step 804 and forming a p-type III-N layer on the N-face of the III-N channel layer instead in step 805. Furthermore, when forming a recess in the gate region of the device (step 809 of method 800), the recess is formed through the III-N cap layer but not through the p-type III-N layer. All other steps for forming device 1000 are the same as those of method 800.

[0036] 11 is a cross-sectional view of another N-polar III-N device 1100 similar to the device 1000 of FIG. 10, except that the device 1100 further includes an n-type III-N layer 1118 between the III-N channel layer 512 and the p-type III-N layer 717, thereby forming a p-n junction in the gate region. The inclusion of the n-type III-N layer 1118 may increase the 2DEG charge density, which may at least partially offset the decrease in 2DEG charge density due to the inclusion of the p-type III-N layer 717. Additionally, as shown in FIG. 11, the gate insulator 532 may be omitted, with the gate contact 523 directly contacting the p-type III-N layer 717. Thus, a voltage applied to gate contact 523 relative to source contact 521 to modulate the 2DEG charge density in the gate region is applied directly to p-type III-N layer 717, thereby modulating the voltage across the p-n junction formed by p-type III-N layer 717 and n-type III-N layer 1118.

[0037] When selecting the doping densities and thicknesses of the p-type III-N layer 717 and the n-type III-N layer 1118, it may be preferable to select a small thickness for each of these layers to maintain a large coupling between the gate contact 523 and the 2DEG channel 520 in the gate region of the device 1100. Furthermore, a large donor density in the n-type III-N layer 1118 is preferable to increase the 2DEG charge density, but in order to fully deplete the n-type III-N layer 1118, the areal donor density of the n-type III-N layer 1118 needs to be smaller than the areal acceptor density of the p-type III-N layer 717. If the n-type III-N layer 1118 is not fully depleted, there may be a path for source-drain leakage current through the n-type III-N layer 1118 during operation of the device. Furthermore, it may be preferable to have a large doping density in the p-type III-N layer such that the areal acceptor density in the p-type III-N layer 717 is large enough to suppress the formation of a parasitic 2DEG channel in the III-N cap layer 515. As used herein, the "area density" of a dopant (e.g., donor or acceptor) or charge carrier (e.g., electron or hole) in a material layer refers to the density of the dopant or charge carrier per unit cross-sectional area in the layer when viewed perpendicular to the surface (or interface) of the layer. If the dopant or charge carrier density is uniform throughout the layer, the areal density of the dopant or charge carrier is simply the product of the dopant / carrier density and the thickness of the layer. If the dopant or charge carrier density varies across the thickness of the layer, the areal density is equal to the integral of the dopant / carrier density over the thickness of the layer.

[0038] In view of the above, the thickness of the p-type III-N layer 717 can be less than 20 nm, less than 15 nm, less than 12 nm, or less than 10 nm, and the concentration of the acceptors can be less than 5×10 17 cm -3 Greater than 10 18 cm -3 Larger, 4×10 18 cm -3 Larger, 8×10 18 cm-3 Greater than or 10 19 cm -3 The thickness of the n-type III-N layer 1118 can be less than 20 nm, less than 15 nm, less than 12 nm, less than 10 nm, or less than 5 nm, and the concentration of donors can be less than 5×10 17 cm -3 Greater than 10 18 cm -3 Larger, 4x10 18 cm -3 Larger, 8x10 18 cm -3 Greater than 10 19 cm -3 Larger, 2x10 19 cm -3 Larger or 3x10 19 cm -3 The areal donor density of the n-type III-N layer 1118 may be lower than the areal acceptor density of the p-type III-N layer 717, and may be, for example, less than 90%, less than 80%, less than 60%, less than 40%, less than 20%, or less than 10% of the areal acceptor density of the p-type III-N layer 717. The areal donor density of the n-type III-N layer 1118 may be in the range of 10% to 99% of the areal acceptor density of the p-type III-N layer 717.

[0039] 12 is a cross-sectional view of another configuration 1100′ of the device shown in FIG. 11. In the configuration 1100′, both the III-N cap layer 515 and the p-type III-N layer 717 are removed in the contact regions, but the n-type III-N layer 1118 is not removed in the contact regions, and the source contact 521 and the drain contact 522 are directly on and in contact with the n-type III-N layer 1118, respectively. Because the p-type III-N layer 717 is removed in the contact regions, the n-type III-N layer 1118 is not depleted in these regions. Thus, low resistance ohmic contacts can be formed at the source contact 521 and the drain contact 522, respectively, and the source contact and the drain contact can be electrically connected to the 2DEG channel 520.

[0040] A method for forming the device 1100' is shown in Figures 13A-13F. First, the various N-polar III-N layers (510, 511, 513, 512, 1118, 717, 515) of the device 1100' are sequentially formed on a substrate 510, and a mask layer 1333 is formed on the III-N cap layer 515 (Figure 13A). The mask layer 1333 can be formed of silicon dioxide (SiO2) or other dielectric or polymeric materials. An opening 1342 is then etched through the mask layer 1333 (Figure 13B). The mask layer 1333 is then used as a hard mask to form a recess 1343 in the III-N cap layer 515 in the gate region of the device (Figure 13C). A gate contact 523 is then deposited in the recess of the III-N cap layer 515, in the opening of the mask layer 1333, and on a portion of the top surface of the mask layer 1333 (Figure 13D). Next, the portion of the gate contact 523 on the top surface of the mask layer 1333 is used as an etch mask to remove the mask layer 1333, the III-N cap layer 515, and the p-type III-N layer 717 in the contact region of the device (FIG. 13E). Next, metal deposition is performed to deposit the source contact 521 and the drain contact 522, respectively, and a portion of the source-drain metal 1223 is also deposited on the gate contact 523 (FIG. 13F). Note that in the method 1300, the source contact 521 and the drain contact 522 can be self-aligned to the gate contact 523 by using a line of sight deposition technique such as metal evaporation for each of these contacts. The thickness of the source contact 521 and the drain contact 522 can be less than the combined thickness of layers 717, 515, and 1333 to prevent the source and / or drain contacts from shorting to the gate contact 523. Finally, the remainder of the mask layer 1333 is removed to obtain the device 1100′ of FIG. 12.

[0041] FIG. 14 is a cross-sectional view of another N-polar III-N device 1400 similar to the device 1100′ of FIG. 12. The device 1400 differs in that it further includes a second p-type III-N layer 1417 and further includes a III-N barrier layer 1414 between the p-type III-N layers 717 and 1417. The III-N barrier layer 1414 can have a similar or identical composition and thickness as the III-N barrier layer 514 of FIGS. 5-7 and 9. The III-N barrier layer 1414 serves as an etch stop layer during fabrication of the device 1400, allowing for good process control when etching III-N material in the device contact regions prior to depositing the source and drain contacts 521 and 522, respectively.

[0042] FIG. 15 is a cross-sectional view of another N-polar III-N device 1500 similar to the device 500 of FIG. 5. The device 1500 differs in that it does not include a gate insulator between the gate contact 523 and the underlying III-N material (e.g., III-N barrier layer 514 and III-N cap layer 515). Instead, after forming a recess through the III-N cap layer 515 and III-N barrier layer 514 and forming an insulating layer 1532 on the III-N material, the material of the insulating layer 1532 (which serves as the gate insulator for the device 500) on the gate region of the device 1500 is removed, and a p-type III-N layer 1517 (e.g., p-type GaN) is regrown in the gate region on the top surface of the III-N barrier layer 514 and along the sidewalls of the III-N cap layer 515. The gate contact 523 is formed directly on and in contact with the p-type III-N layer 1517, as shown. The thickness of the regrown p-type III-N layer 1517 can be less than 20 nm, less than 15 nm, less than 12 nm, in the range of 2 nm to 20 nm, in the range of 2 nm to 15 nm, or in the range of 2 nm to 12 nm. The acceptor concentration of the p-type III-N layer 1517 can be the same as that described above for the p-type III-N layer 717 of the device 700 of FIG. 7. Although not shown in FIG. 15, the p-type III-N layer 1517 can be optionally formed on the top surface of the III-N cap layer 515 (between layers 515 and 1532 or instead of layer 1532) and / or the p-type III-N layer 1517 can be optionally formed on the III-N n-type region 516.

[0043] Various devices and their material structures have been described above, along with methods of forming the devices. It should be understood, however, that these are presented by way of example only, and not by way of limitation. While several embodiments have been specifically illustrated and described, it will be understood that various changes in form and detail may be made. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. 1. A semiconductor device comprising: a III-N back barrier comprising one or more III-N layers, the one or more III-N layers of the III-N back barrier comprising a first III-N layer; a III-N channel layer on an N-face of the first III-N layer; a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the first III-N layer; a p-type III-N layer on an N-face of the III-N channel layer; a III-N cap layer on the N-face of the p-type III-N layer; wherein the III-N channel layer and the III-N cap layer each have a bandgap smaller than a bandgap of the first III-N layer.

2. 2. The semiconductor device of claim 1, wherein the bandgap of the p-type III-N layer is smaller than the bandgap of the first III-N layer.

3. 2. The semiconductor device of claim 1, wherein the thickness of the III-N channel layer is greater than the thickness of the p-type III-N layer.

4. 2. The semiconductor device of claim 1, wherein a thickness of the III-N cap layer is greater than a thickness of the III-N channel layer.

5. 2. The semiconductor device of claim 1, further comprising a III-N barrier layer between the III-N channel layer and the p-type III-N layer, wherein the bandgaps of the III-N channel layer and the p-type III-N layer are each smaller than the bandgap of the III-N barrier layer.

6. 2. The semiconductor device of claim 1, further comprising an n-type III-N layer between the III-N channel layer and the p-type III-N layer.

7. The n-type III-N layer has at least 10 １６ cm －３ 7. The semiconductor device of claim 6, wherein the donor is doped at a concentration of

8. 7. The semiconductor device of claim 6, wherein the p-type III-N layer is a first p-type III-N layer, the semiconductor device further comprising a second p-type III-N layer and a III-N barrier layer, the III-N barrier layer being between the first p-type layer and the second p-type layer.

9. 9. The semiconductor device of claim 8, wherein the bandgaps of the III-N channel layer, the n-type III-N layer, the first and second p-type III-N layers, and the III-N cap layer are each smaller than the bandgap of the III-N barrier layer.

10. the III-N channel layer includes a gate region and a plurality of access regions opposite the gate region; The semiconductor device further includes a source contact, a drain contact, and a gate contact; 2. The semiconductor device of claim 1, wherein the gate contact is on the gate region of the III-N channel layer.

11. 11. The semiconductor device of claim 10, wherein the III-N cap layer is over an access region of the III-N channel layer but not over the gate region of the III-N channel layer.

12. 1. A semiconductor device comprising: a III-N back barrier comprising one or more III-N layers, the one or more III-N layers of the III-N back barrier comprising a first III-N layer; a III-N channel layer on an N-face of the first III-N layer; a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the first III-N layer; a p-type III-N layer on an N-face of the III-N channel layer; a III-N cap layer on the N-face of the p-type III-N layer; wherein a conduction band energy of the first III-N layer adjacent the interface between the III-N channel layer and the first III-N layer is greater than a conduction band energy of the III-N channel layer.

13. 13. The semiconductor device of claim 12, further comprising a plurality of contacts on the N-face of the III-N channel layer, the plurality of contacts including a source contact, a gate contact, and a drain contact.

14. the III-N channel layer includes a gate region and a plurality of access regions opposite the gate region; the III-N cap layer overlies the access region of the III-N channel layer but not overlies the gate region of the III-N channel layer; The semiconductor device of claim 13 , wherein the gate contact is on the gate region of the III-N channel layer.

15. The semiconductor device of claim 14 , further comprising a gate insulator between the gate contact and the III-N channel layer.

16. The thickness of the p-type III-N layer is less than 8 nm, and the acceptor concentration in the p-type III-N layer is less than 10 １８ cm －３ The semiconductor device of claim 12 .

17. 1. A semiconductor device comprising: a III-N back barrier comprising one or more III-N layers, the one or more III-N layers of the III-N back barrier comprising a first III-N layer; a III-N channel layer on an N-face of the first III-N layer, the first III-N layer having a larger bandgap than the III-N channel layer; and a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the first III-N layer; a p-type III-N layer on an N-face of the III-N channel layer; an n-type III-N layer between the III-N channel layer and the p-type III-N layer; A semiconductor device comprising:

18. 18. The semiconductor device of claim 17, wherein an acceptor concentration in the p-type III-N layer is lower than a donor concentration in the n-type III-N layer.

19. The donor concentration in the n-type III-N layer is at least 10 １６ cm －３ 20. The semiconductor device of claim 17, wherein:

20. 1. A semiconductor device comprising: a III-N back barrier comprising one or more III-N layers, the one or more III-N layers of the III-N back barrier comprising a first III-N layer; a III-N channel layer on an N-face of the first III-N layer, the III-N channel layer including a gate region and a plurality of access regions opposite the gate region; a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the first III-N layer; a III-N barrier layer on an N-face of the III-N channel layer; a III-N cap layer on the N-face of the III-N barrier layer; A p-type III-N layer; Including, the III-N channel layer and the III-N cap layer each have a bandgap smaller than a bandgap of both the first III-N layer and the III-N barrier layer; a gate region of the III-N channel layer, the gate region being not overlying the III-N channel layer; and a barrier layer of the III-N channel layer and a cap layer of the III-N channel layer.

21. 21. The semiconductor device of claim 20, further comprising a gate contact on the gate region of the III-N channel layer, the p-type III-N layer being between the gate contact and the III-N channel layer.

22. 22. The semiconductor device of claim 21, wherein the p-type III-N layer is in direct contact with the III-N channel layer, the III-N barrier layer, and the III-N cap layer.

23. 1. A method of forming a semiconductor device, comprising: forming a III-N back barrier on a substrate, the III-N back barrier having a group III face proximate to the substrate and an N face opposite the group III face, the III-N back barrier including one or more III-N layers, the one or more III-N layers of the III-N back barrier including a first III-N layer; forming a III-N channel layer on an N-face of the first III-N layer; forming a p-type III-N layer on an N-face of the III-N channel layer; forming a III-N cap layer on the N-face of the p-type III-N layer; Including, the III-N channel layer and the III-N cap layer each have a bandgap smaller than a bandgap of the first III-N layer; the semiconductor device includes a 2DEG channel in the III-N channel layer adjacent an interface between the III-N channel layer and the first III-N layer.

24. 24. The method of claim 23, further comprising forming a recess through the entire thickness of the III-N cap layer in a gate region of the semiconductor device and depositing a gate contact on the gate region of the semiconductor device.

25. The method of claim 24, wherein the recess extends through the entire thickness of the p-type III-N layer.

26. 25. The method of claim 24, further comprising forming a III-N barrier layer between the III-N channel layer and the p-type III-N layer.

27. 27. The method of claim 26, further comprising forming a gate insulator between the III-N barrier layer and the gate contact.

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