High electron mobility transistor and method for fabricating same

Abstract

2. A method for fabricating a high electron mobility transistor (1), comprising: providing a target wafer (10) comprising a target substrate (100); providing a donor wafer (20) comprising an epitaxial donor film (21); bonding the donor film (21) to the target wafer (10); forming a sub-200 nm top surface layer (221) on the target wafer (10) by separating the donor wafer (20) and the target wafer (10) along the first donor III-N layer (201); epitaxially growing an epitaxial III-N semiconductor layer stack (31, 32) on the top surface layer (221); forming a gate contact (41) at a gate region (401); and forming a substrate galvanic contact (42) in contact with the target substrate (100).

Description

[Technical field]

[0001]

[01] The present invention relates generally to, among other things, semiconductor structures and methods for their growth. More particularly, the present invention relates to high electron mobility transistors including nitride-based active layers that exhibit superior performance for high power and high frequency applications, and methods for their fabrication. [Background technology]

[0002]

[02] Semiconductor devices including gallium nitride, also referred to as GaN, and / or III-nitride based heterostructures, such as InAlGaN / GaN heterostructures, can carry large currents and support high voltages. As such, they are increasingly desirable for power semiconductor devices. Devices fabricated for high power / high frequency applications are generally based on device structures that exhibit high electron mobility and high critical electric fields, and are referred to as heterojunction field effect transistors (also referred to as HFETs), high electron mobility transistors (also referred to as HEMTs), or modulation doped field effect transistors (also referred to as MODFETs). HEMTs are useful for analog circuit applications, such as RF / microwave power amplifiers and power switches. Such devices are typically capable of withstanding high voltages, such as up to 1.000 volts, or operating at high frequencies, such as 100 kHz to 100 GHz.

[0003]

[03] GaN HEMTs are typically fabricated on conventional substrates, such as semi-insulating silicon carbide substrates, also known as SiC, or high-resistivity silicon substrates. For high power and high frequency applications, it is indeed essential to maximize the resistivity of the substrate on which the device is based. The growth of GaN HEMTs typically begins with the growth of an AlN nucleation layer on top of the substrate. Such AlN nucleation layers typically exhibit a high threading dislocation density. To obtain better crystal quality when growing GaN HEMTs on an AlN nucleation layer, i.e. to obtain a lower threading dislocation density when growing GaN HEMTs on an AlN nucleation layer, it is customary to grow a GaN buffer layer, e.g. 1 μm thick, on top of the AlN nucleation layer.

[0004]

[04] Such GaN HEMTs are prone to trapping effects from both the surface of the HEMT and the GaN buffer layer or GaN bulk layer grown on top of the AlN nucleation layer. The traps in the GaN buffer / bulk layer result from intentional impurities, e.g., carbon and iron, that are introduced into the GaN buffer / bulk layer to make it more resistive. The addition of these intentional impurities allows for a higher breakdown voltage and lower leakage current in the GaN HEMT. In other words, there are always background impurities in the GaN buffer / bulk layer to increase the confinement, which creates trapping effects in the resulting GaN HEMT.

[0005]

[05] Moreover, such GaN buffer layers create a thermal impedance between the active GaN HEMT and the heat sink at the bottom of the substrate on which the active GaN HEMT is fabricated, causing a decrease in performance and a decrease in the reliability of the GaN HEMT. Similarly, in addition to the AlN nucleation layer, when growing GaN HEMTs on silicon substrates, a strain management buffer must be grown in addition to the GaN buffer layer, which increases the total thickness of the layer stack, for example to 2 μm. These buffer layers constitute a significant thermal impedance for the GaN HEMT.

[0006]

[06] As the need for higher power and higher frequency solutions increases, the telecommunications industry faces the challenge of making such III-nitride based active devices compatible with existing technologies. For example, III-nitride based active devices should enable the continued miniaturization and performance improvement of microelectronic devices. Summary of the Invention

[0007]

[07] Accordingly, embodiments of the present invention aim to propose a high electron mobility transistor and a method for fabricating the same that do not exhibit the drawbacks inherent in the prior art. More particularly, embodiments of the present invention aim to propose a high electron mobility transistor and a method for fabricating the same that have improved performance and reliability at high power and high frequency.

[0008]

[08] The scope of protection sought for various embodiments of the invention is defined by the independent claims.

[0009]

[09] The embodiments and features described in this specification that do not fall within the scope of the independent claims, if any, should be construed as examples useful for understanding various embodiments of the invention.

[0010]

[10] There is a need for high electron mobility transistors with improved resistivity, reduced power loss and linearity issues, and semiconductor structures that are fabrication compatible with existing technologies.

[0011]

[11] There is a need for high electron mobility transistors that can be grown on any substrate and that have reduced thermal impedance. There is also a need for high electron mobility transistors whose specific properties or parameters can be controlled or altered through the substrate on which they are grown. Finally, there is a need for high electron mobility transistors that minimize or even eliminate trapping effects.

[0012]

[12] This object is achieved, according to a first exemplary embodiment of the present disclosure, by a method of fabricating a high electron mobility transistor, the method comprising: Providing a target wafer including a target substrate; Providing a donor wafer, comprising: Providing a sacrificial substrate; providing a donor film on a sacrificial substrate, the donor film including a first donor III-N layer; Bonding the donor film to a target wafer; separating the donor wafer and the target wafer by splitting the first donor III-N layer or separating the donor wafer and the target wafer at an interface between the first donor III-N layer and a sacrificial substrate, thereby forming a top surface layer on the target wafer at least partially including the first donor III-N layer bonded to the target wafer, the top surface layer having a thickness of 200 nm or less; epitaxially growing an epitaxial III-N semiconductor layer stack on the top surface layer, the epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; a second active III-N layer on the first active III-N layer; epitaxially growing a two-dimensional electron gas between the first active III-N layer and the second active III-N layer; forming a gate contact contacting the second active III-N layer in the gate region; forming a substrate galvanic contact in contact with the target substrate.

[0013]

[13] The method according to the present disclosure allows high electron mobility transistors to be grown on any substrate, even foreign substrates. The method according to the present disclosure allows high electron mobility transistors to be fabricated from epitaxial III-N semiconductor layer stacks grown on top layers bonded to silicon substrates, e.g. high resistivity silicon substrates, or SiC substrates, e.g. semi-insulating SiC substrates, or silicon-on-insulator substrates, or germanium substrates, or germanium-on-insulator substrates, or sapphire substrates, i.e. transferred by smart cut. Furthermore, the method according to the present disclosure allows the donor film to be bonded to a target wafer without providing a buffer layer on the target wafer between the substrate and the high electron mobility transistor before bonding. In other words, no buffer layer should be grown on the target substrate before bonding the donor film on the target substrate. Thus, the high electron mobility transistors fabricated by the method according to the present disclosure are less susceptible to trapping effects than prior art high electron mobility transistors grown on e.g. semi-insulating SiC substrates or high resistivity Si substrates.

[0014]

[14] Another advantage of the method according to the present disclosure is the improvement of the thermal impedance of the fabricated high electron mobility transistor. Due to the absence of a buffer layer between the epitaxial III-N semiconductor layer stack and the target substrate, the thickness of the transferred first donor III-N layer being kept as thin as possible, and the limited thickness of the total layer stack formed on the target wafer, a low thermal resistance can be achieved for the high electron mobility transistor. In other words, there is less thermal impedance between the heat sink at the bottom of the substrate and the active device, for example, the high electron mobility transistor fabricated by the method according to the present disclosure. The thickness of the first donor III-N layer transferred onto the target substrate is kept as low as possible, the thickness of this layer being at most 200 nm, preferably less than 100 nm, preferably less than 50 nm.

[0015]

[15] An additional advantage of the disclosed method is that the thin layer stack formed on the target wafer allows the substrate to be used as the fourth terminal of the high electron mobility transistor. In this way, the substrate galvanic contact in contact with the target substrate can actually be used to impose a bottom voltage bias on the target substrate relative to the source contact of the high electron mobility transistor. Due to the low thickness of the layer between the bottom surface of the target substrate and the 2DEG, this substrate galvanic contact can be used to control or modify certain characteristics or parameters of the high electron mobility transistor, such as the threshold voltage and / or off-state leakage of the high electron mobility transistor. The substrate galvanic contact can also be used to modulate the charge state of buffer or bulk traps present in the target substrate, for example, thereby minimizing or eliminating the trapping effect of the high electron mobility transistor and reducing the memory effect of the high electron mobility transistor. The substrate galvanic contact can be formed on the bottom surface of the target substrate and substantially below the gate region of the high electron mobility transistor that will be fabricated on the target wafer after bonding and epitaxial growth of the epitaxial III-N semiconductor layer stack. Alternatively, the substrate galvanic contact can be formed on the bottom surface of the target substrate and substantially below the high electron mobility transistor that will be fabricated on the target wafer after bonding and epitaxial growth of the epitaxial III-N semiconductor layer stack.

[0016]

[16] In existing prior art solutions, when fabricating high electron mobility transistors, for example on SiC substrates, the SiC substrates in RF applications typically have a thermal conductivity of 1.10 5It is very difficult to affect the properties of active GaN HEMT devices through the substrate because of their very high resistivity, e.g., resistivity higher than Ohm.cm. In existing prior art solutions, when fabricating high electron mobility transistors on highly resistive substrates, a very high bias voltage, e.g., greater than 100V, is required to affect the active HEMT device due to the thick buffer stack between the active HEMT device and the substrate. In contrast to these prior art solutions, the method according to the present disclosure does not require very high voltages applied through the substrate galvanic contacts to affect the properties of active devices fabricated on the target substrate, since the total thickness of the layer stack between the substrate and the 2DEG is kept low.

[0017]

[17] In the context of the present disclosure, forming a donor film on a sacrificial substrate includes providing a first donor III-N layer, the first donor III-N layer being epitaxially grown. For example, forming a donor film on a sacrificial substrate includes epitaxially growing a first donor III-N layer on the sacrificial substrate. In the context of the present disclosure, the first donor III-N layer includes GaN. The first donor III-N layer includes N-polar GaN epitaxially grown on the donor wafer, for example, by MOCVD or MBE. The donor wafer is turned upside down, and the first donor III-N layer is bonded to the top surface of the target wafer. The donor wafer and the target wafer are then bonded together. In this way, the first donor III-N layer bonded to the top surface of the target wafer is Ga-polar. The density of threading dislocations in the epitaxial III-N semiconductor layer stack grown on the top surface layer is thereby minimized. Alternatively, for example, the first donor III-N layer comprises GaN, which is grown as a Ga polar layer on a temporary wafer by MOCVD or MBE and then bonded to the upper surface of the donor wafer using the Smart Cut technique, and then prepared on the donor wafer. The donor wafer and the target wafer are separated from each other by a Smart Cut in the first donor III-N layer of the donor film. In the context of the present disclosure, an interface is formed between the first donor III-N layer and the sacrificial substrate, and the first donor III-N layer and the sacrificial substrate are in contact with each other. The separation of the donor wafer from the target wafer by the Smart Cut at the level of the first donor III-N layer occurs by the first donor III-N layer cracking at the interface between the first donor III-N layer and the sacrificial substrate. In other words, the first donor III-N layer is cut at the interface between the first donor III-N layer and the sacrificial substrate. The separation forms a top surface layer on the target wafer that includes the first donor III-N layer initially grown on the sacrificial substrate and bonded to the target wafer, the top surface layer on the target wafer having a thickness that substantially matches the thickness of the first donor III-N layer grown on the sacrificial substrate, and according to the present disclosure, the top surface layer has a thickness of 200 nm or less on the target wafer.Alternatively, the separation of the donor wafer from the target wafer by the Smart Cut at the level of the first donor III-N layer occurs by splitting the first donor III-N layer, such that a first remaining portion of the first donor III-N layer, later referred to as the top surface layer, is left on the sacrificial substrate separated from the target substrate, and a second remaining portion of the first donor III-N layer, later referred to as the donor surface layer, is left on the target substrate, the sum of the thicknesses of the first remaining portion and the second remaining portion substantially corresponds to the total thickness of the first donor III-N layer grown on the sacrificial substrate before bonding. In other words, the first donor III-N layer is split within its thickness. This separation results in the formation of a top surface layer on the target wafer, which at least partially comprises the first donor III-N layer initially grown on the sacrificial substrate and bonded to the target wafer, the thickness of the top surface layer on the target wafer being less than or equal to 200 nm.

[0018]

[18] In the context of the present disclosure, a donor wafer is, for example, a wafer having a diameter of 125 mm or 150 mm or 200 mm or 300 mm. Alternatively, in the context of the present disclosure, a donor wafer is, for example, a wafer having a diameter of a few mm. 2 Or a few centimeters 2 The first donor III-N layer comprises a plurality of dies or tiles of material. In the context of the present disclosure, the target wafer is, for example, a wafer having a diameter of 125 mm or 150 mm or 200 mm or 300 mm, the diameter of the target wafer being larger than the diameter of the donor wafer. In this way, for example, one donor wafer can be bonded to one target wafer. Alternatively, for example, several donor wafers can be bonded to one target wafer to increase the production yield.

[0019]

[19] In the context of this disclosure, a sacrificial substrate is one of a silicon substrate, a silicon-on-insulator substrate, a silicon carbide substrate, a sapphire substrate, a germanium substrate, a germanium-on-insulator substrate, or any other suitable alternatives to the above. Other alternatives to sacrificial substrates are described below.

[0020]

[20] In the context of the present disclosure, the target substrate is one of a silicon substrate, a silicon-on-insulator substrate, a silicon carbide substrate, a sapphire substrate, a germanium substrate, a germanium-on-insulator substrate, or any other suitable alternative to the above. In this manner, the method of fabricating high electron mobility according to the present disclosure is compatible with existing fabrication techniques developed for complementary metal oxide semiconductor technologies and processes. In other words, the fabrication of high electron mobility transistors is CMOS compatible since the present features and process steps can be integrated without significant additional effort. This reduces the complexity and costs associated with fabricating transistors and the like. For example, the target substrate can be, for example, a quartz substrate. <111> A substrate may be a silicon substrate, such as a Si substrate or a combination thereof, or a substrate including an initial layer, such as a stack of layers. For example, <111> A Si substrate can be used when an epitaxial layer needs to be grown on a Si substrate. Alternatively, the target substrate can be, for example, <100> For example, silicon substrates, such as Si substrates, which may enable, for example, GaN / CMOS integration. Alternatively, target substrates for high electron mobility transistors include free-standing GaN substrates, free-standing AlN substrates.

[0021]

[21] In the context of this disclosure, when the target substrate is a silicon-on-insulator substrate, the target substrate includes a base layer comprising bulk silicon. The resistivity of the base layer of a silicon-on-insulator substrate is typically 3-5 kOhm.cm, preferably higher than 1 kOhm.cm. In this way, the resistivity of the target substrate, which serves as the basis for the epitaxial III-N semiconductor layer stack, is maximized for high power and high frequency applications.

[0022]

[22] In the context of this disclosure, the technology of silicon-on-insulator, also referred to as SOI, corresponds to the fabrication of semiconductor devices in layered silicon-insulator silicon substrates. The choice of insulator largely depends on the intended application of the semiconductor device. Within the context of this disclosure, several types of silicon-on-insulator substrates can be used.

[0023]

[23] Isolation of the base layer of a silicon-on-insulator substrate from bulk silicon reduces parasitic capacitances in semiconductor devices fabricated from III-nitride heterostructures, thereby improving power consumption and performance. Semiconductor devices fabricated on silicon-on-insulator also have higher latch-up resistance and better performance at equivalent VDD than semiconductor devices integrated on other types of substrates. The temperature dependence of semiconductor devices fabricated on SOI is reduced compared to semiconductor devices integrated on other types of substrates. Due to isolation, semiconductor devices fabricated on SOI have lower leakage currents, resulting in higher power efficiency.

[0024]

[24] High frequency silicon-on-insulator substrates, also known as RF-SOI substrates, enable high RF performance, high linearity RF isolation and power signals, low RF losses, and integration of digital processing and power management in a silicon film that is compatible with standard CMOS processes.

[0025]

[25] For example, an enhanced signal integrity substrate for RF applications includes a base layer comprising high resistivity silicon, a trap rich layer formed on the base layer, a buried insulator formed on the trap rich layer, and a top layer formed on the buried insulator, the top layer comprising single crystal. The resistivity of the base layer is typically greater than 3 kOhm.cm. The thickness of the top layer is typically 50 nm to 200 nm. The addition of the trap rich layer provides superior RF performance. Such substrates are particularly suitable for devices with stringent linearity specifications. Applications are typically targeted, for example, at LTE-Advanced and 5G specifications, which address different performance requirements. Compared to high resistivity SOI substrates, enhanced signal integrity substrates exhibit better linearity, lower RF losses, lower crosstalk, improved quality factor of passives, smaller die size, and higher thermal conductivity. Enhanced signal integrity substrates typically further exhibit harmonic quality factors lower than -80 dBm.

[0026]

[26] Another example of RF-SOI includes a base layer including medium resistivity silicon, a trap rich layer formed on the base layer, a buried insulator formed on the trap rich layer, and a top layer including a thin single crystal. Such substrates are particularly well suited for cost-sensitive highly integrated devices, e.g., for Wi-Fi, IoT, and other consumer application specifications.

[0027]

[27] Another example of RF-SOI, called high-resistivity SOI, is intended for devices with lower linearity specifications, for example. The substrate includes a base layer comprising high-resistivity silicon, a buried insulator formed on the base layer, and a top layer comprising a thin single crystal.

[0028]

[28] Power silicon-on-insulator substrates address the requirements for integrating, for example, high voltage and analog functions into intelligent, energy-efficient and reliable power IC devices for the automotive and industrial markets. Power silicon-on-insulator substrates provide excellent electrical isolation and are ideal for integrating devices operating at different voltages, from a few volts to hundreds of volts, while reducing die area and improving reliability. These substrates are ideal for applications such as CAN / LIN transceivers, switched-mode power supplies, brushless motor drivers, and LED drivers. Power SOI includes a base layer containing silicon, an overlying buried insulator containing oxide, and a top layer containing silicon. The buried insulator is typically 0.4 μm to 1 μm thick, and the top layer is typically 0.1 μm to 1.5 μm thick.

[0029]

[29] Photonic silicon-on-insulator substrates address the requirements of optical function integration into CMOS chips, for example for low-cost and high-speed optical transceivers. Such substrates comprise a base layer comprising silicon, a buried insulator formed on top of the base layer and comprising oxide, and a top layer formed on top of the buried insulator and comprising monocrystalline silicon. The buried insulator typically has a thickness of 0.7 μm to 2 μm, and the top layer typically has a thickness of 0.1 μm to 0.5 μm. The crystalline silicon layer of the insulator can be used to create optical waveguides and other optical devices, which can be either passive or active, for example by suitable implantation. The buried insulator allows the propagation of infrared light in the silicon layer, for example based on total internal reflection. The top surface of the waveguide can either be left uncovered and exposed to air, for example for sensing applications, or covered with a cladding, for example made of silica.

[0030]

[30] From a fabrication perspective, SOI substrates are compatible with most conventional fabrication processes. In general, SOI-based processes can be implemented without special equipment or significant retooling of existing fabs. Among the challenges unique to SOI are new metrology requirements to account for the buried insulator and concerns regarding differential stresses in the top layers, including silicon.

[0031]

[31] The two-dimensional electron gas, also called 2DEG, is a gas of electrons that are free to move in two dimensions but are tightly confined in one dimension. This tight confinement quantizes the energy levels for motion in that direction. The electrons appear to be a 2D sheet embedded in a 3D world. III-nitride-based heterostructures that contain a first active III-N layer and a second active III-N layer, such as the AlGaN / GaN heterostructure, are highly suitable for high power and high frequency applications due to the high electron velocity and high critical electric field. In this heterostructure, the two-dimensional electron gas, also called 2DEG, is generated by spontaneous and piezoelectric polarization between the first and second active III-N layers, i.e., between AlGaN and GaN, for example.

[0032]

[32] In the context of this disclosure, III-nitrides refer to semiconductor compounds formed between elements in group III of the periodic table, such as boron (also referred to as B), aluminum (also referred to as Al), gallium (also referred to as Ga), indium (also referred to as In), and nitrogen (also referred to as N). Examples of binary III-nitride compounds are GaN, AlN, BN, etc. III-nitrides further refer to ternary and quaternary compounds, such as AlGaN and InAlGaN.

[0033]

[33] In the context of this disclosure, the first active III-N layer comprises one or more of N, P, As and one or more of B, Al, Ga, In, and Tl. The first active III-N layer comprises, for example, GaN. The second active III-N layer comprises one or more of N, P, As and one or more of B, Al, Ga, In, and Tl. The second active III-N layer comprises, for example, AlGaN. The term AlGaN refers to a composition comprising Al, Ga, and N in any stoichiometric ratio (Al x Ga y N), x is between 0 and 1, and y is between 0 and 1. Alternatively, the second active III-N layer comprises, for example, AlN. Alternatively, the second active III-N layer comprises InAlGaN. A composition such as InAlGaN comprises In in any suitable amount. Alternatively, both the first active III-N layer and the second active III-N layer comprise InAlGaN, the second active III-N layer comprises a bandgap larger than that of the first active III-N layer, and the second active III-N layer comprises a polarization larger than that of the first active III-N layer. Alternatively, both the first active III-N layer and the second active III-N layer comprise BInAlGaN, the second active III-N layer comprises a bandgap larger than that of the first active III-N layer, and the second active III-N layer comprises a polarization larger than that of the first active III-N layer. The composition of the active layers can be selected in view of the properties to be obtained, and the composition can be varied accordingly.

[0034]

[34] In the context of the present disclosure, a gate contact, e.g., a gate electrode, is provided in the gate region of the high electron mobility transistor. Forming the gate contact in the gate region includes multiple process steps. For example, this step includes depositing a photoresist and performing a lithography step to define the foot of the gate contact by completely removing a potential passivation layer over the second active III-N layer, e.g., an oxide or one or more dielectric layers. Alternatively, this step includes depositing a photoresist and performing a lithography step to define the foot of the gate contact by partially removing a potential passivation layer over the second active III-N layer, e.g., an oxide or one or more dielectric layers. In this way, some layers of the passivation layer remain under the gate of the high electron mobility transistor, forming a gate dielectric to further reduce trapping effects and leakage currents. The gate electrode of the gate contact can be, for example, a metal oxide semiconductor gate, also called a MOS gate, and can be made by depositing a metal stack, e.g., Ni, Pt, W, WN, or TiN, capped by Al, Au, or Cu. A metal pattern is successively defined by performing a lift-off of the metal on top of the photoresist. Alternatively, a gate metal stack is deposited, for example comprising Ni, Pt, W, WN or TiN, capped with Al, Au or Cu. A photoresist step and a lithography step are then performed, the photoresist pattern thus defined serving as a mask for dry etching of the metal stack in the undesired areas. The photoresist is then removed.

[0035]

[35] According to an exemplary embodiment, providing the target wafer further includes forming a target dielectric layer over the target substrate, the target dielectric layer having a thickness of 50 nm or less.

[0036]

[36] In the context of this disclosure, the donor film of the donor wafer is bonded to the target substrate of the target wafer by direct bonding. In other words, in direct bonding, the donor film of the donor wafer is in direct contact with the target substrate of the target wafer.

[0037]

[37] Alternatively, in the context of the present disclosure, a target dielectric layer is provided on a target substrate. The target dielectric layer is, for example, silicon dioxide, also known as SiO2. For example, the target dielectric layer is a buried oxide layer, also known as BOX. The thickness of the target dielectric layer is, for example, 50 nm or less, such as 20 nm, 10 nm, 5 nm, etc. Thus, the thickness of the target dielectric layer is kept as low as possible. The target dielectric layer is used to facilitate bonding of a donor film to the target substrate. In other words, the donor film of the donor wafer is bonded to the target dielectric layer of the target wafer.

[0038]

[38] According to an exemplary embodiment, forming the donor film further includes forming a donor dielectric layer over the first donor III-N layer, wherein the donor dielectric layer has a thickness of 10 nm or less.

[0039]

[39] The donor dielectric layer is a layer of silicon nitride, such as an amorphous layer of silicon nitride. For example, the donor dielectric layer is epitaxially grown on the first donor III-N layer. The thickness of the donor dielectric layer is kept as thin as possible, such as 5-10 nm. The donor dielectric layer serves as a current blocking layer between the target substrate and the high electron mobility transistor fabricated by the method according to the present disclosure.

[0040]

[40] According to an exemplary embodiment, bonding the donor film to the target wafer corresponds to bonding the donor dielectric layer to the target dielectric layer, thereby forming a dielectric layer stack including the target dielectric layer and the donor dielectric layer.

[0041]

[41] The thickness of the target dielectric layer and the donor dielectric layer are kept as low as possible to ensure a minimal thickness of the dielectric layer stack between the target substrate and the first donor III-N layer, e.g., a thickness of 60 nm or less. This further improves the thermal impedance of the high electron mobility transistor fabricated by the method according to the present disclosure.

[0042]

[42] Alternatively, when the donor film does not include a donor dielectric layer over the first donor III-N layer, bonding the donor film to the target wafer corresponds to directly bonding the first donor III-N layer to the target dielectric layer, thereby forming a dielectric layer stack including the target dielectric layer.

[0043]

[43] According to an exemplary embodiment, forming the donor film further includes providing a second donor III-N epitaxial layer between the first donor III-N layer and the donor dielectric layer.

[0044]

[44] The second donor III-N epitaxial layer may, for example, comprise aluminum nitride. For example, the second donor III-N epitaxial layer may comprise epitaxially grown N-polar AlN. This second donor III-N epitaxial layer confines electrons to the first active III-N layer of the epitaxial III-N semiconductor layer stack by acting as a back barrier for the high electron mobility transistor that is fabricated after bonding the donor film to the target wafer. In this way, there is no need to introduce impurities into the first active III-N layer, thus further reducing the trapping effect.

[0045]

[45] According to an exemplary embodiment, the second donor III-N epitaxial layer has a thickness of 10 nm or less.

[0046]

[46] In this way, the thickness of the donor film on the donor wafer is kept as low as possible, which in turn minimizes the thickness of the top layer of the target wafer after bonding, thereby improving the thermal impedance of high electron mobility transistors fabricated by the methods of the present disclosure.

[0047]

[47] According to an exemplary embodiment, providing a second donor III-N epitaxial layer corresponds to forming a second donor III-N epitaxial layer epitaxially grown as an N-polar layer on the donor wafer and between the first donor III-N layer and the donor dielectric layer.

[0048]

[48] ​​In this way, when the donor wafer is inverted and bonded to the target wafer, the second donor III-N epitaxial layer bonded to the target substrate will be Ga polar. The density of threading dislocations in the epitaxial III-N semiconductor layer stack grown on top of the top layer is thereby minimized.

[0049]

[49] For example, providing a second donor III-N epitaxial layer corresponds to epitaxially growing a second donor III-N epitaxial layer on a donor wafer and between the first donor III-N layer and the donor dielectric layer as an N-polarity layer, or providing a second donor III-N epitaxial layer corresponds to epitaxially growing a second donor III-N epitaxial layer on a temporary wafer as a Ga-polarity layer and between the donor dielectric layer and the layer of material for the first donor III-N layer, bonding the temporary wafer to the donor wafer, and separating the temporary wafer and the donor wafer at the level of the layer of material for the first donor III-N layer, thereby forming a first donor III-N layer on the donor wafer with the second donor III-N layer on the first donor III-N layer and the donor dielectric layer on the second donor III-N epitaxial layer.

[0050]

[50] According to an exemplary embodiment, forming the donor film includes epitaxially growing a first donor III-N layer, where epitaxially growing the first donor III-N layer corresponds to epitaxially growing a first section and a second section of the first donor III-N layer and epitaxially growing a third donor III-N epitaxial layer between the first section and the second section of the first donor III-N layer, and the donor wafer and the target wafer are separated by splitting the first section of the first donor III-N layer.

[0051]

[51] For example, forming the donor film may include epitaxially growing a first donor III-N layer, where epitaxially growing the first donor III-N layer corresponds to epitaxially growing a first section and a second section of the first donor III-N layer on a sacrificial substrate and epitaxially growing a third donor III-N epitaxial layer between the first section and the second section of the first donor III-N layer on the sacrificial substrate. In this embodiment, the first donor III-N layer is epitaxially grown, for example, as an N-polar layer. Alternatively, preparing the first donor III-N layer corresponds to epitaxially growing the first donor III-N layer on a temporary wafer as a Ga polarity layer, the first donor III-N layer including a first section and a second section on the first section, and forming the first donor III-N layer on the donor wafer by epitaxially growing, bonding the temporary wafer to the donor wafer, and separating the temporary wafer and the donor wafer at the level of the first section, where the second section of the temporary wafer becomes the first section of the first donor III-N layer of the donor wafer, and the first section of the temporary wafer becomes the second section of the first donor III-N layer of the donor wafer.

[0052]

[52] In this manner, the donor wafer and the target wafer are separated from each other by the Smart Cut by splitting the first section of the first donor III-N layer of the donor wafer, leaving a first remainder of the first section of the first donor III-N layer on a sacrificial substrate separated from the target substrate, and leaving a second remainder of the first section of the first donor III-N layer on the target substrate, such that the sum of the thickness of the first remainder and the thickness of the second remainder substantially corresponds to the total thickness of the first section of the first donor III-N layer grown on the sacrificial substrate prior to bonding. In other words, the first section of the first donor III-N layer is split within its thickness. This separation results in the target wafer having a top surface layer including at least partially the first section of the first donor III-N layer originally grown on the sacrificial substrate and bonded onto the target wafer, including a third donor III-N epitaxial layer, and including a second section of the first donor III-N layer originally grown on the sacrificial substrate, the top surface layer of the target wafer having a thickness of 200 nm or less.

[0053]

[53] Furthermore, the third donor III-N epitaxial layer can be used as an etch stop to precisely and reliably control the thickness of the second section of the first donor III-N layer. Indeed, after bonding the donor film to the target wafer and after separating the donor wafer and the target wafer at the level of the first section of the first donor III-N layer, the first section of the first donor III-N layer is thinned, for example by chemical mechanical polishing, also called CMP. The first section of the first donor III-N layer is thinned down to the third donor III-N epitaxial layer. The third donor III-N epitaxial layer can then be selectively etched with respect to the second section underneath the first donor III-N layer. For example, a wet etch with KOH can be used to selectively etch the AlN of the third donor III-N epitaxial layer without etching the GaN of the second section of the first donor III-N layer. This chemical etching of the third donor III-N epitaxial layer can thus expose the second section of the first donor III-N layer. In this way, the thickness of the second section of the first donor III-N layer remaining on the target substrate can be very accurately and reliably controlled in a simple manner. This allows the thickness of the second section of the first donor III-N layer on the target substrate to be minimized by growing the second section of the first donor III-N layer of the desired thickness on the donor wafer.

[0054]

[54] According to an exemplary embodiment, the third donor III-N epitaxial layer includes aluminum nitride.

[0055]

[55] The third donor III-N epitaxial layer may, for example, comprise AlN. For example, the third donor III-N epitaxial layer may comprise N-polar AlN epitaxially grown on a sacrificial substrate. In this way, when the donor wafer is turned upside down and the donor film is bonded to the target wafer, the third donor III-N epitaxial layer comprises Ga-polar AlN. The density of threading dislocations in the epitaxial III-N semiconductor layer stack grown on the top surface layer is thereby minimized.

[0056]

[56] According to an exemplary embodiment, providing the donor wafer further includes providing a III-N buffer formed between the sacrificial substrate and the donor film.

[0057]

[57] The III-N buffer formed between the sacrificial substrate and the donor film includes, for example, a Ga-polar epitaxial growth buffer. In this way, the quality of the epitaxial growth of the first donor III-N layer is improved. The thickness of the III-N buffer is, for example, several hundred nanometers or several micrometers. For example, the III-N buffer formed between the sacrificial substrate and the donor film includes, for example, Ga-polar GaN. In this way, the quality of the epitaxial growth of the first donor III-N layer, for example, the quality of the epitaxial growth of N-polar GaN, is improved. Optionally, the donor wafer may further include a donor dielectric layer on the first donor III-N layer, and the thickness of the donor dielectric layer is 10 nm or less. Optionally, the donor film further includes a second donor III-N epitaxial layer epitaxially grown between the first donor III-N layer and the donor dielectric layer, the second donor III-N epitaxial layer including an N-polar material such as N-polar AlN, and a thickness of the second donor III-N epitaxial layer is 10 nm or less.

[0058]

[58] The III-N buffer may be of a different nature than the sacrificial substrate in the sense that the III-N buffer has a high bandgap to provide the present features, e.g., a high breakdown voltage, e.g., greater than 250 V, preferably greater than 500 V, greater than 2000 V, even more preferably greater than 1000 V, or even greater, in that the bandgaps of the sacrificial substrate and the III-N buffer are relatively far apart, e.g., 1.1 eV and 6.2 eV, respectively. The III-N buffer may be, e.g., a III-N buffer having a high bandgap, where III refers to a group III element, e.g., B, Al, Ga, In, Tl, Sc, Y, and the lanthanide and actinide series. The III-N buffer may include a stack of layers, and in one example, typically the first layer of the sacrificial substrate is, e.g., a nucleation layer.

[0059]

[59] According to an exemplary embodiment, a method comprises: loading the target wafer including the top surface layer into an epitaxial chamber after separating the donor wafer and the target wafer along the first donor III-N layer and prior to epitaxially growing the epitaxial III-N semiconductor layer stack; desorbing the top layer in-situ in an epitaxial chamber; Further includes:

[0060]

[60] The target wafer including the top surface layer is prepared for epitaxy, for example, the target wafer including the top surface layer is sent to chemical mechanical polishing to prepare the top surface layer for epitaxy. The target wafer including the top surface layer is loaded into an epitaxial chamber for growth of an epitaxial III-N semiconductor layer stack. The surface of the top surface layer is cleaned by an in-situ desorption step to remove any surface or implant damage. In this way, the surface of the top surface layer is pristine for epitaxial growth of the epitaxial III-N semiconductor layer stack on top of the top surface layer in-situ in the epitaxial chamber. This improves the quality of the epitaxial growth of the active layers of the high electron mobility transistor, thereby improving the electrical and thermal properties of the high electron mobility transistor. In the context of the present disclosure, the epitaxial growth is performed by MOCVD or MBE or any other suitable epitaxial chamber. The epitaxial layers of the donor wafer can be formed in-situ by epitaxial growth in an MOCVD or MBE epitaxial chamber. The first active III-N layer and the second active III-N layer can be formed in-situ by epitaxial growth in an MOCVD or MBE epitaxial chamber.

[0061]

[61] According to an exemplary embodiment, forming the donor film includes epitaxially growing a first donor III-N layer on a sacrificial substrate, where epitaxially growing the first donor III-N layer corresponds to epitaxially growing the first donor III-N layer as an N-polar layer.

[0062]

[62] For example, forming the donor film may include epitaxially growing a first donor III-N layer, and epitaxially growing the first donor III-N layer on the sacrificial substrate may correspond to epitaxially growing the first donor III-N layer as an N-polar layer on the sacrificial substrate.

[0063]

[63] The first donor III-N layer comprises N-polar GaN epitaxially grown on a donor wafer, for example by MOCVD or MBE. The donor wafer is turned upside down and the first donor III-N layer is bonded to the top surface of the target wafer. The donor wafer and the target wafer are then bonded together. In this way, the first donor III-N layer bonded to the top surface of the target wafer is Ga-polar. The density of threading dislocations in the epitaxial III-N semiconductor layer stack grown on top of the top layer is thereby minimized.

[0064]

[64] According to an exemplary embodiment, forming the donor film includes providing a first donor III-N layer. In this exemplary embodiment, a material for the temporary first donor III-N layer is epitaxially grown on a temporary sacrificial substrate, e.g., a temporary wafer, and the material for the temporary first donor III-N layer is epitaxially grown on the temporary sacrificial substrate, e.g., a temporary wafer, as a Ga-polar layer. For example, the temporary first donor III-N layer includes Ga-polar GaN epitaxially grown on the temporary sacrificial substrate. In this exemplary embodiment, the method includes: providing a temporary wafer including a temporary first donor III-N layer; bonding a temporary first donor III-N layer to a donor wafer; forming a first donor III-N layer in the donor wafer, the first donor III-N layer at least partially including the temporary first donor III-N layer bonded to the donor wafer, by separating the temporary wafer and the donor wafer by splitting the temporary first donor III-N layer; Further includes:

[0065]

[65] Thus, the temporary wafer corresponds to a temporary donor wafer further comprising a temporary sacrificial substrate and a temporary first donor III-N layer. Thus, by this bonding, the temporary first donor III-N layer is bonded to the sacrificial substrate. Furthermore, the above separation can also be achieved by separating the temporary wafer and the donor wafer at the interface between the temporary first donor III-N layer and the temporary sacrificial substrate.

[0066]

[66] In this way, two successive layer transfers via Smart Cut are performed. The first transfer starts with a temporary first donor III-N layer, for example grown as a Ga-polar layer on a temporary wafer. This temporary first donor III-N layer, grown as a Ga-polar layer, is transferred to the donor wafer to form the first donor III-N layer as an N-polar layer of the donor wafer. A second Smart Cut transfer is then performed from this donor wafer to the target wafer, thereby again inverting the material of the original temporary first donor III-N layer, so that the Ga-polar surface of the material of the first donor III-N layer is formed as the top layer of the target wafer. With these additional method steps corresponding to a double layer transfer, it is not necessary to epitaxially grow the first donor III-N layer as an N-polar layer, for example on a sacrificial substrate of the donor wafer. The quality of the first donor III-N layer on the sacrificial substrate is improved when epitaxially grown as a Ga-polar layer than when grown as an N-polar layer.

[0067] According to an exemplary embodiment, providing a temporary wafer includes: Preparing a temporary sacrificial substrate; epitaxially growing a temporary first donor III-N layer on the temporary sacrificial substrate; Alternatively, preparing the temporary wafer corresponds to growing a temporary first donor III-N layer as a Ga-polar bulk III-N layer, and bonding the temporary first donor III-N layer to the donor wafer corresponds to tiling the sacrificial substrate with one or more temporary wafers by bonding the temporary first donor III-N layer of the temporary wafer to the donor wafer.

[0068]

[68] Thus, the donor film is obtained either by epitaxial growth of a temporary first donor III-N layer on a temporary sacrificial substrate of a temporary wafer, or by tiling a free-standing bulk III-N material on a sacrificial substrate. For example, the donor film is obtained from tiling of a free-standing bulk GaN material on a sacrificial substrate. The free-standing bulk III-N material of the temporary first donor III-N layer has a thickness of several hundred micrometers, for example 500 μm. In this exemplary embodiment, the temporary wafer used for tiling is generally not epitaxially grown and is made using some bulk crystal growth method (although a temporary wafer comprising a substrate on which the III-N layer is epitaxially grown can also be envisaged). The simplest approach is to tile the bulk substrate with the N-face up to the sacrificial substrate of the donor wafer along the lateral direction 4 shown in the figure, and then smart cut the bulk substrate into target wafers. The thickness of the temporary first donor III-N layer is, for example, several hundred micrometers, so that the process of Smart Cut from the donor wafer to which the temporary first donor III-N layer is bonded to the target wafer can be repeated multiple times, with a refresh CMP of the temporary first donor III-N layer in between, reducing processing costs. The temporary first donor III-N layer can be formed on a set of small substrates, for example, Ga polarity, and transferred to a larger donor wafer to form, for example, an N polarity layer. This allows the creation of donor wafers from one or more diameter III-N compatible substrates smaller than the diameter of the donor wafer.

[0069]

[69] According to an exemplary embodiment, the first active III-N layer includes gallium nitride, and the first active III-N layer has a thickness of 50 nm or less.

[0070]

[70] The first active III-N layer is epitaxially grown and preferably comprises pure gallium nitride, preferably a monolayer of gallium nitride.

[0071]

[71] According to an exemplary embodiment, the first active III-N layer comprises InAlGaN, the second active III-V layer comprises InAlGaN, the second active III-N layer comprises a bandgap larger than a bandgap of the first active III-N layer, and the second active III-N layer comprises a polarization larger than a polarization of the first active III-N layer.

[0072]

[72] In this manner, the use of different materials in adjacent first and second active III-N layers, particularly in the first active III-N layer containing a narrower bandgap than that of the second active III-N layer, can result in polarization contributing to a conductive 2DEG region near the junction between the first and second active III-N layers.

[0073]

[73] According to an exemplary embodiment, the second active III-N layer includes indium gallium aluminum nitride.

[0074]

[74] The second active III-N layer has a thickness of, for example, 10 to 100 nm, preferably 20 to 50 nm. Such a thickness combination provides excellent properties of the active layer, for example with respect to the obtained 2DEG.

[0075]

[75] According to an exemplary embodiment, the epitaxial III-N semiconductor layer stack is configured to host an electron channel between the source and drain regions when a positive bias voltage is applied to the gate contact.

[0076]

[76] In this way, when a bias voltage greater than the threshold voltage of the high electron mobility transistor is applied to the gate contact, electrons flow into an electronic channel under the gate, between the source and drain of the high electron mobility transistor.

[0077]

[77] According to an exemplary embodiment, a method comprises: forming a source contact contacting the second active III-N layer of the source region; forming a drain contact contacting the second active III-N layer in the drain region; Further includes:

[0078]

[78] The source and / or drain contacts are preferably ohmic contacts formed on the source and / or drain regions, respectively.

[0079]

[79] The source and drain contacts are ohmic contacts to the 2DEG and can be made by depositing a metal stack, such as Ti / Al / Ni / Au, Ti / Al / Mo / Au, Ti / Al / Ti / Au, Ti / Al / Ti / W, Ti / Al / W, Ti / Al / W / Cr, Ta / Al / Ta, V / Al / Ni / Au, in contact with the second active III-N layer of the epitaxial III-N semiconductor layer stack. The second active III-N layer can be recessed prior to metal deposition. Contact properties can be further improved by thermal annealing at temperatures between 800°C and 900°C, e.g., 850°C, typically in a nitrogen or forming gas atmosphere. Alternatively, additional metal interconnect layers can be defined using methods known to those skilled in the art to enable low resistance current paths for the gate, source, and drain currents.

[0080]

[80] Forming ohmic contacts at the source region and forming ohmic contacts at the drain region involves several process steps. For example, this is done by starting with depositing a photoresist and then defining the respective areas of the respective ohmic contacts with a lithography step. The potential passivation layer is then partially or completely removed at the source and / or drain regions, respectively. Alternatively, the potential passivation layer is completely removed at the source and / or drain regions. Once the areas of the ohmic contacts are defined, i.e. once the source and drain regions are defined, a metal layer or a stack of metal layers can be deposited, for example by thermal evaporation, sputtering or electron beam evaporation. On top of the photoresist, the metal pattern is successively defined by lifting off the metal without contacting the second active III-N layer. Alternatively, the photoresist can be first removed and a metal stack, for example including Ti and Al, deposited, followed by a second photoresist deposition step and a photolithography step to dry etch the metal stack in the undesired areas and remove the photoresist. The defined ohmic contacts may then be subjected to one or more alloying steps, such as a rapid thermal annealing step at a temperature of, for example, 800°C to 900°C for 1 minute in a reducing or inert atmosphere, for example hydrogen or forming gas or nitrogen gas.

[0081]

[81] According to an exemplary embodiment, a method comprises: Etching away the epitaxial III-N semiconductor layer stack in one or more regions; forming one or more recesses extending through the top surface layer at least partially into the target substrate in one or more regions, the one or more recesses not being located between the gate region and the source region or between the gate region and the drain region, thereby defining one or more electrical isolation regions; providing a dielectric layer in one or more of the recesses; forming contacts on the dielectric layer to one or more electrical isolation regions, thereby forming one or more electrical isolations; Further includes:

[0082]

[82] The recess or recesses extending at least partially through the top layer into the target substrate can extend at least partially through the target substrate, e.g., through the III-N buffer, for example, to create electrically isolated islands with different substrate biases in combination with a SOI target substrate and the above-described electrically isolated deep trench etch.

[0083]

[83] According to an exemplary embodiment, the method further includes providing a passivation stack over the second active III-N layer.

[0084]

[84] Providing a passivation stack on the epitaxial III-N semiconductor layer stack corresponds to epitaxially growing a passivation stack on the epitaxial III-N semiconductor layer stack.

[0085]

[85] The passivation stack is formed in-situ, for example by the formation of an epitaxial III-N semiconductor layer stack. The passivation stack is formed, for example, on top of the second active III-N layer. In this way, a fully crystalline passivation stack is epitaxially grown on top of the epitaxial III-N semiconductor layer stack. Alternatively, a partially crystalline passivation stack is epitaxially grown on top of the epitaxial III-N semiconductor layer stack. The passivation stack may also be formed by ex-situ deposition with the aid of an epitaxy tool such as atomic layer deposition, also called ALD, chemical vapor deposition, also called CVD, or physical vapor deposition, also called PVD. Alternatively, the passivation stack may be formed by in-situ deposition in an MOCVD or MBE chamber. Alternatively, the passivation stack may be formed by depositing an amorphous film of the same material and recrystallizing the film using thermal annealing. The passivation stack on top of the second active III-N layer comprises, for example, silicon nitride. Alternatively, the passivation stack on the second active III-N layer may for example comprise gallium nitride, or the passivation stack on the second active III-N layer may comprise gallium nitride and silicon nitride.

[0086]

[86] The passivation stack is formed between the epitaxial III-N semiconductor layer stack and, for example, the gate of a transistor. The passivation stack can be formed only under the gate and further function as a gate dielectric. Alternatively, the passivation stack can be formed on top of the epitaxial III-N semiconductor layer stack and completely cover the epitaxial III-N semiconductor layer stack. Alternatively, the passivation stack can be formed on top of the epitaxial III-N semiconductor layer stack and partially cover the surface of the epitaxial III-N semiconductor layer stack, for example, the passivation stack can be formed in the non-gated region between the source and drain of a high mobility electron transistor, where the passivation stack functions as a passivation and prevents depletion of the underlying 2DEG.

[0087]

[87] According to an exemplary embodiment, the passivation stack further comprises an oxide layer and / or silicon nitride.

[0088]

[88] Thus, the passivation stack includes a silicon nitride and / or oxide layer that functions as a passivation layer that provides an electrically clean interface to the second active III-N layer, exhibits a high dielectric constant that maximizes capacitive coupling between the 2DEG and electrical contacts formed on the semiconductor structure, provides increased transconductance for, for example, high electron mobility transistors fabricated with the semiconductor structure, and is thick enough to avoid dielectric breakdown and leakage due to quantum tunneling.

[0089]

[89] The passivation stack includes, for example, a high-density SiN deposited in-situ in a MOCVD reactor. The SiN may be stoichiometric or non-stoichiometric. Experimentally by the inventors, for example, a HEMT structure capped with in-situ SiN has been shown to be unaffected by processing steps even if it has a high-temperature budget. Alternatively, the passivation stack includes, for example, AlSiN. The Al doping can increase the bandgap of the dielectric material. Alternatively, the electron-donating dielectric layer includes one or more of Si, Al, O, and N. The passivation stack has a thickness of, for example, 1 to 500 nm, preferably 30 to 400 nm, more preferably 50 to 300 nm (such as 100 to 200 nm). The in-situ SiN may be thickened externally by PECVD or LPCVD SiN or SiOx, for example, for a thickness exceeding 500 nm, before any other processing is performed. The thin passivation stack enables the formation of a low-resistance ohmic contact. Further, the passivation stack includes, for example, Si, and the Si can diffuse into the AlGaN and function as a donor. By introducing a donor type into the AlGaN layer, the formation of an ohmic contact becomes easier, and the contact resistance decreases. The passivation stack is formed at a temperature of 700 °C to 1300 °C, 700 °C to 1250 °C, 700 °C to 1100 °C. When SiN is mentioned, it should be understood to mean a compound composed of Si and N. The SiN can include Si3N4, but also includes other chemical formulas including, but not limited to, different stoichiometric ratios or non-stoichiometric ratios of Si x N y etc., and also includes other chemical formulas not limited thereto. The chemical formula Si x N y in which, x and y can be defined as real numbers where 0 < x ≤ 100 and 0 < y ≤ 100. When the epitaxial III-N semiconductor layer stack grows, NH3 continues to flow in the reaction chamber, the SiH4 line is opened, enabling the growth of SiN and high temperature. After the growth of SiN, the flow of SiH4 is stopped, and the structure is cooled to room temperature while flowing NH3 to avoid desorption from the top layer.

[0090]

[90] According to an exemplary embodiment, a passivation stack is epitaxially grown on the second active III-N layer.

[0091]

[91] The advantage is that the crystallinity of the in-situ grown SiN is maintained by doping or adding species such as Al or B. When grown on top of the second active III-N layer, the in-situ SiN deforms to accommodate the strain due to the lattice mismatch between the materials. It is well known that a large lattice mismatch triggers the epitaxial growth mode to switch back from the two-dimensional Franck-Van der Merwe layer-by-layer growth mode to the three-dimensional Volker-Weber growth mode, which is more prone to change to an amorphous growth mode. Thus, atoms smaller than Si, e.g. Al or B, can be incorporated into SiN to reduce the lattice constant of the β-phase SiN to better match it to the lattice constant of the second active III-N layer. An additional advantage of including Al in the SiN lattice is the improved resistance to dry etching in fluorine-based plasmas due to the interaction of Al with F resulting in the highly non-volatile AlF. The passivation stack may be completely crystalline, or it may be partially crystalline and include at least some crystalline monolayers.

[0092]

[92] According to an exemplary embodiment, the passivation stack is etched away in the source and drain regions, respectively.

[0093]

[93] In this manner, openings are defined in the electron donating dielectric layer to reveal the source and drain regions, respectively, where the device terminals will be formed. For example, a photolithography step can be performed and the electron donating dielectric layer can be etched away in the source and drain regions, respectively. For example, the passivation stack can be removed by wet etching in HF or buffered HF, or by dry etching in RIE or ICP plasma tools in fluorine chemistry.

[0094]

[94] Both dry and wet etching of the fluorine chemistry passivation stack will stop at the second active III-N layer, which acts as a very highly selective etch stop. For example, etching of the electron donating dielectric layer is performed in a dry etching system based on fluorine chemistry, e.g., in an inductively coupled plasma system, using SF6 or CF4 as etching gas and RF or "platen" and ICP or "coil" etching powers of 10 W to 150 W, respectively. This allows for the complete removal of the remaining passivation stack without removing either the second active III-N layer or the layers below it. Alternatively, the second active III-N layer can be partially etched with a wet etch, e.g., in an alkaline solution or resist developer, to partially form ohmic contacts at the source and drain regions of the active layer, respectively.

[0095]

[95] According to a second aspect of the present disclosure, there is provided a high electron mobility transistor, the high electron mobility transistor comprising: A target substrate; a top surface layer over the target substrate, the top surface layer having a thickness of less than 200 nm; an epitaxial III-N semiconductor layer stack on the top surface layer, the epitaxial III-N semiconductor layer stack comprising: a first active III-N layer; a second active III-N layer on the first active III-N layer; an epitaxial III-N semiconductor layer stack having a two-dimensional electron gas between a first active III-N layer and a second active III-N layer; a gate contact contacting the second active III-N layer in the gate region; a substrate galvanic contact in contact with the target substrate; Equipped with.

[0096]

[96] The high electron mobility transistor according to the present disclosure can be formed on any substrate, even a foreign substrate. The high electron mobility transistor according to the present disclosure is formed from an epitaxial III-N semiconductor layer stack grown on a top layer bonded to a silicon substrate, e.g., a high resistivity silicon substrate, or a SiC substrate, e.g., a semi-insulating SiC substrate, or a silicon-on-insulator substrate, or a germanium substrate, or a germanium-on-insulator substrate, or a sapphire substrate, i.e., transferred by Smart Cut. Furthermore, the donor film is bonded to the target wafer without the need for a buffer layer on the target wafer between the substrate and the high electron mobility transistor before bonding. In other words, no buffer layer should be grown on the target wafer before bonding the donor film onto the target wafer. Thus, the high electron mobility transistor according to the present disclosure is less susceptible to trapping effects than prior art high electron mobility transistors grown on, e.g., semi-insulating SiC substrates or high resistivity Si substrates.

[0097]

[97] Another advantage of the high electron mobility transistor according to the present disclosure is the improved thermal impedance. Due to the absence of a buffer layer between the epitaxial III-N semiconductor layer stack and the target substrate, the thickness of the transferred first donor III-N layer forming the top layer being kept as thin as possible, and the limited thickness of the total layer stack formed on the target substrate, a low thermal resistance can be achieved in the high electron mobility transistor. In other words, there is less thermal impedance between the heat sink at the bottom of the target substrate and the active device, for example, the high electron mobility transistor made according to the present disclosure. The thickness of the top layer is kept as low as possible, the thickness of this layer being a maximum of 200 nm, preferably less than 100 nm, preferably less than 50 nm.

[0098]

[98] An additional advantage of the high electron mobility transistor according to the present disclosure is that the thin layer stack formed on the target substrate allows the substrate to be used as the fourth terminal of the high electron mobility transistor. In this way, the substrate galvanic contact in contact with the target substrate can actually be used to impose a bottom voltage bias on the target substrate relative to the source contact of the high electron mobility transistor. Due to the low thickness of the layers between the bottom surface of the target substrate and the 2DEG, this substrate galvanic contact can be used in a similar manner to control or modify certain characteristics or parameters of the high electron mobility transistor, such as the threshold voltage and / or off-state leakage of the high electron mobility transistor. The substrate galvanic contact can also be used to modulate the charge state of buffer or bulk traps present in the target substrate, for example, thereby minimizing or eliminating trapping effects and reducing memory effects of the high electron mobility transistor. The substrate galvanic contact can be formed on the bottom surface of the target substrate and substantially below the gate region of the high electron mobility transistor that will be fabricated on the target wafer after bonding and epitaxial growth of the epitaxial III-N semiconductor layer stack. Alternatively, the substrate galvanic contact can be formed on the bottom surface of the target substrate and substantially below the high electron mobility transistor that will be fabricated on the target wafer after bonding and epitaxial growth of the epitaxial III-N semiconductor layer stack.

[0099]

[99] According to an exemplary embodiment, the HEMT further includes a dielectric layer stack formed between the target substrate and the top layer, the dielectric layer stack having a thickness of 60 nm or less.

[0100]

[0100] According to an exemplary embodiment, the HEMT further includes a second donor III-N epitaxial layer formed between the dielectric layer stack and the top layer, the second donor III-N epitaxial layer having a thickness of 10 nm or less.

[0101]

[0101] Some exemplary embodiments will now be described with reference to the attached drawings, which for clarity reasons illustrate cross-sections of wafers and high electron mobility transistors according to the present disclosure. It will be clear that the wafers and high electron mobility transistors illustrated in the attached drawings can have any shape and extend in any direction along the longitudinal direction 3 and / or the lateral direction 4, and / or along a third direction 5 transverse to the longitudinal direction 3 and transverse to the lateral direction 4. The above directions will not be repeatedly mentioned in all the attached drawings in order to keep the drawings simple. [Brief description of the drawings]

[0102] [Figure 1A] 1A-1D are schematic diagrams illustrating exemplary embodiments of method steps for fabricating a high electron mobility transistor according to the present disclosure. [Figure 1B] 1A-1D are schematic diagrams illustrating exemplary embodiments of method steps for fabricating a high electron mobility transistor according to the present disclosure. [Figure 1C] 1A-1D are schematic diagrams illustrating exemplary embodiments of method steps for fabricating a high electron mobility transistor according to the present disclosure. [Figure 1D] 1A-1D are schematic diagrams illustrating exemplary embodiments of method steps for fabricating a high electron mobility transistor according to the present disclosure. [Figure 1E] 1A-1D are schematic diagrams illustrating exemplary embodiments of method steps for fabricating a high electron mobility transistor according to the present disclosure. [Figure 1F] 1A-1D are schematic diagrams illustrating exemplary embodiments of method steps for fabricating a high electron mobility transistor according to the present disclosure. [Figure 1G] 1A-1D are schematic diagrams illustrating exemplary embodiments of method steps for fabricating a high electron mobility transistor according to the present disclosure. [Figure 1H] 1A-1D are schematic diagrams illustrating exemplary embodiments of method steps for fabricating a high electron mobility transistor according to the present disclosure. [Figure 1I] 1A-1D are schematic diagrams illustrating exemplary embodiments of method steps for fabricating a high electron mobility transistor according to the present disclosure. [Figure 1J] 1A-1C are schematic diagrams illustrating exemplary embodiments of high electron mobility transistors according to the present disclosure; [Figure 1K] FIG. 1C illustrates an alternative embodiment of the fabrication step shown in FIG. 1F. [Diagram 2] FIG. 2 illustrates a schematic diagram of an exemplary embodiment of a target wafer according to the present disclosure. [Figure 3A] FIG. 2 illustrates a schematic diagram of an exemplary embodiment of a donor wafer according to the present disclosure. [Figure 3B] 3B and 3C are schematic diagrams illustrating an exemplary embodiment of a target wafer according to the present disclosure illustrated in FIG. 3A and after bonding a donor wafer according to the present disclosure. [Figure 4] FIG. 2A illustrates a schematic diagram of an exemplary embodiment of a target wafer according to the present disclosure after bonding. [Diagram 5] FIG. 2 illustrates a schematic diagram of an exemplary embodiment of a donor wafer according to the present disclosure. [Figure 6] FIG. 2 illustrates a schematic diagram of an exemplary embodiment of a donor wafer according to the present disclosure. [Figure 7] FIG. 2 illustrates a schematic diagram of an exemplary embodiment of a donor wafer according to the present disclosure. [Figure 8A] 1A-1D are schematic diagrams illustrating exemplary embodiments of steps of a method for fabricating a high electron mobility transistor from a donor wafer according to the present disclosure. [Figure 8B] 1A-1D are schematic diagrams illustrating exemplary embodiments of steps of a method for fabricating a high electron mobility transistor from a donor wafer according to the present disclosure. [Figure 8C] 1A-1D are schematic diagrams illustrating exemplary embodiments of steps of a method for fabricating a high electron mobility transistor from a donor wafer according to the present disclosure. [Figure 8D] 1A-1D are schematic diagrams illustrating exemplary embodiments of steps of a method for fabricating a high electron mobility transistor from a donor wafer according to the present disclosure. [Figure 8E] 1A-1D are schematic diagrams illustrating exemplary embodiments of steps of a method for fabricating a high electron mobility transistor from a donor wafer according to the present disclosure. [Figure 8F] 1A-1D are schematic diagrams illustrating exemplary embodiments of steps of a method for fabricating a high electron mobility transistor from a donor wafer according to the present disclosure. [Figure 8G] 1A-1D are schematic diagrams illustrating exemplary embodiments of steps of a method for fabricating a high electron mobility transistor from a donor wafer according to the present disclosure. [Figure 8H] 1A-1D are schematic diagrams illustrating exemplary embodiments of steps of a method for fabricating a high electron mobility transistor from a donor wafer according to the present disclosure. [Figure 8I] FIG. 8C illustrates an alternative embodiment of the fabrication steps as shown in FIG. 8F. [Figure 9] FIG. 1 illustrates a schematic diagram of an exemplary embodiment of a high electron mobility transistor according to the present disclosure with source and drain contacts. [Figure 10] FIG. 1 illustrates a schematic diagram of an exemplary embodiment of a high electron mobility transistor having electrical isolation according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0103]

[0112] 1A-1J diagrammatically illustrate an exemplary embodiment of steps of a method for fabricating a high electron mobility transistor 1 according to the present disclosure. As shown in FIG. 1A, a donor wafer 20 is provided. The donor wafer 20 includes a sacrificial substrate 200. A donor film 21 is formed on the sacrificial substrate 200. The donor film 21 includes a first donor III-N layer 201. For example, the first donor III-N layer 201 is epitaxially grown on the sacrificial substrate 200. As shown in FIG. 1B, a target wafer 10 including a target substrate 100 is also provided. In FIG. 1C, the donor wafer 20 is inverted with respect to its initial orientation and with respect to the target wafer 10. The inverted donor wafer 20 is then lowered towards the target wafer 10 as shown in FIG. 1D. FIG. 1E shows the donor film 201 bonded to the target wafer 10. The donor wafer 20 and the target wafer 10 are separated from each other using the Smart Cut technique along a plane 40 as shown in FIG. 1F. As shown in FIG. 1G, the donor wafer 20 and the target wafer 10 are separated by dividing the first donor III-N layer 201 at the level of the plane 40, thereby forming a top surface layer 221 on the target wafer 10, which at least partially includes the first donor III-N layer 201 bonded to the target wafer 10, and further forming a donor surface layer 222 on the donor wafer 20, which at least partially includes the first donor III-N layer 201 epitaxially grown on the donor wafer 20. The top surface layer 221 has a thickness of 200 nm or less. Furthermore, the sum of the thicknesses of the top surface layer 221 and the donor surface layer 222 substantially corresponds to the thickness of the first donor III-N layer 201 epitaxially grown on the donor wafer 20. 1K, according to an alternative embodiment, the donor wafer 20 and the target wafer 10 are separated at the interface 40 between the first donor III-N layer 201 and the sacrificial substrate 200, thereby forming a top surface layer 221 on the target wafer 10, which includes the first donor III-N layer 201 bonded to the target wafer 10. In this alternative embodiment, the thickness of the top surface layer 221 is 200 nm or less, which substantially corresponds to the thickness of the first donor III-N layer 201 epitaxially grown on the donor wafer 20.Thus, the method according to the present disclosure results in the semiconductor structure illustrated in FIG. 1H with the top surface layer 221 formed on the target substrate 100 of the target wafer 10. FIG. 1I illustrates the following method steps for epitaxially growing an epitaxial III-N semiconductor layer stack 300 on the top surface layer 221. The epitaxial III-N semiconductor layer stack 300 includes a first active III-N layer 31 and a second active III-N layer 32 with a two-dimensional electron gas 33 between the first active III-N layer 31 and the second active III-N layer 32. As shown in FIG. 1J, the method further includes forming a gate contact in contact with the second active III-N layer 32 in the gate region 401 and forming a substrate galvanic contact 42 in contact with the back side of the target substrate 100 along the lateral direction 4. A high electron mobility transistor 1 has been fabricated.

[0104]

[0113] FIG. 2 illustrates an exemplary embodiment of a target wafer 10 according to the present disclosure. Components having the same reference numbers as in FIGS. 1A-1J perform the same functions. Providing the target wafer 10 may further include forming a target dielectric layer 101 on the target substrate 10. The target dielectric layer 101 has a thickness of 50 nm or less. In this target wafer 10, a donor film 201 of a donor wafer 20 is bonded to the target dielectric layer 101 of the target wafer 10.

[0105]

[0114] FIG. 3A illustrates an exemplary embodiment of a donor wafer 20 according to the present disclosure. Components with the same reference numbers as in FIG. 1A-1J or FIG. 2 perform the same functions. Forming the donor film 201 further includes forming a donor dielectric layer 202 on the first donor III-N layer 201. The donor dielectric layer 202 has a thickness of 10 nm or less. The donor wafer 20 of FIG. 3A is then turned upside down before being bonded to the target wafer 10. FIG. 3B illustrates an exemplary embodiment of a target wafer 10 according to the present disclosure illustrated in FIG. 3A after bonding the donor wafer 20 according to the present disclosure to the target wafer 10 of FIG. 1B. FIG. 3B shows the target substrate 100 with the donor dielectric layer 202 and the top surface layer 221 bonded thereto. The top surface layer 221 is formed after splitting the first donor III-N layer 201 to separate the donor wafer 20 and the target wafer 10. According to an alternative embodiment, a donor wafer 20 according to the present disclosure and illustrated in FIG. 3A can be bonded to the target wafer 10 of FIG.

[0106]

[0115] FIG. 4 illustrates a schematic representation of an exemplary embodiment of a target wafer according to the present disclosure after bonding. Components with the same reference numbers as in FIG. 1A-1J or FIG. 2 or FIG. 3A or FIG. 3B perform the same functions. Forming the donor film further includes forming a donor dielectric layer 202 on the first donor III-N layer of the donor wafer. The donor dielectric layer 202 has a thickness of 10 nm or less. The donor wafer is then turned upside down before being bonded to a target wafer including a target substrate 100 on which a target dielectric layer 101 is formed. The target dielectric layer 101 has a thickness of 50 nm or less. FIG. 4 illustrates a target wafer after bonding the donor wafer to the target wafer. The donor dielectric layer 202 and the top layer 221 are bonded to the target dielectric layer 101 to form a dielectric layer stack 22 including the target dielectric layer 101 and the donor dielectric layer 202. The dielectric layer stack 22 has a thickness of 60 nm or less. The top surface layer 221 is formed after dividing the first donor III-N layer 201 to separate the donor wafer and the target wafer.

[0107]

[0116] FIG. 5 illustrates a schematic diagram of an exemplary embodiment of a donor wafer 20 according to the present disclosure. Components having the same reference numbers as in FIG. 1A-1J or FIG. 2 or FIG. 3A or FIG. 3B or FIG. 4 perform the same functions. The target wafer 20 includes a sacrificial substrate 200 on which a donor film 21 is formed. The donor film 21 includes a first donor III-N layer 201 and a donor dielectric layer 202 on the first donor III-N layer 201. The donor dielectric layer 202 has a thickness of 10 nm or less. The donor film 21 further includes a second donor epitaxial layer 203 provided between the first donor III-N layer 201 and the donor dielectric layer 202. The second donor epitaxial layer 203 is epitaxially grown between the first donor III-N layer 201 and the donor dielectric layer 202. For example, the second donor epitaxial layer 203 is epitaxially grown as an N-polar layer between the first donor III-N layer 201 and the donor dielectric layer 202. The second donor epitaxial layer 203 has a thickness of 10 nm or less.

[0108]

[0117] FIG 6 illustrates a schematic diagram of an exemplary embodiment of a donor wafer 20 according to the present disclosure. Components having the same reference numbers as in FIG 1A-1J or FIG 2 or FIG 3A or FIG 3B or FIG 4 or FIG 5 perform the same functions. The donor wafer 20 of FIG 6 includes a sacrificial substrate 200. A donor film 21 is formed on the sacrificial substrate 200 of the donor wafer 20. Forming the donor film 21 includes epitaxially growing the first donor III-N layer 201, which corresponds to, for example, epitaxially growing a first section 211 and a second section 212 of the first donor III-N layer 201 on the sacrificial substrate 200 and epitaxially growing a third donor III-N epitaxial layer 205 between the first section 211 and the second section 212 of the first donor III-N layer 201. The donor wafer 20 and the target wafer are then separated by splitting the first section 211 of the first donor III-N layer 201, and the third donor III-N epitaxial layer 205 acts as an etch stop on the second section 212 of the first donor III-N layer 201 to form a top surface layer on the target wafer, the top surface layer including the second section 212 of the first donor III-N layer 201 after removing the third donor III-N epitaxial layer 205. For example, the third donor III-N epitaxial layer 205 includes AlN.

[0109]

[0118] FIG. 7 illustrates in a schematic manner an exemplary embodiment of a donor wafer 20 according to the present disclosure. Components having the same reference numbers as in FIG. 1A-1J or FIG. 2 or FIG. 3A or FIG. 3B or FIG. 4 or FIG. 5 or FIG. 6 perform the same functions. The donor wafer 20 comprises a sacrificial substrate 200 on which a III-N buffer 204 is provided. In other words, the III-N buffer 204 is formed between the sacrificial substrate 200 of the donor wafer 20 and the donor film 21. The donor film 21 comprises, for example, a first donor III-N layer 201. According to an alternative embodiment, the donor film 21 comprises, for example, a first donor III-N layer 201 and a donor dielectric layer 202. According to a further alternative embodiment, the donor film 21 includes, for example, a first donor III-N layer 201, a donor dielectric layer 202, and a second donor epitaxial layer 203 disposed between the first donor III-N layer 201 and the donor dielectric layer 202.

[0110]

[0119] 8A-8H illustrate schematic diagrams of exemplary embodiments of steps of a method for fabricating a high electron mobility transistor from a donor wafer 20 according to the present disclosure. Components with the same reference numbers as in FIG. 1A-1J or FIG. 2 or FIG. 3A or FIG. 3B or FIG. 4 or FIG. 5 or FIG. 6 or FIG. 7 perform the same functions. As shown in FIG. 8A, a temporary donor wafer 30 is provided. According to this exemplary embodiment, the temporary donor wafer 30 includes a temporary sacrificial substrate 400. As shown in FIG. 8A, a temporary first donor III-N layer 401 is epitaxially grown on the temporary sacrificial substrate 400. A donor wafer 20 is provided. The donor wafer 20 includes, for example, a sacrificial substrate 200. According to an alternative embodiment, the donor wafer 20 includes, for example, a sacrificial substrate 200, and further includes a dielectric layer on the sacrificial layer, the dielectric layer having a thickness of 50 nm or less, and the dielectric layer facilitates bonding. As shown in Fig. 8C, the temporary first donor III-N layer 401 is inverted with respect to the donor wafer 20 and with respect to its original orientation. The temporary first donor III-N layer 401 is bonded to the donor wafer 20, for example directly to the sacrificial substrate 200 as shown in Fig. 8D or via a dielectric layer formed on the sacrificial substrate 200. The temporary donor wafer 30 and the donor wafer 20 are separated by splitting the temporary first donor III-N layer 401 at the level of the plane 410, thereby forming in the donor wafer 20 a first donor III-N layer 201 that at least partially comprises the temporary first donor III-N layer 401 bonded to the donor wafer 20. According to a further embodiment, shown in Fig. 8I, the temporary donor wafer 30 and the donor wafer 20 are separated at the interface 410 between the temporary first donor III-N layer 401 and the temporary sacrificial substrate 400, thereby forming a first donor III-N layer 201 in the donor wafer 20, which includes the temporary first donor III-N layer 401 bonded to the donor wafer 20. According to a further alternative embodiment, the temporary donor wafer 30 corresponds to the temporary first donor III-N layer 401, for example, grown as a Ga-polar bulk III-N layer. The temporary first donor III-N layer 401 is then bonded to the donor wafer 20.For example, one or more temporary donor wafers 30 are bonded to the donor wafer 20, and the diameter of the donor wafer 20 is larger than that of the temporary donor wafer 30. The donor wafer 20 includes, for example, a sacrificial substrate 200. According to an alternative embodiment, the donor wafer 20 includes, for example, a sacrificial substrate 200, and further includes a dielectric layer on the sacrificial layer, the thickness of the dielectric layer is 50 nm or less, and the dielectric layer facilitates bonding. As shown in FIG. 8C, the temporary first donor III-N layer 401 is turned upside down with respect to the donor wafer 20 and its original orientation. The temporary first donor III-N layer 401 is bonded to the donor wafer 20, for example, directly to the sacrificial substrate 200, or with a dielectric layer formed on the sacrificial substrate 200, as shown in FIG. 8D. The temporary donor wafer 30 and the donor wafer 20 are separated by splitting the temporary first donor III-N layer 401 at the level of the plane 410, thereby forming in the donor wafer 20 a first donor III-N layer 201 at least partially comprising the temporary first donor III-N layer 401 bonded to the donor wafer 20. The donor film 21 including the first donor III-N layer 201 is then bonded to a target wafer, e.g. the target wafer of FIG. 1B, and the method steps illustrated in FIGS. 1C-1J are applied using the donor wafer 20 and the target wafer.

[0111]

[0120] 9 illustrates a schematic diagram of an exemplary embodiment of a high electron mobility transistor 1 according to the present disclosure having a source contact 43 and a drain contact 44. Components having the same reference numbers as in FIGS. 1A-1J or 2 or 3A or 3B or 4 or 5 or 6 or 7 perform the same functions. The method illustrated in FIGS. 1A-1J further includes forming a source contact 43 contacting the second active III-N layer 32 of the source region 403 and forming a drain contact 44 contacting the second active III-N layer 32 of the drain region 404.

[0112]

[0121] FIG. 10 illustrates a schematic diagram of an exemplary embodiment of a high electron mobility transistor 1 according to the present disclosure with electrical isolation. Components with the same reference numbers as in FIG. 1A-1J or FIG. 2 or FIG. 3A or FIG. 3B or FIG. 4 or FIG. 5 or FIG. 6 or FIG. 7 perform the same functions. The method illustrated in FIG. 1A-1J further includes forming a source contact 43 contacting the second active III-N layer 32 of the source region 403 and forming a drain contact 44 contacting the second active III-N layer 32 of the drain region 404 of the high electron mobility transistor 1 fabricated by the method according to the present disclosure. The method further includes etching away the epitaxial III-N semiconductor layer stack 300 in the one or more electrical isolation regions. The method further includes forming one or more recesses 500 extending at least partially through the top layer 221 into the target substrate 100, the one or more recesses 500 not being disposed between the gate region 401 and the source region 403 or between the gate region 401 and the drain region 404, thereby defining one or more electrical isolation regions. The method further includes providing a dielectric layer 501 along one or more sidewalls 505, 506 of the recesses 500. The method further includes forming contacts 502 in the one or more electrical isolation regions such that the contacts 502 directly contact the target wafer 100 at a bottom 504 of each of the recesses 500 along the lateral direction 4, and the contacts 502 contact the dielectric layer 501 along each of the sidewalls 505, 506 of the recesses 500, thereby forming one or more electrical isolations.

[0113]

[0122] Although the present invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be embodied with various changes and modifications without departing from the scope of the present invention. The present embodiments are therefore considered in all respects to be illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than the foregoing description, and all modifications which come within the scope of the claims are therefore intended to be embraced therein.

[0114]

[0123] Furthermore, readers of this patent application will understand that the words "comprising" or "comprise" do not exclude other elements or steps, that the words "a" or "an" do not exclude a plurality, and that a single element, such as a computer system, processor, or another integrated unit, may perform the functions of several means referred to in the claims. Any reference signs in the claims should not be construed as limiting the respective claims. Terms such as "first", "second", "third", "a", "b", "c", etc., when used in the description and claims, are introduced to distinguish between similar elements or steps and do not necessarily describe a sequential or chronological order. Similarly, terms such as "top", "bottom", "upper", "lower", etc., are introduced for explanatory purposes and do not necessarily indicate a relative position. It will be understood that the terms used in this way are interchangeable under appropriate circumstances, and that embodiments of the invention can operate according to the invention in other sequences or with orientations different from those described or illustrated above.

Claims

1. A method for fabricating a high electron mobility transistor (1), comprising: Providing a target wafer (10) including a target substrate (100); Providing a donor wafer (20), Providing a sacrificial substrate (200); providing a donor film (21) on the sacrificial substrate (200), the donor film (21) comprising a first donor III-N layer (201); bonding the donor film (21) to the target wafer (10); Separating the donor wafer (20) and the target wafer (10) by splitting the first donor III-N layer (201), or separating the donor wafer (20) and the target wafer (10) at an interface between the first donor III-N layer (201) and the sacrificial substrate (200), thereby forming a top surface layer (221) on the target wafer (10) that at least partially includes the first donor III-N layer (201) bonded to the target wafer (10), and the top surface layer (221) has a thickness of 200 nm or less; epitaxially growing an epitaxial III-N semiconductor layer stack (300) on the top surface layer (221), wherein the epitaxial III-N semiconductor layer stack (300) comprises: a first active III-N layer (31); a second active III-N layer (32) on the first active III-N layer (31); epitaxially growing a two-dimensional electron gas (33) between the first active III-N layer (31) and the second active III-N layer (32); forming a gate contact (41) contacting the second active III-N layer (32) in the gate region (401); forming a substrate galvanic contact (42) in contact with the target substrate (100); A method comprising:

2. 2. The method of claim 1, wherein the step of preparing the target wafer (10) further comprises forming a target dielectric layer (101) on the target substrate (100), the target dielectric layer (101) having a thickness of 50 nm or less.

3. 2. The method of claim 1, wherein the forming the donor film further comprises forming a donor dielectric layer on the first donor III-N layer, the donor dielectric layer having a thickness of 10 nm or less.

4. The forming of the donor film (21) further comprises forming a donor dielectric layer (202) on the first donor III-N layer (201), wherein the donor dielectric layer (202) has a thickness of 10 nm or less; 3. The method of claim 2, wherein the step of bonding the donor film (21) to the target wafer (10) corresponds to bonding the donor dielectric layer (202) to the target dielectric layer (101), thereby forming a dielectric layer stack (22) including the target dielectric layer (101) and the donor dielectric layer (202).

5. 4. The method of claim 3, wherein forming the donor film further comprises providing a second donor III-N epitaxial layer between the first donor III-N layer and the donor dielectric layer, and wherein the second donor III-N epitaxial layer has a thickness of 10 nm or less.

6. 6. The method of claim 5, wherein the providing the second donor III-N epitaxial layer corresponds to forming a second donor III-N epitaxial layer (203) epitaxially grown as an N-polar layer between the first donor III-N layer (201) and the donor dielectric layer (202).

7. 2. The method of claim 1, wherein forming the donor film includes epitaxially growing the first donor III-N layer, wherein the epitaxially growing the first donor III-N layer corresponds to epitaxially growing a first section and a second section of the first donor III-N layer and epitaxially growing a third donor III-N epitaxial layer between the first section and the second section of the first donor III-N layer, and wherein the donor wafer and the target wafer are separated by splitting the first section of the first donor III-N layer.

8. The method of claim 7, wherein the third donor III-N epitaxial layer (205) comprises aluminum nitride.

9. 2. The method of claim 1, wherein the forming the donor film (21) comprises epitaxially growing the first donor III-N layer (201), and the epitaxially growing the first donor III-N layer (201) corresponds to epitaxially growing the first donor III-N layer (201) as an N-polar layer.

10. providing a temporary donor wafer (30) including a temporary sacrificial substrate (400) and a temporary first donor III-N layer (401); bonding the temporary first donor III-N layer (401) to the sacrificial substrate (200); separating the temporary donor wafer (30) from the donor wafer (20) by splitting the temporary first donor III-N layer (401), or separating the temporary wafer (30) from the donor wafer (20) at the interface between the temporary first donor III-N layer (401) and the temporary sacrificial substrate (400), thereby forming the first donor III-N layer (201) in the donor wafer (20) at least partially comprising the temporary first donor III-N layer (401) bonded to the donor wafer (20); The method of claim 1 further comprising:

11. The step of preparing a temporary donor wafer (30) comprises: providing the temporary sacrificial substrate (400); epitaxially growing the temporary first donor III-N layer (401) on the temporary sacrificial substrate (400); Alternatively, the step of preparing a temporary donor wafer (30) corresponds to growing the temporary first donor III-N layer (401) as a Ga-polar bulk III-N layer, and the step of bonding the temporary first donor III-N layer (401) to the sacrificial substrate (200) corresponds to tiling the sacrificial substrate (200) with one or more temporary donor wafers (30) by bonding the temporary first donor III-N layer (401) of the temporary donor wafer (30) to the sacrificial substrate (200).

12. forming a source contact (43) contacting the second active III-N layer (32) in a source region (403); forming a drain contact (44) contacting the second active III-N layer (32) in the drain region (404); The method of any one of claims 1 to 11, further comprising:

13. Etching away the epitaxial III-N semiconductor layer stack (300) in one or more areas; forming one or more recesses (500) in the one or more regions extending through the top surface layer (221) and at least partially into the target substrate (100), wherein the one or more recesses (500) are not located between the gate region (401) and the source region (403) or between the gate region (401) and the drain region (404), thereby defining one or more electrical isolation regions; providing a dielectric layer (501) in one or more of said recesses (500); forming contacts (502) on the dielectric layer (501) to the one or more electrical isolation regions, thereby forming one or more electrical isolations; The method of claim 12 further comprising:

14. a target substrate (100); a top surface layer (221) on the target substrate (100), the top surface layer (221) having a thickness of less than 200 nm; an epitaxial III-N semiconductor layer stack (300) on the top surface layer (221), a first active III-N layer (31); a second active III-N layer (32) on the first active III-N layer (31); an epitaxial III-N semiconductor layer stack (300) having a two-dimensional electron gas (33) between the first active III-N layer (31) and the second active III-N layer (32); a gate contact (41) contacting the second active III-N layer of the gate region (401); a substrate galvanic contact (42) in contact with the target substrate (100); A high electron mobility transistor (1) comprising:

15. 15. The high electron mobility transistor (HEMT) (1) of claim 14, further comprising at least two dielectric layers (101, 202) between the target substrate (100) and the top surface layer (221), wherein the thickness of the at least two dielectric layers (101, 202) is 60 nm or less.

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