Fan-out flip chip semiconductor package

Abstract

The described example (475) includes a reconfigured semiconductor device (451) flip-chip mounted on a device side surface (449) of a package substrate (453), the package substrate having terminals (457) for connecting the package substrate to a circuit board. The reconfigured semiconductor device further includes a semiconductor die (402) mounted on the dielectric layer (405) and having bond pads spaced apart from one another by at least a first pitch distance of less than 100 micrometers, a redistribution layer (415) formed on the bond pads and having conductors in the passivation layer, solder bumps on the redistribution layer coupled to the bond pads of the semiconductor die, the solder bumps being spaced apart from one another by at least a second pitch distance greater than the first pitch distance, and solder joints formed between the package substrate and the solder bumps, coupling the package substrate to the semiconductor die in the reconfigured semiconductor device.

Description

[Technical field]

[0001] The present invention relates generally to packaging electronic devices, and more particularly to assembling flip-chip packaged semiconductor devices. [Background technology]

[0002] A process for manufacturing a packaged semiconductor device includes mounting the semiconductor device to a package substrate and then covering the electronic device with a molding compound in a molding process to form a package. When a semiconductor device is mounted on a package substrate in a flip chip package, the semiconductor die has interconnects extending from a proximal end to a distal end that rest on bond pads on a device side surface of the semiconductor die. In a flip chip package, the semiconductor die is mounted with the device side surface facing the package substrate. The interconnects can include conductive post connects with proximal ends on the bond pads and distal ends facing away from the bond pads, and solder, such as solder balls or solder bumps, on the distal ends of the post connects. Alternatively, the interconnects can include a conductive adhesive, or in another example, a metal-to-metal bond can be formed between the post connects and the metal lands. In an example using solder bumps, when the semiconductor die is flip-chip mounted to the package substrate, the solder bumps on the distal ends of the post connects are subjected to a thermal reflow process, causing the solder to melt and flow to form solder joints. The solder joints mechanically attach and electrically couple the semiconductor die to the package substrate. The solder joints attach the conductive post connects to conductive areas of the package substrate. The package substrate provides terminals for the packaged device, e.g., ball grid array (BGA) balls. The packaged semiconductor device can then be mounted to a circuit board or module for use.

[0003] As the size and number of connections increase and as the size of the semiconductor die decreases, the pitch distance, measured center-to-center between the conductive post connects, decreases. For some example dies, the maximum pitch that allows all interconnects to be placed on the die is smaller than the minimum pitch distance available for manufacturing or assembly. The pitch requirement for manufacturing and assembly using solder bumps may be due to processing constraints in the formation of the post connects and solder bumps, including tight dimensional requirements due to photolithography constraints, or may be due to minimum pitch limitations in the assembly process. To meet the spacing requirements for the post connect locations on the package substrate, the size of the semiconductor die may be increased to a size larger than the die area required to fabricate the circuit elements on the semiconductor die, such that the bond pads on the semiconductor die are spaced sufficiently apart to provide the spacing required for the post connect and solder bump processes. Increasing the die area also increases the cost per die substantially, since going larger than a silicon die reduces the number of dies fabricated on a single wafer. To improve integration and reduce the cost per device, flip chip package assemblies are needed that allow the use of smaller silicon dies. Summary of the Invention

[0004] A described example includes a reconfigured semiconductor device flip-chip mounted on a device side surface of a package substrate, the package substrate having terminals for connecting the package substrate to a circuit board, the reconfigured semiconductor device further including a semiconductor die mounted in a dielectric layer and having bond pads spaced apart from one another at a first pitch distance of at least less than 100 micrometers, a redistribution layer formed over the bond pads and having conductors in the passivation layer, solder bumps on the redistribution layer and coupled to the bond pads of the semiconductor die, the solder bumps being spaced apart from one another at least at a second pitch distance greater than the first pitch distance, and solder bonds formed between the package substrate and the solder bumps, coupling the package substrate to the semiconductor die in the reconfigured semiconductor device. [Brief description of the drawings]

[0005] [Figure 1A] FIG. 1 is a cross-sectional view of a flip-chip packaged semiconductor device in a ball grid array (BGA) package. [Figure 1B] FIG. 1 is a cross-sectional view of a flip-chip packaged semiconductor device in a ball grid array (BGA) package.

[0006] [Figure 2A] FIG. 1 is a perspective view of a semiconductor wafer including multiple semiconductor dies. [Figure 2B] 1 is a close-up view of an individual semiconductor die from a semiconductor wafer.

[0007] [Figure 3A] 1 illustrates, in cross-sectional views, selected steps for fabricating a reconfigured semiconductor device for use in an arrangement. [Figure 3B] 1 illustrates, in cross-sectional views, selected steps for fabricating a reconfigured semiconductor device for use in an arrangement. [Figure 3C] 1 illustrates, in cross-sectional views, selected steps for fabricating a reconfigured semiconductor device for use in an arrangement. [Figure 3D] 1 illustrates, in cross-sectional views, selected steps for fabricating a reconfigured semiconductor device for use in an arrangement. [Figure 3E] 1 illustrates, in cross-sectional views, selected steps for fabricating a reconfigured semiconductor device for use in an arrangement. [Figure 3F] 1 illustrates, in cross-sectional views, selected steps for fabricating a reconfigured semiconductor device for use in an arrangement. [Figure 3G] 1 illustrates, in cross-sectional views, selected steps for fabricating a reconfigured semiconductor device for use in an arrangement. [Figure 3H]1 illustrates, in cross-sectional views, selected steps for fabricating a reconfigured semiconductor device for use in an arrangement.

[0008] [Figure 4A] 1 illustrates, in cross-sectional views, a process for forming a flip-chip semiconductor device package using a reconstituted semiconductor device of the present configuration. [Figure 4B] 1 illustrates, in cross-sectional views, a process for forming a flip-chip semiconductor device package using a reconstituted semiconductor device of the present configuration. [Figure 4C] 1 illustrates, in cross-sectional views, a process for forming a flip-chip semiconductor device package using a reconstituted semiconductor device of the present configuration. [Figure 4D] 1 illustrates, in cross-sectional views, a process for forming a flip-chip semiconductor device package using a reconstituted semiconductor device of the present configuration. [Figure 4E] 1 illustrates, in cross-sectional views, a process for forming a flip-chip semiconductor device package using a reconstituted semiconductor device of the present configuration.

[0009] [Diagram 5] In one arrangement, a method for creating a semiconductor device package using a reconfigured semiconductor device is illustrated in a flow chart. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Corresponding numbers and symbols in the different drawings generally refer to corresponding parts unless otherwise noted. The drawings are not necessarily drawn to scale.

[0011] In this specification, various elements are described as being "coupled." The term "coupled" includes elements that are directly connected and elements that are indirectly connected, as well as elements that are electrically connected through intervening elements or wiring.

[0012] The term "semiconductor die" is used herein. As used herein, a semiconductor die may be a number of separate semiconductor devices, such as bipolar transistors, a pair of power FET switches fabricated together on a single semiconductor die, or an integrated circuit having multiple semiconductor devices, such as multiple capacitors in an A / D converter. A semiconductor die may include passive devices, such as resistors, inductors, filters, or active devices, such as transistors. A semiconductor die may be an integrated circuit having hundreds or thousands of transistors coupled to form a functional circuit, such as a microprocessor or a memory device. A semiconductor die may be a passive device, such as a sensor, examples of which include photocells, transducers, and charge-coupled devices (CCDs), or a microelectromechanical system (MEMS) device, such as a digital micromirror device (DMD). A semiconductor die includes a semiconductor substrate having a device surface and an opposing back surface. A semiconductor process forms devices on the device surface of the semiconductor die.

[0013] The term "packaged semiconductor device" is used herein. A packaged semiconductor device has at least one semiconductor die electrically coupled to terminals and may have a package body that protects and covers the semiconductor die, although in some device packages, the backside of the semiconductor die is exposed. In some arrangements, multiple semiconductor dies may be packaged together. For example, a power metal-oxide-semiconductor (MOS) field-effect transistor (FET) semiconductor die and a logic semiconductor die (such as a gate driver die or a controller device die) may be packaged together to form a single packaged electronic device. Additional components, such as passive elements, may be included in the packaged electronic device. The semiconductor die is mounted to a package substrate that provides conductive leads, some of which form the terminals of the packaged electronic device. The semiconductor die may be flip-chip mounted with a device side surface facing the package substrate surface, where the semiconductor die is mounted to the leads of the package substrate by conductive post connects that are attached to the package substrate by solder, such as solder balls or bumps. The packaged electronic device may have a package formed by a thermosetting epoxy resin in a molding process, or by the use of an epoxy, plastic, resin that is liquid at room temperature and then hardens, or by the use of a laminate film. The package body may be formed using an additive manufacturing process with continuous material deposition or a drop-on-demand process. The package body may provide a hermetic package for the packaged electronic device. The package body may be formed in a mold using an encapsulation process, but with some of the leads of the package substrate not covered during encapsulation, and these exposed lead portions provide exposed terminals for the packaged electronic device.

[0014] The term "package substrate" is used herein. A package substrate is a substrate that is arranged to receive and support a semiconductor die in a completed semiconductor package. The package substrate can include a conductive leadframe, which can be formed from copper, aluminum, stainless steel, and alloys such as alloy 42 and copper alloys. In a flip chip package, a portion of the leads is arranged to receive solder joints between the leads and conductive post connects for the semiconductor die. The solder joints form the physical die attachment and electrical connection to the package substrate. When a leadframe is used as the package substrate, the leadframe can be provided in a strip or array. The die can be placed on the strip or array, the die is flip chip mounted to the leadframe, and the leadframe and die are covered with a molding compound in a molding process.

[0015] Alternative package substrates include pre-molded lead frames (PMLFs) and molded interconnect substrates (MISs) for receiving semiconductor dies. Rewireable lead frames can be used that include multiple levels of conductors in a dielectric material. These package substrates can include a dielectric, such as a liquid crystal polymer (LCP) or a mold compound, and can include one or more layers of conductive portions in the dielectric. Repeated plating and patterning can form multiple layers of conductors separated by a dielectric, and conductive vias connecting the conductor layers through the dielectric, which can be a mold compound. Package substrates can include lead frames, and can include plated, stamped, and partially etched lead frames. In partially etched lead frames, a metal substrate configured for the lead frame can be etched from one side and then etched from the other to form two levels of metal, forming full thickness and partial thickness portions, and in some areas, the metal can be etched all the way through to form openings through the partially etched lead frame. Package substrates can also be tape-based and film-based, which can form the substrate carrying the conductors. Package substrates can include ceramic substrates, laminate substrates having multiple conductor and insulator layers, and ceramic, fiberglass or resin printed circuit boards, or glass-reinforced epoxy substrates such as flame-retardant 4 (FR4).

[0016] The term "post connect" is used herein. As used herein, a post connect is a structure made of conductive material, such as copper or a copper alloy, gold or a gold alloy, or a combination of conductive metals that provides a connection between a semiconductor die and a package substrate. A proximal end of the post connect is mounted to a bond pad on the device side surface of the semiconductor die, while a distal end of the post connect extends away from the bond pad of the semiconductor die. When a packaged semiconductor device is oriented in a flip-chip orientation with the semiconductor die positioned above and facing the die mounting surface of the package substrate, the post connect vertically connects between the conductive portion of the package substrate and the bond pad of the semiconductor die. Some references describe one type of post connect as a "controlled collapse chip connection" or "C4" bump. A conductive post connect includes a post of conductive material and has a distal end that faces away from the surface of the bond pad on the semiconductor die, and a proximal end of the post connect is mounted to the bond pad.

[0017] A package substrate, such as a lead frame, molded interconnect substrate (MIS), pre-molded lead frame (PMLF) or multi-layer package substrate, has conductive portions on a planar die side surface. The leads of a metal lead frame are conductive along the entire surface, while for other substrate types, conductive lands in the dielectric substrate material are configured and aligned to electrically and mechanically connect to conductive post connects. The post connects may run along the same direction as the conductive leads in the package substrate, such that the post connects look like rails or have a rectangular cross section. If the post connect is copper, pillar-shaped, and has a solder bump at its end, it may be called a "copper pillar bump." Thus, a copper pillar bump or copper bump is an example of a post connect. In addition to being pillar-shaped, the post connects may also be cylindrical, rectangular, or rail-shaped, and may have an oval, round, square, or rectangular cross section. In various examples, multiple post connects can be configured in parallel with one another, with additional post connects bonded to a common trace on the package substrate to provide a low resistance path between the semiconductor die and the package substrate. A thermal reflow process is used to melt the solder between the post connects and the package substrate to create the solder joint. The solder joint provides both mechanical attachment and electrical connection between the semiconductor die and the package substrate. Post connects are used in fine pitch semiconductor packages to make a few, tens, hundreds, or thousands of connections between the semiconductor die and the package substrate. As device sizes continue to shrink and the density of connections increases, these sizes may decrease. The spacing between post connects may also decrease.

[0018] In packaging a semiconductor device, a mold compound may be used to partially cover the package substrate, cover the semiconductor die, and cover the connections from the semiconductor die to the package substrate. This "encapsulation" process is often an injection molding process and may use a curable mold compound such as an epoxy resin. The mold compound, which is solid or powdery at room temperature, may be heated to a liquid state and then molded. Transfer molding may be used. A unit mold shaped to enclose the individual devices may be used or block molding may be used to simultaneously form packages for several devices using molten mold compound. The devices may be provided in arrays of several, hundreds, or even thousands of devices in rows and columns molded together. After molding, the individual packaged devices are cut from one another in a saw operation by cutting the mold compound and package substrate at saw streets formed between the devices. Portions of the package substrate leads are exposed from the mold compound package to form terminals of the packaged semiconductor device.

[0019] In a flip chip die attach process, solder balls, columns, or bumps are used to form solder joints between conductive post connects and conductive leads or lands on a package substrate. The post connects are formed extending from bond pads on the semiconductor die. The semiconductor die is then oriented with the distal ends of the post connects facing the die mounting surface of a circuit board or package substrate. A solder reflow process is used to attach the post connects to the conductive die pads or leads on the package substrate, with the solder joints forming the physical attachment and electrical connection between the package substrate and the semiconductor die.

[0020] The term "scribe lane" is used herein. A scribe lane is a portion of a semiconductor wafer between semiconductor dies. The term "scribe street" is sometimes used in related literature. Once semiconductor processing is finished and the semiconductor device is completed, the semiconductor device is separated into individual semiconductor dies by cutting the semiconductor wafer along the scribe lanes. The separated dies can then be removed and individually handled for further processing, including packaging. This process of removing the dies from the wafer is called "singulation" or sometimes called "dicing". The scribe lanes are located on the four sides of the semiconductor die, and when the dies are singulated from each other, rectangular semiconductor dies are formed.

[0021] The term "saw street" is used herein. Saw streets are areas between molded electronic devices that allow a saw, such as a mechanical blade, laser, or other cutting tool, to pass between the molded electronic devices to separate the devices from one another. This process is another form of singulation. When the molded electronic devices are provided in a strip, one device adjacent to another along the strip, the saw streets are parallel and orthogonal to the length of the strip. When the molded electronic devices are provided in an array of devices in rows and columns, the saw streets include two parallel groups of saw streets, the two groups being orthogonal to one another, such that the saw traverses the molded electronic devices in two different directions to separate the packaged electronic devices from one another in the array.

[0022] The term "quad flat no-lead" or "QFN" is used herein for certain types of electronic devices. QFN packages have conductive leads that are coextensive with the sides of the molded package body, with the leads on four sides. Alternative flat no-lead packages may have leads on two sides or only one side. These may be called "small outline no-lead" or "SON" packages. Electronic devices packaged without leads may be surface mounted to a substrate. Leaded packages are shaped such that the leads extend away from the package body and form portions for soldering to a substrate. Dual in-line packages, or DIPs, may be used in conjunction with these configurations. Small outline packages, or SOPs, may be used in conjunction with these configurations.

[0023] The term "ball grid array" or "BGA" is used herein for another type of electronic device. A BGA package has solder balls on a substrate side surface, which form the terminals of the semiconductor device package. The BGA package can be mounted to a printed circuit board by a solder reflow process to form solder joints between the BGA package and the printed circuit board. For semiconductor devices with many input and output terminals, the BGA package can have a grid or array of solder balls on the substrate side of the semiconductor device package.

[0024] The term "reconfigured semiconductor device" is used herein. The reconfigured semiconductor device includes a semiconductor die partially coated in a dielectric material, and a redistribution layer formed over the semiconductor die. In an example arrangement, the semiconductor die has bond pads at a first pitch distance, and the redistribution layer has conductors in a passivation layer that couple the bond pads to conductive lands configured for solder balls or post connects, the solder balls or post connects being at a second pitch that is greater than the first pitch distance.

[0025] In such an arrangement, a semiconductor die has a post connect mounted with a proximal end on a device side surface of the semiconductor die, and a solder ball or bump is formed on a distal end of the post connect. The semiconductor die is singulated from the semiconductor wafer. The semiconductor die has bond pads on the device side surface with a first minimum pitch distance between the bond pads. The semiconductor die is placed on a carrier spaced apart from one another. A dielectric, such as a mold compound, thermoplastic, resin or epoxy, is formed over a portion of the semiconductor die to form a reconstituted wafer comprising the semiconductor die with the bond pads exposed from the dielectric. A redistribution layer is formed over the bond pads of the semiconductor die, and bumps or post connects are formed on the redistribution layer to form solder balls or solder bumps with a second pitch distance therebetween, the second pitch distance being greater than the first pitch distance. The redistribution layer is then singulated to form a reconstituted semiconductor device including the semiconductor die and the redistribution layer with the solder bumps. The reconstituted semiconductor device is then flip-chip mounted to a package substrate using a solder reflow process. The package substrate can be a ceramic circuit board, a fiberglass printed circuit board such as flame retardant 4 (FR4) or other dielectric, a pre-molded lead frame, a multi-layer package substrate formed by additive manufacturing using layered conductor and dielectric plating, or another package substrate. In an exemplary arrangement, the package substrate is a ball grid array (BGA) package substrate with solder balls on a surface opposite the device surface. A protective lid or molding process can provide a protective package to complete the packaged device. Using a reconstituted semiconductor device with a second pitch distance between the bumps or solder balls allows a semiconductor die with a first smaller pitch between bond pads to be flip-chip mounted to the semiconductor device package, allowing the use of smaller semiconductor die. Smaller semiconductor die, which are increasingly being manufactured in advanced semiconductor processes, can be used in conjunction with flip-chip BGA packages to reduce the cost per device.

[0026] FIG. 1A illustrates a semiconductor device package 100 in cross-section, which is a BGA package. The semiconductor device package 100 has a body 103 formed from a dielectric, such as a thermosetting molding compound, for example an epoxy resin molding compound. Other dielectric materials, such as resin, epoxy, or plastic, can also be used. The epoxy resin molding compound can include a filler to improve thermal conductivity. The BGA balls 116 are part of the package substrate 104 that supports the semiconductor die (not visible in FIG. 1 because it is obscured by the package body 103, see FIG. 1B) in the semiconductor device package 100, and the BGA balls 116 are exposed from the package body 103 and form the electrical terminals of the semiconductor device package 100. The semiconductor device package 100 can be mounted to a circuit board using surface mount technology (SMT) with the solder balls 116 to form solder joints. Package sizes for semiconductor devices continue to shrink and may currently be from a few millimeters on a side to less than a millimeter on a side, but larger or smaller sizes are also used. Future package sizes may be smaller. The number of terminals 116 increases with the integration of additional circuit elements on several semiconductor dies, as the entire system is formed on a single semiconductor die.

[0027] FIG. 1B illustrates the BGA package 100 of FIG. 1A in another cross-sectional view with the dielectric forming the package body 103 of the package 100 shown in transparent form. The semiconductor die 102 is flip-chip mounted to a device side surface 112 of a package substrate 104 by solder bumps 114. An underfill 115, which may be an epoxy, resin or polymer, is shown protecting the solder joints between the solder bumps 114 and the package substrate 104. Alternatively, the underfill 115 may be omitted and the material forming the package body 103, which may be a mold compound, may extend into the area underlying the semiconductor die 102. The semiconductor die 102 may be connected by solder balls formed on bond pads or by post connects, such as copper pillar bumps, having solder bumps formed on the post connects.

[0028] As semiconductor processes continue to advance, the minimum feature size that can be fabricated on a semiconductor die continues to shrink. The size of the semiconductor die shrinks along with the minimum feature size of the process node. Smaller semiconductor dies tend to reduce device costs as the number of semiconductor devices fabricated on a single wafer increases, while the process cost per wafer remains relatively stable. Thus, as the minimum feature size shrinks and the die size shrinks, the number of dies fabricated per wafer increases and the cost per finished device decreases. As the semiconductor die gets smaller, the pitch between bond pads on the device side surface of the semiconductor die also shrinks, in certain instances to a bond pad pitch of less than about 60 micrometers. However, the processes used to form the solder balls or bumps are not affected by the minimum feature size of the semiconductor process node, and these processes have a larger minimum pitch requirement, such as 150 micrometers center-to-center. As in FIG. 1B, when the semiconductor die is flip-chip mounted, the minimum bond pad pitch that can be used may be limited by the solder bump process rules, which means that the semiconductor die cannot be fabricated at the minimum die size for flip-chip packaging. One approach to solving this problem is a semiconductor die with a larger area and a correspondingly larger bond pad pitch distance, but to meet the solder bump process requirements, this approach significantly reduces the device yield per wafer and increases the cost of the semiconductor die.

[0029] In such an arrangement, a reconfigured semiconductor device is formed with a redistribution layer over a semiconductor die to map a first bond pad pitch on the semiconductor die to a second, larger solder bump pitch for use in a flip chip package. Using this arrangement, smaller semiconductor dies manufactured at lower cost can be packaged in a flip chip BGA package.

[0030] FIG. 2A illustrates, in a perspective view, and FIG. 2B illustrates, in a close-up view, a semiconductor wafer including semiconductor dies and individual semiconductor dies useful in the present arrangement. In FIG. 2A, a semiconductor wafer 201 is shown with semiconductor dies 202 arranged in rows and columns. Scribe lanes 203 and 204 are shown between the dies, running in mutually orthogonal directions, providing areas for separating the completed semiconductor dies from one another by sawing, scribing, or laser cutting methods. The semiconductor dies 202 each have bond pads 208 on their device-side surface. FIG. 2B illustrates, in a close-up view, one semiconductor die 202 with bond pads 208 on their device-side surface. The bond pads 208 provide terminals, such as input, output, and input / output pins, for the semiconductor die. More than 100 input / output (IO) pins, for example 180 pins, may be used. Examples of high pin count semiconductor dies include high speed data converters (HSDCs) that may have multiple analog-to-digital data channels, embedded processors that may include multiple processor cores on a single semiconductor device with corresponding input and output data paths, and integrated systems on a chip, such as systems with antennas on package (AoP), such as radar, lidar, cellular, WiFi and other communication devices. These highly integrated semiconductor devices require many bond pad terminals, and the pitch between bond pads can be a critical design parameter for reducing device size, thus increasing device yield and reducing cost.

[0031] 3A-3H illustrate, in a series of cross-sectional views, selected steps for forming a completed reconstituted semiconductor device for use in an arrangement. FIG 3A illustrates, in cross-sectional view, a semiconductor wafer 201 having semiconductor dies 202 arranged with bond pads 208 formed on a device side surface. The semiconductor wafer 201 can be singulated such that the semiconductor device dies 202 are separated from one another by cutting the semiconductor wafer 201 along scribe lanes 203 between the semiconductor device dies 202, as shown in FIG 3A.

[0032] 3B illustrates in another cross-sectional view the semiconductor device die 202 after being mounted to a carrier 301 by die attach 303. Die attach 303 may be a tape, film, or adhesive layer that is removable by ultraviolet (UV) or thermal energy, or peelable by mechanical means. Carrier 301 provides a support surface and may be a glass, semiconductor, or metal substrate. Carrier 301 can be cleaned and reused for additional processing.

[0033] FIG. 3C illustrates the semiconductor die 202 of FIG. 3B in another cross-sectional view after additional processing. In FIG. 3C, a dielectric material 305 covers the backside surface of the semiconductor die 202 to form a protective body. The dielectric material 305 may be a thermosetting epoxy resin molding compound in one example. In an alternative arrangement, the dielectric material 305 may be a thermoplastic such as acrylonitrile butadiene styrene (ABS) or acrylonitrile styrene acrylate (ASA) or other plastics. The dielectric 305 may be a liquid crystal polymer (LCP). The dielectric 305 may be an epoxy, resin, or other molding compound.

[0034] 3D illustrates in cross-sectional view the dielectric material 305 and the semiconductor device die 202 after they have been removed from the carrier 301. The semiconductor device die 202 is positioned in spaced apart relation with the bond pads 208 exposed from the dielectric material 305 for additional processing.

[0035] 3E illustrates another cross-sectional view of the dielectric material 305 and the semiconductor device die 202 after additional processing. In this arrangement, a passivation layer 307 is formed as a first step in forming a redistribution layer over the dielectric material 305. The redistribution layer is used to connect the bond pads 208 to additional conductive lands arranged at a larger pitch to meet the requirements of the solder bump process. The process of forming the redistribution layer begins by depositing a first passivation layer 307 over the bond pads 208 as shown in FIG. 3E. The passivation layer may be a polymer, such as polyimide.

[0036] FIG. 3F illustrates the semiconductor device die 202, bond pads 208, and dielectric layer 305 in a further cross-sectional view. A first trace layer 308 is formed over the passivation layer 307 in a plating operation. The first trace layer 308 is patterned to form conductors coupled to the bond pads 208. The conductors may be copper, gold, tungsten, or other plated conductors. Electroplating or electroless plating may be used. The first trace layer 308 is patterned to provide conductors extending a distance from the bond pads 208 at a first pitch distance p1. In one example, the first distance p1 is less than 60 micrometers center-to-center.

[0037] FIG 3G illustrates the dielectric material 305 and semiconductor die 202 of FIG 3F in another cross-sectional view after further processing. The dielectric material 305 is covered with a second passivation layer 309, and a second trace layer 310 is patterned on the second passivation layer 309. The second trace layer 310 is patterned to form conductive lands spaced apart at a distance greater than the pitch p1 in FIG 3F. The pitch distance between the lands in the trace layer 310 is selected to be at least large enough to allow solder bumps 311 to be plated onto the second trace layer 310. In FIG 3G, the reconstituted semiconductor device 351 is shown as one unit of multiple devices formed simultaneously. The pitch distance between the lands in the trace layer 310 (which corresponds to the solder bump pitch distance) is greater than the pitch distance p1 between the bond pads on the semiconductor device, and in one example may be greater than 100 micrometers, and in another particular example is about 150 micrometers, while the pitch distance between the bond pads may be less than 100 micrometers, and in some examples is less than 60 micrometers. Solder bumps 311 are shown formed on the conductive lands in the trace layer 310 and have a second pitch distance. Using an arrangement with a reconfigured semiconductor device having a second pitch distance p2 between interconnects that is greater than the first pitch distance p1 between the bond pads on the semiconductor die allows for the assembly of packaged devices using solder bumps having the required second pitch distance while using smaller semiconductor dies, reducing costs for the semiconductor dies, and reducing the cost of the assembled device.

[0038] Figure 3H illustrates in more detail the features of the reconfigured semiconductor device 351 of Figure 3G. The semiconductor die 202 has a backside surface coated with a dielectric material 305 and bond pads 208 on its device side surface. The bond pads 208 are coupled to solder bumps 311 by conductive traces 310 and conductive traces 308 in passivation layers 309, 307 of the redistribution layer 315. The passivation layers 307, 309 are disposed above the dielectric material 305. The solder bumps 311 are at a second pitch distance p2 and are spaced farther apart than the bond pads 208 at the first pitch distance p1. By rerouting the bond pad connections from a first pitch distance on the semiconductor die to a larger pitch distance, the rerouting layer 315 in such an arrangement, along with the passivation layers 307, 309 and conductive trace layers 308, 310, allows a smaller die size for the semiconductor die 202 to be used in conjunction with a flip chip package having solder bumps 311.

[0039] 4A-4E illustrate, in a series of cross-sectional and projected views, a process for forming a packaged semiconductor device in one configuration. FIG. 4A is a cross-sectional view of a reconfigured semiconductor device 451, illustrating another example similar to the reconfigured semiconductor device 351 of FIG. 3H, but with a dielectric layer 405 covering the backside of the semiconductor die 402. The reconfigured semiconductor device 415 is configured for use in a flip-chip semiconductor device package, with a redistribution layer 415 including a passivation layer and conductors (not shown for clarity of illustration) having post connects 410 including solder 411 at distal ends of the post connects 410.

[0040] FIG. 4B illustrates the reconfigured semiconductor device 451 of FIG. 4A in a perspective view, with solder bumps 411 shown extending from the reconfigured semiconductor device 451. FIG. 4C illustrates the reconfigured semiconductor device 451 mounted to a device-side surface 449 of a package substrate 453. The reconfigured semiconductor device 451 includes a semiconductor die 402 with a dielectric material 405 and solder bumps 411, and is mounted to the device-side surface 449 of the package substrate 453 by forming solder joints between the solder bumps 411 and the package substrate 453. The package substrate 453 may be a multi-layer package substrate, which may be a lead frame, PMLF, MIS, or ceramic package substrate, a printed circuit board such as flame-retardant 4 (FR4), a BT resin substrate, or a multi-layer package substrate constructed using an additive plating process to form a layer of conductor with a layer of dielectric, such as a thermoplastic, resin, or mold compound. Thermoplastic materials useful in such arrangements include ABS and ASA. The package substrate 453 has conductive lands (not shown for clarity of illustration) on the device side surface 449, and the reconfigured semiconductor device 451 is flip-chip mounted to the conductive lands by a solder reflow process to form solder joints.

[0041] 4D illustrates in cross-section a reconstituted semiconductor device 451 and a package substrate 453 with a mold compound 455 on a device side surface 449 of the reconstituted semiconductor device 451. The mold compound 455 may be formed by a transfer molding process in which the reconstituted semiconductor device 451 and a portion of the package substrate 453 are covered with a thermosetting epoxy resin mold compound. The package substrate 453 is at least partially covered with the mold compound 455. In an alternative arrangement, a protective cover or lid may be used instead of the mold compound 455 to protect the reconstituted semiconductor device 451, and the lid may be sealed to the package substrate 453.

[0042] 4E illustrates in another cross-sectional view the completed semiconductor device package 475 formed with BGA solder balls 457. The reconfigured semiconductor device 451 is flip-chip mounted to a package substrate 453, and the reconfigured semiconductor device 451 is mounted to the device package substrate 453 by solder bonds. The BGA solder balls 457 form the terminals of the completed packaged semiconductor device 475. The semiconductor die 402 is within the reconfigured semiconductor device 451 and is flip-chip mounted onto the package substrate 453. The BGA solder balls 457 are coupled to the reconfigured semiconductor device 451 and to the semiconductor die 202 by conductive traces in the package substrate 453 and by a redistribution layer 415 in the reconfigured semiconductor device 451.

[0043] In one example, the die size of a semiconductor device packaged in a flip chip BGA package was reduced from a bond pad pitch of 155 micrometers (a pitch compatible with solder bump processes) to a bond pad pitch of 50 micrometers using the present arrangement. The required die size was reduced from 3.1×3.1 millimeters to 1×1 millimeters, resulting in approximately a 90% reduction in silicon die cost due to the increased number of dies per wafer. Although the use of a redistribution layer on top of the dielectric material of the reconfigured semiconductor device increases the cost per packaged unit, the total cost of the packaged semiconductor device was reduced by more than 60%, so that the present arrangement was approximately one-third the cost of a packaged device produced without the present arrangement. This result was found for several different types of semiconductor devices produced on both 8-inch and 12-inch wafers using different processes. By enabling the use of smaller semiconductor die, the present arrangement reduces overall device cost, even when adding components (materials used in forming the reconfigured semiconductor device of the present arrangement include a dielectric material and a redistribution layer over the dielectric material that comprises conductors and a passivation layer).

[0044] FIG. 4E illustrates some relevant width dimensions. Dw is the die width, Rw is the reconfigured semiconductor device width, and Pw is the package width for the exemplary semiconductor device package 475. In a specific example, the die width (with the smaller die size enabled by the use of the present configuration) was 1 millimeter, the reconfigured semiconductor device width Rw was 3 millimeters, which provides the necessary bump pitch for the reconfigured semiconductor device solder bumps, and the package width Pw was 7 millimeters. A variety of die and package sizes are useful for the present arrangement. As semiconductor processes continue to advance, die sizes continue to shrink. The present configuration advantageously allows for the use of flip-chip BGA packages with smaller die sizes and lower overall device costs than previous approaches.

[0045] 5 illustrates in a flow chart a method for forming the present configuration. In step 501, the method begins by forming a reconstituted wafer comprising semiconductor dies having bond pads on a device side surface with a first pitch between the bond pads. (See FIG. 3F, pitch distance p1). In step 503, a redistribution layer is formed over the semiconductor dies on the reconstituted wafer. (See FIGS. 3F-3G, redistribution layer 315).

[0046] In step 505, the method continues by forming solder bumps on the redistribution layer with a second pitch between the solder bumps that is greater than the first pitch. (See FIG. 3H, solder bumps 311). In step 507, the reconstituted wafer is singulated to form individual bumped reconstituted semiconductor devices (See FIG. 4A, reconstituted semiconductor device 451). In step 509, the singulated reconstituted semiconductor devices are flip-chip mounted to a package substrate (See FIG. 4C, package substrate 453). In step 511, overmolding is performed or a lid is mounted on the package substrate (See FIG. 4D, mold compound 455). The package may be a BGA package, or a QFN, or other package type. For devices with many terminals, the present configuration can be used to efficiently form a BGA or pin grid array (PGA) package. Other package types such as a quad flat no-lead (QFN) package can also be used.

[0047] Using these processes and arrangements allows a semiconductor die having a first minimum pitch between bond pads to be flip-chip mounted to a package substrate using solder bumps with a second minimum pitch between the solder bumps that is greater than the first bond pad pitch. In some examples, the first pitch distance is less than 100 micrometers and may be less than 60 micrometers. The second pitch distance is greater than the first pitch distance and in some examples may be 100 micrometers or 150 micrometers. Using this arrangement, smaller die sizes are possible for flip-chip semiconductor device packages by using a reconfigured semiconductor device with a redistribution layer to increase from the bond pad pitch of the semiconductor die to a pitch for the larger solder bumps.

[0048] Modifications in the described arrangements are possible and other alternative configurations are possible within the scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor package, Forming bond pads on the device-side surface of a semiconductor die, wherein the bond pads are spaced apart from each other by a first pitch distance of less than 100 micrometers, The device-side surface of the semiconductor die is placed on a carrier, To form a reconfigured wafer containing the semiconductor dies that are spaced apart from each other, a dielectric layer is formed on the back surface opposite to the device-side surface of the semiconductor dies, Removing the support from the semiconductor die, Forming a redistribution layer on the bond pad on the device-side surface of the semiconductor die, Forming interconnections on the redistribution layer, wherein the interconnections are bonded to the bond pads by conductors in the redistribution layer, and the interconnections are spaced apart from each other by a second pitch distance greater than the first pitch distance, The process of separating a reconstructed semiconductor device from the reconstructed wafer, wherein the reconstructed semiconductor device includes one of the semiconductor dies and a solder bump on one of the semiconductor dies. The aforementioned reconfigured semiconductor device is mounted on the device-side surface of the package substrate, The reconfigured semiconductor device and the device-side surface of the package substrate are covered with a protective cover. Methods that include...

2. The method according to claim 1, A method for mounting the reconfigurable semiconductor device on the device-side surface of a package substrate, which includes flip-chip mounting the reconfigurable semiconductor device on a ball grid array package substrate.

3. The method according to claim 1, A method wherein the package substrate is a ball grid array substrate, a pre-molded lead frame, a metal lead frame, a ceramic package substrate, or a multilayer package substrate.

4. The method according to claim 1, Forming the aforementioned redistribution layer Forming a layer of passivation material on the bond pad of the semiconductor die, Patterning the layer of the passivation material in order to expose the bond pad, Plating a conductive layer on the bond pad, Forming conductive lands configured to receive solder bumps on the layer of passivation material, Forming solder bumps on the conductive land such that the solder bumps are spaced apart from each other by at least the second pitch distance, Methods that include...

5. The method according to claim 1, A method wherein the first pitch distance is less than 60 micrometers.

6. The method according to claim 5, The method wherein the second pitch distance is greater than 150 micrometers.

7. The method according to claim 1, The method wherein the first pitch distance is greater than 10 micrometers and less than 60 micrometers.

8. The method according to claim 7, wherein the second pitch distance is greater than 100 micrometers.

9. The method according to claim 1, A method for forming the reconfigured wafer, comprising coating the back surface of the semiconductor die with one of the following: thermoplastic, acrylonitrile butadiene styrene (ABS), acrylonitrile styrene acrylate (ASA), resin, epoxy, plastic, or epoxy resin mold compound.

10. The method according to claim 1, A method for forming the interconnection, comprising forming a conductive post-connector that extends from a nearby end on the redistribution layer and has solder at a distal end facing away from the redistribution layer.

11. A method for manufacturing a semiconductor package, Placing the device-side surface of the semiconductor die on a carrier, To form a reconfigured wafer including the semiconductor dies spaced apart by a first pitch distance, a dielectric layer is formed on the back surface of the semiconductor dies opposite the device-side surface, Removing the carriers from the semiconductor die, Forming a redistribution layer on the bond pad on the device-side surface of the semiconductor die, Forming interconnections on the redistribution layer, wherein the interconnections are bonded to the bond pads by the conductor of the redistribution layer, and the interconnections are spaced apart from each other by a second pitch distance greater than the first pitch distance. The process of separating a reconstructed semiconductor device from the reconstructed wafer, wherein the reconstructed semiconductor device includes one of the semiconductor dies and a solder bump on one of the semiconductor dies. Methods that include...

12. The method according to claim 11, The aforementioned reconfigured semiconductor device is mounted on the device-side surface of the package substrate, The reconfigured semiconductor device and the device-side surface of the package substrate are covered with a protective cover. Methods that further include the above.

13. The method according to claim 11, Forming the aforementioned redistribution layer Forming a layer of passivation material on the bond pad of the semiconductor die, Patterning the layer of the passivation material in order to expose the bond pad, Plating a conductive layer onto the bond pad, Forming a conductive land on the layer of the passivation material, Forming solder bumps on the conductive land, wherein the solder bumps are spaced apart from each other by at least the second pitch distance, Methods that include...

14. The method according to claim 12, A method for mounting the reconfigurable semiconductor device on the device-side surface of a package substrate, which includes flip-chip mounting the reconfigurable semiconductor device onto a ball grid array package substrate.

15. The method according to claim 12, A method wherein the package substrate is a ball grid array substrate, a pre-molded lead frame, a metal lead frame, a ceramic package substrate, or a multilayer package substrate.

16. The method according to claim 11, A method for forming the reconfigured wafer, comprising covering the back surface of the semiconductor die with one of the following: thermoplastic, acrylonitrile butadiene styrene (ABS), acrylonitrile styrene acylate (ASA), resin, epoxy, plastic, or epoxy resin mold compound.

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