Process for producing a structure comprising at least two chips on a substrate - Patent application

Abstract

The present invention relates to a process for manufacturing a structure comprising at least two chips (p11, p12, p13, p14) in a receiver substrate (3), comprising the steps of forming a pseudo donor substrate (10) by arranging tiles (P1, P2, P3) of a donor substrate (2) on a support substrate (1), bonding the pseudo donor substrate (10) to the receiver substrate (3) via the tiles such that each tile covers a different target area (Z1, Z2, Zn) of the receiver substrate (3), transferring portions (P'1, P'2, P'3) of the tiles (P1, P2, P3) to the receiver substrate (3), chemical mechanical polishing of the tiles of the pseudo donor substrate and / or the tile portions transferred to the receiver substrate, and removing material from the tile portions so as to divide each tile portion into chips (p11, p12, p13, p14) respectively arranged in the target areas (Z1, Z2, Zn).

Description

[Technical field]

[0001] The present invention relates to a process for producing a structure comprising at least two chips on a substrate. [Background technology]

[0002] In the fields of microelectronics, optics or optoelectronics, the design of multilayer structures sometimes requires tiles in the form of parts of layers of a donor substrate that are to be transferred to a receiver substrate.

[0003] This type of process is commonly referred to as a tiling process and involves the partial transfer of a layer taken from a donor substrate to form one or more tiles arranged in a pattern or at predetermined locations on a receiver substrate.

[0004] Such tiling may be necessary due to size differences between the donor and receiver substrates, in particular, due to which the entire layer of the donor substrate cannot be transferred to the receiver substrate.

[0005] A known layer transfer process is the Smart Cut™ process, in which a donor substrate is bombarded with atomic species to form a weakened zone that defines the layer to be transferred, the donor substrate is bonded to a receiver substrate, and the donor substrate is detached along the weakened zone to transfer the layer from the donor substrate to the receiver substrate, provided that the donor and receiver substrates are of the same size.

[0006] However, while silicon substrates with relatively large sizes, typically 300 mm in diameter, are available, other materials of interest currently exist only in the form of bulk substrates with smaller sizes, for example 10 or 15 cm in diameter. Furthermore, these materials of interest are in some cases particularly expensive, so it is desirable to minimize potential waste during transfer. This is particularly true for III-V semiconductor materials, including nitrides (e.g., for binary compounds, indium nitride (InN), gallium nitride (GaN) and aluminum nitride (AlN)), arsenides (e.g., for binary compounds, indium arsenide (InAs), gallium arsenide (GaAs) and aluminum arsenide (AlAs)), and phosphides (e.g., for binary compounds, indium phosphide (InP), gallium phosphide (GaP) and aluminum phosphide (AlP)).

[0007] Instead of transferring the entire layer of the donor substrate, a solution based on the Smart Cut™ process consists of taking one or more tiles from at least one donor substrate and transferring said tiles to a support substrate having the same diameter as the receiver substrate, thereby forming an intermediate substrate known as a pseudo-donor substrate. The process then involves transferring a portion of each tile to the receiver substrate by forming a weakened area in each tile by implanting atomic species, bonding the pseudo-donor substrate to the receiver substrate via the tiles and detaching each tile along the weakened area.

[0008] During this process, it is generally necessary to polish the tiles after the formation of the pseudo donor substrate and / or after the transfer of the tile portions to the receiver substrate. Such polishing, typically chemical mechanical polishing (CMP), aims to planarize the free surfaces of the tiles or tile portions.

[0009] One particular difficulty occurs when the tiling is not very dense, i.e. when the coverage of the tiles on the receiver substrate, corresponding to the ratio of the total surface area of ​​the tiles to the total surface area of ​​the receiver substrate, is typically less than 50% or even less than 30%. In that situation, there is a large distance between the tiles on the pseudo donor substrate and on the receiver substrate, typically of the order of several millimeters.

[0010] However, the polishing cloth applied to the tiles can deform in the recesses formed by the spaces between the tiles, resulting in differences in polishing height between the tiles and excess material consumption at the edges of the tiles compared to the centers of the tiles.

[0011] These inhomogeneities caused by polishing are detrimental to the subsequent use of the tiles to form electronic, optical or optoelectronic components. Summary of the Invention

[0012] The aim of the present invention is to design a process for producing a structure comprising at least two chips on a support substrate, which makes it possible to overcome the above-mentioned polishing drawbacks.

[0013] For this purpose, the invention relates to a process for producing a structure comprising at least two chips on a receiver substrate, the process comprising: forming a pseudo donor substrate by disposing at least one tile of at least one donor substrate on a support substrate; bonding the pseudo donor substrate to a receiver substrate via tiles such that each tile at least partially covers at least two different target areas of the receiver substrate; transferring portions of the tile to a receiver substrate; - at least one step of chemical mechanical polishing of the tiles of the pseudo donor substrate and / or the tile portions transferred to the receiver substrate; removing material from the tile portions after at least one step of chemical mechanical polishing to divide each tile portion into at least two chips, each chip being disposed in a respective target area; We propose a process that includes:

[0014] By modifying the size of the tile portions after they have been transferred to the receiver substrate to form the chips, it is possible to increase the density of tiles in the pseudo donor substrate and reduce the distance between the tiles and between the transferred tile portions, thus minimizing polishing drawbacks associated with these excessively large distances between tiles or transferred tile portions.

[0015] Advantageously, after the etching step, the coverage of the chips on the receiver substrate, ie the ratio of the total surface area of ​​the chips to the total surface area of ​​the receiver substrate, is less than 50%, preferably less than 30%.

[0016] It is particularly advantageous for the coverage of the tiles on the pseudo donor substrate, ie the ratio of the total surface area of ​​the tiles to the total surface area of ​​the support substrate, to be greater than 50%, preferably greater than 75%.

[0017] Each tile may have a side with a length of 5mm or more, preferably 8mm or more, preferably 10mm or more.

[0018] Further, each chip may have a side having a length of 5 mm or less, preferably 3 mm or less, preferably 1 mm or less.

[0019] It is particularly advantageous for the distance between two adjacent tiles to be less than or equal to 3 mm, preferably less than or equal to 1 mm.

[0020] On the other hand, the distance between two adjacent chips may be greater than or equal to 3 mm, preferably greater than or equal to 5 mm.

[0021] In a particular embodiment, each tile at least partially covers two different target areas of a receiver substrate, and chips are formed from the tiles in each respective target area.

[0022] In another embodiment, each tile covers at least a corner of each of four different target areas of a receiver substrate arranged in a square or rectangle, and a chip is formed from the tile at each corner of each target area.

[0023] In another embodiment, each tile is in the form of a strip at least partially covering at least three aligned target areas of the receiver substrate, and a chip is formed from said tiles in each respective target area.

[0024] It is particularly advantageous for the support substrate and the receiver substrate to have substantially the same diameter, which is larger than the diameter of the donor substrate.

[0025] The pseudo donor substrate may be bonded to the receiver substrate by molecular adhesion.

[0026] In one preferred embodiment, the transfer of each tile portion sequentially involves forming a weakened region by implanting atomic species into each tile of a pseudo donor substrate to define the tile portion to be transferred, bonding the pseudo donor substrate to a receiver substrate via the tile, and detaching each tile along the weakened region.

[0027] In another embodiment, the transfer of each tile portion includes thinning each tile of the pseudo donor substrate by grinding and / or etching.

[0028] Each tile may have a thickness between 20 μm and 1000 μm, preferably between 100 μm and 700 μm, and the transferred portion of each tile may have a thickness between 30 nm and 1.5 μm.

[0029] Each tile is Semiconductor materials such as III-V materials, in particular indium nitride (InN), gallium nitride (GaN), aluminium nitride (AlN), indium arsenide (InAs), gallium arsenide (GaAs), aluminium arsenide (AlAs), indium phosphide (InP), gallium phosphide (GaP) or aluminium phosphide (AlP), or group IV or IV-IV materials, in particular germanium or silicon carbide (SiC), Lithium tantalate (LiTaO3), lithium niobate (LiNbO3), potassium sodium niobate (K x Na 1-x Piezoelectric materials such as lead oxide (NbO3 or KNN), barium titanate (BaTiO3), quartz, lead zirconate titanate (PZT), lead magnesium niobate and lead titanate combinations (PMN-PT), zinc oxide (ZnO), aluminum nitride (AlN) or aluminum scandium nitride (AlScN), and / or Electrically insulating materials such as diamond, strontium titanate, yttria stabilized zirconia, or sapphire The present invention may also include:

[0030] In some embodiments, the process includes forming at least one epitaxial layer on each tile portion by epitaxy, and removal of material to separate each tile portion into chips is performed after the epitaxy step.

[0031] In some embodiments, the removal of material comprises: forming a mask having a protective film partially covering each tile portion in a pattern defining the chips, and at least one opening defining a space to be formed between two chips; etching each tile portion through each opening in a mask to form the spaces separating the chips from one another; Includes.

[0032] The etching may be performed using an etching solution, and the mask is formed from a photoresist.

[0033] Alternatively, the etching may be performed using an ion beam, with the mask being formed from a metal.

[0034] In another embodiment, material removal is selectively performed with a focused ion beam, which is controlled to sweep only the areas of the tile portion that are to be removed. [Brief description of the drawings]

[0035] Other features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Figure 1] FIG. 2 is a top view of a receiver substrate with the target area shown. [Diagram 2] 13 illustrates the step of removing the tile from the donor substrate. [Diagram 3] 4 illustrates the step of placing the tile on a support substrate to form a pseudo donor substrate. [Figure 4] 4 illustrates the step of forming a weakened area in the tile. [Diagram 5] 13 illustrates the step of bonding a pseudo donor substrate to a receiver substrate via tiles. [Figure 6] 3 illustrates the step of transferring portions of the tile to a second support substrate following removal of the tile along the weakened region. [Figure 7] 1 illustrates forming a mask on a tile portion to define the chips to be formed. [Figure 8] 13 shows the step of etching the areas of the tile not protected by the mask to form the chips. [Figure 9] 4 shows the step of removing the protective film after etching. [Figure 10A] 1 illustrates an embodiment in which each tile partially covers two adjacent target areas. [Figure 10B] 4 shows an example of the distribution of chips formed from the tiles. [Figure 11A]1 illustrates an embodiment in which each tile partially covers several aligned target regions. [Figure 11B] 4 shows an example of the distribution of chips formed from the tiles. [Figure 12A] 1 illustrates an embodiment in which each tile partially covers four target areas arranged in a square. [Figure 12B] Figure 1 shows an example of a distribution of chips formed from the tiles. For readability, the drawings are not necessarily drawn to scale. Furthermore, the number and shapes of target areas, tiles and chips shown in the drawings are given by way of example only. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] The invention proposes to form a structure comprising at least two chips on a receiver substrate, using a substrate known as a pseudo donor substrate, comprising tiles each intended to form at least two chips distributed over at least two different target areas of the receiver substrate, to avoid polishing inhomogeneities even when the chips are separated by a relatively large distance and / or are not very densely distributed on the receiver substrate. The pseudo donor substrate is bonded to the receiver substrate via the tiles in order to transfer a portion of the tiles to the receiver substrate. Then, removal of material in each tile, especially between the chips, allows each chip to be formed.

[0037] The term "not very dense" is understood in this document to mean that the coverage of the chips on the receiver substrate, corresponding to the ratio of the total surface area of ​​the chips to the total surface area of ​​the receiver substrate, is typically less than 50%, or even less than 30%, and / or the distance between two adjacent chips is greater than or equal to 3 mm, or even greater than 5 mm.

[0038] The term "target area" is understood in this document to mean an area of ​​a receiver substrate intended for the subsequent formation of an electronic circuit different from that formed in an adjacent area, in particular in a subsequent step of fabricating said electronic circuit, the receiver substrate may be cut to form individual chips.

[0039] The target area is not necessarily visible on the receiver substrate and may in particular be defined in a plane that indicates the position of each component on the receiver substrate at each step of the manufacturing process. The position of the target area on the receiver substrate is linked to said plane by the reference system of the receiver substrate, i.e. a coordinate system that is attached to the receiver substrate and makes it possible to define the position of each point on the surface of the receiver substrate. For example, said reference system may include a reference point that can be located on the edge of the receiver substrate, such as a notch conventionally used in the semiconductor industry, and two orthogonal axes that run in the plane of the substrate, one of which runs diametrically from the notch and the other of which intersects the first axis at the center of the substrate.

[0040] 1 shows an example of a distribution of target areas on a receiver substrate. The receiver substrate 3 has a number of target areas Z1, Z2, Zn (n is an integer between 1 and the total number of target areas) defined by dotted lines. These areas are not necessarily marked on the surface of the receiver substrate, but the position of each target area in the reference frame of the receiver substrate is known.

[0041] 1, the target areas all have the same rectangular shape and are arranged on the receiver substrate in rows and columns to form a grid, however, in other embodiments not shown, the target areas may have different sizes and / or shapes.

[0042] The transfer process involves at least one chemical-mechanical polishing of the tiles, which may be performed after placing the tiles on a support substrate to form a pseudo donor substrate, before bonding to the receiver substrate, on the tile portions transferred to the receiver substrate, or even on both the tiles of the pseudo donor substrate and the tile portions transferred to the receiver substrate.

[0043] By having the tiles sized to form at least two chips, it is possible to increase the coverage of the tiles and / or decrease the distance between the tiles in the pseudo donor substrate relative to the coverage of the chips and the distance between the chips in the receiver substrate, respectively.

[0044] Thus, the coverage of the tiles on the pseudo donor substrate, i.e. the ratio of the total surface area of ​​the tiles to the total surface area of ​​the support substrate, is advantageously greater than 50%, preferably greater than 75%. The receiver substrate may have substantially the same diameter as the support substrate. In this case, this coverage also corresponds to the portion of the tiles transferred to the receiver substrate.

[0045] Advantageously, the distance between two adjacent tiles is less than or equal to 3 mm, preferably less than or equal to 1 mm.

[0046] Furthermore, the pseudo donor and receiver substrates may have the shape of relatively thin disks, typically having a thickness of a few hundred μm (commonly referred to as "wafers" in the field of microelectronics), or rectangular shapes, or any geometric shape.

[0047] As a result, it is advantageous for the tiles (and transferred tile portions) to be distributed sufficiently densely for chemical mechanical polishing to avoid thickness non-uniformities between the tiles or transferred tile portions, specifically, deformation of the polishing cloth between adjacent tiles is minimized so that polishing is substantially uniform across the surface of the tile or tile portion.

[0048] Only after this polishing step do the chips form by removal of material from the tile portions transferred to the receiver substrate, which causes a reduction in the density of the chips relative to that of the tiles, but without any risk of compromising the homogeneity of their thickness and shape, unless a further step of chemical-mechanical polishing of the chips has to be performed.

[0049] The removal of material may be carried out by various techniques known per se.

[0050] Some techniques use a mask to protect the surface of the chip and expose the surface of the tile portion that is intended to be removed by application of an etchant.

[0051] It is particularly advantageous if the mask is formed by photolithography and then the protective film is formed from a photoresist that is resistant to the etching agent, which is a chemical etching composition. Photolithography is very precise and therefore makes it possible to ensure that the chips have the desired shape and position.

[0052] Alternatively, the etchant is an ion beam (a technique known as "sputtering"). The mask may include a metal protective film or photoresist that protects the tile material from the ion beam in areas covered by the protective film.

[0053] The mask is removed after the tile portion has been etched through all or part of its thickness.

[0054] It should be noted that the use of a mask may be omitted if a selective etching process is used that uses a controlled, focused etching ion beam to sweep only the areas of the tile portion that are to be removed.

[0055] The pseudo donor substrate may be generated by placing tiles, one at a time or in small groups of tiles, on a support substrate, for example by a "pick and place" process, while transfer of the tiles from the pseudo donor substrate to a receiver substrate may be performed simultaneously.

[0056] The process thus allows subdivision of a tile into several smaller chips extending over several different target areas, preferably adjacent, and thus has the advantage of forming chips of very small dimensions without the need to place the chips individually on a receiver substrate, whilst avoiding the non-uniformity problems resulting from chemical mechanical polishing when the chips are not very densely distributed.

[0057] For example, each tile initially has a side having a length of 5 mm or more, preferably 8 mm or more, preferably 10 mm or more.

[0058] The tiles are advantageously made from materials that are not commercially available in the form of donor substrates with large dimensions. Thus, the donor substrate may have a diameter of less than 30 cm, for example around 10 or 15 cm.

[0059] This is particularly true for III-V semiconductor materials, including nitrides (e.g., for binary compounds, indium nitride (InN), gallium nitride (GaN), and aluminum nitride (AlN)), arsenides (e.g., for binary compounds, indium arsenide (InAs), gallium arsenide (GaAs), and aluminum arsenide (AlAs)), and phosphides (e.g., for binary compounds, indium phosphide (InP), gallium phosphide (GaP), and aluminum phosphide (AlP)).

[0060] This is also true for Group IV or IV-IV semiconductor compounds, such as germanium and silicon carbide.

[0061] The tiles may also be made of a piezoelectric material, such as lithium tantalate (LiTaO3) or else lithium niobate (LiNbO3), potassium sodium niobate (K x Na 1-x The optical fibers may be made from lead, zinc, aluminum nitride (AlN) or aluminum scandium nitride (AlScN) (a non-limiting list).

[0062] The tiles may also be made from an electrically insulating material such as diamond, strontium titanate (SrTiO3), yttria stabilized zirconia (YSZ) or else sapphire.

[0063] 2-9 show diagrammatically the formation of a pseudo donor substrate comprising tiles disposed on a first support substrate, the transfer of tile portions to a receiver substrate, and then the division of each tile portion into at least two chips.

[0064] With reference to Fig. 2, tiles P1 to P3 are cut out from a donor substrate 2. The tiles can be cut out using any technique known to the person skilled in the art. This may in particular be carried out by sawing and / or cleaving, or else by laser cutting. This may also be combined with a step of partial plasma etching of the cutting lines, for example a technique also known as "plasma dicing".

[0065] FIG. 3 shows the placement of tiles removed from the donor substrate in FIG. 2 onto a support substrate 1 to form a pseudo donor substrate 10.

[0066] Placement may also be performed using a "pick and place" technique, in which a robot picks up a pre-cut tile or group of tiles from a donor substrate and places it at a pre-defined location on the support substrate.

[0067] In a particular embodiment, each tile is attached to the support substrate by molecular adhesion. For this purpose, surface treatments of the tiles and / or the support substrate may be carried out beforehand to promote good molecular adhesion. These treatments may include, inter alia, cleaning, deposition of a bonding layer such as silicon oxide (SiO2), plasma activation before bonding, and annealing.

[0068] In other embodiments (not shown), bonding of the tile to the support substrate may involve an intermediate bonding layer, such as a polymeric, eutectic, or ceramic bonding layer.

[0069] Advantageously, the support substrate 1 has a larger diameter or dimension than the donor substrate 2. For example, the support substrate 1 may have the shape of a disk with a diameter of the order of 300 mm.

[0070] 4 shows the formation of weakened areas in the tiles P1-P3 in order to define the surface portions of the tiles P1-P3 intended to be transferred to a receiver substrate. As indicated by the arrows, the weakened areas 11 are advantageously formed by implantation of atomic species such as hydrogen and / or helium into the tiles at a depth corresponding to the thickness of the layer to be transferred.

[0071] Optionally, the pseudo donor substrate may be subjected to chemical mechanical polishing of the surface of the tile.

[0072] FIG. 5 shows bonding of the pseudo donor substrate of FIG. 3 to a receiver substrate via a tile.

[0073] During this bonding, the two substrates are positioned relative to each other such that each tile of the pseudo donor substrate 10 at least partially covers at least two different target areas of the receiver substrate 3 .

[0074] In the illustrated example, each tile partially covers four target areas arranged in a square or rectangle, i.e. the four target areas belong to two adjacent rows and two adjacent columns, the centers of the four target areas forming the four vertices of the square or rectangle. Each tile therefore covers not only a part of the surface of said target areas, but also the surface of the receiver substrate, which is arranged between the target areas, which in this example have a cross shape. In general, the distance between the target areas is minimized in order to optimize the surface of the receiver substrate and minimize material loss. The surface of each target area covered by a tile is adapted depending on the size of the chip or component to be formed in or on the target area.

[0075] It is particularly advantageous for each tile to be attached to the receiver substrate 3 by molecular adhesion. For this purpose, surface treatments of the tiles and / or of the receiver substrate may be carried out beforehand in order to promote good molecular adhesion. These treatments may include, in particular, cleaning, deposition of a bonding layer such as silicon oxide (SiO2), plasma activation before bonding, polishing and annealing, preferably at low temperatures (i.e. typically below 300° C.).

[0076] Advantageously, the support substrate 1 and the receiver substrate 3 have substantially the same diameter, for example around 300 mm.

[0077] Next, referring to FIG. 6, the tile is removed along the weakened areas 11, thereby transferring the portions P'1, P'2, P'3 defined by said weakened areas to a receiver substrate.

[0078] The tiles disposed on the support substrate typically have a thickness between 20 μm and 1000 μm, preferably between 100 μm and 700 μm. The transferred portion of each tile generally has a thickness between 30 nm and 1.5 μm.

[0079] According to an alternative to the Smart Cut™ process mentioned above, the tile portions may be obtained by thinning each tile of the pseudo donor substrate by grinding and / or etching after bonding of the pseudo donor substrate to the receiver substrate, although one advantage of the Smart Cut™ process is that it minimizes material loss, and the pseudo donor substrate can be optionally reused and used to transfer tile portions again to the same or another receiver substrate.

[0080] Optionally, after transferring the tile portions to a receiver substrate, chemical mechanical polishing of the surfaces of the tile portions can be performed.

[0081] FIG. 7 shows the formation, for example by photolithography, of protective films M11, M12, M13, M14 partially covering each tile portion, and a mask with openings extending between portions of the protective films.

[0082] The protective film is configured to define a pattern that corresponds to the geometry and location of each tip in each respective target area.

[0083] The openings typically correspond to the surface of the receiver substrate that is to be disposed between the target areas. Thus, in the illustrated example, the openings are cross-shaped and define four rectangular portions M11-M14 of the protection film in each tile portion.

[0084] According to one embodiment, the protective film does not extend to the edge of the tile portion that is placed in the target area, which allows a subsequent etching step to remove peripheral areas of the tile portion, for example to change the size of said portion, although in terms of minimizing material loss, the tiles are preferably sized to minimize the peripheral areas that are removed.

[0085] The film may be made of any suitable resist. Such photoresists, in particular in the field of microelectronics, sold for example by the companies Shipley or AZ Electronic Materials, are supplied in a highly viscous state and spread on the substrate with the aid of a spinner (known as the "spin-coating" process) and then annealed. A UV exposure step makes it possible to retain or, on the contrary, remove the exposed areas after development. According to the variant known as "dry film photoresist", these resists may be applied by lamination of thick films, typically with a thickness between 15 and 50 μm, supplied in the form of rolls.

[0086] Referring to Fig. 8, an etching solution is applied to the structure in Fig. 7. The composition of the etching solution is chosen depending on the material of the tile. For example, if the tile is made of InP, wet etching in a bath of hydrochloric acid (HCl) and phosphoric acid (H3PO4) can be used. Plasma etching based on halogenated gases (for example based on chlorine or based on methane / dihydrogen (CH4 / H2) mixtures) can also be used.

[0087] Advantageously, the etching solution does not or barely attacks the material of the receiver substrate 3 .

[0088] Alternatively, etching by ion beam sputtering, for example argon ion beam sputtering, may be used, in which case the protective film is advantageously made of metal.

[0089] At the end of the etching, the parts of the tile not covered by the protective film have been removed over all or part of the thickness of the tile in order to separate the chips.

[0090] 9, the protective film is removed to release the surface of the chip, so that the structure is ready for subsequent manufacturing steps, such as deposition or epitaxy of one or more additional layers on the chip, formation of electronic components in or on the chip, etc.

[0091] It should be noted that no chemical mechanical polishing is performed after the formation of the chips, so as not to cause inhomogeneities within the chips. In other words, any chemical mechanical polishing step is performed either on the pseudo donor substrate or on the receiver substrate after the transfer of the tile portions but before the removal of material that results in the fabrication of the chips. Thus, chemical mechanical polishing is performed on tiles or tile portions that have relatively large dimensions, in any case larger than those required to fabricate the targeted chips. More specifically, each tile has a dimension that is larger than a multiple of the dimension of the targeted chip in the fabrication process. For example, each tile may have a dimension that is two or four times larger than the targeted dimension.

[0092] Several geometries may be obtained depending on the intended use of the final structure and the location of the target area.

[0093] In a particular embodiment, each tile at least partially covers two different target areas of a receiver substrate, and chips are formed from the tiles in each respective target area.

[0094] For example, as shown in Fig. 10A, each tile and transferred tile portion P'1 may be arranged to cover a portion of two adjacent target areas as well as the surface of the receiver substrate between said target areas. Material removal may be performed to remove material from each tile portion facing the surface separating the target areas and, if necessary, material from each tile portion facing each target area, to fit the desired geometry for each chip p11, p12 (see Fig. 10B).

[0095] According to another example shown in Fig. 11A, each tile and transferred tile portion P'1, P'2, P'n may be in the form of an elongated strip partially covering multiple aligned target areas, whereby one or more aligned chips p11, p12, p1n can be formed in each of the target areas belonging to the same row or column (see Fig. 11B).

[0096] In another embodiment, as shown in Figure 12A, which is an enlarged view of Figure 5, each tile and transferred tile portion P'1 may be arranged to cover each corner of four different target areas of a receiver substrate arranged in a square, and chips p11, p12, p13, and p14 are formed from the tiles at each corner of each target area (see Figure 12B).

[0097] Of course, these various configurations may be combined: for example, it is possible to transfer tile portions with different (e.g. pairwise perpendicular) orientations depending on the target area to be covered.

[0098] Thus, the process provides a large degree of latitude for the formation of the chips depending on the components to be formed from them.

[0099] Application Examples The invention presents various cases of particularly advantageous application, in particular in the field of microelectronics.

[0100] The process may allow a less dense arrangement of chips on a 300 mm diameter receiver substrate, which may be a silicon substrate or a silicon-on-insulator (SOI) type substrate.

[0101] In photonic applications, the active layer of the receiver substrate may comprise photonic circuits with passive or active elements, such as one or more waveguides, one or more multiplexers, one or more microresonators, etc. The chip transferred to this layer may be made of InP, a material more suitable than silicon for epitaxial growth of stacks of III-IV materials to form lasers.

[0102] In radio frequency (RF) applications, the active layer of the receiver substrate may comprise components operating at relatively low frequencies, while the chip, advantageously made from InP or GaN, may comprise components operating at higher frequencies.

[0103] In micro-LED applications, the size of the GaN chip is advantageously less than 50 μm.

Claims

1. A process for manufacturing a structure comprising at least two chips (p11, p12, p13, p14) on a receiver substrate (3), comprising: forming a pseudo donor substrate (10) by placing at least one tile (P1, P2, P3) of at least one donor substrate (2) on a support substrate (1); bonding the pseudo donor substrate (10) to a receiver substrate (3) via the tiles such that each tile at least partially covers at least two different target areas (Z1, Z2, Zn) of the receiver substrate (3); transferring portions (P'1, P'2, P'3) of said tiles (P1, P2, P3) onto said receiver substrate (3); - at least one step of chemical mechanical polishing of the tiles (P1, P2, P3) of the pseudo donor substrate and / or the tile portions transferred to the receiver substrate; removing material from the tile portions (P'1, P'2, P'3) after at least one step of chemical mechanical polishing so as to divide each tile portion into at least two chips (p11, p12, p13, p14) each arranged in a respective target area (Z1, Z2, Zn); The process includes:

2. 2. The process according to claim 1, wherein after the etching step the coverage of the chips (p11, p12, p13, p14) on the receiver substrate (3), i.e. the ratio of the total surface area of ​​the chips to the total surface area of ​​the receiver substrate, is less than 50%, preferably less than 30%.

3. 2. The process according to claim 1, wherein the coverage of the tiles (P1, P2, P3) on the pseudo donor substrate (10), i.e. the ratio of the total surface area of ​​the tiles to the total surface area of ​​the support substrate, is greater than 50%, preferably greater than 75%.

4. 2. The process according to claim 1, wherein each tile (P1, P2, P3) has a side with a length of 5 mm or more, preferably 8 mm or more, more preferably 10 mm or more.

5. 2. The process according to claim 1, wherein each chip (p11, p12, p13, p14) has a side with a length of 5 mm or less, preferably 3 mm or less, more preferably 1 mm or less.

6. 2. The process according to claim 1, wherein the distance between two adjacent tiles (P1, P2, P3) is less than or equal to 3 mm, preferably less than or equal to 1 mm.

7. 2. The process according to claim 1, wherein the distance between two adjacent chips (p11, p12, p13, p14) is 3 mm or more, preferably 5 mm or more.

8. The process of claim 1 , wherein each tile at least partially covers two different target areas of the receiver substrate, and chips are formed from the tiles in each respective target area.

9. 2. The process of claim 1, wherein each tile covers at least a corner of each of four different target areas of the receiver substrate arranged in a square or rectangle, and a chip is formed from the tile at each corner of each of the target areas.

10. The process of claim 1 , wherein each tile is in the form of a strip at least partially covering at least three aligned target areas of the receiver substrate, and a chip is formed from the tile in each respective target area.

11. The process of claim 1 , wherein the support substrate (1) and the receiver substrate (3) have substantially the same diameter, which is larger than the diameter of the donor substrate (2).

12. The process of claim 1 , wherein the pseudo donor substrate (10) is bonded to the receiver substrate (3) by molecular adhesion.

13. 2. The process of claim 1, wherein the transfer of each tile portion (P'1, P'2, P'3) comprises, in sequence, forming weakened regions (11) by implanting atomic species into each tile (P1, P2, P3) of the pseudo donor substrate (10) to define the tile portion (P'1, P'2, P'3) to be transferred, bonding the pseudo donor substrate (10) to the receiver substrate (3) via the tiles (P1, P2, P3), and detaching each tile along the weakened regions (11).

14. 2. The process of claim 1, wherein the transfer of each tile portion (P'1, P'2, P'3) comprises thinning each tile (P1, P2, P3) of the pseudo donor substrate by grinding and / or etching.

15. 2. The process according to claim 1, wherein each tile (P1, P2, P3) has a thickness between 20 μm and 1000 μm, preferably between 100 μm and 700 μm, and wherein the transferred portion of each tile has a thickness between 30 nm and 1.5 μm.

16. Each tile (P1, P2, P3) III-V materials, in particular indium nitride (InN), gallium nitride (GaN), aluminum nitride (AlN), indium arsenide (InAs), gallium arsenide (GaAs), aluminum arsenide (AlAs), indium phosphide (InP), gallium phosphide (GaP) or aluminum phosphide (AlP), or semiconductor materials such as IV or IV-IV materials, in particular germanium or silicon carbide (SiC), Lithium tantalate (LiTaO ３ ), lithium niobate (LiNbO ３ ), potassium sodium niobate (K ｘ Na １－ｘ NbO ３ or KNN), barium titanate (BaTiO ３ ), quartz, lead zirconate titanate (PZT), lead magnesium niobate and lead titanate (PMN-PT), zinc oxide (ZnO), aluminum nitride (AlN) or aluminum scandium nitride (AlScN), and / or Electrically insulating materials such as diamond, strontium titanate, yttria-stabilized zirconia, or sapphire The process of claim 1 , comprising:

17. 2. The process of claim 1, including the step of epitaxy forming at least one epitaxial layer on each tile portion, and wherein said removal of material to chip each tile portion is performed after said epitaxy step.

18. said removing material forming a mask having a protective film partially covering each tile portion in a pattern defining the chips in each tile portion, and at least one opening defining a space to be formed between two chips; etching each tile portion through each opening in the mask to form the spaces separating the chips from one another; The process according to any one of claims 1 to 17, comprising:

19. 20. The process of claim 18, wherein the etching is performed with an etching solution and the mask is formed from photoresist.

20. 20. The process of claim 18, wherein the etching is performed with an ion beam and the mask is formed from a metal.

21. 18. A process according to any preceding claim, wherein the removal of material is carried out selectively by a focused ion beam, the beam being controlled to sweep only over the area of ​​the tile portion that is to be removed.

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