Trench gate power MOSFET and manufacturing method thereof

Abstract

The present application discloses a trench-gate power MOSFET including a substrate of a wide bandgap semiconductor having a first conductivity type, an epitaxial layer grown on the substrate and having the first conductivity type, a body region formed in the epitaxial layer and having a second conductivity type, a trench etched into the body region and having a length parallel to a projection on the wafer surface of one selected crystal direction of all crystal directions of the wafer, a second conductivity type column formed by implanting first ions into a bottom region of the trench along a crystal direction of the wide bandgap semiconductor material, the bottom region of the trench being located below the trench and in contact with the bottom of the trench, and a vertical depth of the column being at least 50% or more of the thickness of the epitaxial layer located in the bottom region of the trench, and a trench gate formed by filling the trench with a filler. The present invention is advantageous in that it can improve the current capability and reliability of a trench-type MOSFET.

Description

[Technical field]

[0001] Technical Field FIELD OF THE DISCLOSURE The present application relates to the field of semiconductors, and in particular to a trench-gate power MOSFET and a method for fabricating the same.

[0002] Background technology Semiconductor devices such as power MOSFETs have been widely used in the fields of automotive electronics, switching power supplies, industrial control, and so on. In order to constantly improve power conversion efficiency and power density, it is extremely important to design efficient power switching devices such as power MOSFETs. The most important performance parameter of a power MOSFET is the specific on-resistance Rsp, and the magnitude of the drain-source on-resistance is directly proportional to the power consumed by the power MOSFET device. For a device with the same breakdown voltage and the same on-resistance, the smaller the specific on-resistance, the smaller the chip area, and the smaller the parasitic capacitance of the power MOSFET, thereby reducing the switching loss in the power conversion process of the power MOSFET. Power devices with trench gate and superjunction structure have lower on-resistance, which means lower switching loss and faster switching speed, and have become one of the most widely used power switching devices at present. However, at present, power devices with trench gate and superjunction structure have high manufacturing costs and very difficult process control. Summary of the Invention

[0003] Summary of the Invention In order to solve the above problems in the prior art, the present invention provides a trench-gate power MOSFET and a manufacturing method thereof.

[0004] According to a first aspect, the present invention provides a trench-gate power MOSFET, the trench-gate power MOSFET being formed in a wafer, a substrate of wide band gap semiconductor material having a first conductivity type; an epitaxial layer grown on the substrate and having the first conductivity type; a body region having a second conductivity type formed in the epitaxial layer; a trench etched into the body region, the length of the trench being parallel to a projection on the wafer surface of a crystal direction in which a channel effect is most pronounced among all crystal directions of the wafer; a second conductivity type column formed by implanting first ions into a bottom region of the trench that is located below the trench and in contact with the bottom of the trench along a crystal direction in which a channel effect of the wide band gap semiconductor material is most prominent, the second conductivity type column having a vertical depth of 50% or more of a thickness of the epitaxial layer located in the bottom region of the trench; and a trench gate formed by filling the trench with a filling material.

[0005] In one possible embodiment of the first aspect, the power trench gate power MOSFET further includes a connection body having the second conductivity type between the second conductivity type column and the body region, one end of the connection body being electrically connected to the body region and the other end of the connection body being electrically connected to the second conductivity type column.

[0006] In one possible embodiment of the first aspect, the trench-gate power MOSFET further includes a drain located below the substrate, a gate located on a central axis of the body region, and sources located on either side of the gate.

[0007] In one possible embodiment of the first aspect, in the power trench-gate power MOSFET, the epitaxial layer is a single epitaxial layer.

[0008] In one possible embodiment of the first aspect, in the power trench-gated power MOSFET, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is located below the second epitaxial layer, the thickness of the first epitaxial layer is smaller than the thickness of the second epitaxial layer, the doping concentration of the first epitaxial layer is smaller than the doping concentration of the second epitaxial layer, the bottom of the trench and the second conductivity type columns are located in the second epitaxial layer, and a vertical depth of the second conductivity type columns is greater than or equal to 50% of a thickness of the second epitaxial layer located in the bottom region of the trench.

[0009] In one possible embodiment of the first aspect, in the trench-gate power MOSFET, the wide bandgap semiconductor material is silicon carbide.

[0010] In one possible embodiment of the first aspect, in the trench-gate power MOSFET, the silicon carbide includes 4H-SIC or 6H-SIC.

[0011] In one possible embodiment of the first aspect, in the trench-gate power MOSFET, a ratio of the depth of the trench to the width of the trench is in the range of 1:1 to 5:1.

[0012] In one possible embodiment of the first aspect, in the trench-gate power MOSFET, an oxide is formed on an inner surface of the trench.

[0013] In one possible embodiment of the first aspect, in the trench-gate power MOSFET, the filling includes polycrystalline silicon.

[0014] In one possible embodiment of the first aspect, in the trench-gate power MOSFET, the first ions include aluminum ions, and the first ions are implanted in at least two portions, i.e., with a first dose, a first energy, and a second dose, a second energy, into a bottom region of the trench along a C-axis direction of the silicon carbide crystalline body.

[0015] According to a second aspect, the present invention provides a method for producing a trench-gate power MOSFET in a wafer, the method comprising the steps of: growing an epitaxial layer having a first conductivity type on a wide bandgap semiconductor substrate; forming a body region having a second conductivity type in the epitaxial layer; forming a trench by etching in the body region, the length of the trench being parallel to a projection on the wafer surface of a crystal direction in which a channel effect is most pronounced among all crystal directions of the wafer; implanting first ions into a bottom region of the trench along a crystal direction in which a channel effect of a wide band gap semiconductor material is most pronounced, thereby forming a second conductivity type column, the bottom region of the trench being located below and in contact with a bottom of the trench, and the vertical depth of the second conductivity type column being 50% or more of a thickness of the epitaxial layer located at the bottom region of the trench; and filling the trench with a filler.

[0016] In one possible embodiment of the second aspect, in the manufacturing method, forming a trench by etching in the body region further includes forming a connector having the second conductivity type by implanting first ions into the body region and the epitaxial layer, one end of the connector being electrically connected to the body region and the other end of the connector being electrically connected to the second conductivity type column, and a depth of the connector being equal to or greater than a depth of the trench.

[0017] In one possible embodiment of the second aspect, in the manufacturing method, the wide band gap semiconductor material is silicon carbide, and the crystal direction in which the channel effect of the wide band gap semiconductor material is most prominent is a C-axis direction of a silicon carbide crystal.

[0018] In one possible embodiment of the second aspect, in the manufacturing method, the silicon carbide includes 4H—SIC or 6H—SIC.

[0019] In one possible embodiment of the second aspect, the step of implanting first ions into a bottom region of the trench along a crystal direction in which a channel effect of the wide band gap semiconductor material is most pronounced comprises: The first ions are implanted at least twice, i.e., with a first dose, a first energy, and a second dose, a second energy, into the bottom region of the trench along the C-axis direction of the silicon carbide crystal body.

[0020] In one possible embodiment of the second aspect, in the manufacturing method, the first dose is 5E13 to 5E14 atoms / cm 2 the first energy is 500 kev to 1500 kev, and the second dose is 5E12 to 5E13 atoms / cm 2 and the second energy is between 50 kev and 300 kev.

[0021] In one possible embodiment of the second aspect, the manufacturing method further includes a step of growing the first epitaxial layer having the first conductivity type on the wide band gap semiconductor substrate, and growing the second epitaxial layer having the first conductivity type on the first epitaxial layer, the epitaxial layer including a first epitaxial layer and a second epitaxial layer.

[0022] In one possible embodiment of the second aspect, the method is characterized in that a thickness of the first epitaxial layer is less than a thickness of the second epitaxial layer, and a doping concentration of the first epitaxial layer is less than a doping concentration of the second epitaxial layer.

[0023] In one possible embodiment of the second aspect, the manufacturing method further comprises the step of: a bottom of the trench and the second conductivity type column are located within the second epitaxial layer, and a vertical depth of the second conductivity type column is greater than or equal to 50% of a thickness of the second epitaxial layer located in the bottom region of the trench.

[0024] In one possible embodiment of the second aspect, in the manufacturing method, the ratio of the depth of the trench to the width of the trench is in the range of 1:1 to 5:1.

[0025] In one possible embodiment of the second aspect, in the manufacturing method, the step of filling the trench with a filling material includes: The method includes forming an oxide on an interior surface of the trench and then filling the trench with a filler.

[0026] In one possible embodiment of the second aspect, in the method, the filling comprises polycrystalline silicon.

[0027] In one possible embodiment of the second aspect, in the method, the first ions include aluminum ions.

[0028] Compared with the conventional trench-type superjunction structure MOSFET, the trench-gate power MOSFET of the present invention can not only protect the bottom of the trench by introducing a second conductive type column, for example, a deep P column, under the trench, but also play a role of charge balancing as a P column in the superjunction. At the same time, the specific on-resistance Rsp is reduced, thereby reducing the chip area and the parasitic capacitance of the power MOSFET, as well as the switching loss in the power conversion process of the power MOSFET.

[0029] According to the manufacturing method of the present invention, deep P columns are formed by implanting high energy ions. Unlike the conventional technology in which ions are implanted along the normal direction of the wafer, the manufacturing method of the present invention implants ions along a specific crystal direction of the semiconductor material (in the case of silicon carbide wafers, implantation along its C-axis), and due to the channel effect of the crystal, the range of implantation energy is from several tens of Kev to more than a thousand Kev for the same implantation depth, which can significantly reduce the implantation energy compared to the conventional technology, thereby significantly reducing the manufacturing cost and making the manufacturing process easier to control.

[0030] In addition, in the present invention, the length direction of the trench is set parallel to the projection of the specific crystal direction on the wafer surface, so that a symmetrical P column structure can be formed. As known to those skilled in the art, the structure of the superjunction structure requires a symmetrical P column structure, and an asymmetrical structure is likely to cause uneven distribution of the electric field, thereby causing partial destruction of the MOSFET device and reducing the voltage resistance of the device. [Brief description of the drawings]

[0031] [Figure 1] FIG. 1 is a diagram showing the structure of a planar power MOSFET produced by a conventional process. [Diagram 2] FIG. 2 is a diagram showing the structure of a trench-type power MOSFET produced by a conventional process. [Diagram 3]FIG. 3 is a diagram showing the structure of a type of trench-type power MOSFET manufactured by Infineon. [Figure 4] FIG. 4 is a diagram showing the structure of a type of trench-type power MOSFET manufactured by ROHM. [Diagram 5] FIG. 5 is a diagram showing the angular relationship between a general silicon carbide crystal in a silicon carbide wafer and the surface of the silicon carbide wafer. [Figure 6] FIG. 6 is a diagram showing the structure of a trench-type power MOSFET in which non-axisymmetric P columns are obtained by conventional ion implantation along the C-axis when a silicon carbide wafer is cut in the direction shown in FIG. [Figure 7] FIG. 7 is a diagram illustrating a cross-section of a trench-gate power MOSFET structure according to some embodiments of the present application. [Figure 8a] FIG. 8a is a perspective view of the schematic diagram shown in FIG. 7 viewed from a 45° angle in accordance with some embodiments of the present application. [Figure 8b] FIG. 8b is a diagram showing a mask pattern in the manufacturing process of the P column connector in FIG. 8a. [Figure 8c] FIG. 8c illustrates another P column connector according to some embodiments of the present disclosure. [Figure 9a] FIG. 9a illustrates a trench orientation of a trench-gate power MOSFET according to some embodiments of the present application. [Figure 9b] FIG. 9b shows the trench installation direction according to the prior art. [Figure 10] FIG. 10 is a diagram illustrating the relationship between the C-axis of a silicon carbide crystal in a trench-gate power MOSFET structure and a wafer surface coordinate system according to some embodiments of the present application. [Figure 11] FIG. 11 shows a flow chart of a method for manufacturing a trench-gate power MOSFET according to some embodiments of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Exemplary embodiments of the present application include, but are not limited to, trench-gate power MOSFETs and methods of fabricating the same.

[0033] Exemplary embodiments are described in detail herein, examples of which are illustrated in the figures. Where the following description refers to the drawings, the same numerals in different drawings represent the same or similar elements unless otherwise stated. The embodiments described in the following exemplary embodiments are by no means representative of all embodiments consistent with the present application. Rather, they are merely illustrative of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0034] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural, unless the context clearly indicates otherwise. The term "and / or" as used herein should also be understood to refer to the inclusion of any or all possible combinations of one or more of the associated listed items. Similar terms such as "comprise" and "including" refer to the inclusion of the elements or things listed after "comprise" or "including" and equivalents thereof, but do not in any way exclude other elements or things. Similar terms such as "connected" and "connected" are in no way limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0035] In the present application, terms such as first, second, third, etc. may be used to describe various types of information, but it is understood that such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, first information may be referred to as second information, and similarly, second information may be referred to as first information, without departing from the scope of the present application. Depending on the context, for example, the phrase "if..." used herein may be interpreted as "upon..." or "when..." or "depending on the decision."

[0036] Hereinafter, the embodiments of the present application will be described in more detail with reference to the drawings.

[0037] Fig. 1 is a diagram (cross-sectional view) showing the structure of a MOSFET with a planar structure produced by a conventional process. The MOSFET shown in Fig. 1 includes a highly doped N-type substrate 101, a lightly doped N-type epitaxial layer 102 formed on the substrate 101, a P-type body region 103 formed on the epitaxial layer 102, a source 104 located in the P-type body region 103, and a polycrystalline silicon gate 105 located on the P-type body region 103. A planar MOSFET can be integrated on a plane because its gate, source, and drain are all located on the same plane, but there is a large limit to its size, and it is not possible to achieve sufficient performance.

[0038] FIG. 2 is a cross-sectional view showing the structure of a trench-type MOSFET produced by a conventional process. The MOSFET shown in FIG. 2 includes a highly doped N-type substrate 201, a lightly doped N-type epitaxial layer 202 formed on the substrate 201, a P-type body region 203 formed on the epitaxial layer 202, a source 204 located in the P-type body region 203, a trench 205 etched in the P-type body region 203, a gate oxide film 206 grown on the inner wall of the trench 205, and polycrystalline silicon 207 deposited on the gate oxide film 206. Compared with the planar structure MOSFET shown in FIG. 1, the trench-type MOSFET shown in FIG. 2 does not have a JFET region, and the vertical trench on the sidewall of the trench allows the trench pitch to be smaller. However, the critical electric field of a wide band gap semiconductor such as silicon carbide is ten times that of silicon, so the electric field strength at the bottom region of the trench is relatively large. Such high electric fields in the semiconductor can lead to high electric fields on the trench oxide, leading to device reliability problems.

[0039] Figure 3 is a cross-sectional view showing the structure of a kind of trench-type MOSFET made by Infineon. The MOSFET shown in Figure 3 includes a highly doped N-type substrate 301, a lightly doped N-type epitaxial layer 302 formed on the substrate 301, a P-type body region 303 formed on the epitaxial layer 302, a trench 304 etched in the P-type body region 303, a gate oxide film 306 grown on the inner wall of the trench 304, and polycrystalline silicon 305 deposited on the gate oxide film 306. Compared with the trench-type MOSFET shown in Figure 2, the trench-type MOSFET shown in Figure 3 further includes a first P-type region 307 and a second P-type region 308 with high doping concentrations below the trench 304, so as to reduce the high electric field at the bottom of the trench 304, and the vertical depth of the P-type region is greater than the vertical depth of the P-type body region.

[0040] Fig. 4 is a diagram (cross-sectional view) showing the structure of a kind of trench-type MOSFET made by ROHM Co. The MOSFET shown in Fig. 4 includes a highly doped N-type substrate 401, a lightly doped N-type epitaxial layer 402 formed on the substrate 401, a P-type body region 403 formed on the epitaxial layer 402, a trench 406 etched in the P-type body region 403, a gate oxide film 407 grown on the inner wall of the trench 406, and polycrystalline silicon 408 deposited on the gate oxide film 407. 2, the trench-type MOSFET shown in FIG 4 further includes a first P-type region 404 and a second P-type region 405 with high doping concentration below the trench 406, so as to reduce the high electric field at the bottom of the trench 406, the first P-type region 404 and the second P-type region 405 are located on both sides of the trench 406, respectively, and the vertical depths of the first P-type region 404 and the second P-type region 405 are smaller than the vertical depth of the P-type body region in which they are located. However, the trench-type MOSFET structure shown in FIG 3 and FIG 4 has high manufacturing costs and high process control difficulties.

[0041] For trench MOSFET devices, the source-drain on-resistance Rds (on)It consists of several parts: Rds (on) =R N+ +R CH + R D +R sub

[0042] Here, R N+ is the resistance of the source region and N+ diffusion region. Since the doping concentration of the N+ region is high, the resistance is very small, so the resistance of this part is the source drain on resistance Rds (on) may be neglected with respect to other resistances constituting the

[0043] R CH is the trench resistance, i.e., the resistance of the trench under the gate, and R CH is the source-drain on-resistance Rds (on) The aspect ratio of the trench, the gate oxide thickness, and the gate voltage are all important parameters that affect R CH can affect changes in

[0044] R D is the drift region resistance, i.e., the resistance of the epitaxial layer. The epitaxial layer is a high-resistance layer grown on the substrate to receive high voltage. Under the action of an external voltage, carriers drift in the drift region. For high-voltage MOSFET devices, the drift resistance is the source-drain on-resistance Rds (on) Therefore, the drift region resistance R D Reducing the source-drain on-resistance Rds (on) can be reduced.

[0045] R sub is the wafer substrate resistance, and this resistance can be reduced by processing such as thinning the backside.

[0046] At the same breakdown voltage, characteristic on-resistance Rsp = source-drain on-resistance Rds (on) *The effective area of ​​the chip allows for the same source-drain on-resistance Rds(on) If so, the smaller the specific on-resistance Rsp, the smaller the effective chip area will be, and further the parasitic capacitance of the power MOSFET will be reduced, thereby reducing the switching loss in the power conversion process of the power MOSFET.

[0047] FIG. 5 is a diagram showing the angular relationship between a general silicon carbide crystal in a silicon carbide wafer and the surface of the silicon carbide wafer, that is, the angular relationship between a microscopic crystal and a macroscopic wafer. The drawing shows the X direction of the wafer surface and the Y direction perpendicular to the wafer surface (i.e., the normal direction), as well as two mutually perpendicular crystal directions of a silicon carbide (4H-SIC) crystal, the

[0001] direction and the [11-20] direction (note that, for the notation of negative components of indices according to the crystallographic notation, a minus sign is used before the number instead of an overline above the number that cannot be used in the application procedure. The same applies below.) As is well known, a crystal is a structure in which a large number of microscopic material units (atoms, ions, molecules, etc.) are properly arranged according to a certain rule from a microscopic point of view, so that a crystal usually has a specific shape, and the crystal axis, crystal direction, and crystal plane of the crystal can be defined by the shape. For example, silicon carbide (4H-SIC) crystals define at least two crystal directions, as shown in the figure: the C-axis direction (i.e., the

[0001] direction) and the [11-20] direction. In the semiconductor industry, in order to make the growth of the crystals more stable in the production process, the crystal direction shown in FIG. 5 is usually selected when cutting the wafer, that is, there is an included angle between the axis direction (C-axis) of the crystal and the normal direction (Y direction) of the wafer surface, and the included angle is usually 4°, and the projection of one crystal direction of the crystal, i.e., the [11-20] direction on the wafer surface overlaps with the X direction of the wafer. However, in production practice, for convenience, the included angle may be ignored and the crystal direction of the crystal and the direction of the wafer surface may be directly indicated by a mirror surface.

[0048] FIG. 6 is a diagram (cross-sectional view) showing the structure of a trench-type power MOSFET in which a non-axisymmetric P column is obtained by performing ion implantation along the conventional C-axis when cutting a silicon carbide wafer in the direction shown in FIG. 5. The trench-type power MOSFET shown in the figure includes a substrate 01, an epitaxial layer 02 formed on the substrate 01 by a process such as epitaxial growth, a P-type body region 04 formed in the epitaxial layer 02, and a trench 00 penetrating the P-type body region 04 and deeply penetrating the epitaxial layer 02. A P column is located below the trench 00 and is buried in the epitaxial layer 02, and is usually formed by ion implantation. In order to utilize the channel effect, the crystal direction in which the channel effect is most prominent is usually set as the direction of ion implantation. In a silicon carbide (4H-SIC) crystal, the direction of the C-axis is the crystal direction in which the channel effect is most prominent. As can be seen from the description of FIG. 5, the C-axis of silicon carbide is never perpendicular to the surface of the wafer. That is, in the structure shown in FIG. 6, the P columns 11 formed by ion implantation are not perpendicular to the wafer surface. That is, in the cross-sectional view of one unit cell as shown in FIG. 6, the P columns 11 cannot be symmetrical about the central axis of the unit cell. As a common knowledge in this field, a person skilled in the art should know that the performance of a MOSFET device is optimal when the shape of the P columns is an axially symmetrical pattern in the cross-section shown in FIG. 6. However, the cross-section of the P columns 11 obtained by ion implantation according to the prior art is a parallelogram as shown in FIG. 6, and is not symmetrical about the central axis of the unit cell. This tends to lower the breakdown voltage of the MOSFET device.

[0049] In order to solve the above deficiencies, the present invention puts forward a new trench-gate power MOSFET structure. The following description will be given with reference to FIG. 7 and FIGS. 8a and 8b. FIG. 7 shows a cross-sectional view of a trench-gate power MOSFET structure according to some embodiments of the present application. FIG. 8a shows a perspective view of the MOSFET shown in FIG. 7 viewed from 45° above according to some embodiments of the present application. FIG. 8b shows a mask pattern in the manufacturing process of the P column connector 505 in FIG. 8a.

[0050] The trench gate power MOSFET provided by the present invention includes a power MOSFET having a trench gate and a super junction (or quasi-super junction) structure. The structure and the formation process of the trench gate power MOSFET of the present application will be specifically described below using a case where the wide band gap semiconductor substrate is a silicon carbide material, the first conductivity type is N type, the second conductivity type is P type, the second conductivity type column is a P column, and the first ion is an aluminum ion as an example.

[0051] As shown in FIG. 7, the substrate 501 is a substrate of a wide band gap semiconductor having a first conductivity type. For example, the substrate 501 may be an N-type silicon carbide substrate with a high doping concentration. An N-type first epitaxial layer 502 and a second epitaxial layer 503 with a low doping concentration are grown in this order above the substrate 501 by an epitaxial growth process. The first epitaxial layer 502 is located below the second epitaxial layer 503, the thickness of the first epitaxial layer 502 is smaller than the thickness of the second epitaxial layer 503, and the doping concentration of the first epitaxial layer 502 is smaller than the doping concentration of the second epitaxial layer 503. In one embodiment, the N-type doping concentration of the first epitaxial layer 502 is 1E14 atoms / cm 2 (atoms / cm 2 )~2E16atoms / cm 2 The thickness of the first epitaxial layer 502 is between 0.2 μm and 40 μm. The N-type doping concentration of the second epitaxial layer 503 is between 2E15 atoms / cm 2 ~2E17atoms / cm 2 and the thickness of the second epitaxial layer 503 is between 2 μm and 200 μm. It is understood that the thickness and doping concentration of the first epitaxial layer 502 and the thickness and doping concentration of the second epitaxial layer 503 can be determined by the required withstand voltage rating of the device. In this embodiment, a device with a quasi-superjunction structure is formed using epitaxial layers with two different doping concentrations, and the avalanche withstand capability can be improved.

[0052] It is understood that in the embodiment shown in Figure 7, the wide band gap semiconductor substrate is silicon carbide material for illustrative purposes and is in no way limiting. In other embodiments of the present application, the wide band gap semiconductor substrate may be other wide band gap semiconductor materials, such as gallium nitride, aluminum nitride, etc. With respect to the present invention, the difference in the selection of different substrate materials is the selection of different trench placement directions and ion implantation directions based on the different crystal orientations of different wafers (bodies).

[0053] It is understood that the doped impurities in the N-type doped first epitaxial layer 502 and second epitaxial layer 503 may be nitrogen or phosphorus, or may be other N-type impurities.

[0054] The P body region 504 is located above the second epitaxial layer 503 and is formed by implanting ions of a different conductivity type than the substrate 501, the first epitaxial layer 502, and the second epitaxial layer 503, such as P-type ions, into the upper end of the second epitaxial layer 503.

[0055] The P column connector 505 is formed in the P body region 504 (P body region) and the second epitaxial layer 503 by an ion implantation process. Specifically, as shown in FIG. 8b, a mask pattern 5051 is first formed on the upper surface of the P body region 504 by a photolithography mask process, which presents the P column connector 505. The mask pattern is symmetrical about the central axis of the upper surface of the P body region 504 (see FIG. 8b). Then, a column-shaped P column connector 505 is formed by injecting P-type impurities into the region toward the P body region 504 and the second epitaxial layer 503 by an ion implantation process. The P column connector 505 realizes the connection from the P column 511 to the P body region 504, thereby realizing the electrical connection between the P column 511 and the P body region 504 generated in a subsequent step, and is not electrically floating in any operating state. That is, the depth of the P column connector 505 needs to extend deep into the second epitaxial layer 503 from the upper surface of the P body region 504. Only after the processing of the trench gate power MOSFET is completed can the P column 511 embedded in the second epitaxial layer 503 be electrically connected to the P body region 504 in the horizontal direction (referring to the horizontal direction in FIGS. 7, 8a, and 8b) via the P column connector 505 in the vertical direction (referring to the vertical direction in FIGS. 7, 8a, and 8b).

[0056] By continuing the implantation of ions above the P body region 504 (including the P column connector 505), an ohmic contact resistance portion is formed. For example, by implanting N-type highly doped impurities into the middle portion of the P body region 504, i.e., the portion including the P column connector 505, to obtain an N-type highly doped region 506, i.e., the portion indicated by S in FIG. 7, it is easy to form a relatively low source ohmic contact resistance. Also, by implanting P-type highly doped impurities into both ends of the P body region 504, i.e., the positions connected to both ends of the N-type highly doped region 506, it is easy to form a first P-type highly doped region 507 and a second P-type highly doped region 508, it is easy to form an ohmic contact resistance in the P body (i.e., the P body region 504) that is relatively low.

[0057] As shown in FIG. 8b, a hard mask layer pattern 5002 for processing a trench 500 is formed on both sides of the central axis of the surface of the P body region 504, and the mask pattern is not continuous along the central axis direction, but is complementary to the mask pattern 5051 of the P column connector 505. After etching is subsequently performed based on the hard mask pattern, the P body region 504 under the hard mask layer pattern 5002 of the trench 500 and a part of the second epitaxial layer 503 are etched to form a trench 500, and the P column connector 505 under the mask pattern 5051 of the P column connector 505 is left as a conductor electrically connecting between the P column 511 and the P body region 504. In some embodiments, the component of the hard mask layer may be silicon dioxide or nickel. It is understood that in other embodiments, the component of the hard mask layer may be other elements or compounds.

[0058] Specifically, as shown in FIG. 8a, a bottom 5001 of trench 500 is located within second epitaxial layer 503. A depth-to-width ratio of trench 500 may range from 1:1 to 5:1, for example, trench 500 may have a width of 0.4 μm and a depth of 1.2 μm. In some embodiments, trench 500 may have a depth-to-width ratio of 3:1. It is understood that the width and depth of trench 500 in the illustrated embodiments are exemplary and not limiting, and that in other embodiments of the present application, trench 500 may have other width and depth values.

[0059] The issue of the orientation of the trench 500 is further explained below with reference to Figures 9a and 9b.

[0060] The first pattern 72 and the second pattern 72' in Figures 9a and 9b are for explaining the positional relationship between the trench and the wafer 71. In the first pattern 72 and the second pattern 72', the shaded parts are for showing the relationship between the trench 500, particularly the length direction of the trench 500, and the crystal plane of the wafer 71. The surface of the wafer 71 is shown with a plurality of crystal directions (indicated by square brackets) and crystal planes (indicated by round brackets), but as can be seen from the above description, the axial direction of the silicon carbide wafer surface and the silicon carbide crystal body are not perpendicular to each other, and each direction of the wafer surface shown in the figure is actually a projection of each crystal direction of the silicon carbide crystal body on the wafer surface, and in the industry, for convenience of explanation, it is common to directly refer to each direction of the wafer surface using each crystal direction of the crystal body.

[0061] Many trenches 500 can be etched in one wafer 71, and the direction of these trenches is the same. In the prior art, the trenches are etched in the direction shown in FIG. 9b, that is, the length direction of the trench is perpendicular to the crystal plane (1-100) as shown in the second pattern 72' in FIG. 9b by default. According to the analysis of the present researcher, such a trench direction is the fundamental cause of the parallelogram P column shown in FIG. 6.

[0062] Therefore, the present invention adjusts the industry default trench installation direction so that the length direction of the trench is parallel to the projection of one selected crystal direction of the wafer (body) on the wafer surface. Since the C-axis is the crystal direction in which the channel effect is prominent and also the crystal direction with the smallest deviation angle from the wafer normal in the current SiC wafer fabrication method, the trench installation direction of the present application ensures that the length direction of the trench is parallel to the plane formed by the C-axis and the wafer normal, thus making the implantation along the C-axis not cause a shielding effect due to the influence of the trench sidewall and the mask. Specifically, according to the embodiment of the present application, the selected crystal direction is the crystal direction in which the channel effect is most prominent among all the crystal directions of the wafer, i.e., the direction that can reach the deepest depth during ion implantation. For example, the projection direction of the C-axis on the wafer surface is selected as shown in the first pattern 72 in FIG. 9a. This modification is advantageous for forming symmetric P columns during subsequent ion implantation, such as forming symmetric P columns 511 when implanting ions along the C-axis (out of the page) in Figure 9a. For a specific analysis, see the discussion of Figure 10 below.

[0063] 8a, ions are implanted toward the bottom of trench 500 along the ion implantation direction shown in the figure, i.e., along the C-axis direction of silicon carbide, to obtain P columns 511 with a symmetrical cross-sectional pattern. In some embodiments, the first energy is 500 kev to 1500 kev, the first dose is 5E13 atoms / cm 2 ~5E14atoms / cm 2 , and the second energy is 50kev to 300kev, and the second dose is 5E12atoms / cm 2 ~5E13atoms / cm 2Then, aluminum ions (e.g., Al-27) are implanted into the bottom region of the trench 500 along the C-axis direction of silicon carbide (for 4H-SIC, the included angle between the ion implantation direction and the normal direction of the 4H-SIC wafer is 4°) to achieve uniform doping in silicon carbide, thereby forming P columns 511. Due to the trench effect, aluminum ions can be implanted to a sufficiently deep depth to obtain a sufficiently deep P column 511, which greatly reduces the number of ion implantations and the implantation energy, thereby reducing manufacturing costs. The depth of the P column 511 is more than 50% of the thickness of the second epitaxial layer 503 located under the bottom of the trench 500, the P column 511 is located within the second epitaxial layer 503, and the P column 511 and the N-type low doping concentration second epitaxial layer 503 form a quasi-superjunction structure. This realizes a connection between the P column 511 and the P body region 504 in the width direction.

[0064] In another embodiment, the P column connectors 505 may be realized by implanting ions into the sidewalls of the trench 500 after the etching of the trench 500 is completed. Referring to FIG. 8c, the trench 500 is continuously etched along the central axis of the unit cell, instead of the intermittent etching as shown in FIG. 8b. The etching depth penetrates the P body region 504 and reaches the second epitaxial layer 503. After the trench 500 is formed, the sidewalls of the trench 500 are implanted into the sidewalls to form the P column connectors 505 having a certain thickness on both sides. The depth of the pair of P column connectors 505 is at least the same as the depth of the trench 500, so that the pair of P column connectors 505 may be electrically connected to the subsequently generated P column 511 (the P column 511 is generated at the bottom of the trench 500 by the ion implantation process and connected to the bottom of the trench 500). At the same time, a part of the P-column connector 505 is generated in the P-body region 504, so that the P-column connector 505 can effectively electrically connect the P-body region 504 and the P-column 511.

[0065] FIG. 10 shows the XYZ coordinate system of the upper surface of the wafer, in which the X and Y directions are parallel to the surface of the wafer, and the Z direction is perpendicular to the surface of the wafer. At the same time, FIG. 10 further shows a number of crystal directions and crystal planes of the silicon carbide crystal body. The schematic diagram of the crystal direction is slightly tilted to show that there is an included angle between the crystal body and the wafer. As can be seen from the cutting method of the silicon carbide wafer shown in FIG. 5, the crystal plane (1-100) of silicon carbide is parallel to the XY plane, the projection [11-20]x of the crystal direction [11-20] on the wafer surface is parallel to the X axis, and the projection Cy of the C axis on the YZ plane is parallel to the Y axis. As mentioned before, there is an included angle between the crystal body and the wafer, and the included angle is about 4°. Due to the existence of the included angle, when the length of the trench is perpendicular to the XY plane, i.e., when the length of the trench is parallel to the Z axis (as shown in FIG. 9b), the ions implanted into the bottom of the trench along the C axis can only form non-axisymmetric P columns in the bottom region of the trench that approximate a parallelogram. As mentioned before, it is preferable for the P columns to have a symmetric (axisymmetric) pattern, and the P columns with a parallelogram cross section bring many hidden disadvantages and are prone to causing situations such as device destruction and failure.

[0066] The present invention rotates the default trench direction in the industry by 90°, so that the length direction of the trench is parallel to the X-axis as shown in FIG. 9a. As can be seen from the above analysis, the ions implanted along the C-axis may be understood to be implanted along two directions, the Y-axis (i.e., the Cy direction perpendicular to the wafer) and the X-axis (i.e., the [11-20]x direction parallel to the wafer). Here, the X-direction is the length direction of the trench, and implanting ions along this direction should not affect the cross-sectional shape of the P column 511 in the width direction of the trench 500. Therefore, in this embodiment, the range of ion implantation does not exceed the expected range, and the P column 511 can form a structure that approximates a symmetric rectangle when viewed from the cross section shown in FIG. 8a. Compared with the prior art shown in FIG. 9b, the present invention can improve the stability and reliability of the trench MOSFET.

[0067] The trench-type MOSFET of the present invention can improve the withstand voltage capability compared to the planar-structure MOSFET produced by the conventional process shown in FIG. 1. In addition, the sufficiently deep P column 511 improves the doping concentration of the second epitaxial layer 503 and reduces the resistance R of the drift region. D By reducing the on-resistance Rds (on) can be reduced.

[0068] It will be appreciated that the above values ​​for the number of implants, corresponding energies and doses for implanting aluminum ions (e.g., Al-27) into silicon carbide are exemplary and not limiting, and that in other embodiments of the present application the number of implants, corresponding energies and doses may be selected depending on the required implant depth.

[0069] Here, implanting aluminum ions (e.g., Al-27) from the C-axis direction of the 4H-SIC wafer is illustrative and not limiting, and it is understood that in other embodiments of the present application, ions having another conductivity type of P-type may be implanted into the second epitaxial layer along the crystal direction of another wide band gap semiconductor, thereby achieving a deep implantation depth with low implantation energy due to the trench effect of the crystal.

[0070] Thereafter, there are further steps of activating the ions implanted in the second epitaxial layer 503 by high-temperature annealing, forming silicon dioxide on the inner surface of the trench 500 and then depositing polycrystalline silicon in the trench 500 to form a polycrystalline silicon gate, growing a silicon dioxide insulating layer 515 on the polycrystalline silicon gate, and forming electrodes (source S and gate G) through steps such as a normal ohmic contact process and a metallization process. The structure of the power MOSFET with a trench gate quasi-super junction structure finally formed in this application is shown in FIG.

[0071] The embodiment of the present application further provides a power MOSFET with a trench gate super junction structure (not shown), the structure and manufacturing method of which are similar to those of the power MOSFET with the trench gate quasi-super junction structure described above, and only differ from the power MOSFET with the trench gate quasi-super junction structure in the following respects: In the process of manufacturing the MOSFET with the trench gate super junction structure, only a single epitaxial layer is required, and the depth of the P column formed therein must be more than 50% of the thickness of the epitaxial layer in the region below the bottom of the trench, and the P column and the epitaxial layer form a super junction structure. For detailed description, please refer to the above content, and the description will not be repeated here.

[0072] 11 shows a flow chart of a method for manufacturing a trench-gate power MOSFET according to some embodiments of the present application. Specifically, as shown in FIG. 11, the method for manufacturing a trench-gate power MOSFET of the present application includes the following steps:

[0073] 1) growing an epitaxial layer having a first conductivity type on a wide band gap semiconductor substrate (902), where the material of the wide band gap semiconductor substrate may be silicon carbide, gallium nitride, aluminum nitride, diamond, etc. An epitaxial layer may be formed on the wide band gap semiconductor substrate by an epitaxial growth process. The epitaxial layer of the first conductivity type is an epitaxial layer doped with a first conductivity type element. In some embodiments, the first conductivity type element may be an element such as nitrogen, phosphorus, etc., which makes the epitaxial layer an N-type semiconductor (free electrons are majority carriers, holes are minority carriers). In some embodiments, the first conductivity type element may be a trivalent element such as boron, aluminum, etc., which makes the epitaxial layer a P-type semiconductor (holes are majority carriers, free electrons are minority carriers). It is understood that whether the first conductivity type is P-type or N-type can be selected according to actual needs and is not limited here.

[0074] 2) forming a body region having a second conductivity type in the epitaxial layer (904), where the body region of the second conductivity type is a body region doped with a second conductivity type element. The second conductivity type is different from the first conductivity type, for example, if the first conductivity type is N type, the second conductivity type is P type, and if the first conductivity type is P type, the second conductivity type is N type. It is understood that the first conductivity type and the second conductivity type can be determined according to actual needs and are not limited here.

[0075] In some embodiments, an ion implantation process may be used to implant an element of a second conductivity type into the epitaxial layer to form a body region of the second conductivity type.

[0076] 3) forming a trench by etching in the body region (906). The ion implantation direction may be matched to the direction of the trench in order to obtain a cross-sectionally symmetric second conductivity type column in the subsequent ion implantation. The matching may include that the ion implantation direction is perpendicular to the bottom surface of the trench, or that the ion implantation direction is decomposed into a direction perpendicular to the bottom surface of the trench and a direction parallel to the length of the trench. Based on the ion implantation direction, a crystal direction in which the channel effect is most prominent is generally selected, and if the crystal direction in which the channel effect is most prominent is perpendicular to the wafer surface, the trench can be placed arbitrarily on the wafer surface, and the ion implantation direction can always be perpendicular to the bottom of the trench. If the crystal direction in which the channel effect is most prominent is not perpendicular to the wafer surface, the crystal direction in which the channel effect is most prominent can be decomposed into an X direction parallel to the wafer surface and a Y direction perpendicular to the wafer surface, and the length of the trench can be placed parallel to the X direction.

[0077] For example, in some embodiments, the length direction of the trench is set to be perpendicular to the crystal plane (11-20) of the wafer 71 as shown in Fig. 9a, i.e., the length direction of the trench is parallel to the crystal direction [11-20] (or more precisely, parallel to the projection of the crystal direction [11-20] on the wafer), rather than the direction as shown in Fig. 9b. In addition, in order to maintain an electrical connection between the subsequently formed P column 511 and the P body region 504, a P column connector 505 may be further formed between the bottom 5001 of the trench 500 and the P body region 504 by ion implantation.

[0078] There are two ways to form the P column connector 505.

[0079] First, the P column connector 505 is formed. This can be understood with reference to FIGS. 8a and 8b. After forming a body region having a second conductivity type, for example, the P body region 504, a mask pattern 5051 of the P column connector 505 is created on both sides of the central axis (shown in FIG. 8b) of the upper surface of the P body region 504, and then P-type ions are implanted into the P body region 504 and the second epitaxial layer 503 in the region to obtain the P column connector 505. The depth of the ion implantation is greater than the depth of the trench 500, i.e., the depth reaches the region of the P column 511, so that an electrical connection between the P body region 504 and the subsequently processed P column 511 can be realized through the P column connector 505. Then, in the region of the hard mask layer pattern 5002 for processing the trench shown in FIG. 8b, a trench 500 is formed in the P body region 504 and the second epitaxial layer 503 by an etching process, and the depth and width of the trench can be controlled. Those skilled in the art may understand that the position of the mask pattern 5051 of the P-column connector 505 shown in FIG. 8b may be at any position on the central axis, or there may be multiple positions in one unit cell, and similar settings will not be described here.

[0080] In some embodiments, the body region may be etched to form the trench by a dry etching technique. In some embodiments, the body region may be etched to form the trench by a wet etching technique. It is understood that either dry etching or wet etching may be selected according to the actual situation to form the trench, and the present invention is not limited thereto.

[0081] Furthermore, to ensure an effective electrical connection between the P body region 504 and the P column 511, the P-type ion implantation may be further increased on the sidewall near the P column connector 505 to ensure a sufficient connection between the P column connector 505 and the P body region 504, thereby forming an effective P-type connection and avoiding the electrical floating of the subsequently processed P column 511.

[0082] In some other embodiments, after further forming the first P-type highly doped region 507, the second P-type highly doped region 508 and the N-type highly doped region 506, the region of the P column connector 505 may be surrounded on both sides of the central axis of the device surface by a mask (see FIG. 8a), and then an ion implantation process may be performed to form the P column connector 505 in the P body region 504 and the second epitaxial layer 503.

[0083] Second, the P column connector 505 is formed later. This can be understood with reference to FIGS. 8a and 8c. In contrast to the above-mentioned case where the trench 500 is discontinuous, the P column connector 505 can be formed later to obtain a continuous trench 500. That is, in the embodiment shown in FIG. 8c, there is no P column connector crossing the trench 500, and the complexity of trench etching can be somewhat reduced. After forming a body region having a second conductivity type, for example, the P body region 504, a trench 500 as shown in the figure is etched in the P body region 504 and the second epitaxial layer 503 by a normal process, and then ion implantation is performed on both sidewalls of the trench 500 to form a P ion high doping region of a certain thickness on the sidewall to form a set of P column connectors 505. From another perspective, it can be understood that the P column connectors manufactured by the previous method are fitted into both sidewalls of the trench 500. For the same reason, to ensure an effective electrical connection between the P body regions 504 and the P columns 511, an additional ion implant may be performed down at the connection between the P column connectors 505 and the bottom of the trench 500 to ensure a more reliable electrical connection between the P column connectors 505 and the subsequently processed P columns 511.

[0084] It is well known in the art that the P column is preferably symmetrical, and asymmetrical P columns are disadvantageous in reducing the electric field strength in the superjunction structure, and the electric field strength is too high, which is likely to cause device destruction. Therefore, the present application breaks the industry practice and etches the trench in the [11-20]x direction (see FIG. 10). As can be seen from the illustrations of FIG. 7 and FIG. 8a, 8b, and 8c, the P column 511 is disposed below the trench 500 and has a rectangular structure that matches the shape and dimensions of the trench 500. Only when the length direction of the trench 500 is parallel to the [11-20] direction can the projection of the C-axis direction of silicon carbide (4H-SIC) on the wafer surface be in the [11-20]x direction, and further, when the subsequent ion implantation step is performed, the cross section of the P column obtained is similar to a symmetrical rectangle, and not a P column with a cross section similar to a parallelogram as in some prior art techniques.

[0085] 4) forming a second conductive type column by implanting first ions into the bottom region of the trench along a crystal direction of the wide band gap semiconductor material, the bottom region of the trench being located below and in contact with the bottom of the trench, and the crystal direction being selected so that the implantation of the first ions can fully utilize the trench effect of the crystal (908). In this way, when the first ions are implanted along the crystal direction of the semiconductor, the range of the first ions is significantly increased due to the trench effect compared to when the first ions are implanted along a random direction or the normal direction of the wafer, and the first ions have a stronger penetration effect, so that the energy of the first ion implantation can be greatly reduced and the manufacturing cost can be reduced. In some embodiments, the wide band gap semiconductor material is a hexagonal wide band gap semiconductor material (e.g., silicon carbide, gallium nitride, etc.), and the crystal direction refers to the vertical crystal plane (i.e., the C-axis direction) of the hexagonal wide band gap semiconductor material. In some embodiments, when the wide band gap semiconductor material is silicon carbide, the crystal direction of the wide band gap semiconductor material is selected as the C-axis direction of silicon carbide, and the C-axis direction and the normal direction of the silicon carbide wafer form a certain included angle. In some embodiments, when the wide band gap semiconductor material is 4H-SIC or 6H-SIC, the included angle between the C-axis direction and the normal direction of the 4H-SIC or 6H-SIC wafer is 4°. For other types of silicon carbide wafers, it is understood that the included angle between the corresponding C-axis direction and the normal direction of the corresponding wafer may be other values, and is not limited herein.

[0086] Here, the vertical depth of the second conductivity type columns is at least 50% of the thickness of the epitaxial layer located at least in the bottom region of the trench. In some embodiments, the epitaxial layer is a single epitaxial layer, and the vertical depth of the second conductivity type columns is at least 50% of the thickness of the epitaxial layer located at least in the bottom region of the trench. In some embodiments, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer being located below the second epitaxial layer. The bottom of the trench and the second conductivity type columns are located in the second epitaxial layer, and the vertical depth of the second conductivity type columns is at least 50% of the thickness of the second epitaxial layer located at least in the bottom region of the trench.

[0087] 5) Filling the trench with a filler (910). In some embodiments, the trench may be filled with a filler after forming an oxide (e.g., silicon dioxide) on the inner surface of the trench. The filling of the trench with a filler may be deposition of polysilicon into the trench.

[0088] In one embodiment, a trench silicon carbide MOSFET with a pitch of 2.4 μm is designed using TCAD (semiconductor process / device simulation tool) and has a specific on-resistance Rsp of 0.2 Ω / cm 2 Considering the transition ratio of the trench and the thickness of the silicon carbide substrate (the thickness of the silicon carbide substrate is taken as 180 μm), the specific on-resistance Rsp of the device can reach 0.896 Ω / cm 2and the breakdown voltage of the device was set to 950V (rated voltage 750V or 650V). Silicon carbide super junction structure MOSFET has a typical static output capacitance Coss curve, and as the source-drain voltage Vds increases, the static output capacitance Coss becomes significantly smaller, and due to this characteristic, the Qoss obtained by integrating the curve of the static output capacitance Coss becomes smaller (advantageous for soft switching), and the power consumption due to the static output capacitance Coss becomes smaller (advantageous for hard switching). Compared with silicon carbide devices or silicon devices manufactured by conventional processes in the related art, a MOSFET having a trench gate and a super junction structure (or a quasi-super junction structure) manufactured by the manufacturing method of a power MOSFET having a trench gate and a super junction structure (or a quasi-super junction structure) according to the present application has a thinner epitaxial layer, a lower specific on-resistance, and high device stability at the same breakdown voltage.

[0089] In one comparative experiment, a comparison was made between the conventional process of the power MOSFET and the method of the present invention, using an example in which P-type impurity Al-27 was implanted into a silicon carbide epitaxial layer at a dose of 2e16 cm-3. The total impurity dose was 1E14 / cm 2 In this case, Al-27 is implanted under an energy condition of 500 Kev in the manufacturing method of the present invention, whereas the conventional manufacturing method is implanted under an energy condition of 3.3 Mev. Comparing the two, the technical means of the present invention can achieve a deeper second conductivity type column. This shows that the manufacturing method of the present invention can achieve the same implantation depth as the conventional high energy condition with a much lower implantation energy, and that the manufacturing process can be controlled more easily under low implantation energy conditions.

[0090] In addition, in the examples and specification of this patent, relational terms such as first and second are merely for distinguishing one entity or operation from another entity or operation, and do not necessarily require or imply that any such actual relationship or sequence exists between these entities or operations. Furthermore, the terms "comprise", "include", or any other variant thereof are intended to cover a non-exclusive inclusion, whereby a process, method, article, or equipment that includes a set of elements may not only include those elements, but may also include other elements not expressly listed, or may also include elements inherent to such process, method, article, or equipment. Unless otherwise limited, an element limited by the expression "including a ..." does not exclude the presence of yet another identical element in the process, method, article, or equipment that includes the element.

[0091] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present application.

Claims

1. 1. A trench-gate power MOSFET formed in a wafer, comprising: a substrate of wide band gap semiconductor material having a first conductivity type; an epitaxial layer grown on the substrate and having the first conductivity type; a body region having a second conductivity type formed on the epitaxial layer; a trench etched into the body region, the length of the trench being parallel to a projection on the wafer surface of a crystal direction in which a channel effect is most pronounced among all crystal directions of the wafer; a second conductivity type column formed by implanting first ions into a bottom region of the trench below the trench and in contact with the bottom of the trench along a crystal direction in which the channel effect of the wide band gap semiconductor material is most pronounced, the column having a vertical depth of 50% or more of a thickness of the epitaxial layer located at the bottom region of the trench; and a trench gate formed by filling the trench with a filling material.

2. 2. The trench-gate power MOSFET of claim 1, further comprising a connector having the second conductivity type between the second conductivity type column and the body region, one end of the connector being electrically connected to the body region and the other end of the connector being electrically connected to the second conductivity type column.

3. 2. The trench-gated power MOSFET of claim 1, further comprising a drain located below the substrate, a gate located on a central axis of the body region, and sources located on either side of the gate.

4. 2. The trench-gate power MOSFET of claim 1, wherein said epitaxial layer is a single epitaxial layer.

5. 2. The trench-gate power MOSFET of claim 1, wherein the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer, the first epitaxial layer below the second epitaxial layer, the first epitaxial layer having a thickness less than a thickness of the second epitaxial layer, the first epitaxial layer having a doping concentration less than a doping concentration of the second epitaxial layer, the bottom of the trench and the second conductivity type columns are located within the second epitaxial layer, and a vertical depth of the second conductivity type columns is greater than or equal to 50% of a thickness of the second epitaxial layer located in the bottom region of the trench.

6. 6. A trench-gate power MOSFET according to claim 4 or 5, characterized in that the wide band gap semiconductor material is silicon carbide.

7. 2. The trench-gate power MOSFET of claim 1, wherein a ratio of the trench depth to the trench width ranges from 1:1 to 5:

1.

8. 7. The trench-gate power MOSFET of claim 6, wherein the first ions include aluminum ions, and the first ions are implanted in at least two batches, i.e., with a first dose, a first energy, and a second dose, a second energy, respectively, into the bottom region of the trench along the C-axis direction of the silicon carbide crystal body.

9. 1. A method for producing a trench-gate power MOSFET in a wafer, comprising: growing an epitaxial layer having a first conductivity type on a substrate of wide band gap semiconductor material; forming a body region having a second conductivity type in the epitaxial layer; forming a trench by etching in the body region, the length of the trench being parallel to a projection on the wafer surface of a crystal direction in which a channel effect is most pronounced among all crystal directions of the wafer; forming a second conductivity type column by implanting first ions into a bottom region of the trench along a crystal direction in which the channel effect of the wide band gap semiconductor material is most pronounced, the bottom region of the trench being located below and in contact with a bottom of the trench, and the vertical depth of the second conductivity type column being 50% or more of a thickness of the epitaxial layer located at the bottom region of the trench; and filling the trench with a filler.

10. 10. The method of claim 9, further comprising: forming a connector having the second conductivity type by implanting first ions into the body region and the epitaxial layer, one end of the connector being electrically connected to the body region and the other end of the connector being electrically connected to the second conductivity type column, and a depth of the connector being equal to or greater than a depth of the trench.

11. 10. The method according to claim 9, wherein the wide band gap semiconductor material is silicon carbide, and the crystal direction in which the channel effect is most prominent is the C-axis of a silicon carbide crystal.

12. The step of implanting the first ions into a bottom region of the trench along a crystal direction in which the channel effect is most pronounced comprises:

12. The method according to claim 11, further comprising implanting the first ions in at least two separate times, i.e., with a first dose, a first energy, and a second dose, a second energy, into the bottom region of the trench along the C-axis direction of the silicon carbide crystal body, respectively.

13. The first dose is 5E13 to 5E14 atoms / cm ２ the first energy is between 500 keV and 1500 keV, and the second dose is between 5E12 and 5E13 atoms / cm ２ and the second energy is between 50 keV and 300 keV.

14. 10. The method of claim 9, wherein the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer, the method comprising the steps of growing the first epitaxial layer having the first conductivity type on a substrate of the wide band gap semiconductor material, and growing the second epitaxial layer having the first conductivity type on the first epitaxial layer.

15. 15. The method of claim 14, wherein the first epitaxial layer has a thickness less than that of the second epitaxial layer, and the first epitaxial layer has a doping concentration less than that of the second epitaxial layer.

16. 15. The method of claim 14, wherein the bottom of the trench and the second conductivity type column are located within the second epitaxial layer, and the vertical depth of the second conductivity type column is greater than or equal to 50% of the thickness of the second epitaxial layer located in the bottom region of the trench.

17. The method of claim 9, wherein the ratio of the depth of the trench to the width of the trench is in the range of 1:1 to 5:1.

Images