Photoelectric detectors and electronic devices

Abstract

The present disclosure provides a photoelectric detector and an electronic device, belonging to the technical field of flat panel detectors. The photoelectric detector of the present disclosure is divided into a pixel region and a peripheral region surrounding the pixel region, the photoelectric detector includes a base substrate and a plurality of pixel units disposed on the base substrate and located in the pixel region, the pixel units include a thin film transistor, a photodiode and a storage capacitor, for each pixel unit, a first pole of the thin film transistor is connected to a first electrode of the photodiode and a first electrode plate of the storage capacitor, a second electrode of the photodiode is connected to a first bias signal line, a second electrode plate of the storage capacitor is connected to a second bias signal line, the first bias signal line and the second bias signal line are electrically connected, and a connection node is located in the peripheral region.

Description

[Technical field]

[0001] The present disclosure is in the field of flat panel detectors, and more particularly, photoelectric detectors and electronic devices. [Background technology]

[0002] X-ray inspection technology is widely used in industrial non-destructive testing, container scanning, circuit board inspection, medical, security, industrial and other fields, and is expected to be widely applied. Traditional X-ray imaging technology belongs to analog signal imaging, and has low resolution and poor image quality. X-ray digital imaging technology (Digital Radio Graphy, DR), which emerged in the late 1990s, uses X-ray photoelectric detectors to directly convert X-ray images into digital images, and the converted digital images are clear, have high resolution, and are easy to store and transmit, so it has become a hotspot in current research. X-ray photoelectric detectors are divided into direct conversion type (Direct DR) and indirect conversion type (Indirect DR) according to the difference in structure. Among them, indirect conversion type X-ray photoelectric detectors have more mature technology, relatively low cost, high detective quantum efficiency (DQE), high reliability and other advantages, so they have been widely developed and applied.

[0003] FPDs generally include a scintillator, an image sensor, a control module, a signal processing module, and a communication module. The scintillator absorbs X-rays and converts them into visible light, and the image sensor is made up of a pixel array consisting of photodiodes and TFT switches (Thin Film Transistors), and converts the visible light generated by the scintillator into an electrical signal under the control of a control circuit. The signal processing module amplifies the electrical signal, converts it into a digital signal through an analog-to-digital converter, and creates an image through correction and compensation processing.

[0004] The PIN type X-ray photoelectric detector mainly includes a transistor (Thin Film Transistor, TFT) and a photodiode (PIN). When irradiated with X-rays, the scintillator layer or phosphor layer of the indirect conversion type X-ray photoelectric detector converts the X-ray photons into visible light, and the visible light is converted into an electrical signal by the action of the PIN, and finally the electrical signal is read through the TFT, and the electrical signal is output to obtain a display image.

[0005] Photoelectric detectors with a metal-semiconductor-metal (MSM) structure have the advantages of not requiring a doping process, being simple in manufacturing process, and being low in cost, and also have a relatively high filling rate and a relatively fast response speed. Photoelectric detectors with a metal-semiconductor-metal (MSM) structure are compatible with the manufacturing process of thin film transistors and are easy to integrate, so radiation detectors using photoelectric detectors with a metal-semiconductor-metal (MSM) structure have the advantages of a simple manufacturing process and low cost. However, photoelectric detectors with a metal-semiconductor-metal (MSM) structure have a large dark current, a low quantum detection efficiency (DQE), and a low modulation transfer function (MTF).

[0006] The radiation detector further includes a scintillator that absorbs radiation and converts the radiation energy into light detectable by a photoelectric sensor. The scintillator can be selected to have sensitivity to X-rays, gamma rays, or other radiation according to actual needs. This allows the radiation detector to function as a detector such as an X-ray detector or a gamma ray detector. Summary of the Invention

[0007] The present invention has been made to solve at least one of the technical problems existing in the prior art, and provides a photoelectric detector and an electronic device.

[0008] In a first aspect, an embodiment of the present disclosure provides a photodetector divided into a pixel area and a peripheral area surrounding the pixel area, the photodetector including: a base substrate; and a plurality of pixel units disposed on the base substrate and located in the pixel area; The pixel unit includes a thin film transistor, a photodiode and a storage capacitor; For one of the pixel units, a first electrode of the thin film transistor is connected to a first electrode of the photodiode and a first electrode plate of the storage capacitor, a second electrode of the photodiode is connected to a first bias signal line, and a second electrode plate of the storage capacitor is connected to a second bias signal line, the first bias signal line and the second bias signal line are electrically connected, and a connection node is located in the peripheral region.

[0009] The plurality of pixel units form a plurality of first pixel groups arranged side by side along a first direction and a plurality of second pixel groups arranged side by side along a second direction, the pixel units in the first pixel groups are arranged side by side along the second direction, and the pixel units in the second pixel groups are arranged side by side along the first direction, For one of the second pixel groups, the gate electrodes of the thin film transistors are connected to the same gate line; For one of the first pixel groups, the second electrodes of the thin film transistors are connected to the same data line, the second electrodes of the photodiodes are connected to the same first bias signal line, and the second electrode plates of the storage capacitors are connected to the same second bias signal line, and the first bias signal line and the second bias signal line are electrically connected.

[0010] The orthogonal projection areas of the first connection portion, the second connection portion, and the first connection via on the base substrate are a first area, a second area, and a third area, respectively, and the ratio of the first area to the third area and the ratio of the second area to the third area are all 16:9 to 4:1.

[0011] The center of the orthogonal projection of the first connection via onto the base substrate overlaps with the center of the orthogonal projection of the first connection portion and the second connection portion, which are electrically connected via the first connection via, onto the base substrate.

[0012] For the first connection portion, the second connection portion, and the first connection via which overlap at the center of the orthogonal projection onto the base substrate, the distance between the orthogonal projection of the first connection via and the first connection portion onto the base substrate is defined as a first distance, and the distance between the orthogonal projection of the first connection via and the second connection portion onto the base substrate is defined as a second distance, and both the first distance and the second distance are 1.5 to 3 μm.

[0013] At least some of the adjacently arranged first connection portions are connected to each other via a connection bar.

[0014] The first connection portion and the connection bar electrically connected thereto are connected as an integral structure.

[0015] For the first bias signal line, the second bias signal line, and the data line electrically connected to the same first pixel group, the first extension portion is located between the second extension portion and the data line.

[0016] A distance between the first extension portion and the second extension portion in the first direction is greater than a distance between the first extension portion and the data line in the first direction.

[0017] The photodetector includes a first conductive layer, a first insulating layer, and a second conductive layer disposed in sequence on the base substrate; the first electrode and the second electrode of the thin film transistor, the data line, the second bias signal line, and the second electrode plate of the storage capacitor are located on the first conductive layer; A first electrode plate of the storage capacitor is located on the second conductive layer and is shared with a first electrode of the photodiode, and is electrically connected to a first electrode of the thin film transistor through a second connection via that penetrates the first insulating layer.

[0018] The pixel unit further includes a first connection electrode located on the first conductive layer, a first electrode of the thin film transistor electrically connected to the first connection electrode, and the first connection electrode electrically connected to a first electrode plate of the storage capacitor through the second connection via.

[0019] the PIN semiconductor layer and the second electrode of the photodiode are disposed in order on a side of the second conductive layer away from the base substrate, and the photoelectric detector further includes a second insulating layer and a third conductive layer disposed in order on a side of the layer in which the second electrode is disposed away from the base substrate; The first bias signal line is located in the third conductive layer and is electrically connected to a second electrode of the photodiode through a third connection via that penetrates the first insulating layer.

[0020] The pixel unit further includes a light blocking pattern located on the third conductive layer, The orthogonal projection of the light-shielding pattern in the pixel unit onto the base substrate covers an area where the thin film transistor is present.

[0021] The second insulating layer includes a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer, which are arranged in this order in a direction away from the base substrate.

[0022] In a second aspect, embodiments of the present disclosure provide an electronic device including a photodetector according to any of the above. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic diagram of an exemplary photodetector. [Diagram 2] FIG. 2 is a schematic diagram of a photodetector according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a partial cross-sectional view of one pixel unit in a photodetector according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a plan view of a layer in which a second bias signal line and a second electrode plate of a storage capacitor are formed in a photoelectric detector according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a plan view of a photodetector according to an embodiment of the present disclosure with a first bias signal line formed thereon. [Figure 6]FIG. 6 is a plan view of a photodetector having a gate metal layer formed thereon according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a plan view of a photodetector having active semiconductor layers formed thereon according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a plan view of a photodetector having a first conductive layer formed thereon according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a plan view of a photodetector according to an embodiment of the present disclosure with a second conductive layer formed thereon. [Figure 10] FIG. 10 is a plan view of a photodetector according to an embodiment of the present disclosure with a second electrode layer formed thereon. [Figure 11] FIG. 11 is a plan view of a photodetector according to an embodiment of the present disclosure with a third conductive layer formed thereon. [Figure 12] FIG. 12 is a layout diagram of one pixel unit in a photodetector according to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure. Specific embodiments

[0024] In order for those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in combination with drawings and specific embodiments.

[0025] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning as understood by those skilled in the art in the field to which this disclosure belongs. The terms "first", "second" and similar terms used in this disclosure do not denote any order, number or importance, but are merely used to distinguish different components. Similarly, similar terms such as "one", "one" or "the" do not denote a number limitation, but indicate the presence of at least one. Similar terms such as "comprise" or "include" refer to the preceding element or member covering the subsequently listed element or member and their equivalents, without excluding other elements or members. Similar terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect connections. "Top", "bottom", "left", "right", etc. only refer to relative positions, and if the absolute positions of the objects described change, the relative positions may change accordingly.

[0026] FIG 1 is a schematic diagram of an exemplary photoelectric detector. As shown in FIG 1, the photoelectric detector includes a base substrate, a plurality of pixel units 10 arranged on the base substrate, a plurality of gate lines Gate, a plurality of data lines Data, and a plurality of first bias signal lines Bias1. The plurality of pixel units 10 form a plurality of first pixel groups 11 arranged side by side along a first direction X, and a plurality of second pixel groups 12 arranged side by side along a second direction Y, where each pixel unit 10 in the first pixel group 11 is arranged side by side along the second direction Y, and each pixel unit 10 in the second pixel group 12 is arranged side by side along the first direction X. Each pixel unit 10 includes a thin film transistor TFT, a photodiode PIN, and a storage capacitance C. For one pixel unit 10, a first pole of the thin film transistor TFT is electrically connected to a first electrode of the photodiode PIN and a first electrode plate CC1 of the storage capacitance C, and a second electrode plate CC2 of the storage capacitance C is electrically connected to a second electrode of the photodiode PIN. The second electrodes of the thin film transistors TFT in the same first pixel group 11 are connected to the same data line Data, and the second electrodes of the photodiodes PIN are connected to the same first bias signal line Bias1. The gate electrodes of the thin film transistors TFT in the same second pixel group 12 are connected to the same gate line Gate.

[0027] In order to clearly understand the working principle of the photoelectric detector, the working process of one of the pixel units 10 will be described. The photodiode PIN in the pixel unit 10 is arranged to convert the received optical signal into an electrical signal. When an operating level signal is written to the gate line Gate, the thin film transistor TFT is turned on, and the data line Data reads the photodiode PIN through the thin film transistor TFT to generate an electrical signal, which is output to the image processing module, so that the image processing module generates an image according to the read electrical signal and provides it for display by the display device. It should be noted that the reason for increasing the storage capacitance C in each pixel unit 10 is that, with the increasing requirements for image resolution, the number of pixel units 10 in the photoelectric detector gradually increases, and the effective area of ​​the photodiode PIN gradually decreases, that is, the storage capacity of the capacitance in the photodiode PIN gradually decreases. At this time, the amount of stored charge can be increased by connecting a capacitance in parallel to the photodiode PIN, and thus the dynamic range of the photodiode PIN can be increased.

[0028] The inventors discovered that increasing the storage capacitance C in the pixel unit 10 also increases the size of the pixel unit 10, and that there is a limit to how high a resolution of an image can be achieved. The technical problem to be solved is how to increase the amount of charge of the storage capacitance C without increasing the size of the pixel unit 10.

[0029] In response to the above problems, the embodiments of the present disclosure provide the following technical solutions.

[0030] In the first embodiment, FIG. 2 is a schematic diagram of a photoelectric detector according to an embodiment of the present disclosure, FIG. 3 is a partial cross-sectional view of one pixel unit in the photoelectric detector according to an embodiment of the present disclosure, FIG. 4 is a plan view of a layer in which a second bias signal line and a second electrode plate of a storage capacitor are formed in the photoelectric detector according to an embodiment of the present disclosure, and FIG. 5 is a plan view of a photoelectric detector according to an embodiment of the present disclosure in which a first bias signal line is formed. As shown in FIGS. 2 to 5, the embodiment of the present disclosure provides a photoelectric detector divided into a pixel region Q1 and a peripheral region surrounding the pixel region Q1. The photoelectric detector includes a base substrate 100, a plurality of pixel units 10 arranged on the base substrate 100, a plurality of gate lines Gate, a plurality of data lines Data, a plurality of first bias signal lines Bias1, and a plurality of second bias signal lines Bias2. Each pixel unit 10 includes a thin film transistor TFT, a photodiode PIN, and a storage capacitor C. Here, for one pixel unit 10, the first pole of the thin film transistor TFT is connected to the first electrode 501 of the photodiode PIN and the first electrode plate CC1 of the storage capacitor C, the second pole of the thin film transistor TFT is connected to the data line Data, the gate electrode of the thin film transistor TFT is connected to the gate line Gate, the second electrode 505 of the photodiode PIN is connected to the first bias signal line Bias1, the second electrode plate CC2 of the storage capacitor C is connected to the second bias signal line Bias2, the first bias signal line and the second bias signal line are electrically connected, and the connection node A is located in the peripheral region Q2. In this way, the photoelectric detector according to the embodiment of the present disclosure can reduce the hole in the pixel region Q1 to electrically connect the second electrode 505 of the photodiode PIN and the second electrode plate CC2 of the storage capacitor C, which is helpful to increase the size of the storage capacitor C in the pixel unit 10, thereby increasing the amount of accumulated charge of the photodiode PIN, and thus increasing the dynamic range of the photodiode PIN.

[0031] In some examples, the pixel units 10 are all arranged in the pixel region Q1, forming a plurality of first pixel groups 11 arranged side by side along the first direction X and a plurality of second pixel groups 12 arranged side by side along the second direction Y. The pixel units 10 in the first pixel group 11 are arranged side by side along the second direction Y, and the pixel units 10 in the second pixel group 12 are arranged side by side along the first direction X. For one second pixel group 12, the gate electrodes 101 of the thin film transistors TFT are connected to the same gate line Gate, for one first pixel group 11, the second electrodes of the thin film transistors TFT are connected to the same data line Data, the second electrodes 505 of the photodiodes PIN are connected to the same first bias signal line Bias1, the second electrode plates CC2 of the storage capacitors C are connected to the same second bias signal line Bias2, the first bias signal line Bias1 and the second bias signal line Bias2 are electrically connected, and the connection node A is located in the peripheral region.

[0032] In the embodiment of the present disclosure, the second electrodes 505 of the photodiodes PIN in one first pixel group 11 are connected to the same first bias signal line Bias1, the second electrode plates CC2 of the storage capacitors C are connected to the same second bias signal line Bias2, and the first bias signal line Bias1 and the second bias signal line Bias2 are electrically connected in the peripheral region, that is, the same bias voltage is applied to the second electrodes 505 of the photodiodes PIN and the second electrode plate CC2 of the storage capacitor C. As can be seen from the photoelectric detector shown in FIG. 1, applying the same bias voltage to the second electrodes 505 of the photodiodes PIN and the second electrode plate CC2 of the storage capacitor C can be achieved by directly electrically connecting the second electrodes 505 of the photodiodes PIN and the second electrode plate CC2 of the storage capacitor C, but usually the second electrodes 505 of the photodiodes PIN and the second electrode plate CC2 of the storage capacitor C are not present in the same layer, in which case it is necessary to provide a via hole in the pixel region Q1 to electrically connect the two. In the embodiment of the present disclosure, the second bias line may be directly electrically connected to the second electrode plate CC2 of the storage capacitance C, i.e., may be disposed in the same layer, and in this case, it is only necessary to open a hole in the peripheral region to electrically connect the first bias signal line Bias1 and the second bias signal line Bias2, so that the same bias voltage can be applied to the second electrode 505 of the photodiode PIN and the second electrode plate CC2 of the storage capacitance C. In this way, the photoelectric detector according to the embodiment of the present disclosure can reduce the number of holes in the pixel region Q1, which helps to increase the size of the storage capacitance C in the pixel unit 10, thereby increasing the amount of accumulated charge of the photodiode PIN, and thus increasing the dynamic range of the photodiode PIN.

[0033] In addition, the layers in which the first bias signal line Bias1 and the second bias signal line Bias2 exist are both conductive layers, and in order to prevent the two layer structures from shorting, an interlayer insulating layer is provided between the layers in which they exist, so the so-called "drilling a hole" mentioned above means etching a via hole in the interlayer insulating layer.

[0034] In some embodiments, the first bias signal line Bias1 includes a first extension portion Bias11 and a first connection portion Bias12, and the second bias signal line Bias2 includes a second extension portion Bias21 and a second connection portion Bias22. The first extension portion Bias11 and the second extension portion Bias21 are both extended along the second direction Y, the first connection portion Bias12 and the second connection portion Bias22 are both located in the peripheral region, the first connection portion Bias12 is electrically connected to the first extension portion Bias11, and the second connection portion Bias22 is electrically connected to the second extension portion Bias21. The first connection portion Bias12 and the second connection portion Bias22 are electrically connected to the first bias signal line Bias1 and the second bias signal line Bias2 electrically connected to the same first pixel group 11 through the first connection via 601. The first bias signal line Bias1 and the second bias signal line Bias2 electrically connected to the same first pixel group 11 refer to the first bias signal line Bias1 connected to the second electrode 505 of each photodiode PIN in one first pixel group 11 and the second bias signal line Bias2 connected to the second electrode plate CC2 of each storage capacitor C in the first pixel group 11. In the embodiment of the present disclosure, the first bias signal line Bias1 and the second bias signal line Bias2 electrically connected realize electrical connection between them via the first connection part Bias12 and the second connection part Bias22, ensuring connection stability and improving product yield. In addition, the first bias signal line Bias1 and the second bias signal line Bias2 are arranged in layers, and an interlayer insulating layer is provided between them, and the first connection via 601 refers to a via hole penetrating the interlayer insulating layer.

[0035] Furthermore, the areas of the first connection portion Bias12, the second connection portion Bias22, and the first connection via 601, which are electrically connected through the first connection via 601, when orthogonally projected onto the base substrate 100, are a first area, a second area, and a third area, respectively. Here, the ratio of the first area to the third area and the ratio of the second area to the third area are all within the range of 16:9 to 4:1. In this case, by electrically connecting the first connection portion Bias12 and the second connection portion Bias22, the first connection via 601 between them can be completely covered, and a reliable connection between the first connection portion Bias12 and the second connection portion Bias22 is ensured.

[0036] Furthermore, the first connection portion Bias12 and the second connection portion Bias22, which are electrically connected through the first connection via 601, and the first connection via 601 overlap at the center of the orthogonal projection onto the base substrate 100. For the first connection portion Bias12, the second connection portion Bias22, and the first connection via 601, which overlap at the center of the orthogonal projection onto the base substrate 100, the distance between the first connection via 601 and the first connection portion Bias12 in the orthogonal projection onto the base substrate 100 is set as a first distance, and the distance between the first connection via 601 and the second connection portion Bias22 in the orthogonal projection onto the base substrate 100 is set as a second distance, and both the first distance and the second distance are about 1.5 to 3 μm. Here, the first distance and the second distance may be equal in value, may be approximately equal in value, or may not be equal in value. By electrically connecting the first connection portion Bias12 and the second connection portion Bias22 using the above-mentioned arrangement method, the first connection via 601 between the two can be completely covered, ensuring a reliable connection between the first connection portion Bias12 and the second connection portion Bias22.

[0037] In some examples, when each of the first bias signal lines Bias1 includes a first extension portion Bias11 and a first connection portion Bias12 that are electrically connected, at least some of the adjacently arranged first connection portions Bias12 are connected to each other via a connection bar 702. For example, any adjacently arranged first connection portions Bias12 are connected to each other via a short bar. This effectively reduces the number of pins of a driver chip that supplies a bias signal to the first bias signal line Bias1, thereby reducing costs.

[0038] Furthermore, in the embodiment of the present disclosure, the first connection portion Bias12 of the first bias signal line Bias1 and the connection bar 702 connected thereto are connected as an integral structure. In this case, the manufacture of the first bias signal line Bias1 and the connection bar 702 can be completed in one process, and the two are connected as an integral structure to ensure the stability of the connection between them.

[0039] 2, in some examples, for the first bias signal line Bias1, the second bias signal line Bias2, and the data line Data electrically connected to the same first pixel group 11, the first extension part Bias11 of the first bias signal line Bias1 is located between the second extension part Bias21 of the second bias signal line Bias2 and the data line Data. With this arrangement, the second pole of the thin film transistor TFT in the same group is electrically connected to the data line Data, the second electrode 505 of the photodiode PIN is electrically connected to the first bias signal line Bias1, and the second electrode plate CC2 of the storage capacitor C is electrically connected to the second bias signal line Bias2, which makes wiring easy and ensures uniformity of wiring in the pixel area Q1.

[0040] Furthermore, when the first bias signal line Bias1, the second bias signal line Bias2, and the data line Data of the same first pixel group 11 are electrically connected and the first extension portion Bias11 of the first bias signal line Bias1 is located between the second extension portion Bias21 of the second bias signal line Bias2 and the data line Data, the distance between the first extension portion Bias11 and the second extension portion Bias21 in the first direction X is greater than the distance between the first extension portion Bias11 and the data line Data in the first direction X. Still referring to FIG. 2, the reason for this arrangement is that the thin film transistor TFT and the photodiode PIN are arranged between the data line Data and the first extension portion Bias11 of the first bias signal line Bias1, but only the storage capacitance C is arranged between the first extension portion Bias11 of the first bias signal line Bias1 and the second extension portion Bias21 of the second bias signal line Bias2, so that it is necessary to secure a large arrangement space for the thin film transistor TFT and the photodiode PIN.

[0041] The specific film layer structure of the photoelectric detector in the embodiment of the present disclosure will be described below. Note that the following description only takes as an example the case where the thin film transistor TFT used in the photoelectric detector is a bottom gate type thin film transistor TFT, and the first pole and the second pole of the thin film transistor TFT are the source electrode 301 and the drain electrode 302, respectively, but it should be understood that this does not limit the scope of protection of the embodiment of the present disclosure.

[0042] In one example, a photodetector in an embodiment of the present disclosure includes, in a direction away from the base substrate 100, a gate metal layer, a gate insulating layer, an active semiconductor layer, a first conductive layer, a first insulating layer, a second conductive layer, a P-type semiconductor layer, an intrinsic semiconductor layer, an N-type semiconductor layer, a second electrode 505 layer, a second insulating layer, and a third conductive layer, in that order.

[0043] 6 is a plan view of a gate metal layer formed on a photoelectric detector according to an embodiment of the present disclosure. As shown in FIG. 6, the gate metal layer includes a gate electrode 101 of each thin film transistor TFT and a gate line Gate, and the gate electrode 101 of each thin film transistor TFT and the gate line Gate electrically connected thereto are integrally formed. An insulating layer of the gate electrode 101 is formed on the side of the gate metal layer away from the base substrate 100.

[0044] 7 is a plan view of a photoelectric detector according to an embodiment of the present disclosure having an active semiconductor layer formed thereon. As shown in FIG. 7, the active semiconductor layer includes an active layer 201 of each thin film transistor TFT. For example, the active semiconductor layer can be formed using amorphous silicon, polycrystalline silicon, an oxide semiconductor material, or the like. Note that the source electrode 301 region and the drain electrode 302 region of the active layer 201 may be regions doped with n-type impurities or p-type impurities. The semiconductor layer of the active layer 201 may or may not be covered with an insulating layer.

[0045] FIG. 8 is a plan view of a photoelectric detector according to an embodiment of the present disclosure, in which a first conductive layer is formed. As shown in FIG. 8, the first conductive layer includes a source electrode 301, a drain electrode 302, a second electrode plate CC2 of the storage capacitor C, a second bias signal line Bias2, and a data line Data of the thin film transistor TFT. Here, the source electrode 301 and the drain electrode 302 of the thin film transistor TFT are electrically connected to the source electrode 301 region and the drain electrode 302 region of the active layer 201, respectively. The second electrode plate CC2 of the storage capacitor C is electrically connected to the second bias signal line Bias2. The data line Data is electrically connected to the drain electrode 302 of the thin film transistor TFT. A first insulating layer covers the side of the first conductive layer away from the base substrate 100, and a second connection via 401 in each pixel unit 10 is formed in the first insulating layer, which facilitates the electrical connection between the first electrode plate CC1 of the photodiode PIN to be formed later and the source electrode 301 of the thin film transistor TFT.

[0046] In some examples, the second bias signal line Bias2 electrically connected to the second electrode plate CC2 of the storage capacitance C in the same first pixel group 11 and the second electrode plate CC2 of the capacitance electrically connected thereto have an integral structure. For example, the second bias signal line Bias2 includes a second extension portion Bias21 extending along the second direction Y and a second connection portion Bias22 electrically connected to the second extension portion Bias21, the second connection portion Bias22 is located in the peripheral region, the second extension portion Bias21 penetrates the peripheral region and the pixel region Q1, the second extension portion Bias21 penetrates the second electrode plate CC2 of each storage capacitance C in the first pixel group 11, and is electrically connected to the second electrode plate CC2 of the storage capacitance C.

[0047] In some examples, the data line Data electrically connected to the drain electrode 302 of the thin film transistor TFT in the same first pixel group 11 and the data line Data electrically connected thereto have an integral structure, and the data line Data extends along the second direction Y.

[0048] 8, in some examples, the first conductive layer may further include a first connection electrode 303 in each pixel unit 10, which is electrically connected to the source electrode 301 of the thin film transistor TFT. The first connection electrode 303 is also electrically connected to the second electrode plate CC2 of the storage capacitor C and the first electrode 501 of the photodiode PIN in the pixel unit 10 to be formed later.

[0049] 9 is a plan view of a photoelectric detector according to an embodiment of the present disclosure, in which a second conductive layer is formed. As shown in FIG. 9, the second conductive layer includes a first electrode 501 of a photodiode PIN and a second electrode plate CC2 of a storage capacitor C. In each pixel unit 10, the first electrode 501 of the photodiode PIN and the second electrode plate CC2 of the storage capacitor C may be integral with each other, and are connected to the source electrode 301 of the thin film transistor TFT through a second connection via 401.

[0050] 10 is a plan view of a photoelectric detector according to an embodiment of the present disclosure, in which a second electrode layer is formed. As shown in FIG. 10, a P-type semiconductor layer, an intrinsic semiconductor layer, an N-type semiconductor layer, and a second electrode layer are arranged in order on the side of the second conductive layer away from the base substrate 100. Here, the P-type semiconductor layer includes a P-type semiconductor pattern 502 of each photodiode PIN, the intrinsic semiconductor layer includes an intrinsic semiconductor pattern 503 of each photodiode PIN, the N-type semiconductor layer includes an N-type semiconductor pattern 503 of each photodiode PIN, and the second electrode layer includes a second electrode 505 of each photodiode PIN. In each pixel unit 10, the first electrode 501, the P-type semiconductor pattern 502, the intrinsic semiconductor pattern 503, the N-type semiconductor pattern 504, and the second electrode 505 are arranged in a stacked manner to form a photodiode PIN.

[0051] A second insulating layer covers the side of the second electrode 505 away from the base substrate 100. The second insulating layer includes a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer arranged in this order in a direction away from the base substrate 100. Here, the first inorganic insulating layer and the second inorganic insulating layer may be passivation layers, and the organic insulating layer may be a planarization layer, with the thickness of the planarization layer being greater than the thickness of the passivation layer.

[0052] Each pixel unit 10 further includes a first connection via 601 located in the peripheral region and a third connection via 602 located in the pixel region Q1. The first connection via 601 is for electrically connecting a first bias signal line Bias1 and a second bias signal line Bias2 to be formed later. The third connection via 602 electrically connects the first bias signal line Bias1 and the second electrode 505 of the photodiode PIN.

[0053] 11 is a plan view of a photoelectric detector according to an embodiment of the present disclosure, in which a third conductive layer is formed. As shown in FIG. 11, the third conductive layer includes a first bias signal line Bias1. The first bias signal line Bias1 is electrically connected to a second bias signal line Bias2 through a first connecting via 601, and is electrically connected to a second electrode 505 of the photodiode PIN through a third connecting via 602.

[0054] In some examples, for one first pixel group 11, the second electrodes 505 of the photodiodes PIN in each pixel unit 10 are connected to the same second bias signal line Bias2.

[0055] In some examples, when the second bias signal line Bias2 includes the second extension portion Bias21 and the second connection portion Bias22, the first bias signal line Bias1 may include a first extension portion Bias11 extending along the second direction Y and a first connection portion Bias12 electrically connected to the first extension portion Bias11, and for the first bias signal line Bias1 and the second bias signal line Bias2 electrically connected to the same first pixel group 11, the first connection portion Bias12 of the first bias signal line Bias1 is electrically connected to the second connection portion Bias22 of the second bias signal line Bias2 through the first connection via 601. The first extension portion Bias11 of the first bias signal line Bias1 is electrically connected to the second electrode 505 of the photodiode PIN through the third connection via 602.

[0056] Furthermore, the first bias signal line Bias1 may further include a plurality of third connection portions Bias13 electrically connected to the first extension portion Bias11 and arranged in one-to-one correspondence with the pixel units 10, and one of the third connection portions Bias13 is electrically connected to the second electrode 505 of the photodiode PIN through the third connection via 602.

[0057] Furthermore, the third conductive layer may further include a connection bar 702 electrically connecting adjacently arranged first connection portions Bias12. Here, the connection bar 702 may extend along the first direction X.

[0058] In some examples, the third conductive layer may further include a light-shielding pattern 701. The orthogonal projection of the light-shielding pattern 701 in the pixel unit 10 onto the base substrate 100 covers the area where the thin film transistor TFT exists, thereby effectively avoiding light from being irradiated onto the thin film transistor TFT and affecting the optical properties of the thin film transistor TFT to cause the photodetector to fail.

[0059] Furthermore, the light blocking pattern 701 may be connected to the first bias signal line Bias1 as an integral structure.

[0060] In some examples, Figure 12 is a layout diagram of one pixel unit in a photoelectric detector according to an embodiment of the present disclosure. As shown in Figure 12, the orthogonal projection of the second electrode plate CC2 of the storage capacitance C onto the base substrate 100 is within the orthogonal projection of the first electrode plate CC1 of the storage capacitance C onto the base substrate 100.

[0061] In some examples, with continued reference to FIG. 12, the contour of the orthogonal projection of the second electrode plate CC2 of the storage capacitance C onto the base substrate 100 includes a first line segment S1, and the contour of the orthogonal projection of the second electrode 505 of the photodiode PIN onto the base substrate 100 includes a second line segment S2, and the first line segment S1 and the second line segment S2 are parallel, i.e., the distance between the two is equal at any position.

[0062] Of course, the photoelectric detector according to the embodiment of the present disclosure may further include a third insulating layer and a scintillator layer arranged in order on the side of the third conductive layer away from the base substrate 100. The scintillator layer absorbs radiation and converts the radiation energy into light detectable by the photoelectric sensor. The scintillator layer may be selected to have sensitivity to X-rays, gamma rays, or other radiation according to actual needs. This allows the radiation detector to function as a detector such as an X-ray detector or a gamma ray detector.

[0063] In a second embodiment, Fig. 13 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure. As shown in Fig. 13, the electronic device 200 includes a photoelectric detector according to any of the previous embodiments. Examples of the electronic device 200 include, for example, medical diagnostic equipment, industrial inspection equipment, geological exploration equipment, etc. The electronic device 200 has similar advantages to the radiation detector embodiment.

[0064] It should be noted that the above embodiments are merely illustrative and are used to explain the principles of the present disclosure, and the present invention is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and gist of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A photoelectric detector divided into a pixel area and a peripheral area surrounding the pixel area, the photoelectric detector including a base substrate and a plurality of pixel units disposed on the base substrate and located in the pixel area, the pixel units including a thin film transistor, a photodiode and a storage capacitor; For each pixel unit, a first electrode of the thin film transistor is connected to a first electrode of the photodiode and a first electrode plate of the storage capacitor, a second electrode of the photodiode is connected to a first bias signal line, and a second electrode plate of the storage capacitor is connected to a second bias signal line, the first bias signal line and the second bias signal line are electrically connected to each other, and a connection node is located in the peripheral region. Photoelectric detector.

2. The plurality of pixel units form a plurality of first pixel groups arranged side by side along a first direction and a plurality of second pixel groups arranged side by side along a second direction, the pixel units in the first pixel groups are arranged side by side along the second direction, and the pixel units in the second pixel groups are arranged side by side along the first direction, For one of the second pixel groups, the gate electrodes of the thin film transistors are connected to the same gate line; For one of the first pixel groups, the second electrodes of the thin film transistors are connected to the same data line, the second electrodes of the photodiodes are connected to the same first bias signal line, and the second electrode plates of the storage capacitors are connected to the same second bias signal line, and the first bias signal line and the second bias signal line are electrically connected.

2. The photoelectric detector of claim 1.

3. the first bias signal line includes a first extension portion and a first connection portion, the first extension portion extends along a second direction, the first connection portion is located in the peripheral region and is connected to the first extension portion, the second bias signal line includes a second extension portion and a second connection portion, the second extension portion extends along the second direction, the second connection portion is located in the peripheral region and is connected to the second extension portion, For a first bias signal line and a second bias signal line electrically connected to the same first pixel group, the first connection portion and the second connection portion are electrically connected via a first connection via.

2. The photoelectric detector of claim 1.

4. The areas of the first connection portion, the second connection portion, and the first connection via, when projected onto the base substrate, are a first area, a second area, and a third area, respectively, and a ratio of the first area to the third area and a ratio of the second area to the third area are all in a range of 16:9 to 4:

1.

4. A photoelectric detector as claimed in claim 3.

5. The center of the orthogonal projection of the first connection via onto the base substrate overlaps with the center of the orthogonal projection of the first connection portion and the second connection portion, which are electrically connected via the first connection via, onto the base substrate.

4. A photoelectric detector as claimed in claim 3.

6. For the first connection portion, the second connection portion, and the first connection via that overlap at the center of the orthogonal projection onto the base substrate, a distance between the orthogonal projection of the first connection via and the first connection portion onto the base substrate is defined as a first distance, and a distance between the orthogonal projection of the first connection via and the second connection portion onto the base substrate is defined as a second distance, and both the first distance and the second distance are 1.5 to 3 μm.

6. A photoelectric detector as claimed in claim 5.

7. At least some of the adjacently arranged first connection portions are connected to each other via a connection bar.

4. A photoelectric detector as claimed in claim 3.

8. The first connection portion and the connection bar electrically connected thereto are connected as an integral structure.

8. A photoelectric detector as claimed in claim 7.

9. The first extension portion is disposed between the second extension portion and the data line for the first bias signal line, the second bias signal line, and the data line that are electrically connected to the same first pixel group.

4. A photoelectric detector as claimed in claim 3.

10. A distance between the first extension portion and the second extension portion in the first direction is greater than a distance between the first extension portion and the data line in the first direction.

10. A photoelectric detector as claimed in claim 9.

11. The photodetector includes a first conductive layer, a first insulating layer, and a second conductive layer disposed in sequence on the base substrate; the first electrode and the second electrode of the thin film transistor, the data line, the second bias signal line, and the second electrode plate of the storage capacitor are located on the first conductive layer; A first electrode plate of the storage capacitor is located on the second conductive layer and is shared with a first electrode of the photodiode, and is electrically connected to a first electrode of the thin film transistor through a second connection via that penetrates the first insulating layer.

2. The photoelectric detector of claim 1.

12. The pixel unit further includes a first connection electrode located on the first conductive layer, a first electrode of the thin film transistor electrically connected to the first connection electrode, and the first connection electrode is electrically connected to a first electrode plate of the storage capacitor through the second connection via.

12. A photoelectric detector as claimed in claim 11.

13. the PIN semiconductor layer and the second electrode of the photodiode are disposed in order on a side of the second conductive layer away from the base substrate, and the photoelectric detector further includes a second insulating layer and a third conductive layer disposed in order on a side of the layer in which the second electrode is disposed away from the base substrate; The first bias signal line is located in the third conductive layer and is electrically connected to the second electrode of the photodiode through a third connection via that penetrates the first insulating layer.

12. A photoelectric detector as claimed in claim 11.

14. The pixel unit further includes a light blocking pattern located on the third conductive layer, The orthogonal projection of the light-shielding pattern on the base substrate in the pixel unit covers an area where the thin film transistor is present.

14. A photoelectric detector as claimed in claim 13.

15. The second insulating layer includes a first inorganic insulating layer, an organic insulating layer, and a second inorganic insulating layer, which are arranged in this order in a direction away from the base substrate.

14. A photoelectric detector as claimed in claim 13.

16. An electronic device comprising a photodetector according to any one of the preceding claims.

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