Three-dimensional (3D) integrated circuit (IC) (3DIC) package using redistribution layer (RDL) interposer to facilitate semiconductor die stacking, and related manufacturing method

Abstract

A three-dimensional (3D) integrated circuit (IC) (3DIC) package using a redistribution layer (RDL) interposer facilitating semiconductor die ("die") and related manufacturing methods. The 3DIC package includes an RDL interposer having one or more RDL metallization layers formed adjacent to a first bottom die(s). A second top die(s) is stacked on the RDL interposer. The RDL interposer provides an extended die area to which the top die may be bonded such that the manufacturing process of the 3DIC package is die size independent. The bottom die(s) may be singulated and placed into the RDL metallization layer(s) as part of the reconfigured RDL interposer(s) regardless of whether the top die(s) are larger or smaller than the size of the bottom die(s). Additionally, the RDL interposer, which is the substrate on which the bottom die(s) are placed and to which the top die(s) are bonded, provides efficient signal routing paths to the top and bottom dies.

Description

[Technical field]

[0001] Priority Application

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 657,760, filed April 4, 2022, and entitled "THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) (3DIC) PACKAGE EMPLOYING A REDISTRIBUTION LAYER (RDL) INTERPOSER FACILITATING SEMICONDUCTOR DIE STACKING, AND RELATED FABRICATION METHODS," which is incorporated by reference in its entirety into this specification. [Background technology]

[0002] I. Field of Disclosure The field of the disclosure relates to integrated circuit (IC) packages, and more particularly to three-dimensional (3D) IC packages that include multiple stacked semiconductor dies.

[0003] II. Background

[0003] Integrated circuits (ICs) are the basis of electronic devices. ICs are packaged in IC packages, also called "semiconductor packages" or "chip packages". An IC package includes one or more semiconductor dice ("dies" or "dice") as IC(s) attached to and electrically coupled with a package substrate to provide physical support and an electrical interface to the die(s). The package substrate includes one or more metallization layers that include electrical traces (e.g., metal lines), and vias couple the electrical traces together between adjacent metallization layers to provide an electrical interface between the die(s). The die(s) are electrically interfaced to metal interconnects exposed on a top or outer layer of the package substrate to electrically couple the semiconductor die(s) to the electrical traces of the package substrate. The package substrate includes an outer metallization layer bonded to external metal interconnects (e.g., solder bumps) to provide an external interface between the die(s) in the IC package for mounting the IC package on a circuit board and interfacing the die(s) with other circuitry.

[0004]

[0004] Some IC packages are known as "hybrid" IC packages that include multiple dies for different purposes or applications. For example, a hybrid IC package may include a modem die as part of a front-end circuit for supporting a communication interface. The hybrid IC package may also include one or more memory dies that provide memory to support data storage and access by the modem die, such as for buffering and transmitting modulated and / or demodulated data. Therefore, in these hybrid IC packages, to save the area consumed by the IC die package in a first horizontal direction, it is common to stack multiple dies on top of each other in a second vertical direction as a three-dimensional (3D) stack within the IC package to provide a 3DIC package. In a 3DIC package, the bottom die directly adjacent to the package substrate of the IC package is electrically coupled to the metal interconnects of the upper metallization layer of the package substrate via die interconnects. Other stacked dies that are not directly adjacent to the package substrate of the IC package are also coupled to the package substrate. For example, other stacked dies may be electrically coupled to the package substrate by wire bonds or by through silicon vias (TSVs) that extend through the middle die layer(s) and / or the bottom die layer to the package substrate. External connections to the die are made through electrical connections in the package substrate. Also, die-to-die (D2D) connections between the stacked dies are made through electrical connections in the package substrate.

[0005]

[0005] 3DIC packages can be bottom-greater-than-top (BGT) or top-greater-than-bottom (TGB) die configurations. In a BGT 3DIC package, the bottom die has a greater horizontal length than the top die stacked on the bottom die. In a TGB 3DIC package, the top die has a greater horizontal length than the bottom die on which it is stacked. The manufacturing process is different for BGT and TGB 3DIC packages because in each process, a smaller die is fabricated separately and bonded to a wafer on which a larger die is formed. In a BGT 3DIC package, a top die, prefabricated and diced into chip form in a separate manufacturing process, is bonded to a bottom wafer in a top chip-to-bottom wafer bonding process. The stacked top die and the bottom wafer with the bottom die can then be diced. If the top die is longer than the bottom die, there is no need to use an overmolding material to fill the gap that would otherwise exist. However, in the TGB 3DIC package, since the top die is longer than the bottom die, a bottom chip-to-top wafer bonding process is used. In the TGB 3DIC package, the bottom die, which is prefabricated and diced into chip form in a separate manufacturing process, is bonded to the top wafer in a bottom chip-to-top wafer bonding process. Summary of the Invention

[0006]

[0006] Aspects disclosed herein include a three-dimensional (3D) integrated circuit (IC) (3DIC) package that uses a redistribution layer (RDL) interposer to facilitate semiconductor die ("die") stacking. Related manufacturing methods are also disclosed. In an exemplary aspect, the 3DIC package includes an RDL interposer having one or more RDL metallization layers formed adjacent to a first bottom die(s). The redistribution metallization layer(s) in the RDL interposer are metallization layer(s) that include metal interconnects (e.g., metal lines, metal traces) that provide branching connections (e.g., metal pads) from the die interconnects of the first bottom die and / or the second top die to other locations within the 3DIC package for signal routing. The 3DIC package also includes a second top die(s) stacked vertically on the RDL interposer in a 3D stacked die configuration. The redistribution metallization layer(s) in the RDL interposer are metallization layer(s) that include metal interconnects (e.g., metal lines, metal traces) that provide branching connections (e.g., metal pads) from the die interconnects of the first bottom die and / or the second top die to other locations in the 3DIC package for signal routing. Also, by integrating the first bottom die to the RDL interposer, the RDL interposer provides an extended die area where the top die can be bonded to the RDL interposer and / or the first bottom die to provide a 3DIC package. In this way, as an example, the manufacturing process of the stacked top and bottom dies in the 3DIC package can be independent of whether the top die is larger than the bottom die in a top-die-larger-than-bottom-die (TGB) configuration or the bottom die is larger than the top die in a bottom-die-larger-than-top (BGT) configuration. The bottom die(s) can be singulated and placed on the formed RDL metallization layer(s) as part of a reconfigured RDL interposer. The top die can then be bonded to the RDL interposer, regardless of whether the 3DIC package is in a TGB or BGT configuration.In a conventional 3DIC package manufacturing process, smaller dies are manufactured and singulated in a separate process and then bonded to the wafer on which the larger die is formed. The use of RDL interposers to facilitate 3D die stacking in a 3DIC package can be independent of further packaging, such as performing an external bumping process to bond the 3DIC package to a package substrate.

[0007]

[0007] Also, the RDL interposer in the 3DIC package, which is the substrate on which the bottom die(s) are internally disposed and to which the top die is bonded, provides an efficient signal routing path to the top and bottom dies. In one example, the bottom die is bonded to metal interconnects in the redistribution metallization layer(s) in the RDL interposer to provide a signal routing path between the bottom die and the external interconnects of the 3DIC package (e.g., ball grid array (BGA) interconnects). The external interconnects may be bonded directly to the RDL interposer and / or the RDL metallization layer in the 3DIC package. In another example, the top die is bonded to metal interconnects in the outer redistribution metallization layer of the RDL interposer as a result of bonding the top die to the RDL interposer to provide a signal routing path(s) between the top die and the external interconnects of the 3DIC package. In another example, the top die is coupled to through silicon vias (TSVs) that extend through the bottom die to provide signal routing path(s) between the top die and the RDL interposer. When the bottom die is disposed in the RDL interposer, the top die may be vertically aligned with the bottom die and coupled to the bottom die to provide die-to-die (D2D) interconnects between the top and bottom dies. Other dies may also be coupled to the RDL interposer outside the bottom die(s), with signal routing paths provided in the RDL interposer between such other dies and the top and / or bottom dies.

[0008]

[0008] In this regard, in one exemplary aspect, an IC package is provided. The IC package includes an interposer. The interposer has a first surface and a second surface opposite the first surface. The interposer also has one or more RDL metallization layers between the first surface and the second surface. The IC package also includes a first die disposed within the interposer. The first die has a first die interconnect coupled to a first metal interconnect in a first RDL metallization layer of the one or more RDL metallization layers, and a second die coupled to the first surface of the interposer. The second die has a second die interconnect coupled to the first RDL metallization layer.

[0009]

[0009] In another exemplary aspect, a method of manufacturing an IC package is provided. The method includes forming an interposer including forming a first RDL metallization layer adjacent to a first die, the first RDL metallization layer having a first surface and a second surface opposite the first surface, and bonding a first die interconnect of the first die to a first metal interconnect in the first RDL metallization layer. The method also includes bonding a second die to the first surface of the interposer. The method also includes bonding a second die interconnect of the second die to the first RDL metallization layer. [Brief description of the drawings]

[0010] [Figure 1]

[0010] FIG. 1 is a side view of a three-dimensional (3D) integrated circuit (IC) (3DIC) package that includes a semiconductor die ("die") that includes an upper die in an upper die package coupled to a lower die in a lower die package. [Figure 2A]

[0011] FIG. 1 is a side view of an exemplary 3DIC package in a bottom die larger than top die (BGT) configuration, the 3DIC package including a reconfigured redistribution layer (RDL) interposer that facilitates expanded die area for 3D stacking of the top die onto the bottom die, and also including one or more RDL metallization layers to provide signal routing paths for the top die and / or bottom die. [Figure 2B] FIG. 1 is a side view of an exemplary 3DIC package in a bottom die larger than top die (BGT) configuration, the 3DIC package including a reconfigured redistribution layer (RDL) interposer that facilitates expanded die area for 3D stacking of the top die onto the bottom die, and also including one or more RDL metallization layers to provide signal routing paths for the top die and / or bottom die. [Diagram 3]

[0012] FIG. 1 is a side view of another exemplary 3DIC package in a top die larger than bottom die (TGB) configuration, the 3DIC package including an RDL interposer that facilitates extended die area for 3D stacking of the top die to the bottom die, and also including one or more RDL metallization layers to provide signal routing paths for the top die and / or bottom die. [Figure 4]

[0013] FIG. 4 is a side view of another exemplary 3DIC package similar to the 3DIC package of FIGS. 2A and 2B, but also including an additional die coupled to the RDL interposer outside of the bottom die in the RDL interposer. [Diagram 5]

[0014] FIG. 5 is a side view of another exemplary 3DIC package similar to the 3DIC package of FIG. 4, including an additional die coupled to the RDL interposer outside of a bottom die in the RDL interposer, and an interposer die disposed within the RDL interposer. [Figure 6]

[0015] FIG. 5 is a side view of another exemplary 3DIC package in a BGT configuration, similar to the 3DIC package of FIG. 4, in which the top die is bonded to an RDL interposer, and the RDL interposer is bonded onto a reconfigured RDL interposer that includes the bottom die. [Figure 7]

[0016] FIG. 5 is a side view of another exemplary 3DIC package similar to the 3DIC package of FIG. 4, where the top die is integrated into a chiplet that includes an integrated decoupling capacitor coupled to an RDL interposer. [Figure 8]

[0017] FIG. 5 is a side view of the 3DIC package of FIG. 4 with its external interconnects bonded to a package substrate. [Figure 9]

[0018] FIG. 1 is a flowchart illustrating an example process for manufacturing a 3DIC package that includes an RDL interposer that facilitates extended die area for 3D stacking of a top die to a bottom die, and also includes one or more RDL metallization layers to provide signal routing paths for the top die and / or bottom die. [Figure 10A]

[0019] FIG. 11 is a flowchart illustrating another exemplary manufacturing process for manufacturing a 3DIC package that includes an RDL interposer that facilitates extended die area for 3D stacking of a top die to a bottom die, and also includes one or more RDL metallization layers to provide signal routing paths for the top die and / or bottom die. [Figure 10B] FIG. 11 is a flowchart illustrating another exemplary manufacturing process for manufacturing a 3DIC package that includes an RDL interposer that facilitates extended die area for 3D stacking of a top die to a bottom die, and also includes one or more RDL metallization layers to provide signal routing paths for the top die and / or bottom die. [Figure 10C]FIG. 11 is a flowchart illustrating another exemplary manufacturing process for manufacturing a 3DIC package that includes an RDL interposer that facilitates extended die area for 3D stacking of a top die to a bottom die, and also includes one or more RDL metallization layers to provide signal routing paths for the top die and / or bottom die. [Figure 10D] FIG. 11 is a flowchart illustrating another exemplary manufacturing process for manufacturing a 3DIC package that includes an RDL interposer that facilitates extended die area for 3D stacking of a top die to a bottom die, and also includes one or more RDL metallization layers to provide signal routing paths for the top die and / or bottom die. [Figure 11A]

[0020] 10A-10D illustrate exemplary manufacturing stages according to the exemplary 3DIC package manufacturing process. [Figure 11B] 10A-10D illustrate exemplary manufacturing stages according to the exemplary 3DIC package manufacturing process. [Figure 11C] 10A-10D illustrate exemplary manufacturing stages according to the exemplary 3DIC package manufacturing process. [Figure 11D] 10A-10D illustrate exemplary manufacturing stages according to the exemplary 3DIC package manufacturing process. [Figure 11E] 10A-10D illustrate exemplary manufacturing stages according to the exemplary 3DIC package manufacturing process. [Figure 11F] 10A-10D illustrate exemplary manufacturing stages according to the exemplary 3DIC package manufacturing process. [Figure 11G] 10A-10D illustrate exemplary manufacturing stages according to the exemplary 3DIC package manufacturing process. [Figure 11H] 10A-10D illustrate exemplary manufacturing stages according to the exemplary 3DIC package manufacturing process. [Figure 12]

[0021] A block diagram of an exemplary processor-based system that may include components that may include a 3DIC package, the 3DIC package including an RDL interposer that facilitates extended die area for 3D stacking of an upper die(s) to a lower die(s), and also including one or more RDL metallization layers to provide signal routing paths for the upper die and / or lower die, including but not limited to the 3DIC packages of Figures 2A-8 and Figures 11A-11H, and 3DIC packages according to the exemplary manufacturing processes of Figures 9 and Figures 10A-10D. [Figure 13]

[0022] FIG. 1 is a block diagram of an exemplary wireless communication device including radio-frequency (RF) components that may include a 3DIC package that may include a 3DIC package including an RDL interposer that facilitates extended die area for 3D stacking of an upper die(s) to a lower die(s), and also includes one or more RDL metallization layers to provide signal routing paths for the upper and / or lower die, including but not limited to the 3DIC packages of FIGS. 2A-8 and 11A-11H, and 3DIC packages according to the exemplary manufacturing processes of FIGS. 9 and 10A-10D. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011]

[0023] Several exemplary aspects of the present disclosure will now be described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0012]

[0024] Embodiments disclosed herein include three-dimensional (3D) integrated circuit (IC) (3DIC) packages that use redistribution layer (RDL) interposers to facilitate semiconductor die ("die") stacking. Related manufacturing methods are also disclosed. In an exemplary embodiment, the 3DIC package includes an RDL interposer having one or more RDL metallization layers formed adjacent to a first bottom die(s). The 3DIC package also includes a second top die(s) stacked vertically on the RDL interposer in a 3D stacked die configuration. The redistribution metallization layer(s) in the RDL interposer are metallization layer(s) that include metal interconnects (e.g., metal lines, metal traces) that provide branching connections (e.g., metal pads) from the die interconnects of the first bottom die and / or the second top die to other locations within the 3DIC package for signal routing. Also, by integrating the first bottom die to the RDL interposer, the RDL interposer provides an extended die area where a top die can be bonded to the RDL interposer and / or the first bottom die to provide a 3DIC package. In this way, as an example, the manufacturing process of the stacked top and bottom dies in the 3DIC package can be independent of whether the top die is larger than the bottom die in a top-larger-than-bottom (TGB) configuration or the bottom die is larger than the top die in a bottom-larger-than-top (BGT) configuration. The bottom die(s) can be singulated and placed on the formed RDL metallization layer(s) as part of the reconfigured RDL interposer. The top die can then be bonded to the RDL interposer regardless of whether the 3DIC package is in a TGB or BGT configuration. In a conventional 3DIC package manufacturing process, the smaller die is manufactured and singulated in a separate process and then bonded to the wafer on which the larger die is formed. The use of RDL interposers to facilitate 3D die stacking in a 3DIC package can be independent of further packaging, such as the implementation of an external bumping process to bond the 3DIC package to a package substrate.

[0013]

[0025] The RDL interposer in the 3DIC package, which is the substrate on which the bottom die(s) are placed and to which the top die is bonded, provides an efficient signal routing path to the top and bottom dies. In one example, the bottom die is bonded to metal interconnects in the redistribution metallization layer(s) in the RDL interposer to provide a signal routing path between the bottom die and the external interconnects of the 3DIC package (e.g., ball grid array (BGA) interconnects). The external interconnects may be bonded directly to the RDL interposer and / or the RDL metallization layer in the 3DIC package. In another example, the top die is bonded to metal interconnects in the outer redistribution metallization layer of the RDL interposer as a result of bonding the top die to the RDL interposer to provide a signal routing path(s) between the top die and the external interconnects of the 3DIC package. In another example, the top die is coupled to through silicon vias (TSVs) that extend through the bottom die to provide signal routing path(s) between the top die and the RDL interposer. When the bottom die is disposed within the RDL interposer, the top die may be vertically aligned with and coupled to the bottom die to provide die-to-die (D2D) interconnects between the top and bottom dies. Other dies may also be coupled to the RDL interposer outside the bottom die(s), with signal routing paths provided within the RDL interposer between such other dies and the top and / or bottom dies.

[0014]

[0026] Before discussing examples of 3DIC packages that include an RDL interposer that facilitates extended die area for 3D stacking of a top die(s) to a bottom die(s), and that also include one or more RDL metallization layers to provide signal routing paths for the top and / or bottom die, beginning with FIG. 2A , an exemplary top-over-bottom (TGB) three-dimensional (3D) integrated circuit (IC) (3DIC) package 100 (also referred to as “3DIC package 100”) that does not include an RDL interposer will first be described with reference to FIG. 1 .

[0015]

[0027] In this regard, Figure 1 is a side view of an exemplary IC package 100. The IC package 100 is a 3D stacked die IC package 102 that includes multiple dies 104(1), 104(2) contained in respective die packages 106(1), 106(2) stacked on top of one another in a vertical (Z-axis) direction. A first die package 106(1) of the IC package 100 includes a die 104(1) coupled to a package substrate 108. In this example, the package substrate 108 includes a first top metallization layer 110 disposed on a core substrate 112, also referred to herein as "metallization layer 110." The core substrate 112 is disposed on a second bottom metallization layer 114. The top metallization layer 110 provides an electrical interface for signal routing to the die 104(1). The die 104(1) is coupled to die interconnects 116 (e.g., raised metal bumps) that are electrically coupled to metal interconnects 118 in the top metallization layer 110. The metal interconnects 118 in the top metallization layer 110 are coupled to metal interconnects 120 in the core substrate 112, which are in turn coupled to metal interconnects 122 in the bottom metallization layer 114. In this manner, the package substrate 108 provides interconnects between its metallization layers 110, 114 and the core substrate 112 to provide signal routing to the die 104(1). External interconnects 124 (e.g., ball grid array (BGA) interconnects) are coupled to metal interconnects 122 in the bottom metallization layer 114 to provide interconnects through the package substrate 108, through the die interconnects 116, and to the die 104(1). In this example, a first active side 126(1) of the first die 104(1) is adjacent to and coupled to the package substrate 108, and more specifically, to the top metallization layer 110 of the package substrate 108.

[0016]

[0028] In the example IC package 100 of FIG. 1, a second die package 106(2) is provided and coupled to the first die package 106(1) to support multiple dies to provide 3D stacking of the dies. For example, the first die 104(1) in the first die package 106(1) may include an application processor, and the second die 104(1) may be a memory die, such as a dynamic random access memory (DRAM) die, that provides memory support for the application processor. In this regard, in this example, the first die package 106(1) also includes an interposer substrate 128 disposed on a package mold 130 that encapsulates the first die 104(1) adjacent to a second non-active side 126(2) of the first die 104(1). The interposer substrate 128 also includes one or more metallization layers 132, each including metal interconnects 134, for providing interconnection to the second die 104(2) in the second die package 106(2). The second die package 106(2) is physically and electrically coupled to the first die package 106(1) by being coupled to the interposer substrate 128 via external interconnects 136 (e.g., solder bumps, BGA interconnects). The external interconnects 136 are coupled to the metal interconnects 134 in the interposer substrate 128.

[0017]

[0029] Vertical interconnects 138 (e.g., metal vertical interconnect accesses (vias), such as metal pillars, metal posts, through-mold vias (TMVs) and the like) are disposed within the package mold 130 of the first die package 106(1) to provide interconnects for routing signals from the second die 104(2) through the external interconnects 136 and the interposer substrate 128 to the first die 104(1). The vertical interconnects 138 extend in a vertical direction (Z-axis direction) in this example from a first bottom surface 140 of the interposer substrate 128 to a first top surface 142 of the package substrate 108. The vertical interconnects 138 are coupled to metal interconnects 134 in the interposer substrate 128 adjacent the bottom surface 140 of the interposer substrate 128. The vertical interconnects 138 are also coupled to metal interconnects 118 in the top metallization layer 110 of the package substrate 108 adjacent the top surface 142 of the package substrate 108. In this manner, the vertical interconnects 138 provide a bridge for interconnections, such as input / output (I / O) connections, between the interposer substrate 128 and the package substrate 108. This provides a signal routing path through the package substrate between the second die 104(2) in the second die package 106(1) and the first die 104(1) and the external interconnects 124.

[0018]

[0030] 1, in the IC package 100, stacking of the second die 104(2) on top of the first die 104(1) is achieved by disposing the first die 104(1) and the second die 104(2) in respective first die packages 106(1) and second die packages 106(2). External interconnects 136 are formed for the second die package 106(2) to provide electrical signal routing paths through the interposer substrate 128 to the first die package 106(1). Vertical interconnects 138 are provided within the first die package 106(1) to provide signal routing paths to the second die 104(2). 1, die stacking is achieved by forming and stacking separate die packages 106(1), 106(2), which are coupled together via external interconnects 138, interposer substrate 128, and vertical interconnects 138. External interconnects 138, interposer substrate 128, and vertical interconnects 138 contribute to an overall height H1 of IC package 100. It may be desirable to minimize the height of a 3D stacked IC package, such as IC package 100. It may also be desirable to simplify the manufacture of IC package 100, such that the formation of separate die packages 106(1), 106(2) and interposer substrate 128 is not required to provide first die 104(1) and second die 104(2) in a 3D stacked configuration within the IC package.

[0019]

[0031] 2A and 2B are side views of an example 3DIC package 200 including a reconfigured interposer 202 to facilitate 3D stacking of dies in the vertical direction (Z-axis direction) and provide signal routing to the dies in an efficient manner. In this example, the interposer 202 is an RDL interposer 202 in that the interposer 202 includes one or more RDL metallization layers. The interposer 202 is also referred to herein as an "RDL interposer 202." An RDL interposer, such as the RDL interposer 202 of FIGS. 2A and 2B, includes one or more RDL metallization layers including metal interconnects (e.g., metal lines, metal traces) that can provide branched connections (e.g., metal pads) for signal routing from one portion of an IC package to another location within the IC package to provide better access to such connections. To facilitate smaller (e.g., greater line / space (L / S) density) die interconnects (e.g., microbumps) for die connection, the RDL metallization layer includes additional metal layers that rewire (i.e., reroute) connection access to different parts of the IC package, including outside the area where the die are connected within the package, and link metal interconnects. In this example, the 3DIC package 200 of FIG. 2A is configured in a bottom die larger than top die (BGT) configuration. As shown in FIG. 2A, the 3DIC package 200 includes a plurality of first bottom dies 204(1)-204(3). The 3DIC package 200 also includes a second top die 206 stacked vertically (Z-axis direction) on top of the bottom dies 204(1)-204(3). The lower dies 204(1)-204(3) are integrated into the RDL interposer 202 as a reconfigured RDL interposer to facilitate 3D stacking of the upper die 206 above the lower dies 204(1)-204(3) in a height-efficient manner within the 3DIC package 200 while also providing an effective manner of providing signal routing for the upper die 206 and the lower dies 204(1)-204(3). The upper die 206 shares common vertical planes P1, P2, P3 with each of the lower dies 204(1)-204(3).The RDL interposer 202 extends in the horizontal direction (X-axis direction and Y-axis direction). By integrating the lower dies 204(1)-204(3) with the RDL interposer 202, the lower dies 204(1)-204(3) do not need to be formed in separate die packages that are then bumped to external interconnects to connect the lower dies 204(1)-204(3) in the 3DIC package. The RDL interposer 202 also provides an extended die area in the horizontal direction (X-axis direction and Y-axis direction) to which the upper die 206 is coupled. The upper die 206 is coupled (e.g., stacked) in a 3D stacked die configuration as part of the 3DIC package 200 in a vertical direction (Z-axis direction) perpendicular to the horizontal direction (X-axis direction and Y-axis direction) to a first top surface 212 of the RDL interposer 202 opposite a second outer surface 214 of the RDL interposer 202. The RDL metallization layer 208 of the RDL interposer 202 is disposed between the first surface 212 and the second surface 214. In this manner, the RDL interposer 202 provides a structure for the top die 206 to be stacked above the bottom dies 204(1)-204(3) in a 3D stacked configuration, such that the 3DIC package 200, whether in a BGT configuration (as shown in FIG. 2A) or a TGB configuration, can be manufactured using the same process.

[0020]

[0032] In this manner, by integrating the first lower die 204(1)-204(3) to the RDL interposer 202, the RDL interposer 202 provides an expanded die area to which the upper die 206 may be coupled to the RDL interposer 202. In this manner, as an example, the manufacturing process for producing the 3DIC package 200 may be independent of whether the upper die 206 is larger in horizontal area (X-axis and Y-axis directions) than the lower dies 204(1)-204(3) in a TGB configuration, or whether the lower dies 204(1)-204(3) are larger in horizontal area (X-axis and Y-axis directions) than the upper die 206 in a BGT configuration. The lower dies 204(1)-204(3) may be singulated and disposed within or adjacent to the RDL metallization layer 208 as part of a reconstructed RDL interposer 202. The top die 206 can then be bonded to the RDL interposer 202 regardless of whether the 3DIC package 200 is in a TGB or BGT configuration. In a conventional 3DIC package manufacturing process, smaller dies are manufactured and singulated in a separate process and then bonded to the wafer on which the larger dies are formed. The use of an RDL interposer to facilitate 3D die stacking in a 3DIC package can be independent of further packaging, such as performing an external bumping process to bond the 3DIC package to a package substrate.

[0021]

[0033] 2A , the RDL interposer 202 in the 3DIC package 200, which is the substrate on which the bottom dies 204(1)-204(3) are disposed and to which the top die 206 is bonded, provides an efficient signal routing path to the bottom dies 204(1)-204(3) and the top die 206. The RDL interposer 202 provides a metallization structure that provides signal routing for the bottom dies 204(1)-204(3) and the top die 206 in the 3DIC package 200. In this example, the RDL interposer 202 includes a first RDL metallization layer 208 formed on an interposer substrate 210 (e.g., a silicon interposer substrate). The interposer substrate 210 may also be the RDL metallization layer. The RDL metallization layer 208 is a metallization layer that includes metal interconnects 216 (e.g., metal lines, metal traces) that provide signal routing paths within the RDL interposer 202 for the bottom dies 204(1)-204(3) and the top die 206. To integrate the bottom dies 204(1)-204(3) with the RDL interposer 202, the bottom dies 204(1)-204(3) are positioned adjacent to the RDL metallization layer 208 within the RDL interposer 202.

[0022]

[0034] In this example, the bottom dies 204(1)-204(3) are coupled to metal interconnects 216(1) in the first RDL metallization layer 208 to provide a signal routing path between the bottom dies 204(1)-204(3) and external interconnects 217 (e.g., solder balls) of the 3DIC package 200. In this example, as a result of coupling the top die 206 to the first exterior surface 212 of the RDL interposer 202, the top die 206 is coupled to metal interconnects 216(2) in the RDL metallization layer 208 of the RDL interposer 202 that are branched in an area outside the top die 206. This provides a signal routing path between the top die 206 and external interconnects 217 of the 3DIC package 200. 2A , the top die 206 is coupled to respective through silicon vias (TSVs) 218(1)-218(3) that extend through the bottom dies 204(1)-204(3) to provide signal routing paths between the top die 206 and the RDL interposer 202. The top die 206 is also shown as being vertically aligned (in the Z-axis direction) with and coupled to the bottom dies 204(1)-204(3) to provide die-to-die (D2D) interconnections between the top die 206 and the bottom dies 204(1)-204(3) when the bottom dies 204(1)-204(3) are disposed within the RDL interposer 202. 2A , using any of the signal routing examples described above, signals may be further routed to interposer substrate 210 through metal interconnects 219(3) (e.g., through mold vias (TMVs)) coupled to metal interconnects 216 formed in one or more metallization layers 220(1)-220(2) of interposer substrate 210. Metallization layers 220(1)-220(2) may also be RDL metallization layers. Thus, signals may be routed through metal interconnects 219 of interposer substrate 210 to external interconnects 217, which in this example are coupled to printed circuit board (PCB) 222.

[0023]

[0035] FIG. 2B is another side view illustrating the 3DIC package 200 to discuss additional exemplary details. As shown in FIG. 2B, the top die 206 has die interconnects 224 (e.g., die pads) exposed through an active surface 226 of the top die 206 for coupling the top die 206 to the RDL interposer 202. The die interconnects 224 are coupled to the RDL interposer 202 to provide signal routing between the top die 206 and the RDL interposer 202 and / or to the bottom dies 204(1)-204(3). The die interconnects 224 of the top die 206 may be coupled to metal interconnects 216(2) in the RDL metallization layer 208 that are branched horizontally (in the X-axis and Y-axis directions) in regions A1, A2 outside the top die 206 to provide signal routing path(s) to the RDL interposer 202. In this example, bottom dies 204(1)-204(3) also each have a respective die interconnect 228(1)-228(3) (e.g., die pad) exposed through a respective active surface 230(1)-230(3). Top die 206 may be directly bonded to bottom dies 204(1)-204(3) by bonding the individual die interconnects 224 of top die 206 to the die interconnects 228(1)-228(3) of bottom dies 204(1)-204(3), such as through the use of hybrid bonding, compression bonding, or microbumps. It should be noted that in an alternative configuration, the bottom dies 204(1)-204(3) may be disposed within the RDL interposer 202 in an inverted configuration relative to that shown in FIG. 2B , such that their respective backside non-active surfaces 232(1)-232(2) are adjacent to and face the active surface 226 of the top die 206.

[0024]

[0036] Also, in this example, vias 218(1)-218(3) (e.g., through silicon vias (TSVs)) may be disposed through each of the lower dies 204(1)-204(3) and coupled to die interconnects 224 of the top die 206 to provide signal routing paths from the top die 206 to the RDL interposer 202 below the lower dies 204(1)-204(3) that bypass the lower dies 204(1)-204(3). The vias 218(1)-218(3) are routed to respective metal interconnects 219(2) in the RDL metallization layer 208, which are coupled to metal interconnects 216 in the interposer substrate 210.

[0025]

[0037] 2A and 2B, the RDL interposer 202 in the 3DIC package 200 provides a metallization structure that can provide efficient signal routing for the top die 206 and bottom die 204(1)-204(3), as well as providing a structure onto which the top die 206 can be stacked. In this manner, the 3DIC package 200 provides an efficient stacked die configuration. Other stacked die configurations are possible using an RDL interposer, such as the RDL interposer 202 of FIGs. 2A and 2B, to facilitate efficient signal routing between stacked dies and provide a structure onto which the top die can be stacked.

[0026]

[0038] In this regard, FIG. 3 is a side view of another exemplary 3DIC package 300 that also includes a reconfigured interposer 302 that facilitates 3D stacking of dies in the vertical direction (Z-axis direction) and provides signal routing to the dies in an efficient manner. In this example, the interposer 302 is an RDL interposer 302 in that the interposer includes one or more RDL metallization layers. The interposer 302 is also referred to herein as an "RDL interposer 302." In this example, the 3DIC package 300 of FIG. 3 is configured in a TGB configuration. As shown in FIG. 3, the 3DIC package 300 includes a bottom die 304. The 3DIC package 300 also includes multiple second top dies 306(1), 306(2) stacked vertically (Z-axis direction) on top of the bottom die 304. In this example, the bottom die 304 is integrated into the RDL interposer 302 as a reconfigured RDL interposer to facilitate 3D stacking of the top dies 306(1), 306(2) above the bottom die 304 in a height-efficient manner within the 3DIC package 300 while also providing an effective manner of providing signal routing for the top dies 306(1), 306(2) and the bottom die 304. The top dies 306(1), 306(2) share common vertical planes P4, P5 with the bottom die 304. The RDL interposer 302 extends in the horizontal direction (X-axis direction and Y-axis direction). By integrating the bottom die 304 into the RDL interposer 302, the bottom die 304 does not need to be formed into a separate die package that is then bumped to external interconnects to connect the bottom die 304 in the 3DIC package. The RDL interposer 302 also provides an extended die area horizontally (in the x-axis and y-axis directions) to which the top dies 306(1), 306(2) are coupled. The top dies 306(1), 306(2) are coupled (e.g., stacked) in a 3D stacked die configuration as part of the 3DIC package 300 to a first top surface 312 of the RDL interposer 302 opposite a second outer surface 314 of the RDL interposer 302 in a vertical direction (in the z-axis direction) orthogonal to the horizontal directions (in the x-axis and y-axis directions).The RDL metallization layer 308 of the RDL interposer 302 is disposed between the first surface 312 and the second surface 314. In this manner, the RDL interposer 302 provides a structure for the top die 206 to be stacked above the bottom dies 204(1)-204(3) in a 3D stacked configuration, such that the 3DIC package 300 can be manufactured using the same process, whether in a BGT configuration (as shown in FIG. 2A) or a TGB configuration.

[0027]

[0039] In this manner, by integrating the first bottom die 304 to the RDL interposer 302, the RDL interposer 302 provides an expanded die area to which the top dies 306(1), 306(2) may be coupled to the RDL interposer 302. In this manner, as an example, the manufacturing process for producing the 3DIC package 300 may be independent of whether the top dies 306(1), 306(2) are larger in horizontal area (X-axis and Y-axis directions) than the bottom die 304 in a TGB configuration, or whether the bottom die 304 is larger in horizontal area (X-axis and Y-axis directions) than the top dies 306(1), 306(2) in a BGT configuration as shown in FIG. The bottom die 304 may be located within or adjacent to the RDL metallization layer 308 as part of a singulated and reconstructed RDL interposer 302. The top die 306(1), 306(2) may then be coupled to the RDL interposer 302, regardless of whether the 3DIC package 300 is in a TGB or BGT configuration. In a conventional 3DIC package manufacturing process, smaller dies are manufactured and singulated in a separate process and then bonded to the wafer on which the larger die is formed. The use of an RDL interposer to facilitate 3D die stacking in a 3DIC package may be independent of further packaging, such as performing an external bumping process to bond the 3DIC package to a package substrate.

[0028]

[0040] 3, the RDL interposer 302 in the 3DIC package 300, which is the substrate on which the bottom die 304 is disposed and to which the top dies 306(1), 306(2) are bonded, provides an efficient signal routing path to the bottom die 304 and the top dies 306(1), 306(2). The RDL interposer 302 provides a metallization structure that provides signal routing for the bottom die 304 and the top dies 306(1), 306(2) in the 3DIC package 300. In this example, the RDL interposer 302 includes a first RDL metallization layer 308 formed on an interposer substrate 210 (e.g., a silicon interposer substrate) as shown in the 3DIC package 200 of FIGS. 2A and 2B. The RDL metallization layer 308 is a metallization layer that includes metal interconnects 316 (e.g., metal lines, metal traces) that provide signal routing paths for the bottom die 304 and top die 306(1), 306(2) within the RDL interposer 302. To integrate the bottom die 304 into the RDL interposer 302, the bottom die 304 is positioned adjacent to the RDL metallization layer 308 within the RDL interposer 302.

[0029]

[0041] In this example, the bottom die 304 is bonded to metal interconnects 316(1) within the first RDL metallization layer 308 to provide a signal routing path between the bottom die 304 and the external interconnects 217 of the 3DIC package 300. In this example, as a result of bonding the top dies 306(1), 306(2) to the first exterior surface 312 of the RDL interposer 302, the top dies 306(1), 306(2) are bonded to metal interconnects 316(2) that are branched in the RDL metallization layer 308 of the RDL interposer 302 in an area outside the top dies 306(1), 306(2). This provides a signal routing path between the top dies 306(1), 306(2) and the external interconnects 317 of the 3DIC package 300. 3, the top dies 306(1), 306(2) are coupled to through silicon vias (TSVs) 318 that extend through the bottom die 304 to provide signal routing paths between the top dies 306(1), 306(2) and the RDL interposer 302. The top dies 306(1), 306(2) are also shown as being vertically aligned (in the Z-axis direction) with and coupled to the bottom die 304 to provide die-to-die (D2D) interconnections between the top dies 306(1), 306(2) and the bottom die 304 when the bottom die 304 is disposed within the RDL interposer 302. 3, using any of the signal routing examples discussed above, signals may be further routed to interposer substrate 210 through metal interconnect 219(3), which is coupled to metal interconnect 316 formed in one or more metallization layers 220(1)-220(2) of interposer substrate 210. Thus, signals may be routed through metal interconnect 219 of interposer substrate 210 to external interconnect 217, which in this example is coupled to printed circuit board (PCB) 222.

[0030]

[0042] 3 , the top dies 306(1), 306(2) have die interconnects 324(1), 324(2) (e.g., die pads) exposed through respective active surfaces 326(1), 326(2) of the top dies 306(1), 306(2) for coupling the top dies 306(1), 306(2) to the RDL interposer 302. The die interconnects 324(1), 324(2) are coupled to the RDL interposer 302 to provide signal routing between the top dies 306(1), 306(2) and the RDL interposer 302 and / or to the bottom die 304. The die interconnects 324(1), 324(2) of the top die 306 may be coupled to metal interconnects 316(2) in the RDL metallization layer 308, which branch off horizontally (in the X-axis and Y-axis directions) in areas A3, A4 outside the top die 306(1), 306(2) to provide signal routing path(s) to the RDL interposer 302. In this example, the bottom die 304 also has die interconnects 328 (e.g., die pads) exposed through an active surface 330 of the bottom die 304. The top die 306(1), 306(2) may be directly coupled to the bottom die 304 by coupling the individual die interconnects 324(1), 324(2) of the top die 306(1), 306(2) to the die interconnects 328 of the bottom die 304, such as through the use of hybrid bonding, compression bonding, or microbumps, as examples. It should be noted that in an alternative configuration, the bottom die 304 may be positioned within the RDL interposer 302 in an inverted configuration relative to that shown in FIG. 3 such that its backside, inactive surface 332 is adjacent to and faces the active surfaces 326(1), 326(2) of the top dies 306(1), 306(2).

[0031]

[0043] Also in this example, vias 318 (e.g., through silicon vias (TSVs)) may be disposed through the lower die 304 and coupled to die interconnects 324(1), 324(2) of the upper dies 306(1), 306(2) to provide signal routing paths from the upper dies 306(1), 306(2) to the RDL interposer 302 below the lower die 304, bypassing the lower die 304. The vias 318 are routed to respective metal interconnects 219(1) in the RDL metallization layer 308, which are coupled to metal interconnects 316 in the interposer substrate 210.

[0032]

[0044] FIG. 4 is a side view of another exemplary 3DIC package 400 similar to the 3DIC package 200 of FIG. 2A and FIG. 2B. Common elements between the 3DIC package 400 of FIG. 4 and the 3DIC package 200 of FIG. 2A and FIG. 2B are indicated with common element numbers and therefore will not be described again. As shown in FIG. 4, the 3DIC package 300 includes additional dies 406(1), 406(2) coupled to an interposer 402. In this example, the interposer 402 is an RDL interposer 202 in that the interposer 402 includes one or more RDL metallization layers. The interposer 402 is also referred to herein as an "RDL interposer 402." The RDL interposer 402 is similar to the RDL interposer 202 of FIG. 2A and FIG. 2B, and common elements are indicated with common element numbers. The additional dies 406(1), 406(2) are coupled to the RDL interposer 402 in a two-and-a-half-dimensional (2.5D) configuration, with the additional dies 406(1), 406(2) being horizontally (in the X-axis and Y-axis directions) in respective areas A5, A6 outside the area A7 of the top die. Thus, in the 3DIC package 400 of FIG. 4, the RDL interposer 402 also supports the additional dies 406(1), 406(2). The RDL interposer 402, which increases the die area for coupling dies, in this example, provides additional area for incorporating and coupling the additional dies 406(1), 406(2) within the 3DIC package 400. For example, the additional dies 406(1), 406(2) can be memory dies. The RDL interposer 402 not only provides an area to which the additional dies 406(1), 406(2) may be coupled, but also provides an interposer for signal routing between the additional dies 406(1), 406(2) and the RDL interposer 402, similar to the top die 206.

[0033]

[0045] In this example, external metal interconnects 410(1), 410(2) (e.g., solder bumps, microbumps, die pads) coupled to the additional die 406(1), 406(2) are coupled to the first top surface 212 of the RDL interposer 402 to couple the additional die 406(1), 406(2) to the RDL interposer 402. The external metal interconnects 410(1), 410(2) are coupled to the RDL interposer 402 to provide signal routing between the additional die 406(1), 406(2) and the RDL interposer 402 and / or to the bottom die 304 and / or top die 206(1), 206(2). External metal interconnects 410(1), 410(2) of additional die 406(1), 406(2) may be coupled to metal interconnects 416(3) (e.g., TMVs) in RDL metallization layer 408 that branch off horizontally (X-axis and Y-axis directions) in regions A5, A6 outside region A7 of top die 206 to provide signal routing path(s) to RDL interposer 402. External metal interconnects 410(1), 410(2) may be coupled to external interconnects 217 and bottom dies 204(1)-204(3) through other metal interconnects 416(1), 416(2) and / or to top die 206 through vias 218(1)-218(3).

[0034]

[0046] 4, the RDL interposer 402 in the 3DIC package 400 provides a metallization structure that can provide efficient signal routing for the additional dies 406(1), 406(2), as well as providing a structure onto which the additional dies 406(1), 406(2) can be stacked. In this manner, the 3DIC package 400 provides an efficient stacked die configuration.

[0035]

[0047] FIG. 5 is a side view of another exemplary 3DIC package 500 in a BGT configuration, similar to the 3DIC package 400 of FIG. 4. Common elements between the 3DIC package 500 of FIG. 5 and the 3DIC package 400 of FIG. 4 are indicated with common element numbers and therefore will not be described again. However, in the 3DIC package 500 of FIG. 5, instead of providing an additional die 406(2), another die 504 is provided in an outer area A8 in the horizontal direction (X-axis direction and Y-axis direction) of the top die 206 and the bottom die 204(1)-204(3). The die 504 can be another functional die or chiplet that does not need to communicate with the top die 206, and therefore does not need to be vertically aligned to have a common plane with the top die 206. However, in this example, the die 504 is coupled to metal interconnects 216(3) in the RDL metallization layer 408 to provide signal routing between the die 504 and the RDL interposer 402.

[0036]

[0048] FIG. 6 is a side view of another exemplary 3DIC package 600 in a BGT configuration, similar to the 3DIC package 400 of FIG. 4. Common elements between the 3DIC package 600 of FIG. 6 and the 3DIC package 400 of FIG. 4 are indicated with common element numbers and therefore will not be described again. However, in the 3DIC package 600 of FIG. 6, an interposer 602 is provided that includes the RDL metallization layer 408 in the 3DIC package 400 of FIG. 4. In this example, the interposer 602 is an RDL interposer 602 in that the interposer 602 includes one or more RDL metallization layers. The interposer 602 is also referred to herein as an "RDL interposer 602." However, the RDL interposer 602 of FIG. 6 includes an additional RDL metallization layer 608 disposed vertically (Z-axis direction) between the top die 206(1)-206(3) and the bottom die 204(1)-204(3). The bottom dies 204(1)-204(3) are disposed within an RDL metallization layer 408, which is separated from the top dies 204(1)-204(3) via an intermediate RDL metallization layer 608. Providing an additional RDL metallization layer 608 may provide improved routing capabilities and / or flexibility in the 3DIC package 600.

[0037]

[0049] 6, to couple the top die 206 to the RDL interposer 602, the die interconnects 224 (e.g., die pads) exposed through the active surface 226 of the top die 206 are coupled to a top surface 612 of the RDL interposer 602. The coupling of the die interconnects 224 to the RDL interposer 602 provides signal routing between the top die 206 and the RDL interposer 602 and / or to the bottom dies 204(1)-204(3). To provide the signal routing path(s) to the RDL interposer 602, the die interconnects 224 of the top die 206 are coupled to metal interconnects 616(1) in the RDL metallization layer 608. Metal interconnects 616(1) in the RDL interposer 602 may be routed to lower dies 204(1)-204(3) or other metal interconnects 616(2), 616(3) in the RDL interposer 602 to route signals to additional die 406(1), 406(2), bottom dies 204(1)-204(3), and / or external interconnects 217. Bottom dies 204(1)-204(3) also have respective die interconnects 228(1)-228(3) (e.g., die pads) that may be coupled to metal interconnects 616(1) in the RDL metallization layer 608 to provide signal routing paths to the top die 204. Also, in this example, metal interconnects 616(1) coupled to die interconnects 224 of top die 206 may be coupled to vias 218(1)-218(3) disposed through respective bottom dies 204(1)-204(3) in a manner similar to that previously described in the 3DIC package 200 of Figures 2A and 2B to provide signal routing paths from top die 206 to RDL interposer 602 beneath bottom dies 204(1)-204(3). Vias 218(1)-218(3) are routed to respective metal interconnects 219(2) in RDL metallization layer 208 that are coupled to metal interconnects 216 in interposer substrate 210. Metal interconnects 616(2), 616(3) (e.g., TMVs) are also disposed through the RDL metallization layer 608 to provide connections between the additional die 406(1), 406(2) and the RDL interposer 602.

[0038]

[0050] FIG. 7 is a side view of another exemplary 3DIC package 700, similar to the 3DIC package 400 of FIG. 4. Common elements between the 3DIC package 700 of FIG. 7 and the 3DIC package 400 of FIG. 4 are indicated with common element numbers and therefore will not be described again. As shown in FIG. 7, a top die 706 is integrated into a chiplet 702 coupled to an RDL interposer 408. The chiplet 702 includes an integrated decoupling capacitor 708 that provides decoupling capacitance between the RDL interposer 402 and the top die 706. The top die 706 is stacked vertically (Z-axis direction) on top of the decoupling capacitor 708 in the chiplet 702. Metal interconnects 724 of the chiplet 702 are coupled to the RDL interposer 402 to provide decoupling capacitors 708 and signal routing between the top die 706 and the RDL interposer 402, similar to the die interconnects 224 of the top die 206 in the 3DIC package 400 of Figure 4. To provide signal routing between the top die 706 and the RDL interposer 408, the chiplet 702 includes vias 710 that extend vertically through the chiplet 702 and are coupled to the top die 706.

[0039]

[0051] A 3DIC package as described in the above example may also be provided as part of another IC package including a package substrate to provide additional signal routing options. In this regard, FIG. 8 is a side view of the 3DIC package 400 of FIG. 4. Common elements between the 3DIC package 800 of FIG. 8 and the 3DIC package 400 of FIG. 4 are indicated with common element numbers and therefore will not be described again. However, as shown in FIG. 8, the 3DIC package 400 is not directly bonded to the PCB 222, but rather to a package substrate 802. The package substrate 802 includes one or more metallization layers having metal interconnects for providing signals. The 3DIC package 400 is bonded to the package substrate 802 via external interconnects 804, which in this example are BGA interconnects. The package substrate 802 is bonded to the PCB 222 via external interconnects 217.

[0040]

[0052] 9 is a flow chart illustrating an example manufacturing process 900 for manufacturing a 3DIC package, including but not limited to the 3DIC packages of FIGS. 2A-8, that includes an RDL interposer to facilitate extended die area for 3D stacking of top die(s) to bottom die(s) and also includes one or more RDL metallization layers to provide signal routing paths for the top and / or bottom die. The manufacturing process 900 of FIG. 9 is described with respect to the 3DIC package 200 of FIGS. 2A and 2B. However, it should be noted that the manufacturing process 900 of FIG. 9 may also be used to manufacture the other 3DIC packages 300, 400, 500, 600, 700, 800 of FIGS. 3-8.

[0041]

[0053] In this regard, as shown in FIG. 9 , a first step in a manufacturing process 900 is to place first dies 204(1)-204(3) on a substrate (block 902 of FIG. 9 ). A next step in the manufacturing process 900 is to form an RDL interposer 202 (block 904 of FIG. 9 ). Forming the RDL interposer 202 may include forming a first RDL metallization layer 208 on the substrate adjacent to the first dies 204(1)-204(3) (block 906 of FIG. 9 ), the first RDL metallization layer 208 having a first surface 212 and a second surface 214 opposite the first surface 212, and bonding the first die interconnects 228(1)-228(3) of the first dies 204(1)-204(3) to the first metal interconnects 216 in the first RDL metallization layer 208 (block 908 of FIG. 9 ). The next step in the manufacturing process 900 is to bond the second die 206 bonded to the first surface 212 of the RDL interposer 202 (block 910 of FIG. 9 ). The next step in the manufacturing process 900 is to bond the second die interconnects 224 of the second die 206 to the first RDL metallization layer 208 (block 912 of FIG. 9 ).

[0042]

[0054] 3DIC packages including an RDL interposer that facilitates an extended die area for 3D stacking of top die(s) to bottom die(s) and also includes one or more RDL metallization layers to provide signal routing paths for the top and / or bottom die, including but not limited to the 3DIC packages of Figures 2A-7, including the 3DIC packages 200, 300, 400, 500, 600, 700, 800 of Figures 2A-8, respectively, may be manufactured in other manufacturing processes. For example, Figures 10A-10D are a flow chart illustrating an exemplary manufacturing process 1000 for manufacturing a 3DIC package including a top die(s) coupled to an RDL interposer that includes a bottom die(s), where the RDL interposer also provides signal routing paths for the top and / or bottom die. Figures 11A-11H show exemplary manufacturing stages 1100A-1100H according to the exemplary 3DIC manufacturing process 1000 of Figures 10A-10D. The manufacturing process 1000 of Figures 10A-10D is not limited to manufacturing the 3DIC package 200 of Figures 2A and 2B.

[0043]

[0055] In this regard, as shown in the exemplary manufacturing stage 1100A of FIG. 11A, the first step in the manufacturing process 1000 is to provide a die 1104 (block 1002 of FIG. 10A) that will serve as the bottom die in the final 3DIC package. The die 1104 may be manufactured as part of a separate manufacturing process in which multiple dies 1104 are formed on a semiconductor wafer and then diced and cleaned to form the individual dies 1104. As shown in the exemplary manufacturing stage 1100B of FIG. 11B, the next step in the manufacturing process 1000 is to bond (attach) the die 1104 to the carrier 1102 (block 1004 of FIG. 10A). This allows the die 1104 to be manipulated by handling the carrier 1102 during the manufacturing process 1000. An active surface 1130 of the bottom die 1104 is coupled to the first top surface 1106 of the carrier 1102 such that the die interconnects 1128 are adjacent to the first top surface 1106 of the carrier 1102 .

[0044]

[0056] As shown in the exemplary manufacturing stage 1100C of FIG. 11C, the next step in the manufacturing process 1000 is to bond and form an overmold layer 1107 over the die 1104 bonded to the carrier 1102 (block 1006 of FIG. 10B). The overmold layer 1108 is formed by disposing the overmold material 1100 over the die 204 and adjacent to the die 204 on the first surface 1106 of the carrier 1102. The overmold layer 1107 protects and insulates the die 1104. As an example, the overmold layer 1107 may be formed by spinning on or otherwise disposing an oxide layer 1112 over the die 204 and adjacent to the die 204 on the first surface 1106 of the carrier 1102. Then, as shown in the exemplary manufacturing stage 1100D of FIG. 11D, the next step in the manufacturing process 1000 is to form a first RDL metallization layer 1108 from the overmold layer 1107. The first RDL metallization layer 1108 is formed by forming rerouted metal interconnects 1120 in the overmold layer 1107 to the first surface 1106 of the carrier 1102 and forming vias 1118 in the overmold layer 1107 through the die 1104 to be coupled to the die interconnects 1128 (block 1008 of FIG. 10B). As an example, the metal interconnects 1120 are through-mold vias (TMVs). The metal interconnects 1120 and the vias 1118 may be formed by a metal (e.g., copper) plating process, where the overmold layer 1107 is patterned to form openings in which the metal interconnects 1120 and the vias 1118 will be formed. A metal material is then placed into the opening, the remaining residual metal material on the top surface 1114 of the overmold layer 1107 (Figure 11C) is polished away, and the overmold layer 1107 is ground away to remove the residual metal material and expose the metal interconnects 1120 and vias 1118 through the top surface 1116 of the overmold layer 1107 (Figure 11D).

[0045]

[0057] As shown in the exemplary manufacturing stage 1100E of FIG. 11E, the next step in the manufacturing process 1000 is to form another RDL metallization layer 1124 as an interposer substrate on the first RDL metallization layer 1108 on which the lower die 1104 is disposed (block 1010 of FIG. 10C). Metal interconnects 1122 are formed as part of the formation of the second RDL metallization layer 1124. The metal interconnects 1122 are coupled to the metal interconnects 1120 and to the vias 1118 that extend through the first RDL metallization layer 1108. As shown in the exemplary manufacturing stage 1100F of FIG. 11F, the next step in the manufacturing process 1000 is to remove the carrier 1102 from the first RDL metallization layer 1108 (block 1012 of FIG. 10C). The top surface 1126 of the first RDL metallization layer 1108 may then be cleaned. The first RDL metallization layer 1108 and the second RDL metallization layer 1124 are for an RDL interposer 1125 in this example.

[0046]

[0058] Then, as shown in the exemplary manufacturing stage 1100G of FIG. 11G, the next step in the manufacturing process 1000 is to bond (e.g., bond) the top die 1134 to the top surface 1126 of the bottom die 1104 and the first RDL metallization layer 1108 to form a 3DIC package 1136 (block 1014 of FIG. 10D). The die interconnects 1138 of the top die 1134 are aligned with the exposed surfaces of the metal interconnects 1120 and die interconnects 1128 of the bottom die 1104 to bond the die interconnects 1138 of the top die 1134 to the metal interconnects 1120 and the vias 1118 that extend through the bottom die 1104. This is a die-to-wafer bonding or bonding process. This die-to-wafer bonding or bonding process provides an electrical bond between the top die 1134 and the RDL interposer 1125. As shown in the exemplary manufacturing stage 1100H of Figure 11H, the next step in the manufacturing process 1000 is then to form an overmold layer 1140 over the top die 1134 and adjacent to the top die 1134 on the first RDL metallization layer 1108 to form a 3DIC package 1136 (block 1016 of Figure 10D). External interconnects 1142 are also formed that contact the metal interconnects in the RDL interposer 1125.

[0047]

[0059] 3DIC packages including an RDL interposer that facilitates extended die area for 3D stacking of a top die(s) to a bottom die(s) and including one or more RDL metallization layers to provide signal routing paths for the top die and / or bottom die, including but not limited to the 3DIC packages of FIGS. 2A-8 and 11A-11H and according to the exemplary manufacturing processes of FIGS. 9 and 10A-10D and according to any embodiment disclosed herein, may be provided or integrated into any processor-based device. Examples include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.

[0048]

[0060] In this regard, FIG. 12 illustrates an example of a processor-based system 1200. A component of the processor-based system 1200 is an IC 1202. Some or all of the ICs 1202 in the processor-based system 1200 may be provided as a 3DIC package including an RDL interposer that facilitates an extended die area for 3D stacking of the top die(s) to the bottom die(s) and also includes one or more RDL metallization layers to provide signal routing paths for the top and / or bottom die, including but not limited to 3DIC packages according to the exemplary manufacturing processes of FIGS. 2A-8 and 11A-11H and 9 and 10A-10D and according to any aspect disclosed herein. In this example, the processor-based system 1200 may be formed as an IC package 1204 and as a system-on-chip (SoC) 1206. The processor-based system 1200 includes a CPU 1208 that includes one or more processors 1210, sometimes referred to as a CPU core or processor core. The CPU 1208 may have a cache memory 1212 coupled to the CPU 1208 for rapid access to temporarily stored data. The CPU 1208 is coupled to a system bus 1214, which may interconnect master and slave devices included within the processor-based system 1200. As is well known, the CPU 1208 communicates with these other devices by exchanging address, control, and data information via the system bus 1214. For example, the CPU 1208 may communicate bus transaction requests to a memory controller 1216, an example of a slave device. Although not shown in FIG. 12, multiple system buses 1214 may be provided, with each system bus 1214 constituting a different fabric.

[0049]

[0061] Other master and slave devices may be connected to the system bus 1214. As shown in FIG. 12, these devices may include, by way of example, a memory system 1220 including a memory controller 1216 and a memory array(s) 1218, one or more input devices 1222, one or more output devices 1224, one or more network interface devices 1226, and one or more display controllers 1228. Each of the memory system 1220, the one or more input devices 1222, the one or more output devices 1224, the one or more network interface devices 1226, and the one or more display controllers 1228 may be provided in the same or different circuit packages. The input device(s) 1222 may include any type of input device, including, but not limited to, input keys, switches, audio processors, and the like. The output device(s) 1224 may include any type of output device, including, but not limited to, audio indicators, video indicators, other visual indicators, and the like. The network interface device(s) 1226 may be any device configured to enable the exchange of data with the network 1230. The network 1230 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s) 1226 may be configured to support any type of communication protocol desired.

[0050]

[0062] The CPU 1208 may also be configured to access a display controller(s) 1228 via the system bus 1214 to control information sent to one or more displays 1232. The display controller(s) 1228 sends information to be displayed to the display(s) 1232 via one or more video processors 1234, which process the information to be displayed into a format suitable for the display(s) 1232. The display controller(s) 1228 and the video processor(s) 1234 may be included as the IC package 1204, and in the same or different circuit package, as well as within the same or different circuit package that includes the CPU 1208, by way of example. The display(s) 1232 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0051]

[0063] FIG. 13 illustrates an example wireless communication device 1300 including a radio frequency (RF) component formed from one or more ICs 1302. Any of the ICs 1302 may include a 3DIC package including an RDL interposer that facilitates an extended die area for 3D stacking of the top die(s) to the bottom die(s) and also includes one or more RDL metallization layers to provide signal routing paths for the top die and / or bottom die, including but not limited to 3DIC packages according to the example manufacturing processes of FIGS. 2A-8 and 11A-11H and 9 and 10A-10D and according to any aspect disclosed herein. The wireless communication device 1300 may include or be provided within any of the devices mentioned above, as examples. As illustrated in FIG. 13, the wireless communication device 1300 includes a transceiver 1304 and a data processor 1306. The data processor 1306 may include memory for storing data and program codes. The transceiver 1304 includes a transmitter 1308 and a receiver 1310 supporting bidirectional communication. In general, the wireless communication device 1300 may include any number of transmitters 1308 and / or receivers 1310 for any number of communication systems and frequency bands. All or a portion of the transceiver 1304 may be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0052]

[0064] The transmitter 1308 or receiver 1310 may be implemented using a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, e.g., for the receiver 1310, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and / or have different requirements. In the wireless communication device 1300 of FIG. 13, the transmitter 1308 and receiver 1310 are implemented using a direct-conversion architecture.

[0053]

[0065] On the transmit path, the data processor 1306 processes data to be transmitted and provides I and Q analog output signals to a transmitter 1308. In the example wireless communication device 1300, the data processor 1306 includes digital-to-analog converters (DACs) 1312(1), 1312(2) to convert digital signals generated by the data processor 1306 to I and Q analog output signals, e.g., I and Q output currents, for further processing.

[0054]

[0066] Within the transmitter 1308, low pass filters 1314(1), 1314(2) filter the I and Q analog output signals, respectively, to remove undesired signals resulting from previous digital-to-analog conversion. Amplifiers (AMPs) 1316(1), 1316(2) amplify the signals from low pass filters 1314(1), 1314(2), respectively, to provide I and Q baseband signals. An upconverter 1318 upconverts the I and Q baseband signals using I and Q LO signals from a transmit (TX) local oscillator (LO) signal generator 1322 via mixers 1320(1), 1320(2) to provide an upconverted signal 1324. A filter 1326 filters the upconverted signal 1324 to remove undesired signals resulting from frequency upconversion as well as noise in the receive frequency band. A power amplifier (PA) 1328 amplifies the upconverted signal 1324 from filter 1326 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1330 and transmitted via an antenna 1332.

[0055]

[0067] In the receive path, an antenna 1332 receives a signal transmitted by a base station and provides a receive RF signal, which is routed through a duplexer or switch 1330 and provided to a low noise amplifier (LNA) 1334. The duplexer or switch 1330 is designed to operate using a specific RX to TX duplexer frequency separation such that the receive (RX) signal is separated from the TX signal. To obtain a desired RF input signal, the receive RF signal is amplified by the LNA 1334 and filtered by a filter 1336. Downconversion mixers 1338(1), 1338(2) mix the output of the filter 1336 with an I RX LO signal and a Q RX LO signal (i.e., LO_I and LO_Q) from an RX LO signal generator 1340 to generate an I baseband signal and a Q baseband signal. The I and Q baseband signals are amplified by AMPs 1342(1), 1342(2) and further filtered by low pass filters 1344(1), 1344(2) to obtain I and Q analog input signals, which are provided to data processor 1306. In this embodiment, data processor 1306 includes analog-to-digital converters (ADCs) 1346(1), 1346(2) for converting the analog input signals to digital signals that can be further processed by data processor 1306.

[0056]

[0068] In the wireless communication device 1300 of FIG. 13, a TX LO signal generator 1322 generates an I TX LO signal and a Q TX LO signal used for frequency up-conversion, while a RX LO signal generator 1340 generates an I RX LO signal and a Q RX LO signal used for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. A TX phase-locked loop (PLL) circuit 1348 receives timing information from the data processor 1306 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 1322. Similarly, a RX PLL circuit 1350 receives timing information from the data processor 1306 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 1340.

[0057]

[0069] It should be noted that the terms "top" and "bottom" as used herein are relative terms. A component referred to as an "top" component is disposed in a second vertical direction above another component referred to as a "bottom" component as shown. However, this is not limiting. In the opposite orientation, a component referred to as an "top" component may flow above another component referred to as a "bottom" component.

[0058]

[0070] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, or as instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or as a combination of both. The memories disclosed herein may be of any type and size and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various exemplary components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0059]

[0071] The various example logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0060]

[0072] Aspects disclosed herein may be embodied in hardware and / or instructions stored in the hardware and may reside in, for example, a Random Access Memory (RAM), a Flash memory, a Read Only Memory (ROM), an Electrically Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a register, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0061]

[0073] It should also be noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The described operations can be performed in many different sequences other than the sequence shown. Furthermore, an operation described in a single operational step can actually be performed in several different steps. Furthermore, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps shown in the flow chart diagrams can be modified in many different ways, as would be readily apparent to one of ordinary skill in the art. Those skilled in the art will also appreciate that information and signals can be represented using any of a wide variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips, as may be referred to throughout the above description, can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0062]

[0074] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the embodiments and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0063]

[0075] The following numbered clauses describe example implementations. Clause 1. An integrated circuit (IC) package comprising: An interposer, a first surface and a second surface opposite the first surface; one or more RDL metallization layers between a first surface and a second surface; a first die disposed within the interposer, a first die comprising a first die interconnect coupled to a first metal interconnect in a first RDL metallization layer of the one or more RDL metallization layers; a second die coupled to the first surface of the interposer, a second die, the second die comprising a second die interconnect coupled to the first RDL metallization layer; An IC package comprising: Article 2. The interposer extends in a first direction; the second surface is opposite the first surface in a second direction perpendicular to the first direction; one or more RDL metallization layers are disposed in a second direction between the first surface and the second surface; An IC package as described in clause 1. Clause 3. The IC package of clause 1 or 2, wherein the first die is adjacent to the first RDL metallization layer. Article 4. the one or more RDL metallization layers further comprising a second RDL metallization layer; the first die further comprising a third die interconnect in the second RDL metallization layer coupled to the third metal interconnect; 1. An IC package as defined in clause 1 or 2. Article 5. the second die interconnect is coupled to a second metal interconnect in the first RDL metallization layer; the second metal interconnect is externally rerouted to the first region of the first RDL metallization layer outside the second region of the second die coupled to the first surface of the interposer; 5. An IC package according to any one of clauses 1 to 4. Clause 6. The IC package of clause 5, wherein the first metal interconnect is coupled to the second metal interconnect. Article 7. a second die sharing a first common plane with the first die; 6. The IC package of claim 5, wherein the second die interconnect of the second die is coupled to the third die interconnect of the first die. Article 8. a first die having a first active surface adjacent the first surface and a third die interconnect exposed from the first active surface; a second die having a second active surface adjacent to the first surface, the second die interconnects being exposed from the second active surface; a second die interconnect of the second die being bonded to a third die interconnect of the first die; 8. An IC package according to any one of clauses 1 to 7. Article 9. a first die having a first non-active side adjacent to the first surface and a third die interconnect exposed from the first non-active side; a second die having a second active surface adjacent to the first surface, the second die interconnects being exposed from the second active surface; a second die interconnect of the second die being bonded to a third die interconnect of the first die; 8. An IC package according to any one of clauses 1 to 7. Clause 10. The semiconductor device further comprising a first via disposed through the first die; a second die interconnect of the second die coupled to the first via; 10. An IC package according to any one of clauses 1 to 9. Clause 11. Further comprising a first via extending from the first surface of the interposer to the second surface of the interposer; a second die interconnect of the second die coupled to the first via; 11. An IC package according to any one of clauses 1 to 10. Clause 12. The method further comprising: a third die coupled to a first region on the first surface of the interposer outside the second region of the first die in the interposer; a third die comprising a third die interconnect coupled to the second metal interconnect of the first RDL metallization layer; 12. An IC package according to any one of clauses 1 to 11. Clause 13. The semiconductor device further comprising a third die disposed within the first RDL metallization layer; a third die comprising a third die interconnect coupled to a second metal interconnect in the first RDL metallization layer; 1. An IC package as defined in clause 1 or 2. Clause 14. The IC package of clause 13, wherein the third die is not communicatively coupled to the second die. Article 15. one or more external interconnects coupled to the bottom surface of the interposer, each of the one or more external interconnects being coupled to one or more second metal interconnects in the first RDL metallization layer; a package substrate coupled to one or more external interconnects; 15. The IC package of any one of clauses 1 to 14, further comprising: Clause 16. The IC package of clause 15, wherein the one or more external interconnects comprise one or more ball grid array (BGA) interconnects. Article 17. the second die further comprises an integrated capacitor; the second die further comprising a third die interconnect; a third die interconnect coupled to the integrated capacitor and to the second metal interconnect of the first RDL metallization layer; 17. An IC package according to any one of clauses 1 to 16. Clause 18. The IC package of any of clauses 1-17 integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter. Clause 19. A method of manufacturing an integrated circuit (IC) package, comprising: Forming an interposer, comprising: forming a first RDL metallization layer adjacent to the first die, the first RDL metallization layer having a first surface and a second surface opposite the first surface; bonding a first die interconnect of the first die to a first metal interconnect in the first RDL metallization layer; forming an interposer comprising: coupling a second die to a first surface of the interposer; bonding a second die interconnect of a second die to the first RDL metallization layer; The method includes: Article 20. forming a second RDL metallization layer comprising a second metal interconnect; bonding a third die interconnect of the first die to a second metal interconnect in the second RDL metallization layer; 20. The method of claim 19, further comprising: Clause 21. The method further comprising forming a second metal interconnect in the first RDL metallization layer to a first region of the first RDL metallization layer outside of a second region of a second die coupled to the first surface of the interposer; bonding the second die interconnect of the second die to the first RDL metallization layer includes bonding the second die interconnect to a second metal interconnect in the first RDL metallization layer; 21. The method according to clause 19 or 20. Clause 22. The method of any of clauses 19-21, wherein coupling the second die to the first surface of the interposer includes bonding a second active surface of the second die to a first surface of the first RDL metallization layer adjacent to the first active surface of the first die. Clause 23. The method of any of clauses 19-21, wherein coupling the second die to the first surface of the interposer includes bonding a second active surface of the second die to a first surface of the first RDL metallization layer adjacent to the first non-active surface of the first die. Clause 24. The method further comprising disposing a first via through the first die; coupling the second die interconnect of the second die to the first RDL metallization layer includes coupling the second die interconnect of the second die to the first via; 24. The method according to any one of clauses 19 to 23. Clause 25. The method of claim 20, further comprising forming a first via extending from the first surface of the interposer to the second surface of the interposer; coupling the second die interconnect of the second die to the first RDL metallization layer includes coupling the second die interconnect of the second die to the first via; 25. The method according to any one of clauses 19 to 24. Article 26. coupling a third die to a first area on a first surface of the interposer outside the second area of ​​the first die in the interposer; bonding a third die interconnect of the third die to a second metal interconnect of the first RDL metallization layer; 26. The method of any one of clauses 19 to 25, further comprising: Article 27. disposing a third die within the first RDL metallization layer; bonding a third die interconnect of the third die to a second metal interconnect in the first RDL metallization layer; 27. The method of any one of clauses 19 to 26, further comprising: Clause 28. The method of clause 27, further comprising not communicatively coupling the third die to the second die. Clause 29. The method of any of clauses 19-28, further comprising forming an overmold layer on a first surface of the first RDL metallization layer, the overmold layer adjacent to the second die.

Claims

1. 1. An integrated circuit (IC) package comprising: An interposer, a first surface and a second surface opposite the first surface; an interposer comprising: one or more RDL metallization layers between the first surface and the second surface; a first die disposed within the interposer, a first die, the first die comprising a first die interconnect coupled to a first metal interconnect in a first one of the one or more redistribution layer (RDL) metallization layers; a second die coupled to the first surface of the interposer, a second die, the second die comprising a second die interconnect coupled to the first RDL metallization layer; An IC package comprising:

2. The interposer extends in a first direction; the second surface is opposite the first surface in a second direction perpendicular to the first direction; the one or more RDL metallization layers are disposed between the first surface and the second surface in the second direction; or the first die is adjacent to the first RDL metallization layer; or the one or more RDL metallization layers further comprising a second RDL metallization layer; the first die further comprising a third die interconnect coupled to a third metal interconnect in the second RDL metallization layer; 10. The IC package of claim 1.

3. the second die interconnect is coupled to a second metal interconnect in the first RDL metallization layer; the second metal interconnect is externally rerouted to a first region of the first RDL metallization layer outside a second region of the second die coupled to the first surface of the interposer; 10. The IC package of claim 1.

4. the first metal interconnect is bonded to the second metal interconnect; or the second die shares a first common plane with the first die; 4. The IC package of claim 3, wherein the second die interconnect of the second die is coupled to a third die interconnect of the first die.

5. the first die having a first active surface adjacent the first surface and a third die interconnect exposed from the first active surface; the second die having a second active surface adjacent to the first surface, the second die interconnects being exposed from the second active surface; the second die interconnect of the second die is bonded to the third die interconnect of the first die; or the first die having a first non-active surface adjacent the first surface and a third die interconnect exposed from the first non-active surface; the second die having a second active surface adjacent to the first surface, the second die interconnects being exposed from the second active surface; the second die interconnect of the second die is bonded to the third die interconnect of the first die; 10. The IC package of claim 1.

6. further comprising a first via disposed through the first die; the second die interconnect of the second die is coupled to the first via; or a first via extending from the first surface of the interposer to the second surface of the interposer; the second die interconnect of the second die is coupled to the first via; or a third die coupled to a first area on the first surface of the interposer outside the second area of ​​the first die within the interposer; the third die comprising a third die interconnect coupled to a second metal interconnect of the first RDL metallization layer; 10. The IC package of claim 1.

7. a third die disposed within the first RDL metallization layer; the third die comprising a third die interconnect coupled to a second metal interconnect in the first RDL metallization layer, preferably the third die is not communicatively coupled to the second die; 10. The IC package of claim 1.

8. one or more external interconnects coupled to a bottom surface of the interposer, the one or more external interconnects each coupled to one or more second metal interconnects in the first RDL metallization layer; a package substrate coupled to the one or more external interconnects; and preferably further comprising: the one or more external interconnects comprise one or more ball grid array (BGA) interconnects; 10. The IC package of claim 1.

9. the second die further comprising an integrated capacitor; the second die further comprising a third die interconnect; the third die interconnect is coupled to the integrated capacitor and to a second metal interconnect of the first RDL metallization layer; 10. The IC package of claim 1.

10. 1. A method for manufacturing an integrated circuit (IC) package, comprising: Forming an interposer, forming a first redistribution layer (RDL) metallization layer adjacent to a first die, the first RDL metallization layer having a first surface and a second surface opposite the first surface; coupling a first die interconnect of the first die to a first metal interconnect in the first RDL metallization layer; forming an interposer, coupling a second die to the first surface of the interposer; coupling a second die interconnect of the second die to the first RDL metallization layer; A method comprising:

11. forming a second RDL metallization layer comprising a second metal interconnect; coupling a third die interconnect of the first die to the second metal interconnect in the second RDL metallization layer; or forming a second metal interconnect in the first RDL metallization layer to a first region of the first RDL metallization layer outside a second region of the second die coupled to the first surface of the interposer; coupling the second die interconnect of the second die to the first RDL metallization layer includes coupling the second die interconnect to the second metal interconnect in the first RDL metallization layer. The method of claim 10.

12. or wherein coupling the second die to the first surface of the interposer includes bonding a second active surface of the second die to the first surface of the first RDL metallization layer adjacent to the first active surface of the first die; 11. The method of claim 10, wherein coupling the second die to the first surface of the interposer comprises bonding a second active surface of the second die to the first surface of the first RDL metallization layer adjacent to a first non-active surface of the first die.

13. further comprising disposing a first via through the first die; or wherein coupling the second die interconnect of the second die to the first RDL metallization layer includes coupling the second die interconnect of the second die to the first via; forming a first via extending from the first surface of the interposer to the second surface of the interposer; or wherein coupling the second die interconnect of the second die to the first RDL metallization layer includes coupling the second die interconnect of the second die to the first via; coupling a third die to a first area on the first surface of the interposer outside a second area of ​​the first die within the interposer; coupling a third die interconnect of a third die to a second metal interconnect of the first RDL metallization layer; Further comprising: The method of claim 10.

14. disposing a third die within the first RDL metallization layer; coupling a third die interconnect of the third die to a second metal interconnect in the first RDL metallization layer; and preferably further comprises Not communicatively coupling the third die to the second die The method of claim 10 further comprising:

15. 11. The method of claim 10, further comprising forming an overmold layer on the first surface of the first RDL metallization layer, the overmold layer adjacent to the second die.

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