Dynamic performance of on-chip current sensors

Abstract

A semiconductor device includes a device region and an on-chip sensor region, such as an on-chip current sensor region. The semiconductor device further includes a transition region formed between the device region and the sensor region. A gate contact extends across the transition region. A conductive segment may be formed above the gate contact in the transition region to reduce the resistivity of a material used to form the gate contact. Additionally or alternatively, an isolation region may be formed below the gate contact between a first isolated well region in the device region and a second isolated well region in the sensor region. The isolation region isolates the first isolated well region from the second isolated well region to prevent current in the device region from propagating into the sensor region.

Description

[Technical field]

[0001] This application claims priority from U.S. Patent Application No. 17 / 736,720, filed in the U.S. Patent and Trademark Office on May 4, 2022, the disclosure of which is incorporated by reference herein in its entirety.

[0002] The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices having on-chip current sensors. [Background technology]

[0003] Semiconductor devices are ubiquitous in modern electronic devices. Wide bandgap semiconductor material systems such as gallium nitride (GaN) and silicon carbide (SiC) are increasingly being utilized in semiconductor devices to push the boundaries of device performance in areas such as switching speed, power handling capability, and thermal conductivity. Examples include discrete devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, high electron mobility transistors (HEMTs), and integrated circuits such as monolithic microwave integrated circuits (MMICs) that contain one or more discrete devices.

[0004] Current sensing in semiconductor devices for power switching applications is a method for monitoring the operating load current to detect potential failure mechanisms such as overcurrent or short circuit events. In the example of a MOSFET or metal-insulator-semiconductor field-effect transistor (MISFET), current sensing may be accomplished by providing separate source contacts for a small number of active area unit cells. The separate source contacts are arranged to form separate paths for a proportionately small amount of the total device load current. The amount of load current along the separate paths is measured and can be used to calculate the total load current along the remainder of the semiconductor device. While current sensing arrangements have been proposed within semiconductor devices, conventional structures may not be suitable to withstand the various adverse operating conditions that may be experienced. Summary of the Invention [Means for solving the problem]

[0005] The present disclosure relates to a semiconductor device. The semiconductor device may include a device region and a sensor region, e.g., a current sensor region that occupies a portion of an entire active area of ​​the semiconductor device. The current sensor region may be configured to monitor a device load current in the device region during operation. The semiconductor device further includes a transition region formed between the device region and the sensor region. A gate contact extends across the transition region. A conductive segment may be formed on the gate contact in the transition region to reduce the resistivity of a material used to form the gate contact. Additionally or alternatively, an isolation region may be formed between a first isolated well region in the device region and a second isolated well region in the sensor region below the gate contact. The isolation region isolates the first isolated well region from the second isolated well region to prevent current in the device region from propagating into the sensor region.

[0006] In one aspect, a vertical semiconductor device includes a drift region, a device region including a first portion of the drift region, and a sensor region including a second portion of the drift region. A transition region is formed between the device region and the sensor region. The transition region includes a gate contact and a conductive segment overlying and in direct contact with the gate contact.

[0007] In another aspect, a vertical semiconductor device includes a drift region, a device region including a first portion of the drift region, and a sensor region including a second portion of the drift region. A transition region is formed between the device region and the sensor region. The transition region includes a gate contact and an isolation region below the gate contact. In one embodiment, the isolation region is between a first isolated well region in the first portion of the drift region and a second isolated well region in the second portion of the drift region.

[0008] In yet another aspect, a vertical semiconductor device includes a drift region, a device region including a first portion of the drift region, and a sensor region including a second portion of the drift region. A transition region is formed between the device region and the sensor region. The transition region includes a gate contact, a conductive segment overlying and in direct contact with the gate contact, and an isolation region below the gate contact and between a first isolated well region in the first portion of the drift region and a second isolated well region in the second portion of the drift region.

[0009] In another aspect, a vertical silicon carbide (SiC) device includes a device region and a sensor region. There is a transition region between the device region and the sensor region. The vertical SiC device can be operable to detect a short circuit event in less than 1 microsecond, in 1-3 microseconds, in 1-5 microseconds, or in less than 10 microseconds.

[0010] In yet another aspect, a vertical semiconductor device includes a drift region and a device region including a first portion of the drift region. One or more sensor regions each include a second portion of the drift region. Each sensor region includes one or more sensors. Each sensor in each sensor region is equidistant from a respective gate contact that is electrically connected to the one or more sensors in each sensor region.

[0011] In other aspects, any of the above aspects may be combined individually or together, and / or various separate aspects and features as described herein may be combined to further advantage. Any of the various features and elements as disclosed herein may be combined with one or more of the other disclosed features and elements, unless otherwise indicated herein.

[0012] Those skilled in the art will appreciate the scope of the present disclosure and realize further aspects of the present disclosure after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawing figures.

[0013] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure. [Brief description of the drawings]

[0014] [Figure 1] 1 illustrates a top view layout for an exemplary semiconductor device according to an embodiment of the present disclosure. [Figure 2A] 1 illustrates a first equivalent circuit of a current sensor implementation for a metal-oxide-semiconductor field effect transistor (MOSFET) device or a metal-insulator-semiconductor field effect transistor (MISFET) device according to an embodiment of the present disclosure. [Figure 2B] 1 illustrates a second equivalent circuit for a current sensor implementation for a MOSFET or MISFET device according to an embodiment of the present disclosure. [Diagram 3]1 illustrates a cross-sectional view of a portion of a semiconductor device including a sensor contact integrated within the semiconductor device. [Figure 4] 4 is a cross-sectional view of a portion of a first semiconductor device similar to the semiconductor device of FIG. 3 and further including a protection structure disposed in the transition region. [Diagram 5] 1 illustrates a top view of a portion of a semiconductor device according to an embodiment of the present disclosure. [Figure 6] 1 illustrates a cross-sectional view of a portion of a second semiconductor device including a conductive segment formed above a gate contact according to an embodiment of the present disclosure. [Figure 7] 7 illustrates a cross-sectional view of a portion of a third semiconductor device similar to the first semiconductor device of FIG. 4 and the second semiconductor device of FIG. 6 and including an insulating layer that forms a non-planar shape, according to an embodiment of the present disclosure. [Figure 8] 7 illustrates a cross-sectional view of a portion of a fourth semiconductor device similar to the first semiconductor device of FIG. 4 and the second semiconductor device of FIG. 6 and including an insulating layer formed to cover a larger portion of the top surface of the drift region, according to an embodiment of the present disclosure. [Figure 9] 5 illustrates a cross-sectional view of a portion of a fifth semiconductor device similar to the first semiconductor device of FIG. 4 and including an isolation region positioned between a first isolated well region and a second isolated well region in accordance with an embodiment of the present disclosure. [Figure 10A] 1 shows a graph of turn-on time for a current sensor and a device MOSFET. [Figure 10B] 2 shows a graph of turn-off time for a current sensor and a device MOSFET. [Figure 11] 10 illustrates a cross-sectional view of a portion of a sixth semiconductor device similar to the fifth semiconductor device of FIG. 9 and operable to detect one or more events in one or more device MOSFETs, according to an embodiment of the present disclosure. [Figure 12]1 illustrates a cross-sectional view of a portion of a seventh semiconductor device, which is similar to the third semiconductor device of FIG. 7 and the fifth semiconductor device of FIG. 9 according to an embodiment of the present disclosure and includes an isolation region and an insulating layer that forms a non-planar shape. [Figure 13] 10 illustrates a cross-sectional view of a portion of an eighth semiconductor device according to an embodiment of the present disclosure, which is similar to the fourth semiconductor device of FIG. 8 and the fifth semiconductor device of FIG. 9 and includes an isolation region and an insulating layer formed to cover a larger portion of the top surface of the drift region. [Figure 14] 1 shows an exemplary first layout for sensor areas. [Figure 15] 1 illustrates a second exemplary layout for sensor regions according to an embodiment of the present disclosure. [Figure 16] 13 illustrates a third exemplary layout for sensor regions according to an embodiment of the present disclosure. [Figure 17] 13 illustrates a fourth exemplary layout for a first sensor region and a second sensor region according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The embodiments described below represent the necessary information to enable one skilled in the art to practice the embodiments and show the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawings, one skilled in the art will understand the concepts of the present disclosure and recognize applications of these concepts not specifically addressed herein. It is to be understood that these concepts and applications are within the scope of the present disclosure and the appended claims.

[0016] Terms such as first, second, etc. may be used herein to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element can be called a second element, and similarly, a second element can be called a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0017] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it is understood that it may be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "over" or extending "upon" another element, it is understood that it may be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it should be understood that the element may be directly connected or coupled to the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0018] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of an element, layer, or region to another element, layer, or region as shown in the figures. It should be understood that these terms, and those discussed above, are intended to encompass various orientations of the device in addition to the orientation depicted in the figures.

[0019] The terminology used herein is merely for the purpose of describing particular embodiments and is not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It is further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0020] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is further understood that the terms used herein should be interpreted to have a meaning consistent with their meaning in the context of the present specification and the relevant art, and will not be interpreted as idealized or overly formal concepts unless expressly so defined herein.

[0021] The embodiments are described herein with reference to schematic illustrations of embodiments of the present disclosure. Thus, actual dimensions of layers and elements may vary and variations from the shapes of the illustrations are expected, for example, as a result of manufacturing techniques and / or tolerances. For example, a region shown or described as square or rectangular may have rounded or curved features, and a region shown as straight may have some irregular shape. As such, the regions shown in the figures are schematic, and their shapes are not intended to show the exact shape of a region of a device, nor are they intended to limit the scope of the disclosure. Additionally, the size of a structure or region may be exaggerated relative to other structures or regions for illustrative purposes, and thus are provided to show the general structure of the subject matter, and may or may not be drawn to scale. Common elements between multiple figures may be indicated herein with common element numbers and may not be described again thereafter.

[0022] FIG. 1 illustrates a top view layout for an exemplary semiconductor device 100 according to an embodiment of the present disclosure. For illustrative purposes, the semiconductor device 100 is a vertical metal-oxide-semiconductor field effect transistor (MOSFET) device including a passivation structure 102 formed with openings for a gate contact 104 and a number of source contacts 106. Although a MOSFET is illustrated, the principles of the present disclosure are applicable to other semiconductor devices, such as other MOSFETs, metal-insulator-field effect transistors (MISFETs), diodes, Schottky diodes, Junction Barrier Schottky (JBS) diodes, PiN diodes, and Insulated Gate Bipolar Transistors (IGBTs), among others. The semiconductor device 100 may embody a wide bandgap semiconductor device, such as a silicon carbide (SiC) based device, and even a 4H-SiC based device.

[0023] Semiconductor device 100 is a vertical power device with a drain contact (e.g., drain contact 322 in FIG. 3) located on the backside of semiconductor device 100. Gate contact 104 and source contact 106 may be provided as surfaces for coupling of semiconductor device 100 to external circuitry.

[0024] An edge termination region 108 may be disposed along the periphery of the semiconductor device 100. The edge termination region 108 may be disposed to reduce electric field concentration at the edge of the semiconductor device 100 to improve performance of the semiconductor device 100. For example, the edge termination region 108 may increase the breakdown voltage of the semiconductor device 100 and / or reduce the leakage current of the semiconductor device 100 over time. By way of illustration, the edge termination region 108 may include one or more guard rings, a junction termination extension (JTE), and combinations thereof.

[0025] The semiconductor device 100 may further include a sensor contact 110. The sensor contact 110 may provide a contact for any type of sensor, such as a temperature sensor, a strain sensor, or a current sensor, that is at least partially incorporated within the semiconductor device 100. In the case of a current sensor, a current sensor region corresponding to the sensor contact 110 may occupy an area of ​​the semiconductor device 100 that would otherwise form part of an active region 112 for the semiconductor device 100. In the example of FIG. 1, the edge termination region 108 may serve to delineate the active region 112 of the semiconductor device 100 from the non-active region 114 of the semiconductor device 100, and the sensor contact 110 defines the current sensor region that would otherwise form part of the active region 112. In this regard, the sensor contact 110 may generally have a size that is smaller than the size of the remaining active region 112 of the semiconductor device 100.

[0026] The sensor contacts 110 provide contact pads that may be electrically connected, for example, by wire bonds or other electrical connections, to one or more external circuit elements for sensor monitoring. In the case of a current sensor, the sensor contacts 110 may be electrically connected to one or more external circuit elements for monitoring a portion of a load current flowing through a sensor region of the semiconductor device 100 that is electrically coupled to the sensor contacts 110.

[0027] 2A illustrates a first equivalent circuit 200 for an implementation of a current sensor for a MOSFET or MISFET device according to an embodiment of the present disclosure. The dashed box in FIG. 2A represents the semiconductor device 100 of FIG. 1 with the remainder of the first equivalent circuit 200 being outside of the semiconductor device 100. By forming the sensor contact (e.g., sensor contact 110 of FIG. 1) as a separate source contact, the semiconductor device 100 thereby becomes a device MOSFET (MISFET) connected to a common drain and a common gate. D ) and sensing MOSFET (M sense ) is included. MOSFET(M D and M sense ) is connected to the source of the current flow from the drain (I D ) is a MOSFET (M D and M sense ) are connected in parallel so that the power supply can be divided across the D ) of the current flowing from the source of the sensing MOSFET (M sense ) to the current flow from the source corresponds to the ratio of the area of ​​the semiconductor device 100 occupied by the active region to the area of ​​the semiconductor device 100 occupied by the sensor region.

[0028] 2A shows an embodiment in which the ratio of current flow is set at 1:250 based on the relative areas of the active and sensor regions. In this way, when 1 ampere (A) of current flows through the semiconductor device 100, 4 milliamperes (mA) of current flows through the sensing MOSFET (M sense) will flow through the source path of the sensing MOSFET (M sense ) along the source path from the sense resistor (R sense ) to determine the corresponding sense voltage (V sense ) is measured and the device MOSFET (M D ) load current. Other current sensing configurations are possible using the layout of the semiconductor device 100.

[0029] For example, FIG. 2B illustrates a second equivalent circuit 202 for a current sensor implementation for a MOSFET or MISFET device according to an embodiment of the present disclosure. The exemplary second equivalent circuit 202 illustrates a virtual ground configuration for a portion of the semiconductor device 100 that is external to the semiconductor device. Virtual ground sensing provides a higher value of the sense voltage (V sense ) can be used in applications where a feedback resistor (Rf) is required. In this configuration, an operational amplifier (OA) and a feedback resistor (Rf) are connected to a sensing MOSFET (M sense ) is coupled into the source path from the sense voltage (V sense ) can be calculated based on the feedback resistor (Rf) and the output of the operational amplifier (OA).

[0030] In some cases, the type of current sensor corresponds to the type of semiconductor device. For example, the first equivalent circuit 200 represents a current sensor for a MOSFET device. D and M sense is the device MOSFET (M D ) and sensing MOSFET (M sense ) In another embodiment, M D and M sense may be realized with different types of transistors, where the types of transistors correspond to types of semiconductor devices.

[0031] 3 illustrates a cross-sectional view of a portion of a semiconductor device 300 including the sensor contact 110 of FIG. 1. By way of illustration, the semiconductor device 300 is configured as a planar MOSFET, however the principles of the present disclosure are applicable to other semiconductor devices including trench MOSFETs, MISFETs, diodes, Schottky diodes, JBS diodes, PiN diodes, and IGBTs, among others. The semiconductor device 300 includes a substrate 302 and a drift region 304 above the substrate 302. The drift region 304 may embody one or more drift layers of a wide bandgap semiconductor material, such as SiC.

[0032] The substrate 302 is 1×10 17 cm -3 ~1×10 20 cm -3 In various embodiments, the doping concentration of the substrate 302 may be between 1×10 17 cm -3 ~1×10 20 cm -3 For example, the doping concentration of the substrate 302 may be in any subrange between 1×10 18 cm -3 ~1×10 20 cm -3 Between 1×10 19 cm -3 ~1×10 20 cm -3 Between 1×10 17 cm -3 ~1×10 19 cm -3 Between 1×10 17 cm -3 ~1×10 18 cm -3 Between and 1×10 18 cm -3 ~1×10 19 cm -3 It may be between.

[0033] The drift region 304 is 1×10 14 cm -3 ~1×10 18 cm -3In various embodiments, the doping concentration of the drift region 304 may be between 1×10 14 cm -3 ~1×10 18 cm -3 For example, the doping concentration of the drift region 304 can be provided in any subrange between 1×10 15 cm -3 ~1×10 18 cm -3 Between 1×10 16 cm -3 ~1×10 18 cm -3 Between 1×10 17 cm -3 ~1×10 18 cm -3 Between 1×10 14 cm -3 ~1×10 17 cm -3 Between 1×10 14 cm -3 ~1×10 16 cm -3 Between 1×10 14 cm -3 ~1×10 15 cm -3 Between 1×10 15 cm -3 ~1×10 17 cm -3 Between 1×10 15 cm -3 ~1×10 16 cm -3 Between and 1×10 16 cm -3 ~1×10 17 cm -3 It may be between.

[0034] The vertical dashed lines delineate the device region 308 from the sensor region 310 and one or more transition regions 306 of the semiconductor device 300. T For an embodiment having a single integrated sensor contact 110 as shown in the top view of FIG. 1, the transition region 306 shown by the dashed line in FIG. T 3, a continuous transition region 306 surrounds the sensor contact 110.T The semiconductor device 300 may include one or more unit cells in both the device region 308 and the sensor region 310. A unit cell refers to a single MOSFET transistor or cell. The device region 308 includes one or more unit cells, and the sensor region 310 also includes one or more unit cells. Thus, a semiconductor device (e.g., a MOSFET device) includes multiple unit cells. In a non-limiting example, the sensor region 310 includes one or more current sensors.

[0035] 3, the device region 308 and the sensor region 310 include a pair of junction implants 312 disposed in the drift region 304, specifically, in a top surface 304A of the drift region 304 opposite the substrate 302 (e.g., in an upper region of the drift region 304 near or adjacent to the top surface 304A). The junction implants 312 include a well region 312A having a doping type opposite the doping type of the drift region 304, and a source region 312B having a doping type that is the same as the doping type of the drift region 304 and, in some embodiments, a higher doping concentration than the doping concentration of the drift region 304. The junction implants 312 may be separated from one another by a junction field-effect transistor (JFET) region 314. The JFET region 314 has a doping type that is the same as the doping type of the drift region 304 and, in some embodiments, a higher doping concentration than the doping concentration of the drift region 304.

[0036] A number of source contacts 106 are provided on the top surface 304A of the drift region 304 in the device region 308 above the junction implants 312 such that each source contact 106 contacts a portion of the well region 312A and the source region 312B. Similarly, sensor contacts 110 are provided on the top surface 304A of the drift region 304 in the sensor region 310 above the junction implants 312 such that each sensor contact 110 contacts a portion of a corresponding well region 312A and the source region 312B. In this regard, the sensor contacts 110 can form separate source contacts for the sensor region 310. In a particular embodiment, the drift region 304 can include n-type doping and the source region 312B can include n+-type doping while the well region 312A includes p-type doping, although opposite polarity configurations are also applicable to the present disclosure.

[0037] A gate insulating layer 316, or gate oxide layer depending on the device type, is provided on the upper surface 304A of the drift region 304 above the JFET region 314 and a portion of each one of the junction implants 312 such that the gate insulating layer 316 overlaps each one of the source regions 312B. The gate insulating layer 316 may comprise a thin layer of silicon dioxide in certain embodiments, for example in a MOSFET configuration where the gate insulating layer 316 may be referred to as a gate oxide layer. In other embodiments, the gate insulating layer 316 may comprise any insulating material, including non-oxide insulating materials and other oxide materials beyond silicon dioxide.

[0038] A gate contact 318 is provided to the gate insulating layer 316. As shown, the gate contact 318 and the gate insulating layer 316 are connected to the unit cells in the device region 308, the sensor region 310, and the transition region 306. T1. The gate contacts 318 for each of the unit cells in both the device region 308 and the sensor region 310 may be coupled to the same gate contact 104 of FIG. 1. In an alternative configuration, the semiconductor device 300 may embody a trench MOSFET in which the gate contacts 318 and portions of the gate insulating layer 316 may reside within a trench in the drift region 304 without departing from the principles of the present disclosure.

[0039] A passivation layer 320 is provided over the gate contact 318 to provide electrical isolation from the source contact 106 and the sensor contact 110. In certain embodiments, the passivation layer 320 may include one or more dielectric layers referred to as intermetal dielectrics. The unit cells may be arranged throughout the device region 308 and the sensor region 310, or may be arranged in a desired pattern with one or more other semiconductor devices (e.g., diodes) to provide a desired functionality.

[0040] A drain contact 322 is provided on a surface of the substrate 302 opposite the drift region 304. Thus, portions of the drift region 304 and corresponding unit cell(s) disposed in the device region 308 are electrically connected between the drain contact 322 and the source contact 106. Similarly, portions of the drift region 304 and corresponding unit cell(s) disposed in the sensor region 310 are electrically connected between the drain contact 322 and the sensor contact 110. Although only a small number of unit cells are shown, the ratio of the number of unit cells in the sensor region 310 to the number of unit cells in the device region 308 may be approximately 1:1, or 1:100, or 1:250, or 1:1,000,000, depending on the desired current ratio for the sensor region 310. In particular embodiments, the sensor area 310 may be positioned to occupy at most twenty percent (20%), or at most ten percent (10%), or at most five percent (5%) of the available active area of ​​the semiconductor device 300 within the edge termination area. For current sensing applications, the sensor area 310 may be referred to as a current sensor area.

[0041] transition area 306 T A doped well region 324 may be provided in the drift region 304 that is aligned with the well region 312A. The doped well region 324 may include a doping type that is the same as the doping type of the well region 312A and opposite to the doping type of the drift region 304. In this regard, the doped well region 324 may be provided in the drift region 304 that is aligned with the well region 312A. T 3. However, with this layout, the semiconductor device 300 may be vulnerable to transient voltage events that may occur during operation and / or device testing. In particular, a high rate of voltage change over time (dV / dt) may be induced during a switching event. A high dV / dt may be induced in the transition region 306. T This can cause dielectric breakdown or other defects and damage in the gate insulating layer 316 located at the

[0042] FIG. 4 is similar to the semiconductor device 300 of FIG. 3, but includes a transition region 306 to shield the gate insulating layer 316 from transient voltage events, defects, and other related damage. T 3 shows a cross-sectional view of a portion of a first semiconductor device 400 further including a protective structure disposed on the top surface 304A of the drift region 304. An insulating layer 402 is provided on the top surface 304A of the drift region 304 to provide protection for the gate insulating layer 316. An insulating layer 402 may be further provided on the top surface 304A of the drift region 304 in an area where the top surface 304A includes the doped well region 324. In a particular embodiment, the insulating layer 402 is formed on the drift region 304 before the gate insulating layer 316 and the gate contact 318 are formed, thereby protecting the transition region 306. T An insulating layer 402 can be disposed between the gate contact 318 and the drift region 304 in the transition region 306. Further, the insulating layer 402 can be disposed between the gate contact 318 and the drift region 304 in the transition region 306. T 3A to prevent the drift region 304 from completely covering the upper surface 304A of the drift region 304 in the T In particular embodiments, the insulating layer 402 may be disposed on top of the gate contact 318 and between the gate contact 318 and the drift region 304. Additionally, in some embodiments, the gate insulating layer 316 may be disposed in the transition region 306. T In any of the exemplary embodiments described above, the insulating layer 402 may be disposed between the insulating layer 402 and the gate contact 318 at the gate insulating layer 316 transition region 306 where the gate insulating layer 316 is most susceptible to damage. T In particular, the transition region 306 provides a shield or barrier that reduces the effects of transient voltage events along the T 3B. Weak spots formed by the interface between the gate insulating layer 316 and the top surface 304A of the drift region 304 along the

[0043] In certain embodiments, the insulating layer 402 includes a structure having a breakdown voltage higher than the breakdown voltage of the gate insulating layer 316. For example, the breakdown voltage of the insulating layer 402 may be at least 1.5 times higher, or at least 2 times higher, or at least 3 times higher, or at least 5 times higher, or at least 10 times higher, or at least 50 times higher, or at least 100 times higher, or at least 200 times higher than the breakdown voltage of the gate insulating layer 316, or any range having an endpoint defined by any of the preceding values. For example, the breakdown voltage of the insulating layer 402 may be in a range of 1.5 times to 200 times higher, or in a range of 1.5 times to 100 times higher, or in a range of 5 times to 100 times higher, or in a range of 5 times to 200 times higher than the breakdown voltage of the gate insulating layer 316. In a particular example, the insulating layer 402 has a breakdown voltage in the range of 650 volts (V) to 750V, while the gate insulating layer 316 has a breakdown voltage in the range of 40V to 60V.

[0044] In certain embodiments, the insulating layer 402 may comprise a different material having a higher breakdown voltage than the material of the gate insulating layer 316. In such embodiments, the thickness of the insulating layer 402 and the thickness of the gate insulating layer 316 may be the same or different, so long as the insulating layer 402 has the higher breakdown voltage. In other embodiments, the insulating layer 402 and the gate insulating layer 316 may comprise the same material, and the higher breakdown voltage is achieved by providing the insulating layer 402 with a thickness or height from the drift region 304 that is greater than the corresponding thickness or height of the gate insulating layer 316. For example, the thickness of the insulating layer 402 may be at least 1.5 times, or at least 2 times, or at least 3 times, or at least 100 times, the thickness of the gate insulating layer 316, or may be within a range of 1.5 times to 50 times, or within a range of 1.5 times to 100 times, or within a range of 2 times to 50 times, or within a range of 2 times to 100 times, the thickness of the gate insulating layer 316. In a particular example, the insulating layer 402 has a thickness in the range of 550 nanometers (nm) to 650 nm, and the gate insulating layer 316 has a thickness in the range of 30 nm to 50 nm. For MOSFET applications, the gate insulating layer 316 can include a gate oxide and the insulating layer 402 can include a thicker field oxide layer as described above. In such an embodiment, both the gate insulating layer 316 and the insulating layer 402 can include silicon dioxide, among other gate oxides used in MOSFET applications.

[0045] By having the protective structure provided by the insulating layer 402, the overall structure of the first semiconductor device 400 is more robust for handling transient voltage events, including one or more dV / dt events that may be caused during high speed switching. For example, a SiC MOSFET device having the insulating layer 402 of the present disclosure may thereby be configured to withstand or be rated to withstand a dV / dt of at least 10 kilovolts per microsecond (kV / μs) without device failure. In still further embodiments, the SiC MOSFET device is configured to withstand a dV / dt of at least 30 kV / μs, or at least 50 kV / μs, or at least 100 kV / μs, or in the range of 10 kV / μs to 100 kV / μs, or in the range of 10 kV / μs to 200 kV / μs, or in the range of 50 kV / μs to 150 kV / μs, or in the range of 100 kV / μs to 200 kV / μs, or any range having an endpoint determined by any of the preceding values ​​without device failure. In still further embodiments, the SiC MOSFET device is capable of withstanding any of the above dV / dt values ​​from a single switching cycle to at least 1000 switching cycles or more. In any of the embodiments described above, the exemplary SiC MOSFET may include a 4H-SiC MOSFET device.

[0046] In some cases, the material used to form the gate contact (e.g., gate contact 318 in FIG. 3) is resistive or highly resistive. In a non-limiting, non-exclusive example, the material used to form the gate contact is p-type polysilicon. The higher resistivity of p-type polysilicon can cause the potential across the gate contact to vary based on the location of the gate contact relative to the input for the gate signal. These potential differences can cause propagation delays (e.g., resistance and capacitance (RC) delays) in the gate signal, which can cause the transistor (e.g., transistor M in FIGS. 2A and 2B) to become unstable. D and M sense) are turned on at different times. In general, it is preferable to have the transistors, especially those in the sensor region, turned on as a unit. When the transistors are turned on as a unit, they are turned on simultaneously (or nearly simultaneously).

[0047] One technique that can be used to turn on the transistors in the sensor region as a unit is to reduce the resistance of the gate contact material. FIG. 5 illustrates a top view of a portion of a semiconductor device with reduced resistance of the gate contact material according to an embodiment of the present disclosure. A sensor region 500 (e.g., sensor region 310 in FIG. 3) is electrically connected to a power source (PS) 502 via a gate contact 504 (e.g., gate contact 318 in sensor region 310 in FIG. 4). A conductive segment 506 is disposed above the gate contact 504. In some embodiments, the conductive segment 506 is in direct contact with the gate contact 504. The conductive segment 506 reduces the resistivity of the material of the gate contact 504, which in turn reduces or eliminates the propagation delay (e.g., signal-to-gate propagation delay) for the transistor. For example, the conductive segment 506 can average out the propagation delay to reduce the overall delay.

[0048] The source contacts (e.g., source contact 106), the sensor contacts (e.g., sensor contact 110), the drain contacts (e.g., drain contact 322), and the conductive segments 506 may all be made from the same conductive material, or at least one may be made from a different conductive material. Furthermore, the source contacts, the sensor contacts, the drain contacts, and the conductive segments 506 may embody one or more layers of one conductive material or multiple conductive materials. One example of a conductive material is a metal.

[0049] 6 illustrates a cross-sectional view of a portion of a second semiconductor device 600 similar to the first semiconductor device 400 of FIG. 4 and including a conductive segment 602 formed above the gate contact 318 in accordance with an embodiment of the present disclosure. T A conductive segment 602 is disposed within and above the gate contact 318. In the illustrated embodiment, the conductive segment 602 is in direct contact with the gate contact 318.

[0050] The conductive segment 602 corresponds to the transition region 306 between the source contact 106 and the sensor contact 110. T The conductive segments 602 do not directly contact the source contacts 106 and the sensor contacts 110. The conductive segments 602 are disposed in the transition regions 306 between portions of the passivation layer 320. T The passivation layer 320 is disposed in the transition region 306. T 1. The conductive segments 602 in the

[0051] The conductive segments 602 reduce the resistivity of the material used to form the gate contacts 318. As previously explained, reducing the resistivity can reduce or eliminate propagation delays in gate signals applied to the gate contacts 318 of the transistors in the device region 308 and the sensor region 310. In a non-limiting, non-exclusive example, a metal is used to form the conductive segments 602 and polysilicon is used to form the gate contacts 318.

[0052] 7 illustrates a cross-sectional view of a portion of a third semiconductor device 700 similar to the first semiconductor device 400 of FIG. 4 and the second semiconductor device 600 of FIG. 6 and including an insulating layer 402 having a non-planar shape in accordance with an embodiment of the present disclosure. In FIG. 7, a thicker portion 402' of the insulating layer 402 is formed along the center of the insulating layer 402 to form one or more non-planar surfaces of the insulating layer 402 opposite the drift region 304. In this manner, the increased amount of protection provided by the insulating layer 402 provides a better protection to the transition region 306 without increasing the lateral footprint of the insulating layer 402 relative to the drift region 304. T 7, the increased thickness portion 402' forms a stepped profile for the insulating layer 402. In other embodiments, the increased thickness portion 402' may form a peak that is graded in one or more of a linear and / or curved manner toward the lateral edges of the insulating layer 402. Although the increased thickness portion 402' of the insulating layer 402 is shown in the center of the insulating layer 402, the increased thickness portion 402' may be located closer to either the sensor region 310 or the device region 308 depending on the embodiment. In further embodiments, the insulating layer 402 may be formed with multiple increased thickness portions 402'. In FIG. 7, the increased thickness portion 402' forms a stepped profile for the insulating layer 402. In other embodiments, the increased thickness portion 402' may form a peak that is graded in one or more of a linear and / or curved manner toward the lateral edges of the insulating layer 402.

[0053] The third semiconductor device 700 also includes a transition region 306 T 3 includes a conductive segment 602 disposed between (but not in contact with) the source contact 106 and the sensor contact 110, as previously described. The conductive segment 602 is disposed in a transition region 306 between portions of the passivation layer 320. T and is not covered by the passivation layer 320.

[0054] 8 illustrates a cross-sectional view of a portion of a fourth semiconductor device 800 similar to the first semiconductor device 400 of FIG. 4 and the second semiconductor device 600 of FIG. 6 and including an insulating layer 402 formed to cover a larger portion of the top surface of the drift region 304, in accordance with an embodiment of the present disclosure. As shown, the insulating layer 402 can be formed with a lateral width that is close to or the same as the lateral width of the doped well region 324 of the drift region 304. In this manner, the amount of material for the gate insulating layer 316 can be reduced by a factor of 10. T 4. The gate insulating layer 316 may be further reduced in an area of ​​the fourth semiconductor device 800 along the transition region 306 to further reduce the effect from transient voltage events. T 8 having the same lateral width as the lateral width of doped well region 324, insulating layer 402 may be formed having an incremental width that is less than the width of doped well region 324. For example, insulating layer 402 may be formed having a width that is at least 50%, or at least 75%, or at least 90%, or in the range of 50%-100% of the width of doped well region 324 in various embodiments.

[0055] The fourth semiconductor device 800 includes a transition region 306 T 3. The passivation layer 320 further includes a conductive segment 602 disposed between (but not in contact with) the source contact 106 and the sensor contact 110, as previously described. The conductive segment 602 is disposed in the transition region 306 between portions of the passivation layer 320. T and is not covered by the passivation layer 320.

[0056] As shown in FIG. 4, each doped well region 324 is formed beneath the gate contact 318 and adjacent to each of the transition regions 306. T Each transition region 306 T3. The displacement current in the sensor region 310 extends into a portion of the device region 308 and into a portion of the sensor region 310 that is immediately adjacent to (e.g., abutting) the semiconductor device. In some circumstances, such as when a transistor in the device region 308 switches from an off state to an on state, the current in the device region 308 may propagate into the neighboring sensor region 310. The displacement current in the sensor region 310 may cause some transistors (e.g., current sensors) in the sensor region 310 to switch to an on state, in some cases, even before the transistors in the device region 308 switch to an on state based on the displacement current. When the transistors in the sensor region 310 switch to an on state based on the displacement current, the ratio of current flow set to a particular ratio for the semiconductor device (e.g., a ratio of 1:250) may not remain the same.

[0057] One technique that can be used to reduce or eliminate current displacement into the sensor region 310 is to isolate the doped well regions in the device region 308 from the doped well regions in the sensor region 310. Figure 9 illustrates a cross-sectional view of a portion of a fifth semiconductor device 900 similar to the first semiconductor device 400 of Figure 4 and including an isolation region 902 positioned between an isolated well region 904 in the device region 308 and an isolated well region 906 in the device region 310 in accordance with an embodiment of the present disclosure. The isolation region 902 is located between the transition region 306 and the isolated well region 904 in a portion of the drift region 304 in the device region 308 from the isolated well region 906 in a portion of the drift region 304 in the sensor region 310. T 4 into two isolated well regions 904, 906. The isolation region 902 is formed in a portion of the drift region 304 in FIG. 4 . T (e.g., transition region 306 T (aligned with

[0058] In a non-limiting, non-exclusive embodiment, isolation region 902 and JFET region 314 are associated with the same or substantially similar electric fields such that isolation region 902 forms a current mirror of JFET region 314. Thus, isolation region 902 is formed from the same material and with the same doping type and doping concentration as JFET region 314. Additionally or alternatively, isolation region 902 has a width or area that is equal or substantially equal to the width or area of ​​JFET region 314.

[0059] The isolated well region 904 in the device region 308 is formed between the JFET region 314 and a first edge or side of the isolation region 902. At least a portion of the isolated well region 904 is also formed under the gate contact 318. Similarly, the isolated well region 906 in the sensor region 310 is formed between another JFET region 314 and a second edge of the isolation region 902 opposite the first edge of the isolation region 902. Like the isolated well region 904, at least a portion of the isolated well region 906 is formed under the gate contact 318. In the illustrated embodiment, at least a portion of the isolated well region 904 and at least a portion of the isolated well region 906 are formed under portions of the insulating layer 402.

[0060] The isolation region 902 prevents the current in the device region 308 from propagating into the neighboring sensor region 310. The transistor(s) in the sensor region 310 remain in an off state while the transistor(s) in the device region 308 transition to an on state. Thus, a current flow ratio set to a specific ratio for the semiconductor device (e.g., a 1:250 ratio) is maintained during the switching operation.

[0061] 10A-10B show waveforms for a device MOSFET and a sensing MOSFET during switching operations. In particular, waveform 1000 in FIG. 10A shows the waveform of a sensing MOSFET (e.g., M sense) switches to an on state, while waveform 1002 represents the current when a device MOSFET (e.g., M D ) represents the current as it switches to the on state. A sensing MOSFET is implemented as a current sensor, and waveform 1000 represents the current as the current sensor switches to the on state.

[0062] Waveforms 1004, 1006 in Fig. 10B represent the currents when the current sensors and device MOSFETs, respectively, switch to the OFF state. As shown in Fig. 10A and Fig. 10B, waveforms 1000 and 1004 for the current sensors follow waveforms 1002 and 1006 for the device MOSFETs, respectively, except for variation areas 1008, 1010. Variation area 1008 represents the time period when some current sensors switch to the ON state before the remaining current sensors switch to the ON state. Variation area 1010 represents the time period when some current sensors switch to the OFF state before the remaining current sensors switch to the OFF state.

[0063] If the slope of the waveforms 1000, 1004 is as shown in the variation areas 1008, 1010, the current in the device MOSFET is not detectable by the current sensor. If the waveforms 1000, 1004 follow the waveforms 1002, 1006, respectively, a change or event in the device MOSFET can be detected using a current sensor when or as the event occurs. In a non-limiting, non-exclusive example, a current sensor may be used to detect a short circuit event in the device MOSFET. In another non-limiting, non-exclusive example, the current in the device MOSFET is monitored continuously or at select times for low Rds_on conditions in a solid state relay. Additionally or alternatively, a current sensor may be used for cycle-by-cycle control, in which case the current sensor may eliminate a Hall effect current sensor (e.g., in an inverter circuit) to save cost and die area.

[0064] 11 illustrates a cross-sectional view of a portion of a sixth semiconductor device 1100 similar to the fifth semiconductor device 900 of FIG. 9 and operable to detect one or more events in one or more device MOSFETs in accordance with an embodiment of the present disclosure. The sixth semiconductor device 1100 includes a conductive segment 602 formed on a gate contact 318 and a transition region 306. T and an isolation region 902 formed under the gate contact 318 at 300. As previously described, the isolation region 902 prevents current in each device region 308 (e.g., one or more device MOSFETs) from propagating into the adjacent sensor region 310. The isolation region 902 reduces or eliminates the variation area (e.g., variation areas 1008, 1010) in the current waveform of the current sensor so that the current waveform follows (or nearly follows) the current waveform of the one or more device MOSFETs (e.g., device region 308). The conductive segment 602 reduces the resistivity of the material at the gate contact 318, allowing the current sensors to switch on simultaneously (or nearly simultaneously).

[0065] The combination of the isolation region 902 and the conductive segment 602 to isolate the isolated well regions 904, 906 allows the sixth semiconductor device 1100 to detect an event, such as a short circuit event, in one or more of the device MOSFETs. In some on-chip sensors, such as on-chip current sensors, the time period for detecting a current and / or an event in the device MOSFET is 1 microsecond or longer. This allows the device MOSFET to be turned off or isolated to prevent the device MOSFET from being damaged. In one exemplary embodiment, the sixth semiconductor device 1100 (e.g., the current sensor in the sixth semiconductor device 1100) can detect an event (e.g., a short circuit event) in less than 1 microsecond. In another exemplary embodiment, the sixth semiconductor device 1100 (e.g., the current sensor in the sixth semiconductor device 1100) can detect an event, such as a short circuit event, in 1 to 5 microseconds or in less than 10 microseconds. In yet another illustrative example, the sixth semiconductor device 1100 (eg, a current sensor in the sixth semiconductor device 1100) may detect an event in tens of microseconds.

[0066] FIG. 12 illustrates a cross-sectional view of a portion of a seventh semiconductor device 1200 similar to the third semiconductor device 700 of FIG. 7 and the fifth semiconductor device 900 of FIG. 9 and including an isolation region 902 and an insulating layer 402 forming a non-planar shape according to an embodiment of the present disclosure. As in FIG. 7, a thicker portion 402' of the insulating layer 402 is formed above the insulating layer 402 to form one or more non-planar surfaces of the insulating layer 402 opposite the drift region 304. The increased thickness portion 402' can be formed in any shape or profile, such as with a step profile or peak that is graded in one or more of a linear manner and / or a curved manner toward a lateral edge of the insulating layer 402. Although the increased thickness portion 402' of the insulating layer 402 is illustrated in the center of the insulating layer 402, the increased thickness portion 402' may be located closer to either the sensor region 310 or the device region 308 depending on the embodiment. In a further embodiment, the insulating layer 402 may be formed having multiple portions of increasing thickness 402'.

[0067] The seventh semiconductor device 1200 may further include an isolation region 902 positioned between the isolated well regions 904, 906 in the device region 308 and the sensor region 310, respectively. The isolation region 902 may be aligned with the transition region 306 to separate or isolate the isolated well region 904 from the isolated well region 906. T The isolation regions 902 may be formed from the same material and have the same doping type, doping concentration, and width as the JFET regions 314. In certain embodiments, the isolation regions 902 and isolated well regions 904, 906 are omitted. In such embodiments, the doped well regions 324 are formed in the respective transition regions 306. T , and into portions of the respective device regions 308 and the respective sensor regions 310.

[0068] The seventh semiconductor device 1200 may optionally include a conductive segment 602 (shown in dashed lines). The conductive segment 602 is disposed between (but does not contact) the source contact 106 and the sensor contact 110. The conductive segment 602 may be disposed at a transition region 306 between portions of the passivation layer 320. T and is not covered by the passivation layer 320.

[0069] As previously explained, the conductive segments 602 reduce the resistivity of the material used to form the gate contacts 318. The reduced resistivity can reduce or eliminate propagation delays in gate signals applied to the gate contacts 318 of the transistors in the sensor region 310. Furthermore, the combination of the isolation regions 902 and the conductive segments 602 to isolate the isolated well regions 904, 906 enables the seventh semiconductor device 1200 to detect events such as a short circuit event in the device MOSFET.

[0070] 13 illustrates a cross-sectional view of a portion of an eighth semiconductor device 1300 similar to the fourth semiconductor device 800 of FIG. 8 and the fifth semiconductor device 900 of FIG. 9 according to an embodiment of the present disclosure, and including an isolation region 902 and an insulating layer 402 formed to cover a larger portion of the top surface of the drift region 304. As shown, the insulating layer 402 can be formed with a lateral width that is close to or the same as the lateral width of the doped well region 324 of the drift region 304. In this manner, the amount of material for the gate insulating layer 316 can be reduced by a factor of 10. T Thus, in embodiments where the gate insulating layer 316 is not formed above the insulating layer 402, the gate insulating layer 316 may be formed in the transition region 306 to further reduce the effect from transient voltage events. T is spaced further away from

[0071] Although insulating layer 402 is shown having a lateral width that is the same as the lateral width of combined isolation region 902 and isolated well regions 904, 906, insulating layer 402 may be formed with an incremental width that is less than the width of doped well region 324. For example, insulating layer 402 may be formed with a width that is at least 50%, or at least 75%, or at least 90%, or within a range of 50%-100% of the width of combined isolation region 902 and isolated well regions 904, 906 in various embodiments.

[0072] The eighth semiconductor device 1300 may further include an isolation region 902 positioned between the isolated well region 904 in the device region 308 and the isolated well region 906 in the sensor region 310. The isolation region 902 may be aligned with the transition region 306 to separate or isolate the isolated well region 904 from the isolated well region 906. T The isolation regions 902 may be formed from the same material and have the same doping type, doping concentration, and width as the JFET regions 314. In certain embodiments, the isolation regions 902 and isolated well regions 904, 906 are omitted. In such embodiments, the doped well regions 324 are formed in the respective transition regions 306. T , and into portions of the respective device regions 308 and the respective sensor regions 310.

[0073] The eighth semiconductor device 1300 may optionally include a conductive segment 602 (shown in dashed lines). The conductive segment 602 is disposed between (but does not contact) the source contact 106 and the sensor contact 110. The conductive segment 602 may be disposed at a transition region 306 between portions of the passivation layer 320. T and is not covered by the passivation layer 320.

[0074] As previously explained, the conductive segments 602 reduce the resistivity of the material used to form the gate contacts 318. The reduced resistivity can reduce or eliminate propagation delays in gate signals applied to the gate contacts 318 of the transistors in the sensor region 310. Furthermore, the combination of the isolation regions 902 and the conductive segments 602 to isolate the isolated well regions 904, 906 enables the eighth semiconductor device 1300 to detect events such as a short circuit event in the device MOSFET.

[0075] Delay between current sensors and delay from gate signal are two characteristics that affect the performance of a current sensor. Delay between current sensors represents the delay between when the first current sensor in the sensor area transitions to the on state (turns on) and when the last current sensor in the sensor area turns on. Delay from gate signal represents the delay between when the gate signal is applied to the sensor contact and when the current sensor in the sensor area turns on. The layout of the sensor areas within the active area can have an impact on these delay types.

[0076] 14 shows an exemplary first layout 1400 for a sensor region 1402. The sensor region 1402 is arranged in a rectangular shape and is positioned in the center of a rectangular active region 1404. A gate contact 1406 surrounds the sensor region 1402. When a gate signal is applied to the gate contact 1406 via a gate signal line 1408, the current sensors in the sensor region 1402 receive the gate signal from all directions. Thus, the current sensors turn on at different times because the gate signal propagates to the current sensors at different times. Both delays between the current sensors and from the gate signal can adversely affect the performance of the sensor region 1402.

[0077] Figures 15-17 show example layouts that may reduce delays between current sensors and / or from gate signals. The device regions (not shown in Figures 15-17) and sensor regions shown in Figures 15-17 may be implemented as any one of the embodiments shown in Figures 6-9 and 11-13.

[0078] 15 illustrates an example second layout 1500 for a sensor region 1502 according to an embodiment of the present disclosure. In the second layout 1500, the sensor region 1502 is arranged in a stripe or rectangular shape and positioned along a left edge 1504 of the active region 1404. The gate contact 1506 is arranged in a stripe or rectangular shape and positioned between the sensor region 1502 and the left edge 1504 of the active region 1404. A gate signal line 1508 is electrically connected to the gate contact 1506 and is used to apply a gate signal to a current sensor in the sensor region 1502.

[0079] A gate conductor 1510 is routed along the left edge 1504 of the active area 1404. The gate conductor 1510 electrically connects a contact pad 1512 to a gate signal line 1508. The contact pad 1512 is operable to receive a supply signal used to activate or turn on the current sensors in the sensor area 1502. The supply signal propagates in the gate conductor 1510, and the gate signal is applied to the gate contact 1506 via the gate signal line 1508. When the gate signal is applied to the gate contact 1506, the current sensors in the sensor area 1502 are turned on simultaneously or nearly simultaneously. Because the gate signal propagates to the current sensors nearly simultaneously, the current sensors in the sensor area 1502 are turned on simultaneously (or nearly simultaneously). The current sensors in the sensor area 1502 are positioned equidistant (or nearly equidistant) from the gate contact 1506. The delay between the current sensors and / or from the gate signal is reduced or minimized, thereby improving the performance of the sensor area 1502.

[0080] Other embodiments are not limited to the shape, size, and / or location of the sensor region 1502, the gate contact 1506, and / or the gate conductor 1510. In a non-limiting example, the sensor region 1502 may be positioned along a top edge of the active region 1404, and the gate contact 1506 may be between the sensor region 1502 and the top edge of the active region 1404. In such an embodiment, the gate conductor 1510 may be routed along a top edge of the active region 1404. Additionally, the active region 1404 may have a shape different than the rectangular shape shown in FIG.

[0081] 16 illustrates an exemplary third layout 1600 for a sensor region 1602 according to an embodiment of the present disclosure. The sensor region 1602 is arranged in an "L" shape and positioned along a left edge 1606 and a bottom edge 1608 of the active region 1404 near a bottom left corner 1604. A gate contact 1610 is arranged in an "L" shape and positioned between the sensor region 1602 and the left edge 1606 and a bottom edge 1608 of the active region 1404. A first gate signal line 1612 is electrically connected to the gate contact 1610 at the left edge 1606, and a second gate signal line 1614 is electrically connected to the gate contact 1610 at the bottom edge 1608. The first gate signal line 1612 and the second gate signal line 1614 are used to apply gate signals to the current sensors in the sensor region 1602.

[0082] A gate conductor 1616 is routed along the left edge 1606 and the bottom edge 1608 of the active area 1404. The gate conductor 1616 electrically connects the contact pad 1512 to a first gate signal line 1612 and a second gate signal line 1614. As previously described, the contact pad 1512 is operable to receive a supply signal used to turn on the current sensors in the sensor area 1602. The supply signal propagates in the gate conductor 1616, and the gate signal is applied to the gate contact 1610 via the first gate signal line 1612 and the second gate signal line 1614. When the gate signal is applied to the gate contact 1610, the current sensors in the sensor area 1602 are turned on at the same time or at about the same time because the gate signal propagates to the current sensors at about the same time. The current sensors in the sensor area 1602 are positioned equidistant (or about the same distance) from the gate contact 1610. The delay between the current sensors and / or from the gate signal is reduced or minimized, thereby improving the performance of the sensor area 1602.

[0083] Other embodiments are not limited to the shape, size, and / or location of the sensor area 1602, the gate contact 1610, and / or the gate conductor 1616. In a non-limiting example, the sensor area 1602 may be positioned along the top and right edges of the active area 1404 near the top corners of the active area. The gate contact 1610 may be between the sensor area 1602 and the top and right edges of the active area 1404. The gate conductor 1616 may be routed along the top and right edges of the active area 1404. Additionally, the active area 1404 may have a shape different than the rectangular shape shown in FIG.

[0084] 17 illustrates an exemplary fourth layout 1700 for a first sensor region 1702 and a second sensor region 1704 according to an embodiment of the present disclosure. The first sensor region 1702 is arranged in a stripe or rectangular shape and positioned along a left edge 1706 of the active region 1404. The first gate contact 1708 is arranged in a stripe or rectangular shape and positioned between the first sensor region 1702 and the left edge 1706 of the active region 1404. A first gate signal line 1710 is electrically connected to the first gate contact 1708 and is used to apply a gate signal to the current sensor in the first sensor region 1702.

[0085] The second sensor region 1704 is arranged in a stripe or rectangular shape and is positioned along a right edge 1712 of the active region 1404. The second gate contact 1714 is arranged in a stripe or rectangular shape and is positioned between the second sensor region 1704 and the right edge 1712 of the active region 1404. A second gate signal line 1716 is electrically connected to the second gate contact 1714 and is used to apply a gate signal to the current sensor in the second sensor region 1704.

[0086] A gate conductor 1718 is routed along the top edge 1720, the left edge 1706, and the right edge 1712 of the active area 1404. The gate conductor 1718 electrically connects the contact pad 1512 to the first gate signal line 1710 and the second gate signal line 1716. As previously described, the contact pad 1512 is operable to receive a supply signal used to turn on the current sensor in the first sensor area 1702 and the current sensor in the second sensor area 1704. The supply signal propagates in the gate conductor 1718, and the gate signal is applied via the first gate signal line 1710 to the first gate contact 1708 and via the second gate signal line 1716 to the second gate contact 1714.

[0087] When a gate signal is applied to the first gate contact 1708 and the second gate contact 1714, the current sensors in the first sensor region 1702 and the second sensor region 1704 are turned on simultaneously or at approximately the same time because the gate signal propagates to the current sensors at approximately the same time. The current sensors in the first sensor region 1702 are positioned equidistant (or approximately equidistant) from the first gate contact 1708. Similarly, the current sensors in the second sensor region 1704 are positioned equidistant (or approximately equidistant) from the second gate contact 1714. Thus, the delay between the current sensors and / or from the gate signal is reduced or minimized, thereby improving the performance of the sensor region 1602.

[0088] Other embodiments are not limited to the shape, size, and / or location of the first sensor region 1702, the first gate contact 1708, the second sensor region 1704, and the second gate contact 1714, and / or the gate conductor 1718. In a non-limiting example, the first sensor region 1702 may be positioned along a top edge 1720 of the active region 1404, the second sensor region 1704 may be positioned along a bottom edge of the active region 1404, the first gate contact 1708 may be positioned between the first sensor region 1702 and the top edge 1720, and the second gate contact 1714 may be positioned between the bottom edge and the second sensor region 1704. In such an embodiment, the gate conductor 1718 may be routed along the top and bottom edges of the active region 1404. Additionally, the active region 1404 may have a shape different than the rectangular shape shown in FIG.

[0089] 15-17 show exemplary sensor region shapes and sizes, gate contact shapes and sizes, gate conductors, and layouts that enhance sensor region performance. Other embodiments are not limited to these layouts, the illustrated sensor region and gate contact shapes and / or sizes, or the routing and shapes of the gate conductors. Any layout that positions current sensors in one or more sensor regions equidistant (or approximately equidistant) from respective gate contacts that are electrically connected to the respective sensor regions can be used. The layout for one or more sensor regions can depend on several factors, including, but not limited to, the number of sensor regions, the shape of the sensor region(s), the shape of the gate contact(s), and the routing of the one or more gate conductors.

[0090] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features as described herein may be combined to further advantage. Any of the various embodiments as disclosed herein may be combined with one or more of the other disclosed embodiments, unless otherwise indicated herein.

[0091] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are believed to be within the scope of the concepts disclosed herein and the following claims.

Claims

1. A drift region; a device region including a first portion of the drift region; a sensor region including a second portion of the drift region; a transition region between the device region and the sensor region, a gate contact; a conductive segment overlying and in direct contact with said gate contact; a transition region including A vertical semiconductor device comprising:

2. an insulating layer between the gate contact and the drift region; a gate insulating layer between the gate contact and the drift region; The vertical semiconductor device of claim 1 further comprising:

3. 3. The vertical semiconductor device of claim 2, wherein the thickness of said insulating layer is at least 1.5 times greater than the thickness of said gate insulating layer.

4. 3. The vertical semiconductor device of claim 2, wherein the thickness of the insulating layer is in the range of 1.5 to 100 times greater than the thickness of the gate insulating layer.

5. 3. The vertical semiconductor device of claim 2, wherein a portion of said insulating layer has a thickness greater than a thickness of another portion of said insulating layer.

6. The vertical semiconductor device of claim 1 , wherein the sensor region comprises one or more current sensors.

7. 7. The vertical semiconductor device of claim 1, wherein the first portion of the drift region is electrically connected between a first contact and a second contact, and the second portion of the drift region is electrically connected between the first contact and a sensor contact.

8. 8. The vertical semiconductor device of claim 7, wherein the vertical semiconductor device comprises a metal-oxide-semiconductor field effect transistor (MOSFET), the first contact is a drain contact, and the second contact is a source contact.

9. a first isolated well region in the first portion of the drift region below the gate contact; a second isolated well region in the second portion of the drift region below the gate contact; and an isolation region between the first isolated well region and the second isolated well region below the gate contact in the transition region; The vertical semiconductor device of claim 1 further comprising:

10. 10. The vertical semiconductor device of claim 9, wherein the conductive segment and an isolation region isolating the first isolated well region and the second isolated well region enable detection of a short circuit event in less than 1 microsecond of its occurrence.

11. 10. The vertical semiconductor device of claim 9, wherein the conductive segment and an isolation region isolating the first isolated well region and the second isolated well region enable detection of a short circuit event within 1 microsecond to 5 microseconds of the occurrence of the short circuit event.

12. the device region and the sensor region are in an active area of ​​the vertical semiconductor device; the sensor regions are arranged in stripes and positioned along edges of the active area; the sensor area includes one or more current sensors; 12. The vertical semiconductor device of claim 1, wherein each current sensor in the sensor region is equidistant from a gate contact electrically connected to the one or more current sensors in the sensor region.

13. the device region and the sensor region are in an active area of ​​the vertical semiconductor device; The sensor areas are arranged in an "L" shape with a bottom corner of the sensor area positioned near a corner of the active area; the sensor area includes one or more current sensors; 12. The vertical semiconductor device of claim 1, wherein each current sensor in the sensor region is equidistant from a gate contact electrically connected to the one or more current sensors in the sensor region.

14. A drift region; a device region including a first portion of the drift region; a sensor region including a second portion of the drift region; a transition region between the device region and the sensor region, a gate contact above the drift region; an isolation region in the drift region; a transition region including A vertical semiconductor device comprising:

15. 15. The vertical semiconductor device of claim 14, further comprising a conductive segment directly above said gate contact in said transition region.

16. 16. The vertical semiconductor device of claim 15, wherein the conductive segments and the isolation regions enable detection of a short circuit event in less than 1 microsecond of its occurrence.

17. 16. The vertical semiconductor device of claim 15, wherein the conductive segments and the isolation regions enable detection of a short circuit event within 1 to 5 microseconds of its occurrence.

18. the first portion of the drift region is in the device region; the second portion of the drift region is in the sensor region; the isolation region is an n-type isolation region; the first isolated well region is a first p-well region; 15. The vertical semiconductor device of claim 14, wherein the second isolated well region is a second p-well region.

19. 15. The vertical semiconductor device of claim 14, further comprising an insulating layer between the gate contact and the drift region.

20. 20. The vertical semiconductor device of claim 19, wherein a portion of the insulating layer has a thickness that is greater than a thickness of another portion of the insulating layer.

21. the sensor region forms a current sensor; 21. The vertical semiconductor device of claim 14, wherein the vertical semiconductor device comprises a metal-oxide-semiconductor field effect transistor (MOSFET), and the first portion of the drift region is electrically connected between a drain contact and a source contact and the second portion of the drift region is electrically connected between the drain contact and a sensor contact.

22. the device region and the sensor region are in an active area of ​​the vertical semiconductor device; the sensor regions are arranged in stripes and positioned along edges of the active area; the sensor area includes one or more current sensors; 22. The vertical semiconductor device of claim 14, wherein each current sensor in the sensor region is equidistant from a gate contact electrically connected to the one or more current sensors in the sensor region.

23. 1. A vertical silicon carbide (SiC) device, comprising: A device region; A sensor area; a transition region between the device region and the sensor region, the vertical SiC device being operable to detect a short circuit event in 1 microsecond to 3 microseconds; 1. A vertical silicon carbide (SiC) device comprising:

24. a conductive segment over the gate contact; an isolation region formed in the drift region below the gate contact; 24. The vertical SiC device of claim 23 further comprising:

25. a well region formed in the drift region adjacent to the isolation region; a junction field effect transistor (JFET) region formed in the drift region adjacent the well region, the isolation region being a current mirror of the JFET region; 25. The vertical SiC device of claim 24 further comprising:

26. the device region and the sensor region are in an active region of the vertical SiC device; the sensor regions are arranged in stripes and positioned along edges of the active area; the sensor area includes one or more sensors; 26. The vertical SiC device of claim 23, wherein each sensor in the sensor region is equidistant from a gate contact electrically connected to the one or more sensors in the sensor region.

27. the device region and the sensor region are in an active region of the vertical SiC device; The sensor areas are arranged in an "L" shape with a bottom corner of the sensor area positioned near a corner of the active area; the sensor area includes one or more sensors; 26. The vertical SiC device of claim 23, wherein each sensor in the sensor region is equidistant from a gate contact electrically connected to the one or more sensors in the sensor region.

28. the device region is a metal-oxide-semiconductor field effect transistor (MOSFET) device region including one or more MOSFET transistors; 28. A vertical SiC device according to any one of claims 23 to 27, wherein the sensor region is a current sensor region including one or more current sensors.

29. A drift region; a device region including a first portion of the drift region; one or more sensor regions each including a second portion of the drift region, Each sensor area includes one or more sensors; one or more sensor regions, each sensor in each sensor region being equidistant from a respective gate contact electrically connected to the one or more sensors in the respective sensor region; A vertical semiconductor device comprising:

30. a transition region between the device region and each sensor region, a gate contact above the drift region; an isolation region in the drift region; 30. The vertical semiconductor device of claim 29, further comprising a transition region comprising:

31. a transition region between the device region and each sensor region, a gate contact; a conductive segment overlying and in contact with said gate contact; 30. The vertical semiconductor device of claim 29, further comprising a transition region comprising:

32. the one or more sensor regions are sensor regions; each sensor in the sensor region is equidistant from a gate contact electrically connected to the one or more sensors in the sensor region; 30. The vertical semiconductor device of claim 29, wherein the one or more sensors are one or more current sensors.

33. the one or more sensor regions are a first sensor region and a second sensor region; the first sensor area includes one or more first sensors; each first sensor in the first sensor region is equidistant from a first gate contact electrically connected to the one or more first sensors in the first sensor region; the second sensor area includes one or more second sensors; each second sensor in the second sensor region is equidistant from a second gate contact electrically connected to the one or more second sensors in the second sensor region; the one or more first sensors are one or more first current sensors; 30. The vertical semiconductor device of claim 29, wherein the one or more second sensors are one or more second current sensors.

Images