How a transistor is manufactured

Abstract

The present invention relates to a method for manufacturing a transistor, and more particularly to a method for manufacturing a transistor having improved characteristics. A method for manufacturing a transistor according to an embodiment of the present invention is a method for manufacturing a transistor having a metal line and a channel layer, and includes the steps of providing a patterned substrate to expose a first channel layer including a metal oxide, and forming a second channel layer on the exposed surface of the first channel layer using at least one of IGZO, IZO, InO, and ZnO.

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a transistor, and more particularly to a method for manufacturing a transistor having improved characteristics. [Background technology]

[0002] 2. Description of the Related Art Transistors are used as circuits for independently driving each cell or pixel in semiconductor devices, liquid crystal displays (LCDs), organic electroluminescence (EL) displays, and the like.

[0003] Such a transistor is formed on a lower substrate of a display device together with a gate line and a data line, that is, the transistor includes a gate electrode which is a part of the gate line, a channel layer which is used as a channel, a source electrode and a drain electrode which are a part of the data line, and a gate insulating film.

[0004] In addition, recent semiconductor technology has been developing remarkably, and the speed and integration of semiconductor devices are rapidly increasing, which has led to an ever-increasing need for finer patterns and finer pattern dimensions. However, when the channel length of a transistor is reduced to compactify a semiconductor device, the effective channel length is reduced due to the short channel effect, which increases leakage current and degrades operating characteristics. For this reason, research and development efforts are being made to fabricate transistors in a three-dimensional structure to minimize the size of semiconductor devices.

[0005] In the manufacturing process of such a transistor, the channel layer is exposed to an etching gas during the patterning or planarization process. When the channel layer is exposed to the etching gas, the exposed surface of the channel layer is damaged by the etching gas and loses oxygen. In addition, the channel layer is connected to a source electrode and a drain electrode, which are part of a data line, and oxygen moves from the active layer to the source electrode and the drain electrode when the transistor is driven, resulting in the active layer losing oxygen. When oxygen deficiency occurs in the channel layer in this way, the electrical conductivity of the channel layer unintentionally increases and the channel layer becomes a conductor. This causes a short circuit in the element, which makes it difficult to stably drive the transistor. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Korean Patent Publication No. 10-2004-0013273 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention provides a method for manufacturing a transistor that can prevent oxygen deficiency in a channel layer and improve stability. [Means for solving the problem]

[0008] A method for manufacturing a transistor according to an embodiment of the present invention is a method for manufacturing a transistor having a metal line and a channel layer, the method including the steps of: providing a substrate patterned to expose a first channel layer including a metal oxide; and forming a second channel layer on the exposed surface of the first channel layer using at least one of IGZO, IZO, InO, and ZnO.

[0009] In the step of forming the second channel layer, the second channel layer may be formed by a selective deposition method.

[0010] The selective deposition method may include at least one of an area selective-atomic layer deposition (AS-ALD) method and an area selective-chemical vapor deposition (AS-CVD) method.

[0011] The method for manufacturing the transistor may include the steps of forming an insulating film adjacent to the first channel layer, and forming the metal line adjacent to the insulating film.

[0012] The method of manufacturing the transistor may include forming the metal line after forming the second channel layer.

[0013] The metal lines may include at least one of bit lines and word lines of a memory device.

[0014] Meanwhile, a method for manufacturing a transistor according to an embodiment of the present invention is a method for manufacturing a transistor having a metal line and a channel layer, and includes the steps of providing a substrate patterned to expose a channel layer including a metal oxide, and forming an electrode on an exposed surface of the channel layer using at least one of Ru and RuO.

[0015] In addition, a method for manufacturing a transistor according to an embodiment of the present invention may be a method for manufacturing a transistor having a metal line and a channel layer, the method including the steps of providing a substrate patterned to expose a channel layer including a metal oxide, and forming a treatment layer on an exposed surface of the channel layer.

[0016] In the step of forming the treatment layer, the exposed surface of the channel layer may be treated by at least one of a heat treatment and a plasma treatment.

[0017] The heat treatment may be performed by supplying O2 gas to the exposed surface of the channel layer, and the plasma treatment may be performed by supplying at least one of O2 and NF3 gas to the exposed surface of the channel layer. Effect of the Invention

[0018] According to an embodiment of the present invention, a functional layer for preventing oxygen deficiency in the channel layer is formed on the exposed surface of the channel layer, thereby preventing the channel layer from becoming a conductor and improving the switching characteristics.

[0019] In addition, the contact resistance between the channel layer and the source and drain electrodes can be effectively reduced, improving the characteristics and reliability of the device. [Brief description of the drawings]

[0020] [Figure 1] 1 is a diagram illustrating a semiconductor device in which a transistor according to an embodiment of the invention is used; [Diagram 2] 1 is a diagram illustrating a schematic diagram of a transistor according to a first embodiment of the present invention. [Diagram 3] FIG. 4 is a schematic diagram of a transistor according to a second embodiment of the present invention. [Figure 4] 1A to 1C are views each illustrating a schematic diagram of a method for manufacturing a transistor according to a first embodiment of the present invention. [Diagram 5] 1A to 1C are views each illustrating a schematic diagram of a method for manufacturing a transistor according to a first embodiment of the present invention. [Figure 6] 1A to 1C are views each illustrating a schematic diagram of a method for manufacturing a transistor according to a first embodiment of the present invention. [Figure 7] 5A to 5C are diagrams illustrating a method for manufacturing a transistor according to a second embodiment of the present invention. [Figure 8]5A to 5C are diagrams illustrating a method for manufacturing a transistor according to a second embodiment of the present invention. [Figure 9] 5A to 5C are diagrams illustrating a method for manufacturing a transistor according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various different forms. The following embodiments are provided for the purpose of making the disclosure of the present invention complete and fully conveying the scope of the invention to those skilled in the art.

[0022] Throughout the specification, when a component, such as a film, region, or substrate, is referred to as being "on" another component, it can be interpreted that the component may be directly in contact with the other component, or there may be additional components interposed therebetween.

[0023] Additionally, relative terms and phrases such as "upper" or "lower" may be used in this specification to describe the relative relationship of one element to another element as illustrated. It is to be understood that the relative terms and phrases are intended to include other orientations of the elements in addition to the orientation depicted in the figures. Here, the drawings may be exaggerated to illustrate the invention in detail, and the same reference numerals in the figures refer to the same components.

[0024] FIG. 1 is a diagram illustrating a semiconductor device in which a transistor according to an embodiment of the present invention is used.

[0025] 1, a transistor 100 according to an embodiment of the present invention can be used in a memory device such as a dynamic random access memory (DRAM), which is a type of volatile semiconductor memory device commonly used in electronic devices such as computers and mobile terminals.

[0026] A DRAM may include a number of memory cells arranged in a number of rows and columns, where each memory cell may include, for example, one transistor 100 and one capacitor 200.

[0027] Such a DRAM may include word lines and bit lines. Here, the word lines may be connected to or included in the gate lines of the transistors and determine whether the memory cells are used or not. Meanwhile, the bit lines may be connected to or included in the source or drain electrodes of the transistors and play a role in determining the value (0 or 1) of the stored memory.

[0028] In the following, an example will be described in which the transistor 100 according to an embodiment of the present invention is used in a DRAM. However, it goes without saying that the transistor 100 according to an embodiment of the present invention can be used not only in a DRAM but also in a wide variety of circuits for independently driving each cell or pixel in a semiconductor device, a liquid crystal display device, etc.

[0029] FIG. 2 is a diagram illustrating a schematic diagram of a transistor according to a first embodiment of the present invention, and FIG. 3 is a diagram illustrating a schematic diagram of a transistor according to a second embodiment of the present invention.

[0030] The transistor according to the embodiment of the present invention may include a metal line, a channel layer, and various other insulating layers. Here, Fig. 2 is a schematic diagram of a horizontally stacked transistor according to a first embodiment of the present invention, and Fig. 3 is a schematic diagram of a vertically stacked transistor according to a second embodiment of the present invention. Figs. 2 and 3 show cross sections of the transistor according to the embodiment of the present invention cut along a plane along the stacking direction.

[0031] First, referring to FIG. 2, the transistor 100 according to the first embodiment of the present invention may include a substrate 110, a word line 120 provided on the substrate 110, a gate insulating film 130 provided on the word line 120, a first channel layer 140 provided on the gate insulating film 130, a gate insulating film 130 provided on the first channel layer 140, and a word line 120 provided on the gate insulating film 130. The transistor 100 according to the first embodiment of the present invention may include a bit line 160 provided to penetrate the gate insulating film 130 and the first channel layer 140, and may further include a capacitor line 180 provided outside the word line 120 to be connected to the first channel layer 140, and various insulating layers interposed between the respective layers and lines. Here, the metal line according to the embodiment of the present invention may include at least one of the word line 120, the bit line 160, and the capacitor line 180.

[0032] The substrate 110 may be formed of a material including silicon (Si). An insulating layer may be formed on the substrate 110, and a word line 120 that serves as a gate electrode in the transistor 100 is formed on the insulating layer. Although FIG. 2 shows that the word lines 120 are arranged on both sides of the bit line 160, this shows a cross-sectional shape, and in a three-dimensional structure, the word line 120 may have a ring shape as a whole. Such a word line 120 may be formed of a material having electrical conductivity, for example, at least one metal selected from aluminum (Al), neodymium (Nd), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), and copper (Cu), or an alloy containing these metals. Meanwhile, an insulating layer may be arranged on the inside and outside of the word line 120.

[0033] A gate insulating film 130 may be formed on the word line 120. The gate insulating film 130 may be formed using one or more insulating materials having excellent adhesion to metal materials and excellent dielectric strength, including inorganic insulating materials such as silicon oxide (SiO2), silicon nitride (SiN), alumina (Al2O3), and zirconia (ZrO2).

[0034] A first channel layer 140 may be formed on the gate insulating film 130. The first channel layer 140 may be formed of a metal oxide. Here, the first channel layer 140 may be formed of a metal oxide thin film, or may be formed of a plurality of metal oxide thin films having different compositions. For example, the first channel layer 140 may include an oxide containing at least one of indium (In), gallium (Ga), and zinc (Zn).

[0035] For example, indium (In) is a metal having a relatively low band gap and a relatively high standard electrode potential, and is characterized by increasing the charge concentration and improving the mobility. In contrast, gallium is a metal having a relatively high band gap and a relatively high standard electrode potential, and is characterized by decreasing the charge concentration and improving the stability. Therefore, the electrical conductivity of the first channel layer 140 can be adjusted by controlling the content of indium and gallium contained in the metal oxide thin film. In this way, the first channel layer 140 made of a metal oxide thin film has a characteristic that the higher the oxygen ratio, the lower the electrical conductivity, and the higher the oxygen ratio, the higher the electrical conductivity.

[0036] A gate insulating film 130 may be formed on the first channel layer 140, and a word line 120 having a ring shape as a whole may be formed on the gate insulating film 130. In Fig. 2, two stacked bodies formed as described above are stacked with an interlayer insulating layer sandwiched therebetween, but it goes without saying that the number of stacked bodies stacked with an interlayer insulating layer sandwiched therebetween can be changed in a wide variety of ways.

[0037] The bit line 160 serves as a source electrode in the transistor 100, and may be provided to penetrate the gate insulating film 130, the first channel layer 140, and other insulating layers inside the word line 120. The bit line 160 may be formed by forming a hole to penetrate the gate insulating film 130, the first channel layer 140, and other insulating layers inside the word line 120, and filling the inside of the formed hole with an electrically conductive material. The bit line 160 may be formed of at least one metal selected from the group consisting of aluminum, neodymium, silver, chromium, titanium, tantalum, molybdenum, and copper, or an alloy containing these metals.

[0038] Meanwhile, a capacitor line 180 acting as a drain electrode in the transistor 100 may be formed on the outer side of the word line 120. For example, the gate line 180 may be formed to have a shape surrounding the word lines 120 disposed on the upper and lower sides of the first channel layer 140. The gate line 180 may be made of at least one metal selected from the group consisting of aluminum, neodymium, silver, chromium, titanium, tantalum, molybdenum, and copper, or an alloy containing any of these metals.

[0039] In the transistor 100 according to the first embodiment of the present invention, the second channel layer 170 is formed on the exposed surface of the first channel layer 140. For example, in the transistor 100 according to the first embodiment of the present invention, the second channel layer 170 may be formed between the first channel layer 140 and the bit line 160 as shown in FIG. 2. However, the position where the second channel layer 170 is formed is not limited thereto, and it goes without saying that the first channel layer 170 may be formed on various exposed surfaces where the first channel layer 170 is exposed before the word line 120, the bit line 160, and the capacitor line 180 are formed.

[0040] The second channel layer 170 may be formed of at least one of IGZO (In-Ga-Zn-O), IZO (In-Zn-O), InO, and ZnO. If a metal line is formed to connect with the first channel layer 140 without forming the second channel layer 170, the first channel layer 140 may be exposed by an etching gas in the process of patterning the laminate to form the metal line. If the first channel layer 140 is exposed by the etching gas, the first channel layer 140 is damaged by the etching gas from the exposed surface to a certain depth, losing oxygen and becoming in an oxygen-deficient state. In addition, if a metal line is formed directly on the surface of the first channel layer 140 damaged by the etching gas, oxygen will move from the first channel layer 140 to the metal line when the transistor is driven. In this way, when oxygen deficiency occurs in the first channel layer 140, the electrical conductivity of the first channel layer 140 unintentionally increases and the first channel layer 140 becomes conductive, causing a short circuit in the element and making it impossible to stably operate the transistor.

[0041] In contrast, when the second channel layer 170 made of at least one of IGZO, IZO, InO, and ZnO is formed between the first channel layer 140 and the metal line as in the embodiment of the present invention, the oxygen or metal substance contained in the second channel layer 170 can fill the place where oxygen is removed in the first channel layer 140. That is, the metal element or oxygen contained in the second channel layer 170 spreads to the place where oxygen is removed in the active layer 130, and prevents oxygen from moving from the first channel layer 140 to the metal line, and prevents the first channel layer 140 from becoming a conductor. A method of forming the second channel layer 170 between the first channel layer 140 and the metal line in this way will be described later with reference to FIGS. 4 to 6.

[0042] 3, the transistor 100 according to the second embodiment of the present invention may include a substrate 110, a word line 120 provided on the substrate 110, a first channel layer 140 provided inside the word line 120 and extending in the vertical direction, and a gate insulating film 130 provided to cover the first channel layer. The transistor 100 according to the second embodiment of the present invention may include a bit line 160 provided to penetrate the first channel layer 140 and the gate insulating film 130, and may further include a capacitor line 180 provided inside the gate insulating film 130 to be connected to the first channel layer 140, and various insulating layers interposed between the respective layers and lines. As described above, the metal line according to the embodiment of the present invention includes at least one of the word line 120, the bit line 160, and the capacitor line 180.

[0043] The substrate 110 may be made of a material containing silicon, an insulating layer may be formed on the substrate, and a word line 120 serving as a gate electrode in the transistor 100 is formed on the insulating layer. The word line 120 may be made of a material having electrical conductivity, for example, at least one metal selected from the group consisting of aluminum, neodymium, silver, chromium, titanium, tantalum, molybdenum, and copper, or an alloy containing these metals. An insulating film may be provided on the word line 120.

[0044] A first channel layer 140 and a gate insulating film 130 are formed inside the word line 120. For example, the first channel layer 140 may be provided along the periphery of a part of the bit line 160 provided to penetrate the word line 120 and the insulating layer. A barrier film may be formed between the first channel layer 140 and the bit line 160, and the first channel layer 140 may be provided away from the bit line 160 except for a part of the surface that contacts the bit line 160. A capacitor line 170 connected to the first channel layer 140 is provided on the upper side of the word line 120. In this case, the first channel layer 140 and the capacitor line 170 may be covered by the gate insulating film 130. Here, the transistor 100 according to the second embodiment of the present invention is different from the transistor 100 according to the first embodiment of the present invention described above only in terms of the stacked structure, and the functions of each layer may be the same. Therefore, a description that overlaps with the contents described above regarding the transistor 100 according to the first embodiment of the present invention will be omitted.

[0045] Similarly, in the transistor 100 according to the second embodiment of the present invention, the second channel layer 170 is formed on the exposed surface of the first channel layer 140. For example, in the transistor 100 according to the second embodiment of the present invention, the second channel layer 170 may be formed between the first channel layer 140 and the bit line 160 as shown in FIG. 3. However, the position where the second channel layer 170 is formed is not limited thereto, and as described above, the first channel layer 170 may be formed on various exposed surfaces that are exposed before the word line 120, the bit line 160, and the capacitor line 180 are formed.

[0046] The second channel layer 170 may be formed of at least one of IGZO, IZO, InO, and ZnO. If the second channel layer 170 is not formed and a metal line is formed to connect with the first channel layer 140, the first channel layer 140 may be exposed by the etching gas in the process of patterning the laminate to form the metal line. If the first channel layer 140 is exposed by the etching gas, the first channel layer 140 is damaged by the etching gas from the exposed surface to a certain depth, loses oxygen, and becomes oxygen deficient. In addition, if a metal line is formed directly on the surface of the first channel layer 140 damaged by the etching gas, oxygen moves from the first channel layer 140 to the metal line when the transistor is driven. If oxygen deficient occurs in the first channel layer 140, the electrical conductivity of the first channel layer 140 increases unintentionally and becomes a conductor, causing a short circuit of the element and making it impossible to stably drive the transistor.

[0047] In contrast, when the second channel layer 170 made of at least one of IGZO, IZO, InO, and ZnO is formed between the first channel layer 140 and the metal line as in the embodiment of the present invention, the oxygen or metal substance contained in the second channel layer 170 can fill the place where oxygen is removed in the first channel layer 140. That is, the metal element or oxygen contained in the second channel layer 170 spreads to the place where oxygen is removed in the active layer 130, and prevents oxygen from moving from the first channel layer 140 to the metal line, and prevents the first channel layer 140 from becoming a conductor. A method of forming the second channel layer 170 between the first channel layer 140 and the metal line will be described later with reference to FIGS. 7 to 9.

[0048] On the other hand, in Figures 2 and 3, the second channel layer 170 is formed on the exposed surface of the first channel layer 140 to prevent the first channel layer 140 from becoming a conductor. However, the first channel layer 140 can also be prevented from becoming a conductor by forming an electrode or a treatment layer on the exposed surface of the first channel layer 140.

[0049] That is, in a transistor having a metal line and a channel layer, the channel layer can be prevented from becoming a conductor by forming an electrode from at least one of Ru and RuO on the exposed surface of the channel layer containing metal oxide, or by treating the exposed surface of the channel layer with at least one of heat and plasma to form a treatment layer.

[0050] 4 to 6 are diagrams that roughly show a method for manufacturing a transistor according to a first embodiment of the present invention, and FIGS. 7 to 9 are diagrams that roughly show a method for manufacturing a transistor according to a second embodiment of the present invention.

[0051] 4 to 9, a method for manufacturing a transistor according to an embodiment of the present invention is a method for manufacturing a transistor having a metal line and a channel layer, and includes the steps of providing a patterned substrate to expose a first channel layer 130 containing a metal oxide, and forming a second channel layer 170 made of at least one of IGZO, IZO, InO, and ZnO on the exposed surface of the first channel layer 130.

[0052] First, a method for manufacturing a transistor according to the first embodiment of the present invention will be described with reference to FIGS.

[0053] The step of providing a patterned substrate 110 includes providing a patterned substrate such that a first channel layer 130 including a metal oxide is exposed, as shown in Fig. 4. Here, the patterned substrate may include a substrate 110, a word line 120 provided on the substrate 110, a gate insulating film 130 provided on the word line 120, a first channel layer 140 provided on the gate insulating film 130, the gate insulating film 130 provided on the first channel layer 140, and the word line 120 provided on the gate insulating film 130.

[0054] In the patterned substrate 110, holes for forming the bit lines 160 are formed, and the first channel layer 140 is exposed through the holes. Here, the area of ​​the first channel layer 140 exposed toward the holes is defined as an exposed surface of the first channel layer 140.

[0055] After the patterned substrate 110 is provided, as shown in FIG. 5, a second channel layer 170 is formed on the exposed surface of the first channel layer 140 from at least one of IGZO, IZO, InO, and ZnO. Such a second channel layer 170 can be formed by various thin film formation processes. For example, the step of forming the second channel layer 170 may be performed by a chemical vapor deposition (CVD) method in which a source gas containing a metal element and a reactive gas containing oxygen are simultaneously supplied onto the exposed surface of the first channel layer 140, or an atomic layer deposition (ALD) method in which a process cycle including a step of supplying a source gas containing a metal element and a step of supplying a reactive gas containing oxygen is repeated multiple times onto the exposed surface of the first channel layer 140. In this case, the atomic layer deposition process may be performed by repeating a process cycle including a step of supplying a source gas containing a metal element, a step of purging the source gas, a step of supplying a reactive gas containing oxygen, and a step of purging the reactive gas in this order multiple times.

[0056] Meanwhile, in the step of forming the second channel layer 170, the second channel layer 170 may be formed by a selective deposition method. Here, the selective deposition method means a method of selectively depositing a thin film only on the surface of a specific region. In this case, the selective deposition method may include at least one of a selective chemical vapor deposition method and a selective atomic layer deposition method, and the second channel layer 170 may be formed by applying a variety of known selective deposition methods.

[0057] In addition, the method for manufacturing the transistor according to the first embodiment of the present invention may include a step of forming the gate insulating film 130 adjacent to the first channel layer 140 and a step of forming the word line 120 adjacent to the gate insulating film 130. For example, in the step of providing a patterned substrate in the first embodiment of the present invention, the gate insulating film 130 may be formed on the word line 120, the first channel layer 140 may be formed on the gate insulating film 130, the gate insulating film 130 may be formed on the first channel layer 140, and then the word line 120 may be formed on the gate insulating film 130, the gate insulating film 130 may be formed adjacent to the first channel layer 140, and the word line 120 may be formed adjacent to the gate insulating film 130.

[0058] After forming the second channel layer 170, as shown in Fig. 6, a hole provided inside the word line 120 penetrating the gate insulating film 130, the first channel layer 140 and other insulating layers may be filled with an electrically conductive material to form a bit line 160. Meanwhile, Figs. 4 to 6 show an example in which a patterned substrate on which the capacitor line 180 is already formed is used, but it goes without saying that the capacitor line 180 may be formed after the second channel layer 170 is formed.

[0059] Next, a method for manufacturing a transistor according to a second embodiment of the present invention will be described with reference to FIGS.

[0060] In the step of providing a patterned substrate 110, as shown in Fig. 7, a patterned substrate is provided so that a first channel layer 130 including a metal oxide is exposed. Here, the patterned substrate may include a substrate 110, a word line 120 provided on the substrate 110, a first channel layer 140 provided inside the word line 120 and extending in the vertical direction, and a gate insulating film 130 provided to cover the first channel layer. In addition to these, the patterned substrate may further include a capacitor line 180 provided inside the gate insulating film 130 to be connected to the first channel layer 140.

[0061] After the patterned substrate 110 is provided, as shown in FIG. 8, the second channel layer 170 is formed on the exposed surface of the first channel layer 140 from at least one of IGZO, IZO, InO, and ZnO. Such a second channel layer 170 can be formed by various thin film formation processes. For example, the step of forming the second channel layer 170 may be performed by a chemical vapor deposition method in which a source gas containing a metal element and a reactive gas containing oxygen are simultaneously supplied onto the exposed surface of the first channel layer 140, or an atomic layer deposition method in which a process cycle including a step of supplying a source gas containing a metal element and a step of supplying a reactive gas containing oxygen is repeated multiple times onto the exposed surface of the first channel layer 140. In this case, the atomic layer deposition process may be performed by repeating a process cycle including a step of supplying a source gas containing a metal element, a step of purging the source gas, a step of supplying a reactive gas containing oxygen, and a step of purging the reactive gas in this order multiple times.

[0062] Meanwhile, in the step of forming the second channel layer 170, the second channel layer 170 may be formed by a selective deposition method. Here, the selective deposition method means a method of selectively depositing a thin film only on the surface of a specific region. In this case, the selective deposition method may include at least one of a selective chemical vapor deposition method and a selective atomic layer deposition method, and the second channel layer 170 may be formed by applying various known selective deposition methods.

[0063] Also, the method for manufacturing a transistor according to the second embodiment of the present invention may include a step of forming a gate insulating film 130 adjacent to the first channel layer 140, and a step of forming a word line 120 adjacent to the gate insulating film 130. For example, in the step of providing a patterned substrate in the second embodiment of the present invention, the gate insulating film 130 may be formed to cover the first channel layer 140 in a circumferential direction of a hole for forming the bit line 160, and the word line 120 may be formed outside the gate insulating film.

[0064] After the second channel layer 170 is formed, as shown in Fig. 9, the bit line 160 may be formed by filling the hole provided to penetrate the first channel layer 140 and the gate insulating film 130 with an electrically conductive material. Meanwhile, Figs. 7 to 9 show an example in which a patterned substrate on which the word line 120 is already formed is used, but it goes without saying that the word line 120 may be formed after the second channel layer 170 is formed.

[0065] On the other hand, in Figures 4 to 9, the second channel layer 170 is formed on the exposed surface of the first channel layer 140 to prevent the first channel layer 140 from becoming a conductor. However, the first channel layer 140 can also be prevented from becoming a conductor by forming an electrode or a treatment layer.

[0066] Here, the step of forming the electrode may be performed by chemical vapor deposition or atomic layer deposition, as in the case of forming the second channel layer described above. Also, in the step of forming the electrode, the electrode may be formed by a selective deposition method, and it goes without saying that such a selective deposition method may include at least one of a selective chemical vapor deposition method and a selective atomic layer deposition method.

[0067] On the other hand, in the step of forming the treatment layer, the exposed surface of the channel layer may be treated with at least one of heat and plasma to form the treatment layer. Here, when the exposed surface of the channel layer is heat-treated, O2 gas may be supplied to the exposed surface to perform the heat treatment, and when the exposed surface of the channel layer is plasma-treated, O2 and at least one of NF3 gas may be supplied to the exposed surface to perform the plasma treatment. For example, when NF3 gas is supplied to perform the plasma treatment, physical and electrical damage can be minimized and a high selectivity can be ensured.

[0068] As described above, according to an embodiment of the present invention, by forming a functional layer on the exposed surface of the channel layer to prevent oxygen deficiency in the channel layer, it is possible to prevent the channel layer from becoming a conductor and improve switching characteristics.

[0069] In addition, the contact resistance between the channel layer and the source and drain electrodes can be effectively reduced, improving the characteristics and reliability of the device.

[0070] Although the preferred embodiment of the present invention has been described and illustrated using specific terms, these terms are merely for the purpose of clearly describing the present invention, and it is clear that the embodiments of the present invention and the described terms can be modified and changed in various ways without departing from the technical spirit and scope of the appended claims. These modified embodiments should not be understood separately from the spirit and scope of the present invention, but should be considered to belong to the scope of the claims of the present invention.

Claims

1. A method for manufacturing a transistor having a metal line and a channel layer, The steps include forming holes through a first channel layer containing metal oxide to provide a patterned substrate so that the first channel layer is exposed, The steps include forming a second channel layer on the exposed surface of the first channel layer facing the hole, using at least one of IGZO, IZO, InO, and ZnO, The steps include filling the aforementioned holes with an electrically conductive material to form the metal line, A method for manufacturing transistors, including [the specified part of the method].

2. In the step of forming the second channel layer, The method for manufacturing a transistor according to claim 1, wherein the second channel layer is formed by a selective deposition method.

3. The method for manufacturing a transistor according to claim 2, wherein the selective deposition method includes at least one of a selective atomic layer deposition method and a selective chemical vapor deposition method.

4. The steps include forming an insulating film adjacent to the first channel layer, The steps include forming the metal line adjacent to the insulating film, A method for manufacturing a transistor according to claim 1, including the following:

5. The method for manufacturing a transistor according to claim 1, wherein the metal line includes at least one of the bit line and the word line of the memory element.

6. A method for manufacturing a transistor having a metal line and a channel layer, The steps include forming holes through a channel layer containing metal oxide and providing a patterned substrate so that the channel layer is exposed, The steps include forming an electrode on the exposed surface of the channel layer facing the hole using at least one of Ru and RuO, The steps include filling the aforementioned holes with an electrically conductive material to form the metal line, A method for manufacturing transistors, including [the specified part of the method].

7. A method for manufacturing a transistor having a metal line and a channel layer, The steps include forming holes through a channel layer containing metal oxide and providing a patterned substrate so that the channel layer is exposed, The steps include forming a treatment layer on the exposed surface of the channel layer facing the hole, The steps include filling the aforementioned holes with an electrically conductive material to form the metal line, A method for manufacturing transistors, including [the specified part of the method].

8. In the step of forming the treatment layer, A method for manufacturing a transistor according to claim 7, wherein the exposed surface of the channel layer is treated by at least one of heat treatment and plasma treatment.

9. The heat treatment is performed on the exposed surface of the channel layer. ２ It is carried out by supplying gas. The plasma treatment is performed on the exposed surface of the channel layer. ２ and NF ３ A method for manufacturing a transistor according to claim 8, wherein at least one of the gases is supplied.

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