Semiconductor devices and methods

Abstract

The present disclosure relates to a semiconductor device including a substrate including a first wide bandgap semiconductor material and a first region of a first conductivity type and a second region of a second conductivity type disposed above the substrate, the first region and the second region including a second wide bandgap semiconductor material, the first region and the second region forming a Zener PN diode configured as an antifuse. A corresponding method for manufacturing the semiconductor device is also provided.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. The present disclosure further relates to a method for manufacturing such a semiconductor device. [Background technology]

[0002] An antifuse is a semiconductor electrical device that has a high resistance in its initial state. After a special process called programming, the antifuse becomes low resistance and performs the opposite function of a fuse. Antifuses are widely used in integrated circuits as programmable logic devices (for design customization), one-time programmable read-only memories (OTP), trimming the values ​​of analog components, adjusting voltage reference circuits, or for serial code identification (traceability) of dies and chips.

[0003] One of the most efficient and cost-effective antifuses developed in silicon-based technology is the Zener-type antifuse, also known as the Zener zap. Zener-type antifuses exist in bipolar, complementary metal-oxide semiconductor (CMOS), bipolar CMOS (Bi-CMOS), mixed-signal, and smart power technologies.

[0004] A Zener device, or more generally a PN junction or Zener diode, is formed by at least two semiconductor elements of opposite conductivity type (different doping elements): one element is of the N type, that is, it is doped so that it can provide an excess of negative charges (electrons), while the other element is of the P type, that is, it is doped so that it can provide an excess of positive charges (holes).

[0005] Zener antifuses are programmed by applying either a high voltage or a high current to a Zener diode for a short period of time. The voltage or current spike produces enough energy to overheat the structure and permanently damage it, thereby shorting it out. Programming with a current spike (or voltage spike) is called Zener zapping. Zener zapping is shown diagrammatically in Figure 1.

[0006] Wide band gap (WBG) technology is a new technology being developed to replace silicon technology. Compared to silicon, the superior material properties of WBG technology make it more suitable for various applications and areas, such as power applications. Zener type antifuses are not currently used in WBG semiconductor technology for several reasons, including, for example:

[0007] a) Maturity: WBG technologies are still in research and development and are not yet ready to be integrated into existing technologies, with the exception of, for example, Gallium Nitride (GaN).

[0008] b) Many of the topologies employed in WBGs are vertical, which can make it difficult to integrate devices.

[0009] Currently, there are no known implementations of Zener-type antifuses in WBG technology. In recent years, academia and industry have focused on integrating basic elements and circuits around power GaN high electron mobility transistors (HEMTs).

[0010] A natural solution that the industry could adopt could be to co-embed GaN HEMT power devices with silicon-based antifuses. However, this would mean encapsulating two different dies from two different technologies in one package. This solution may require complex packaging schemes, especially regarding placement and wiring / connection of the different dies. In addition, the reliability of the entire co-packaged system may not be guaranteed, and the use of two dies may result in a large resulting chip area. Summary of the Invention [Means for solving the problem]

[0011] The present disclosure aims to improve upon the above solutions by monolithically incorporating Zener-type antifuses into WBG technology.

[0012] This is achieved by the solutions provided in the independent claims. Advantageous implementations are defined in the dependent claims.

[0013] According to a first aspect, there is provided a semiconductor device comprising: a substrate comprising a first wide bandgap semiconductor material; and a first region of a first conductivity type and a second region of a second conductivity type disposed above the substrate, the first region and the second region comprising a second WBG semiconductor material, the first region and the second region forming a Zener PN diode configured as an anti-fuse.

[0014] WBG semiconductor materials include materials with bandgaps in the range above 2 eV.

[0015] According to a first aspect, the Zener-type antifuse may be monolithically integrated into WBG technology.

[0016] In one implementation of the first aspect, the first region and the second region are arranged in a horizontal configuration with respect to their arrangement above the substrate, with the first region being arranged above the substrate and the second region being arranged above the substrate next to the first region. Alternatively, the first region and the second region are arranged in a vertical configuration with respect to their arrangement above the substrate, with the second region being arranged above the first region and the first region being arranged above the substrate.

[0017] This provides the advantage that the Zener antifuse can be easily integrated into both horizontal and vertical WBG technologies.

[0018] In one implementation of the first aspect, the first region and the second region are separated by a distance. Alternatively, the first region and the second region are adjacent. Alternatively, the first region and the second region overlap.

[0019] This has the advantage that the efficiency of the programming or zapping process can be optimized in terms of time, applied voltage, applied current and / or dissipated energy.

[0020] In one implementation of the first aspect, the first region has a first shape including a first lateral projection. The first lateral projection has a tip shape or a truncated tip shape or another polygonal shape, or the first shape includes a cylindrical shape or a cylindrical shape with the first lateral projection, and the first lateral projection has a tip shape or a truncated tip shape or another polygonal shape. Further, the second region has a second shape including a second lateral projection. The second lateral projection has a tip shape or a truncated tip shape or another polygonal shape, or the second shape includes a cylindrical shape or a cylindrical shape with the second lateral projection, and the lateral projection has a tip shape or a truncated tip shape or another polygonal shape.

[0021] This allows further optimisation of the efficiency of the programming or zapping process in terms of time, applied voltage, applied current and / or dissipated energy.

[0022] In one implementation of the first aspect, the semiconductor device further includes a first metal gate in electrical contact with the first region and a second metal gate in electrical contact with the second region.

[0023] This has the advantage that a metallic filament may be formed between a first region of a first conductivity type and a second region of a second conductivity type to cause an electrical short, thereby enabling programming of the Zener PN junction configured as an antifuse.

[0024] In one implementation of the first aspect, the semiconductor device further includes a semiconductor layer including a third wide band gap semiconductor material, the semiconductor layer being disposed between the substrate and the first region and the second region, respectively.

[0025] This provides the advantage that a channel is formed beneath the semiconductor layer in a region beneath the first and second regions, thereby enabling the implementation of a Zener type antifuse in HEMT technology.

[0026] In one implementation of the first aspect, the semiconductor device further includes a semiconductor layer including a third wide band gap semiconductor material, and the semiconductor layer is disposed above the first region and the second region, or the second region is disposed above the first region and the semiconductor layer is disposed above the second region.

[0027] This provides the advantage that a channel is formed in the region above the first and second regions, thereby enabling the implementation of a Zener type antifuse in vertical HEMT technology.

[0028] In one implementation of the first aspect, the first metal gate and the second metal gate contact the first region and the second region through the semiconductor layer. Alternatively, the second metal gate contacts the second region through the semiconductor layer.

[0029] In one implementation of the first aspect, a semiconductor device includes at least one additional first region of a first conductivity type and at least one additional second region of a second conductivity type disposed above a semiconductor layer, where the at least one additional first region and the at least one additional second region comprise a second wide band gap semiconductor material, at least one additional first metal gate in electrical contact with the at least one additional first region, and at least one additional second metal gate in electrical contact with the at least one additional second region. a second metal gate and at least one additional semiconductor layer comprising a third wide bandgap semiconductor material and disposed above the at least one additional first region and the at least one additional second region, wherein the at least one additional first metal gate and the at least one additional second metal gate contact the at least one additional first region and the at least one additional second region through the at least one additional semiconductor layer, and the at least one additional first region and the at least one additional second region form at least one additional Zener PN diode configured as an antifuse.

[0030] This provides the advantage that multiple stacks of Zener type antifuses in WBG technology can be created.

[0031] In one implementation of the first aspect, the first region and the second region are disposed in an N-well or P-well structure formed in a substrate. Alternatively, the first region is disposed in a first well structure and the second region is disposed in a second well structure, the first well structure and the second well structure comprising an N-well or P-well structure formed in a substrate.

[0032] This provides the advantage that Zener type antifuses can be integrated into WBG and ultra-wide bandgap (UWBG) technologies.

[0033] In this disclosure, UWBG semiconductor materials include semiconductor materials with a bandgap greater than 4 eV.

[0034] In one implementation of the first aspect, the semiconductor device further includes at least one structure of thermal insulation material in partial or complete contact with the first region, additionally or alternatively with the second region, and additionally or alternatively with the substrate, wherein the at least one structure of thermal insulation material includes silicon dioxide (SiO2) or a nitride compound including any one of silicon nitride (Si3N4) or aluminum gallium nitride (AlGaN) or aluminum nitride (AlN).

[0035] This has the advantage that it can cause a thermal increase, e.g. overheating, during the zapping process, which can facilitate programming of the Zener PN diode configured as an anti-fuse.

[0036] In one implementation of the first aspect, the semiconductor device further includes an intermediate region of a third conductivity type disposed between the first region and the second region, the intermediate region including a second wide band gap semiconductor material, and the intermediate region being a P-type region or an N-type region or an undoped type region.

[0037] This has the advantage of making the programming or zapping process of the Zener PN diode configured as an antifuse even easier.

[0038] In one implementation of the first aspect, the second wide band gap semiconductor material includes GaN.

[0039] In one implementation of the first aspect, the third wide band gap material includes AlGaN.

[0040] In one implementation of the first aspect, the first metal gate is in partial or total contact with the first region. Alternatively, the first metal gate extends partially or completely into the first region. The second metal gate is in partial or total contact with the second region, or the second metal gate extends partially or completely into the second region.

[0041] In one implementation of the first aspect, the first metal gate and the second metal gate comprise aluminum, titanium, copper, gold, or another metal element, or a metal stack including any one of Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN.

[0042] In one implementation of the first aspect, the first wide bandgap semiconductor material comprises silicon carbide (SiC) or gallium oxide (Ga2O3).Alternatively, the first wide bandgap semiconductor material comprises a heteroepitaxial bulk material, and the heteroepitaxial bulk material comprises gallium nitride GaN on silicon Si, or GaN on SiC, or GaN on diamond, or a wide bandgap semiconductor on an insulator material.

[0043] According to a second aspect, there is provided a method for manufacturing a semiconductor device, the method comprising the steps of providing a substrate comprising a first wide bandgap semiconductor material and forming a first region of a first conductivity type and a second region of a second conductivity type disposed above the substrate, the first region and the second region comprising a second wide bandgap semiconductor material, the first region and the second region forming a Zener PN diode configured as an antifuse.

[0044] Wide bandgap semiconductor materials include materials with bandgaps in the range greater than 2 eV.

[0045] This has the advantage of providing a Zener type antifuse that can be monolithically integrated into WBG technology.

[0046] In one implementation of the second aspect, the first region and the second region are arranged in a horizontal configuration with respect to their arrangement above the substrate, with the first region being arranged above the substrate and the second region being arranged above the substrate next to the first region. Alternatively, the first region and the second region are arranged in a vertical configuration with respect to their arrangement above the substrate, with the second region being arranged above the first region and the first region being arranged above the substrate.

[0047] This provides the advantage that the Zener antifuse can be easily integrated into both horizontal and vertical WBG technologies.

[0048] In one implementation of the second aspect, the first region and the second region are separated by a distance. Alternatively, the first region and the second region are adjacent. Alternatively, the first region and the second region overlap.

[0049] This has the advantage that the efficiency of the programming or zapping process can be optimized in terms of time, applied voltage, applied current and / or dissipated energy.

[0050] In one implementation of the second aspect, the first region has a first shape including a first lateral projection. The first lateral projection has a tip shape or a truncated tip shape or another polygonal shape, or the first shape includes a cylindrical shape or a cylindrical shape with the first lateral projection, and the first lateral projection has a tip shape or a truncated tip shape or another polygonal shape. Furthermore, the second region has a second shape including a second lateral projection. The second lateral projection has a tip shape or a truncated tip shape or another polygonal shape, or the second shape includes a cylindrical shape or a cylindrical shape with the second lateral projection, and the lateral projection has a tip shape or a truncated tip shape or another polygonal shape.

[0051] This allows further optimisation of the efficiency of the programming or zapping process in terms of time, applied voltage, applied current and / or dissipated energy.

[0052] In one implementation of the second aspect, the method further includes forming a first metal gate in electrical contact with the first region and a second metal gate in electrical contact with the second region.

[0053] This has the advantage that a metallic filament may be formed between a first region of a first conductivity type and a second region of a second conductivity type to cause an electrical short, thereby enabling programming of the Zener PN junction configured as an antifuse.

[0054] In one implementation of the second aspect, the method further includes a semiconductor layer including a third wide band gap semiconductor material disposed between the substrate and the first region and the second region, respectively.

[0055] This provides the advantage that a channel is formed beneath the semiconductor layer in a region beneath the first and second regions, thereby enabling the implementation of a Zener type antifuse in HEMT technology.

[0056] In one implementation of the second aspect, the method further includes forming a semiconductor layer including a third wide band gap semiconductor material, wherein the semiconductor layer is disposed above the first region and the second region, or the second region is disposed above the first region and the semiconductor layer is disposed above the second region.

[0057] This provides the advantage that a channel is formed in the region above the first and second regions, thereby enabling the implementation of a Zener type antifuse in vertical HEMT technology.

[0058] In one implementation of the second aspect, the first metal gate and the second metal gate contact the first region and the second region through the semiconductor layer. Alternatively, the second metal gate contacts the second region through the semiconductor layer.

[0059] In one implementation of the second aspect, the method includes forming at least one additional first region of a first conductivity type and at least one additional second region of a second conductivity type disposed above a semiconductor layer, where the at least one additional first region and the at least one additional second region comprise a second wide band gap semiconductor material; forming at least one additional first metal gate in electrical contact with the at least one additional first region and at least one additional second metal gate in electrical contact with the at least one additional second region; and forming a third wide band gap semiconductor material. and forming at least one additional semiconductor layer comprising a gap semiconductor material and disposed above the at least one additional first region and the at least one additional second region, wherein the at least one additional first metal gate and the at least one additional second metal gate contact the at least one additional first region and the at least one additional second region through the at least one additional semiconductor layer, and the at least one additional first region and the at least one additional second region form at least one additional Zener PN diode configured as an antifuse.

[0060] This provides the advantage that multiple stacks of Zener type antifuses in WBG technology can be created.

[0061] In one implementation of the second aspect, the first region and the second region are disposed in an N-well or P-well structure formed in a substrate. Alternatively, the first region is disposed in a first well structure and the second region is disposed in a second well structure, the first well structure and the second well structure comprising an N-well or P-well structure formed in a substrate.

[0062] This provides the advantage that the Zener antifuse can be integrated into WBG and UWBG technologies.

[0063] In this disclosure, UWBG semiconductor materials include semiconductor materials with a bandgap greater than 4 eV.

[0064] In one implementation of the second aspect, the method further includes forming at least one structure of thermal insulation material in partial or complete contact with the first region, additionally or alternatively with the second region, and additionally or alternatively with the substrate, wherein the at least one structure of thermal insulation material comprises SiO2 or a nitride compound including any one of Si3N4 or AlGaN or AlN.

[0065] This has the advantage that it can cause a thermal increase, e.g. overheating, during the zapping process, which can facilitate programming of the Zener PN diode configured as an anti-fuse.

[0066] In one implementation of the second aspect, the method further includes an intermediate region of a third conductivity type disposed between the first region and the second region, the intermediate region comprising a second wide band gap semiconductor material, and the intermediate region being a P-type region or an N-type region or an undoped type region.

[0067] This has the advantage of making the programming or zapping process of the Zener PN diode configured as an antifuse even easier.

[0068] In one implementation of the second aspect, the second wide band gap semiconductor material includes GaN.

[0069] In one implementation of the second aspect, the third wide band gap material includes AlGaN.

[0070] In one implementation of the second aspect, the first metal gate is in partial or total contact with the first region. Alternatively, the first metal gate extends partially or completely into the first region. The second metal gate is in partial or total contact with the second region, or the second metal gate extends partially or completely into the second region.

[0071] In one implementation of the first aspect, the first metal gate and the second metal gate comprise aluminum, titanium, copper, gold, or another metal element, or a metal stack including any one of Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN.

[0072] In one implementation of the second aspect, the first wide bandgap semiconductor material includes SiC or Ga2O3. Alternatively, the first wide bandgap semiconductor material includes a heteroepitaxial bulk material, the heteroepitaxial bulk material including GaN on Si, or GaN on SiC, or GaN on diamond, or a wide bandgap semiconductor on an insulator material.

[0073] The method according to the second aspect and its implementations provide the same advantages and benefits as those described above for the device of the first aspect and its respective implementations.

[0074] The above aspects and implementations of the present disclosure are explained in the following description in conjunction with the accompanying drawings. [Brief description of the drawings]

[0075] [Figure 1] Schematic diagram of the Zener zapping process. [Diagram 2] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 3a] 1A-1C are top views of examples of a first shape and a second shape according to the present disclosure. [Figure 3b] 1A-1C are top views of examples of a first shape and a second shape according to the present disclosure. [Figure 3c] 1A-1C are top views of examples of a first shape and a second shape according to the present disclosure. [Figure 3d] 1A-1C are top views of examples of a first shape and a second shape according to the present disclosure. [Figure 4] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 5a] 1 is a schematic diagram of an example of a metal gate in a semiconductor device according to the present disclosure. [Figure 5b] 1 is a schematic diagram of an example of a metal gate in a semiconductor device according to the present disclosure. [Figure 5c] 1 is a schematic diagram of an example of a metal gate in a semiconductor device according to the present disclosure. [Figure 6a] 1 is a schematic diagram of an example of a metal gate in a semiconductor device according to the present disclosure. [Figure 6b] 1 is a schematic diagram of an example of a metal gate in a semiconductor device according to the present disclosure. [Figure 7] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 8a] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 8b] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 8c] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 9a] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 9b] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 10] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 11] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 12] 1 is a schematic diagram of a semiconductor device according to the present disclosure. [Figure 13] FIG. 1 illustrates a method for manufacturing a semiconductor device according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0076] 2 shows a schematic diagram of a semiconductor device 10 according to an exemplary embodiment of the present disclosure. The semiconductor device 10 includes a substrate 12, a first region 14a of a first conductivity type, and a second region 14b of a second conductivity type 14b. The first region 14a and the second region 14b are disposed above the substrate 12.

[0077] The substrate 12 includes a first WBG semiconductor material including SiC or Ga2O3. Alternatively, the first WBG semiconductor material includes a heteroepitaxial bulk material including GaN on silicon (Si), or GaN on SiC, or GaN on diamond, or a WBG semiconductor on an insulator material. The substrate 12 may include a base structure having one or more layers formed thereon by an epitaxial growth process.

[0078] The first region 14a and the second region 14b include a second WBG semiconductor material. The second WBG semiconductor material includes GaN.

[0079] Conventional semiconductors, such as silicon, have bandgaps in the range of 0.6-1.5 eV, whereas WBG materials have bandgaps in the range of over 2 eV. Such larger bandgaps enable devices based on WBG semiconductors to operate at higher voltages, frequencies, and temperatures than devices based on conventional semiconductor materials.

[0080] In this disclosure, WBG semiconductor materials include semiconductor materials with bandgaps in the range above 2 eV.

[0081] For example, the bandgap value of GaN is 3.44 eV.

[0082] The first region 14a of the first conductivity type can be a P-type region or an N-type region. Conversely, the second region 14b of the second conductivity type can be an N-type region or a P-type region. In this way, the first region 14a and the second region 14b form a Zener PN diode configured as an antifuse.

[0083] In general, semiconductor device 10 may be fabricated by standard mask / implant processes, controlled sequential epitaxial growth and epitaxy, and etching techniques.

[0084] The first region 14a of the first conductivity type and the second region 14b of the second conductivity type may be made by conventional techniques for WBG technology, for example from undoped GaN by implantation, in-situ or ex-situ incorporation of dopants during epitaxial growth, metalorganic chemical vapor deposition (MOCVD) growth, molecular beam epitaxy (MBE), delta doping, or other deposition / doping techniques.

[0085] Alternatively, the first region 14a of the first conductivity type and the second region 14b of the second conductivity type may be created by successive epitaxial growth combined with selective etching and regrowth, which may allow fine tuning of the dopant profile in each region 14a and 14b.

[0086] The chemical species used to dope the first and second regions 14a, 14b can be, for example, but not limited to, magnesium, iron, or silicon.

[0087] The design of the Zener antifuse relies on the intentional creation of an abrupt geometric layout change in two regions 14a and 14b of different conductivity types to enhance the electric field and cause premature breakdown of the PN diode. The choice of geometry and doping levels can be made to optimize the efficiency of the programming process in terms of time, applied voltage, applied current and / or dissipated energy.

[0088] Thus, in the present disclosure, the first region 14a of a first conductivity type has a first shape and the second region 14b of a second conductivity type has a second shape, which can optimize the efficiency of the programming or zapping process.

[0089] 3a to 3d show top views of various examples of the first shape of the first region 14a and the second shape of the second region 14b. The first region 14a may have a first shape including a first lateral protrusion. The first lateral protrusion may have a tip shape (see FIG. 3a), or a truncated tip shape (see FIG. 3b), or another polygonal shape. Alternatively, the first shape may include a cylindrical shape (e.g., a circular shape shown in the top view of FIG. 3c), or a cylindrical shape with a first lateral protrusion, the first lateral protrusion having a tip shape or a truncated tip shape or another polygonal shape (see FIGS. 3c and 3d).

[0090] The second region 14b may have a second shape including a second lateral protrusion that may have a tip shape (see FIG. 3a) or a truncated tip shape (see FIG. 3b) or another polygonal shape, or the second shape includes a cylindrical shape (see FIG. 3c) or a cylindrical shape with a second lateral protrusion that has a tip shape or a truncated tip shape or another polygonal shape (see FIGS. 3c and 3d).

[0091] The first shape of the first region 14a and the second shape of the second region 14b may be the same or different from each other.

[0092] Additionally, the first region 14a and the second region 14b may be separated by a distance shown as distance D in the first column (left to right) of Figures 3a and 3b. Alternatively, the first region 14a and the second region 14b may be adjacent. Alternatively, the first region 14a and the second region 14b may overlap, for example, as shown in the fourth column of Figures 3a and 3b.

[0093] The first lateral protrusion of the first region 14a and the second lateral protrusion of the second region 14b may be aligned, for example, as shown in the first, second, and fourth rows of Figures 3a and 3b.

[0094] For example, as shown in FIG. 3a, a layout in which a first shape in a first region 14a has a first lateral protrusion having a tip shape and a second shape in a second region 14a has a second lateral protrusion having a tip shape may enable the most energy efficient programming process, and may be separated by a distance, may be adjacent, or may partially overlap.

[0095] For example, in a layout as shown in FIG. 3b, where the first shape of the first region 14a has a first lateral protrusion having a truncated tip shape or another polygonal shape, and the second shape of the second region 14a has a second lateral protrusion having a truncated tip shape or another polygonal shape, the energy required to program the Zener antifuse can be tailored to meet particular technology requirements.

[0096] The fabrication of the first and second regions 14a, 14b, and the first shape of the first region 14a and the second shape of the second region 14b, can be controlled by a combination of epitaxy, etching and implantation processes.

[0097] To achieve an efficient zapping process, the thickness of the first region 14a and the thickness of the second region 14b can be adjusted.

[0098] 2, the first region 14a and the second region 14b are arranged in a horizontal configuration with respect to their location above the substrate 12. This results in the first region 14a being disposed above the substrate 12 and the second region 14b being disposed above the substrate 12 next to the first region 14a.

[0099] 4, the semiconductor device 10 further includes an intermediate region 16 of a third conductivity type disposed between the first region 14a and the second region 14b. The intermediate region 16 includes a second wide bandgap semiconductor material, and the intermediate region 16 is a P-type region or an N-type region. Alternatively, the intermediate region 16 is an undoped region.

[0100] In order to achieve an efficient zapping process, the thickness of the first region 14a, the thickness of the second region 14b, and the thickness of the intermediate region 16 can be adjusted. Furthermore, similar to the first region 14a and the second region 14b, the intermediate region 16 of the third conductivity type can be fabricated by conventional techniques for WBG technology.

[0101] In this embodiment, the semiconductor device 10 further includes a semiconductor layer 20 disposed between the substrate 12 and the first and second regions 14a, 14b, respectively. The semiconductor layer 20 includes a third WBG semiconductor material. For example, the third WBG semiconductor material includes AlGaN and has a band gap value of about 6 eV.

[0102] In this embodiment, the semiconductor layer 20 provides a two-dimensional electron gas (2DEG) at the AlGaN / GaN interface beneath the first and second regions 14a, 14b, e.g., beneath a Zener PN diode configured as an antifuse, which may be tuned by further insulating implants.

[0103] The first region 14a of the first conductivity type, the second region 14b of the second conductivity type, and the intermediate region 16 of the third conductivity type may be epitaxially grown on the semiconductor layer 20. Alternatively, the first region 14a of the first conductivity type, the second region 14b of the second conductivity type, and the intermediate region 16 of the third conductivity type may be grown on regions that do not include the semiconductor layer 20, for example after partial or full etching of the semiconductor layer 20.

[0104] The semiconductor device 10 may further include a first metal gate 18a that may be in electrical contact with the first region 14a and a second metal gate 18b that may be in electrical contact with the second region 14b. The first metal gate 18a and the second metal gate 18b may include aluminum, titanium, copper, gold, or another metal element. Alternatively, the first metal gate 18a and the second metal gate 18b may include a metal stack including any one of Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN. However, other suitable material combinations may also be possible.

[0105] The first metal gate 18a may be in partial or total contact with the first region 14a. Alternatively, the first metal gate 18a may extend partially or completely into the first region 14a. The second metal gate 18b may be in partial or total contact with the second region 14b. Alternatively, the second metal gate 18b may extend partially or completely into the second region 14b.

[0106] Optionally, the first metal gate 18a or the second metal gate 18b may be in partial or total contact with the intermediate region 16.

[0107] Figures 5a-5c show schematic diagrams of example metal gates in semiconductor device 10, and for clarity only show a second region 14b of second conductivity type, a second metal gate 18b, a portion of semiconductor layer 20 below second region 14b, and a portion of substrate 12 below semiconductor layer 20. In the examples shown in Figures 5a and 5c, second metal gate 18b is in partial contact with second region 14b, while the example of Figure 5b shows second metal gate 18b in full contact with second region 14b.

[0108] 6a and 6b show schematic diagrams of examples of metal gates in semiconductor device 10, with only a second region 14b of second conductivity type, a second metal gate 18b, a portion of semiconductor layer 20 below second region 14b, and a portion of substrate 12 below semiconductor layer 20 shown for clarity. In the example shown in FIG. 6a, second metal gate 18b extends partially into second region 14b, e.g., a portion of the width of second metal gate 18b extends into second region 14b. In the example shown in FIG. 6b, second metal gate 18b extends entirely into second region 14b, e.g., the entire width of second metal gate 18b extends into second region 14b.

[0109] The first metal gate 18a and the second metal gate 18b can be fabricated by standard deposition / sputtering / filling / etching of metal elements on the surfaces of the first region 14a and the second region 14b, respectively. The first metal gate 18a and the second metal gate 18b can be easily fabricated, for example, during the fabrication of the wafer. Alternatively, the first metal gate 18a and the second metal gate 18b can be fabricated by metal deposition / sputtering / filling of the wafer backside etching region. Alternatively, the first metal gate 18a and the second metal gate 18b can be fabricated by a combination of both fabrication techniques.

[0110] Electrical isolation (insulation) between the first metal gate 18a and the second metal gate 18b may be provided, which may be achieved by providing a certain distance between the first metal gate 18a and the second metal gate 18b that is filled with a dielectric material.

[0111] The embodiment of the semiconductor device 10 shown in FIG. 4 may be a HEMT device incorporating a Zener-type antifuse, and thus conventional fabrication techniques of HEMT technology may be used to manufacture the semiconductor device 10.

[0112] 4 may allow for a relatively simple implementation of a Zener-type antifuse since no modifications from standard HEMT technology and process flows are required. Moreover, since the first region 14a of the first conductivity type and the second region 14b of the second conductivity type may be formed by a regular mask / implant process of undoped GaN material, the embodiment of the present disclosure provides a cost-effective implementation of the semiconductor device 10. Alternatively, since the first region 14a of the first conductivity type and the second region 14b of the second conductivity type may be created by successive epitaxial growth combined with selective etching and regrowth, the embodiment of the present disclosure may achieve optimal performance of a Zener PN diode configured as an antifuse, although in this example, manufacturing costs and complexity may be increased.

[0113] In an exemplary embodiment, the first region 14a of the first conductivity type and the second region 14b of the second conductivity type are arranged in a vertical configuration with respect to their location above the substrate 12. The vertical configuration may include a fully vertical configuration or a semi-vertical configuration.

[0114] 7 shows a schematic diagram of a semiconductor device 10 in which a first region 14a of a first conductivity type and a second region 14b of a second conductivity type are arranged in a fully vertical configuration. In this embodiment, the second region 14b is disposed above the first region 14a, which is disposed above the substrate 12. The semiconductor device 10 may further include an intermediate region 16 of a third conductivity type disposed between the first region 14a and the second region 14b, and a semiconductor layer 20 disposed between the substrate 12 and the first region 14a and the second region 14b.

[0115] As in the previous illustrative embodiments and examples, substrate 12 includes a first WBG semiconductor material, first region 14a of a first conductivity type, second region 14b of a second conductivity type, and intermediate region 16 include a second WBG semiconductor material, and semiconductor layer 20 includes a third WBG semiconductor material.

[0116] In the exemplary embodiment shown in FIG. 7, the semiconductor device 10 further includes a first metal gate 18a in electrical contact with the first region 14a and a second metal gate 18b in electrical contact with the second region 14b.

[0117] The first metal gate 18a may be in partial or total contact with the first region 14a, or the first metal gate 18a may extend partially or completely into the first region 14a. The second metal gate 18b may be in partial or total contact with the second region 14b, or the second metal gate 18b may extend partially or completely into the second region 14b, as in the case of the examples shown in Figures 5a to 5c or 6a to 6b. The first metal gate 18a or the second metal gate 18b may extend partially into the intermediate region 16. The first metal gate 18a and the second metal gate 18b include the same materials as disclosed in the previous embodiments and examples.

[0118] In this embodiment, the creation of the first region 14a and the second region 14b, as well as the first shape of the first region 14a and the second shape of the second region 14b, is achieved by etching the first region 14a, the second region 14b and / or the intermediate region 16, including, for example, mask bevel etching, thereby generating sharp corners in the first region 14a, the second region 14b and / or the intermediate region 16, respectively, to achieve the desired first and second shapes that may enhance the zapping process.

[0119] Alternatively, after growing the first region 14a, the wafer can be removed from the MOCVD reactor and a mask etch can be performed. The wafer can then be returned to the MOCVD reactor to grow the intermediate region 16, and optionally the wafer can then be removed from the MOCVD reactor and another mask etch can be performed. The wafer can then be returned to the MOCVD reactor to grow the second region 14b, and the wafer can then be removed from the MOCVD reactor and a mask etch can be performed. Sharp corners can be formed in the etched regions of the first region 14a and the second region 14b, thereby realizing the desired first and second shapes that can enhance the zapping process.

[0120] The embodiment semiconductor device 10 shown in FIG. 7 may be a HEMT device incorporating a Zener-type antifuse, and thus conventional fabrication techniques of HEMT technology may be used to manufacture the semiconductor device 10.

[0121] The embodiment of Figure 7 allows for the combination of layer growth in an MOCVD reactor, which may reduce manufacturing costs. Furthermore, due to the vertical configuration, the embodiment of Figure 7 may allow for the incorporation of a Zener PN diode configured as an antifuse into HEMT devices having both horizontal topologies, e.g., GaN HEMTs, and vertical topologies, e.g., GaN-on-GaN, SiC, or Ga2O3 based HEMTs.

[0122] In the exemplary embodiment shown in Figures 8a to 8c, the first region 14a of the first conductivity type and the second region 14b of the second conductivity type are arranged in a semi-vertical configuration. In the semi-vertical configuration, the second region 14b of the second conductivity type may be formed above the first region 14a, where the first region 14a may include one or more recesses. Additionally or alternatively, the second region 14b may include one or more recesses. Additionally or alternatively, the semiconductor device 10 may include an intermediate region 16 of a third conductivity type disposed between the first region 14a and the second region 14b, where the intermediate region 16 may include one or more recesses or may not be recessed.

[0123] In these embodiments, forming the first region 14a may etch one or more portions thereof. Thus, at least a slope 28a may be formed between at least one etched (recessed) portion of the first region 14a and an unetched portion of the first region 14a. Thus, etching one or more portions of the second region 14b may form at least a slope 28b between the recess of the second region 14b and an unetched portion of the second region 14b. Additionally or alternatively, etching a portion of the intermediate region 16 may form at least a third slope 28c between the recess and non-recess of the intermediate region 16.

[0124] This may result in the formation of a first shape of the first region 14a and a second shape of the second region 14, including a pointed or truncated pointed shape or another polygonal shape, to achieve an efficient zapping process.

[0125] In the exemplary embodiment of Fig. 8a, the first region 14a, the second region 14b, and the intermediate region 16 each include a recess, forming a ramp 28a, 28b, and 28c, respectively. The ramps 28a, 28b, and 28c may be the same or different from each other.

[0126] In the exemplary embodiment of Fig. 8b, the first region 14a includes two recesses, thereby forming two slopes 28a-1 and 28a-2, while the second region 14b and the intermediate region 16 include one recess, thereby forming slopes 28b and 28c, respectively. Thus, the first shape of the first region 14a and the second shape of the second region 14b are different from each other. The slopes 28a-1, 28a-2, 28b, and 28c can be the same or different from each other.

[0127] In the exemplary embodiment of Fig. 8c, the first region 14a includes two recesses, thereby forming two inclined portions 28a-1 and 28a-2, the second region 14b includes one recess, thereby forming the inclined portion 28b, and the intermediate region 16 is not recessed. Thereby, the first shape of the first region 14a and the second shape of the second region 14b are different from each other, and the intermediate region 16 may have a shape that can further improve the zapping process. The inclined portions 28a-1, 28a-2, and 28b may be the same or different from each other.

[0128] 9a, the first and second regions 14a, 14b are arranged in a horizontal configuration with respect to their location above the substrate 12, and the semiconductor layer 20 is disposed above the first and second regions 14a, 14b. In this implementation, the first and second metal gates 18a, 18b contact the first and second regions 14a, 14b, respectively, through the semiconductor layer 20. The semiconductor device 10 may also include an intermediate region 16 of a third conductivity type disposed between the first and second regions 14a, 14b.

[0129] As described in previous embodiments and examples, substrate 12 comprises a first WBG semiconductor material, first region 14a of a first conductivity type, second region 14b of a second conductivity type, and intermediate region 16 of a third conductivity type comprise a second WBG semiconductor material, and semiconductor layer 20 comprises a third WBG semiconductor material.

[0130] The first metal gate 18a may be in partial or total contact with the first region 14a, or the first metal gate 18a may extend partially or completely into the first region 14a. The second metal gate 18b may be in partial or total contact with the second region 14b, or the second metal gate 18b may extend partially or completely into the second region 14b, as in the case of the examples shown in Figures 5a to 5c or 6a to 6b. The first metal gate 18a or the second metal gate 18b may extend partially into the intermediate region 16. The first metal gate 18a and the second metal gate 18b include the same materials as disclosed in the previous embodiments and examples.

[0131] In this embodiment, the semiconductor device 10 may further include an isolation implant to remove the 2DEG formed below the semiconductor layer 20, thereby avoiding an electrical short between the first region 14a and the second region 14b.

[0132] 9b, a first region 14a of a first conductivity type and a second region 14b of a second conductivity type are arranged in a fully vertical configuration above the substrate 12, with the second region 14b being arranged above the first region 14a, and the semiconductor layer 20 being arranged above the second region 14b. Optionally, the first region 14a and the second region 14b of the second conductivity type may be arranged in a semi-vertical configuration.

[0133] In this embodiment, the first metal gate 18a is in electrical contact with the first region 14a, and the second metal gate contacts the second region through the semiconductor layer 20. The semiconductor device 10 may include an intermediate region 16 having a third conductivity type disposed between the first region 14a and the second region 14b.

[0134] As described in previous embodiments and examples, substrate 12 comprises a first WBG semiconductor material, first region 14a of a first conductivity type, second region 14b of a second conductivity type, and intermediate region 16 of a third conductivity type comprise a second WBG semiconductor material, and semiconductor layer 20 comprises a third WBG semiconductor material.

[0135] The first metal gate 18a may be in partial or total contact with the first region 14a, or the first metal gate 18a may extend partially or completely into the first region 14a. The second metal gate 18b may be in partial or total contact with the second region 14b, or the second metal gate 18b may extend partially or completely into the second region 14b, as in the case of the examples shown in Figures 5a to 5c or 6a to 6b. The first metal gate 18a or the second metal gate 18b may extend partially into the intermediate region 16. The first metal gate 18a and the second metal gate 18b include the same materials as disclosed in the previous embodiments and examples.

[0136] 10, the first region 14a of the first conductivity type and the second region 14b of the second conductivity type are arranged in a horizontal configuration with respect to their location above the substrate 12. The semiconductor device 10 may include an intermediate region 16 of a third conductivity type disposed between the first region 14a and the second region 14b. The semiconductor device 10 further includes a semiconductor layer 20 disposed above the first region 14a and the second region 14b, and the first metal gate 18a and the second metal gate 18b contact the first region 14a and the second region 14b, respectively, through the semiconductor layer 20.

[0137] As described in previous embodiments and examples, substrate 12 comprises a first WBG semiconductor material, first region 14a of a first conductivity type, second region 14b of a second conductivity type, and intermediate region 16 of a third conductivity type comprise a second WBG semiconductor material, and semiconductor layer 20 comprises a third WBG semiconductor material.

[0138] The first metal gate 18a may be in partial or total contact with the first region 14a, or the first metal gate 18a may extend partially or completely into the first region 14a. The second metal gate 18b may be in partial or total contact with the second region 14b, or the second metal gate 18b may extend partially or completely into the second region 14b, as in the case of the examples shown in Figures 5a to 5c or 6a to 6b. The first metal gate 18a or the second metal gate 18b may extend partially into the intermediate region 16. The first metal gate 18a and the second metal gate 18b include the same materials as disclosed in the previous embodiments and examples.

[0139] In this embodiment, the semiconductor device 10 further includes at least one additional first region 14a-1, 14a-2 of a first conductivity type and at least one additional second region 14b-1, 14b-2 of a second conductivity type disposed above the semiconductor layer 20. The semiconductor device 10 further includes at least one additional first metal gate 18b-1, 18b-2 in electrical contact with the at least one additional first region 14a-1, 14a-2, respectively, and at least one additional second metal gate 18b-1, 18b-2 in electrical contact with the at least one additional second region 14b-1, 14b-2, respectively. Furthermore, the semiconductor device 10 includes at least one additional semiconductor layer 20-1, 20-2 disposed above the at least one additional first region 14a-1, 14a-2 and the at least one additional second region 14b-1, 14b-2, respectively.

[0140] At least one additional first metal gate 18a-1, 18a-2 and at least one additional second metal gate 18b-1, 18b-2 contact at least one additional first region 14a-1, 14a-2 and at least one additional second region 14b-1, 14b-2 via at least one additional semiconductor layer 20-1, 20-2, respectively.

[0141] As described in previous embodiments and examples, the at least one additional first region 14a-1, 14b-2 of the first conductivity type and the at least one additional second region 14b-1, 14b-2 of the first conductivity type include a second WBG semiconductor material, and the at least one additional semiconductor layer 20-1, 20-2 includes a third WBG semiconductor material.

[0142] In this embodiment, at least one additional first region 14a-1 and at least one additional second region 14b-1 form at least one additional Zener PN diode configured as an antifuse, and another additional first region 14b-1 and another additional second region 14b-2, respectively, form another additional Zener PN diode configured as an antifuse.

[0143] The semiconductor device 10 may further include at least one additional intermediate region 16-1, 16-2 of a third conductivity type disposed between the at least one additional first region 14a-1, 14a-2 of the first conductivity type and the at least one additional second region 14b-1, 14b-2 of the first conductivity type. The at least one additional intermediate region 16-1, 16b-2 of the third conductivity type includes a second WBG semiconductor material.

[0144] At least one additional first metal gate 18a-1, 18a-2 may be in partial or total contact with at least one additional first region 14a-1, 14a-2, respectively, or the first metal gate 18a-1, 18a-2 may extend partially or completely into at least one additional first region 14a-1, 14a-2. As in the case of the examples shown in Figures 5a to 5c or 6a to 6b, the second metal gate 18b-1, 18b-2 may be in partial or total contact with at least one additional second region 14b-1, 14b-2, respectively, or the second metal gate 18b-1, 18b-2 may extend partially or completely into at least one additional first region 14b-1, 14b-2, respectively. At least one additional first metal gate 18a-1, 18a-2 or at least one additional second metal gate 18b-1, 18b-2 may extend partially into at least one additional intermediate region 16-1, 16-2, respectively. The at least one additional first metal gate 18a-1, 18a-2 and the at least one additional second metal gate 18b-1, 18b-2 may comprise the same materials as disclosed in the previous embodiments and examples.

[0145] This embodiment makes it possible to create a multi-stack of antifuses in which multiple levels can be created between the semiconductor layer 20 and at least one additional semiconductor layer 20-1, and between the additional semiconductor layer 20-1 and another additional semiconductor layer 20-2.

[0146] In this embodiment, the semiconductor device 10 may further include a network of metal interconnects, e.g., vias or plugs, contacting the first region 14a and at least one additional first region 14a-1 and contacting the first region 14b and at least one additional second region 14b-1. Similarly, as further additional first regions are formed, the network of metal interconnects may further contact the additional first region 14a-1 and another additional second region 14a-2, and may further contact the additional second region 14b-1 and another additional second region 14b-2.

[0147] 11, the semiconductor device 10 further comprises at least one structure 22a, 22b of thermal insulation material in partial or complete contact with the first region 14a and / or the second region 14b and / or the substrate 12. The at least one structure 22a, 22b of thermal insulation material comprises SiO2 or a nitride compound including any one of Si3N4 or AlGaN or AlN.

[0148] Additionally or alternatively, the at least one structure 22a, 22b of thermal insulation material may be in partial or complete contact with the semiconductor layer 20. Alternatively, the at least one structure 22a, 22b of thermal insulation material may be in partial or complete contact with the substrate 12 and / or the semiconductor layer 20. Alternatively, the at least one structure 22a, 22b of thermal insulation material may not be in contact with the first region 14a and / or the second region 14b.

[0149] In particular, this embodiment may cause a thermal increase, eg, overheating, during the zapping process, which may facilitate programming of the anti-fuses.

[0150] 12 shows a schematic diagram of a semiconductor device 10 according to another exemplary embodiment. In this embodiment, a first region 14a of a first conductivity type and a second region 14b of a second conductivity type are disposed in an N-well structure 24 or a P-well structure 24 formed in a substrate 12. Alternatively, the first region 14a is disposed in a first well structure 26a and the second region 14b is disposed in a second well structure 26b, with the first well structure 26a and the second well structure 26b comprising an N-well structure or a P-well structure formed in the substrate 12.

[0151] Additionally or alternatively, the first region 14a is disposed within a first well structure 26a and the second region 14b is disposed within a second well structure 26b, and the first well structure 26a and the second well structure 26b comprise an N-well structure or a P-well structure disposed within an N-well or P-well structure 24 formed in the substrate 12.

[0152] The N-well or P-well structure 24, the first well structure 26a, and the second well structure 26b may be formed by implantation. Alternatively, the N-well or P-well structure 24, the first well structure 26a, and the second well structure 26b may be formed by etching and epitaxial regrowth.

[0153] In this embodiment, the substrate 12 may include a first WBG or UWBG semiconductor material. The first WBG and UWBG semiconductor materials may include, for example, GaN, SiC, Ga2O3. The first WBG or UWBG semiconductor material may include a heteroepitaxial bulk material, including GaN on Si, or GaN on SiC, or GaN on diamond, or a WBG semiconductor material on an insulator material, or a UWBG semiconductor material on an insulator material.

[0154] In this disclosure, UWBG semiconductor materials include semiconductor materials with a bandgap greater than 4 eV.

[0155] In this embodiment, the first region 14a of the first conductivity type, the second region 14b of the second conductivity type, and the intermediate region 16 of the third conductivity type may include a second WBG semiconductor material or a UWBG semiconductor material. The first WBG semiconductor material and the UWBG semiconductor material may include GaN, SiC, or Ga2O3. For example, the band gap value of Ga2O3 is 4.8 eV.

[0156] The chemical species used to dope the first region 14a and the second region 14b may be, for example, but not limited to, magnesium, iron, or silicon when the second WBG semiconductor material includes GaN. Alternatively, when the second WBG semiconductor material includes SiC, the dopant may be, for example, phosphorus, boron, aluminum, or nitrogen. Alternatively, when the second WBG semiconductor material includes Ga2O3, the dopant may be, for example, Si, tin, germanium, nitrogen, magnesium, or iron.

[0157] The semiconductor device 10 may further include a semiconductor layer 20 that includes a third WBG semiconductor material, as described in previous embodiments and examples.

[0158] In this embodiment, the semiconductor device 10 may further include a first metal gate 18a in electrical contact with the first region 14a and a second metal gate 18b in electrical contact with the second region 14b.

[0159] The first metal gate 18a may be in partial or total contact with the first region 14a, or the first metal gate 18a may extend partially or completely into the first region 14a. The second metal gate 18b may be in partial or total contact with the second region 14b, or the second metal gate 18b may extend partially or completely into the second region 14b, as in the case of the examples shown in Figures 5a to 5c or 6a to 6b. The first metal gate 18a or the second metal gate 18b may extend partially into the intermediate region 16. The first metal gate 18a and the second metal gate 18b include the same materials as disclosed in the previous embodiments and examples.

[0160] The semiconductor device 10 may further include at least one structure 22a, 22b of thermal insulation material in partial or complete contact with the first region 14a and / or the second region 14b and / or the substrate 12. The at least one structure 22a, 22b of thermal insulation material may include silicon dioxide SiO2 or a nitride compound including any one of Si3N4 or AlGaN or AlN.

[0161] Additionally or alternatively, the at least one structure 22a, 22b of thermal insulation material may be in partial or complete contact with the semiconductor layer 20. Alternatively, the at least one structure 22a, 22b of thermal insulation material may be in partial or complete contact with the substrate 12 and / or the semiconductor layer 20. Alternatively, the at least one structure 22a, 22b of thermal insulation material may not be in contact with the first region 14a and / or the second region 14b.

[0162] In particular, the embodiment of the semiconductor device 10 shown in FIG. 12 may be used in common WBG and UWBG technologies, and therefore standard fabrication techniques of WBG and UWBG technologies may be used to fabricate the semiconductor device 10. The semiconductor device 10 according to the exemplary embodiment of the present disclosure provides several advantages.

[0163] The semiconductor device 10 enables a cost-free solution for implementing a Zener PN diode configured as an antifuse in WBG power semiconductor technology.

[0164] The semiconductor device 10 makes it possible to perform trimming in WBG technology (currently only feasible in silicon technology).

[0165] The semiconductor device 10 allows for the adjustment of voltage reference circuits (mainly used in integrated circuit design) in WBG.

[0166] The semiconductor device 10 enables implementation of die / chip serial code identification in WBG devices.

[0167] The semiconductor device 10 results in a Zener PN diode configured as an anti-fuse that is "one-time programmable" since it does not need to be reconfigured each time power is removed, applied, or disconnected.

[0168] The semiconductor device 10 is not susceptible to alpha particles.

[0169] FIG. 13 illustrates steps of a method 30 for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0170] In a first step S32, a substrate 12 is provided. The substrate 12 includes a first WBG semiconductor material including SiC or Ga2O3. Alternatively, the first WBG semiconductor material includes a heteroepitaxial bulk material including GaN on Si, or GaN on SiC, or GaN on diamond, or a WBG semiconductor on an insulator material. The substrate 12 may include a base structure having one or more layers formed thereon by an epitaxial growth process.

[0171] In a second step S34, a first region 14a of a first conductivity type and a second region 14b of a second conductivity type are formed over the substrate 12. The first region 14a and the second region 14b include a second WBG semiconductor material. For example, the second WBG semiconductor material includes GaN.

[0172] The first region 14a of the first conductivity type can be a P-type region or an N-type region. Conversely, the second region 14b of the second conductivity type can be an N-type region or a P-type region. In this way, the first region 14a and the second region 14b form a Zener PN diode configured as an antifuse.

[0173] In general, semiconductor device 10 may be fabricated by standard mask / implant processes, controlled sequential epitaxial growth and epitaxy, and etching techniques.

[0174] The method 30 may further include forming an intermediate region 16 of a third conductivity type, which may be disposed between the first region 14a and the second region 14b. The intermediate region 16 may include a second WBG semiconductor material and may be a P-type region or an N-type region or an undoped type region.

[0175] The first region 14a and the second region 14b may be arranged in a horizontal configuration with respect to their location above the substrate 12, with the first region 14a being arranged above the substrate 12 and the second region 14b being arranged above the substrate 12 next to the first region 14a.

[0176] Alternatively, the first and second regions 14 a, 14 b may be arranged in a vertical configuration with respect to their location above the substrate 12.

[0177] The vertical configuration may include a fully vertical configuration or a semi-vertical configuration.

[0178] In a fully vertical configuration, the second region 14b may be disposed above the first region 14a, which may be disposed above the substrate 12.

[0179] In a semi-vertical configuration, a second region 14b of a second conductivity type may be formed above a first region 14a, where the first region 14a may include one or more recesses. Additionally or alternatively, the second region 14b may include one or more recesses. Additionally or alternatively, the semiconductor device 10 may include an intermediate region 16 of a third conductivity type disposed between the first region 14a and the second region 14b, where the intermediate region 16 may include one or more recesses or may not be recessed.

[0180] The first region 14a and the second region 14b may be separated by a distance, or the first region 14a and the second region 14b may be adjacent, or the first region 14a and the second region 14b may overlap.

[0181] The first region 14a may have a first shape, the first shape may include a first lateral projection, the first lateral projection may have a tip shape or a truncated tip shape or another polygonal shape, or the first shape may include a cylindrical shape, or a cylindrical shape with a first lateral projection, the first lateral projection may have a tip shape or a truncated tip shape or another polygonal shape. The second region 14b may have a second shape, the second shape may include a second lateral projection, the second lateral projection may have a tip shape or a truncated tip shape or another polygonal shape, or the second shape may include a cylindrical shape, or a cylindrical shape with a second lateral projection, the lateral projection may have a tip shape or a truncated tip shape or another polygonal shape.

[0182] The method 30 may further include forming a semiconductor layer 20, which may include a third WBG semiconductor material and may be disposed between the substrate 12 and the first and second regions 14a and 14b, respectively. For example, the third WBG semiconductor material may include AlGaN.

[0183] The method 30 may further include forming a semiconductor layer 20 including a third WBG semiconductor material, and the semiconductor layer 20 may be disposed above the first region 14a and the second region 14b. Alternatively, the second region 14b may be disposed above the first region 14a, and the semiconductor layer 20 may be disposed above the second region 14b.

[0184] The method 30 may further include forming a first metal gate 18a in electrical contact with the first region 14a and a second metal gate 18b in electrical contact with the second region 14b.

[0185] The first metal gate 18a and the second metal gate 18b may contact the first region 14a and the second region 14b through the semiconductor layer 20. Alternatively, the second metal gate 18b may contact the second region 14b through the semiconductor layer 20.

[0186] The first metal gate 18a may be in partial or total contact with the first region 14a, or the first metal gate 18a may extend partially or completely into the first region 14a. The second metal gate 18b may be in partial or total contact with the second region 14b, or the second metal gate 18b may extend partially or completely into the second region 14b.

[0187] The first metal gate 18a and the second metal gate 18b may comprise aluminum, titanium, copper, gold, or another metal element, or a metal stack including any one of Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, or TiN / Al / TiN, however, other suitable material combinations may also be possible.

[0188] The method 30 may further include forming at least one additional first region 14a-1, 14a-2 of a first conductivity type and at least one additional second region 14b-1, 14b-2 of a second conductivity type, which may be disposed above the semiconductor layer 20; forming at least one additional first metal gate 18a-1, 18a-2 in electrical contact with the at least one additional first region 14a-1, 14a-2, and at least one additional second metal gate 18b-1, 18b-2 in electrical contact with the at least one additional second region 14b-1, 14b-2; and forming at least one additional semiconductor layer 20-1, 20-2, which may be disposed above the at least one additional first region 14a-1, 14a-2, and the at least one additional second region 14b-1, 14b-2.

[0189] At least one additional first metal gate 18a-1, 18a-2 and at least one additional second metal gate 18b-1, 18b-2 may contact at least one additional first region 14a-1, 14a-2 and at least one additional second region 14b-1, 14b-2 via at least one additional semiconductor layer 20-1, 20-2.

[0190] At least one additional first region 14a-1, 14a-2 and at least one additional second region 14b-1, 14b-2 may include a second wide bandgap semiconductor material, while at least one additional semiconductor layer 20-1, 20-2 may include a third wide bandgap semiconductor material.

[0191] Additionally, the at least one additional first region 14a-1, 14a-2 and the at least one additional second region 14b-1, 14b-2 form at least one additional Zener PN diode configured as an anti-fuse.

[0192] The method may further include forming the first region 14a and the second region 14b, which may be disposed within an N-well structure 24 or a P-well structure 24 formed in the substrate 12. Alternatively, the first region 14a may be disposed within a first well structure 26a and the second region 14b may be disposed within a second well structure 26b, and the first well structure 26a and the second well structure 26a may comprise an N-well structure or a P-well structure formed in the substrate 12.

[0193] The method 30 may further include forming at least one structure 22a, 22b of thermal insulation material that may be in partial or complete contact with the first region 14a and / or the second region 14b and / or the substrate 12. The at least one structure 22a, 22b of thermal insulation material may include SiO2 or a nitride compound including any one of Si3N4 or AlGaN or AlN.

[0194] Examples of fabrication techniques that may be used to form the first region 14a and first shape of the first conductivity type, the second region 14b and second shape of the second conductivity type, the intermediate region 16 of the third conductivity type, the first metal gate 18a, and the second metal gate 18b are the same as those disclosed above in various embodiments and examples of the semiconductor device 10.

[0195] The present disclosure has been described in relation to various exemplary embodiments and implementations. However, other variations can be understood and produced by those skilled in the art and those practicing the claimed subject matter from a study of the drawings, the disclosure and the independent claims. In the claims and the description, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous embodiment. [Explanation of symbols]

[0196] 10. Semiconductor Devices 12 Substrate 14a First Area 14b The second area 14a-1 Additional First Area 14a-2 Additional First Area 14b-1 Additional Secondary Areas 14b-2 Additional Secondary Areas 16 Intermediate area 16-1 Additional intermediate area 16-2 Additional Intermediate Area 18a First metal gate 18b Second metal gate 18a-1 Additional first metal gate 18a-2 Additional first metal gate 18b-1 Additional second metal gate 18b-2 Additional second metal gate 20 Semiconductor layer 20-1 Additional Semiconductor Layer 20-2 Additional Semiconductor Layer 22a At least one structure 22b At least one structure 24 N-well structure, P-well structure 26a First well structure 26b Second Well Structure 28a Slope 28b Slope 28c Slope 28a-1 Slope section 28a-2 Slope section 30 ways S32 First Step S34 Second Step

Claims

1. a substrate (12) comprising a first wide band gap semiconductor material; a first region (14a) of a first conductivity type and a second region (14b) of a second conductivity type disposed above the substrate (12), the first region (14a) and the second region (14b) comprising a second wide band gap semiconductor material; Including, the first region (14a) and the second region (14b) form a Zener PN diode configured as an antifuse; A semiconductor device (10).

2. the first region (14a) and the second region (14b) are arranged in a horizontal configuration with respect to their arrangement above the substrate (12), the first region (14a) being arranged above the substrate (12) and the second region (14b) being arranged above the substrate (12) next to the first region (14a); or the first region (14a) and the second region (14b) are arranged in a vertical configuration with respect to their arrangement above the substrate (12), the second region (14b) being arranged above the first region (14a) and the first region (14a) being arranged above the substrate (12); The semiconductor device (10) of claim 1.

3. The first region (14a) and the second region (14b) are separated by a certain distance, or the first region (14a) and the second region (14b) are adjacent to each other, or the first region (14a) and the second region (14b) partially overlap each other. A semiconductor device (10) according to claim 1 or 2.

4. the first region (14a) has a first shape, the first shape including a first lateral projection, the first lateral projection having a tip shape or a truncated tip shape or another polygonal shape, or the first shape includes a cylindrical shape or a cylindrical shape with a first lateral projection, the first lateral projection having a tip shape or a truncated tip shape or another polygonal shape; the second region (14b) has a second shape, the second shape including a second lateral projection, the second lateral projection having a tip shape or a truncated tip shape or another polygonal shape, or the second shape including a cylindrical shape or a cylindrical shape with a second lateral projection, the lateral projection having a tip shape or a truncated tip shape or another polygonal shape; A semiconductor device (10) according to any one of claims 1 to 3.

5. the semiconductor device (10) further comprises a first metal gate (18a) in electrical contact with the first region (14a) and a second metal gate (18b) in electrical contact with the second region (14b); A semiconductor device (10) according to any one of the preceding claims.

6. the semiconductor device (10) further comprises a semiconductor layer (20) comprising a third wide band gap semiconductor material disposed between the substrate (12) and the first region (14a) and the second region (14b), respectively; A semiconductor device (10) according to any one of the preceding claims.

7. the semiconductor device (10) further comprises a semiconductor layer (20) comprising a third wide band gap semiconductor material; the semiconductor layer (20) is disposed above the first region (14a) and the second region (14b); or the second region (14b) is disposed above the first region (14a), and the semiconductor layer (20) is disposed above the second region (14b); A semiconductor device (10) according to any one of the preceding claims.

8. the first metal gate (18a) and the second metal gate (18b) contact the first region (14a) and the second region (14b) through the semiconductor layer (20); or the second metal gate (18b) contacts the second region (14b) through the semiconductor layer (20); A semiconductor device (10) according to claims 5 and 7.

9. The semiconductor device (10), at least one additional first region (14a-1, 14a-2) of the first conductivity type and at least one additional second region (14b-1, 14b-2) of the second conductivity type arranged above the semiconductor layer (20), wherein the at least one additional first region (14a-1, 14a-2) of the first conductivity type and the at least one additional second region (14b-1, 14b-2) of the second conductivity type comprise the second wide band gap semiconductor material; at least one additional first metal gate (18a-1, 18a-2) in electrical contact with said at least one additional first region (14a-1, 14a-2), and at least one additional second metal gate (18b-1, 18b-2) in electrical contact with said at least one additional second region (14b-1, 14b-2); at least one additional semiconductor layer (20-1, 20-2) including the third wide band gap semiconductor material and disposed above the at least one additional first region (14a-1, 14a-2) and the at least one additional second region (14b-1, 14b-2); Further comprising: the at least one additional first metal gate (18a-1, 18a-2) and the at least one additional second metal gate (18b-1, 18b-2) contact the at least one additional first region (14a-1, 14a-2) and the at least one additional second region (14b-1, 14b-2) via the at least one additional semiconductor layer (20-1, 20-2); said at least one additional first region (14a-1, 14a-2) and said at least one additional second region (14b-1, 14b-2) form at least one additional Zener PN diode configured as an antifuse; The semiconductor device (10) of claim 8.

10. the first region (14a) and the second region (14b) are disposed within an N-well structure (24) or a P-well structure (24) formed within the substrate (12); or the first region (14a) is disposed within a first well structure (26a), the second region (14b) is disposed within a second well structure (26b), and the first well structure (26a) and the second well structure (26a) comprise an N-well structure or a P-well structure formed in the substrate (12); The semiconductor device (10) of claim 1.

11. The semiconductor device (10) further comprises at least one structure (22a, 22b) of thermal insulation material in partial or complete contact with the first region (14a) and / or the second region (14b) and / or the substrate (12), the at least one structure (22a, 22b) of thermal insulation material being made of silicon dioxide (SiO ２ , or silicon nitride Si ３ N ４ or a nitride compound including any one of aluminum gallium nitride AlGaN or aluminum nitride AlN; A semiconductor device (10) according to any one of the preceding claims.

12. the semiconductor device (10) further comprises an intermediate region (16) of a third conductivity type disposed between the first region (14a) and the second region (14b), the intermediate region (16) comprising the second wide band gap semiconductor material, the intermediate region (16) being a P-type region, an N-type region, or an undoped region; A semiconductor device (10) according to any one of the preceding claims.

13. the second wide band gap semiconductor material comprises gallium nitride (GaN); A semiconductor device (10) according to any one of the preceding claims.

14. the third wide band gap semiconductor material comprises aluminum gallium nitride AlGaN; A semiconductor device (10) according to any one of the preceding claims.

15. the first metal gate (18a) is in partial or total contact with the first region (14a) or the first metal gate (18a) extends partially or completely into the first region (14a); the second metal gate (18b) is in partial or total contact with the second region (14b) or the second metal gate (18b) extends partially or completely into the second region (14b); A semiconductor device (10) according to any one of claims 5 to 14.

16. the first metal gate (18a) and the second metal gate (18b) comprise aluminum, titanium, copper, gold, or another metal element, or a metal stack comprising any one of Ni / Au, Ni / Ag, Pd / Au, Cr / Au, Pt / Au, Ti / Pt / Au, Ni / Si, W / Si, Ti / Al, Ti / Al / Ti, TiN / Al / TiN; A semiconductor device (10) according to any one of claims 5 to 15.

17. The first wide band gap semiconductor material is silicon carbide (SiC) or gallium oxide (Ga). ２ O ３ Contains or The first wide band gap semiconductor material comprises a heteroepitaxial bulk material, the heteroepitaxial bulk material comprising gallium nitride GaN on silicon Si, or GaN on SiC, or GaN on diamond, or a wide band gap semiconductor on insulator material; A device according to any one of claims 1 to 16.

18. A method (20) for manufacturing a semiconductor device (10), the method comprising: Providing a substrate (12) comprising a first wide band gap semiconductor material; forming a first region (14a) of a first conductivity type and a second region (14b) of a second conductivity type disposed above the substrate (12), the first region (14a) and the second region (14b) comprising a second wide bandgap semiconductor material; Including, wherein the first region (14a) and the second region (14b) form a Zener PN diode configured as an antifuse.

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