Contact formation process for CMOS devices.

Abstract

A method for forming a contact layer in a semiconductor structure includes performing a pre-cleaning process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, the exposed surfaces of the plurality of first semiconductor regions and the plurality of second semiconductor regions each being disposed in openings formed in a dielectric layer disposed over the substrate; performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surfaces of the second semiconductor regions; performing a patterning process to form a patterned stack, the patterning stack including a patterned layer including openings formed over the first contact layers disposed in each opening in the dielectric layer and portions of the patterned layer disposed over each second contact layer disposed in each opening in the dielectric layer; and performing a selective removal process to selectively remove the first contact layer relative to the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments described herein relate generally to semiconductor device manufacturing, and more particularly to systems and methods for forming contacts in semiconductor structures. [Background technology]

[0002]

[0002] Multi-gate metal oxide semiconductor field effect transistors (MOSFETs), such as complementary metal oxide semiconductor (CMOS) devices, pose manufacturability challenges due to their three-dimensional (3D) design and small size. In advanced CMOS devices, epitaxial layers of silicon-containing materials (e.g., boron-doped p-type silicon germanium or phosphorus-doped n-type silicon) formed at the bottom of trench contacts often reduce contact resistivity by up to 10 -9 Ωcm 2 It is being used to reduce the area required for advanced CMOS technology to achieve the performance required.

[0003]

[0003] However, the formation and patterning of such epitaxial layers, for example using a hard mask to protect nMOS or pMOS regions, can damage various parts of the CMOS device, such as the spacer, gate cap layer, or epitaxial growth layer.

[0004]

[0004] Therefore, what is needed is a method and system that can form contacts that include epitaxial layers of silicon-containing materials to selected portions of semiconductor devices. Summary of the Invention

[0005]

[0005] Several embodiments of the present disclosure provide a method for forming a contact layer in a semiconductor structure. The method includes performing a pre-cleaning process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, the exposed surfaces of the plurality of first semiconductor regions and the plurality of second semiconductor regions each being disposed in an opening formed in a dielectric layer disposed over the substrate; performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surfaces of the second semiconductor regions; performing a patterning process to form a patterned stack, the patterning stack including a patterned layer including openings formed over the first contact layer disposed in each opening in the dielectric layer and a portion of the patterned layer disposed over each second contact layer disposed in each opening in the dielectric layer; and performing a selective removal process to selectively remove the first contact layer from the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.

[0006]

[0006] Several embodiments of the present disclosure provide a method for forming a contact layer in a semiconductor structure, the method including: performing a pre-cleaning process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, the exposed surfaces of the plurality of first semiconductor regions and the plurality of second semiconductor regions being each disposed in an opening formed in a dielectric layer disposed over the substrate; performing a first selective epitaxial deposition process to simultaneously form a first contact layer having a first thickness on the exposed surfaces of the first semiconductor regions and a second contact layer having a second thickness on the exposed surfaces of the second semiconductor regions, the second thickness being greater than the first thickness; and performing a selective removal process to selectively remove the first contact layer and the second contact layer from the plurality of first semiconductor regions and the dielectric layer until the first contact layer is substantially removed from the first semiconductor regions and a portion of the second contact layer remains on the second semiconductor regions.

[0007]

[0007] Embodiments of the present disclosure provide a processing system including a first processing chamber, a second processing chamber, a third processing chamber, and a system controller. The system controller is configured to: perform a pre-cleaning process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate in the first processing chamber; perform a first selective deposition process to epitaxially form a first contact layer on the exposed surfaces of the first semiconductor regions of the substrate and to epitaxially form a second contact layer on the exposed surfaces of the second semiconductor regions; and perform a selective removal process to remove the first contact layer selectively to the first semiconductor regions in the third processing chamber.

[0008]

[0008] In order to allow the above-mentioned features of the present disclosure to be understood in detail, a more particular description of the present disclosure briefly summarized above can be obtained by reference to a number of embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the attached drawings illustrate only typical embodiments of the present disclosure, and the present disclosure may admit of other equally effective embodiments, and therefore the attached drawings should not be considered as limiting the scope of the present disclosure. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic top view of a multi-chamber processing system in accordance with one or more embodiments of the present disclosure. [Figure 2A]

[0010] FIG. 1 illustrates a cross-sectional view of a processing chamber in accordance with one or more embodiments. [Figure 2B]

[0011] FIG. 2B is an enlarged view of a portion of the processing chamber of FIG. 2A. [Diagram 3]

[0012] FIG. 1 illustrates a cross-sectional view of a processing chamber in accordance with one or more embodiments. [Figure 4]

[0013] FIG. 1 illustrates a cross-sectional view of a processing chamber in accordance with one or more embodiments. [Diagram 5]

[0014] 1 shows a process flow diagram of a method for forming a contact layer in a semiconductor structure according to a first embodiment of the present disclosure. [Figure 6A]

[0015] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 5. [Figure 6B] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 5. [Figure 6C] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 5. [Figure 6D] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 5. [Figure 6E] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 5. [Figure 6F] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 5. [Figure 6G] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 5. [Figure 7]

[0016] 4 shows a process flow diagram of a method for forming a contact layer in a semiconductor structure according to a second embodiment of the present disclosure. [Figure 8A]

[0017] 8A-8C are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 7. [Figure 8B] 8A-8D are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 7. [Figure 8C] 8A-8C are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 7. [Figure 8D] 8A-8D are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 7. [Figure 8E] 8A-8D are cross-sectional views of a portion of a semiconductor structure corresponding to various stages of the method of FIG. 7. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0018] For ease of understanding, the same reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is believed that elements and features of one embodiment may be beneficially incorporated in other embodiments without additional recitation.

[0011]

[0019] Several embodiments described herein provide methods and systems for forming contacts including epitaxial layers of silicon-containing materials (e.g., boron-doped p-type silicon germanium or phosphorus-doped n-type silicon) in selected portions of structures used to form CMOS devices (e.g., on exposed surfaces of silicon or silicon germanium layers). The methods and systems may be particularly useful for forming epitaxial layers that selectively include silicon germanium on exposed surfaces of silicon germanium material in openings or features (e.g., contact trenches) formed in a dielectric layer in semiconductor structures having silicon-containing regions, silicon germanium-containing regions, and a dielectric layer formed thereover. Unlike conventional processes that require the formation of hard masks and various etching and patterning process steps to form contacts, which tend to damage the fabricated semiconductor structures (e.g., spacers, gate caps, etc.), the processes described herein are configured to form contacts without damaging these previously formed semiconductor structures.

[0012]

[0020] 1 is a schematic top view of a multi-chamber processing system 100 in accordance with one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in the processing system 100 may be processed in and transferred between the various chambers without exposing the substrate to an ambient environment outside the processing system 100 (e.g., an ambient atmospheric environment that may exist in a manufacturing plant, etc.). For example, substrates may be processed in and transferred between the various chambers that are maintained in a low pressure (e.g., about 300 Torr or less) or reduced pressure environment during various processes performed on the substrate in the processing system 100 without breaking the low pressure or reduced pressure environment. Thus, the processing system 100 may provide an integrated solution for several processing of substrates.

[0013]

[0021] Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems available from Applied Materials, Inc., Santa Clara, Calif., or other suitable processing systems. It is contemplated that other processing systems, including those from other manufacturers, may be adapted to benefit from aspects described herein.

[0014]

[0022] 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate transfer of substrates. The docking station 132 is adapted to receive one or more front opening unified pods (FOUPs) 136. In some embodiments, each factory interface robot 134 generally comprises a blade 138 disposed at one end of the respective factory interface robot 134 adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0015]

[0023] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the holding chambers 116, 118 and respective ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 may be, for example, slit valve openings having slit valves for transferring substrates therethrough by transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas passing between the respective chambers. Generally, any port is opened to transfer a substrate therethrough. Otherwise, the port is closed.

[0016]

[0024] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 134 transfers a substrate from the FOUP 136 through the port 140 or 142 to the load lock chamber 104 or 106. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 at an internal low or reduced pressure environment (which may include an inert gas). Thus, pumping down the load lock chambers 104 or 106 may, for example, facilitate passing a substrate between the atmospheric environment of the factory interface 102 and the low or reduced pressure environment of the transfer chamber 108 .

[0017]

[0025] With the substrate in the pumped down load lock chamber 104 or 106, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 through the port 144 or 146 into the transfer chamber 108. The transfer robot 112 can then transfer the wafer to and / or between any of the processing chambers 120, 122 through the respective ports 152, 154 for processing and the holding chambers 116, 118 through the respective ports 148, 150 for holding awaiting further transfer. Similarly, the transfer robot 114 can access the substrate in the holding chamber 116 or 118 through the port 156 or 158 and can transfer the substrate to and / or between any of the processing chambers 124, 126, 128, 130 through the respective ports 160, 162, 164, 166 for processing and the holding chambers 116, 118 through the respective ports 156, 158 for holding awaiting further transfer. Transferring and holding the substrate in and between the various chambers may be performed in a low or reduced pressure environment provided by a gas and pressure control system.

[0018]

[0026] The processing chambers 120, 122, 124, 126, 128, 130 may be any suitable chambers for processing a substrate. In some embodiments, the processing chamber 120 may perform an etch process, the processing chamber 122 may perform a cleaning process, the processing chamber 124 may perform a selective removal process, and the processing chambers 126, 128, 130 may perform respective epitaxial growth processes. The processing chamber 120 may be a Selectra™ Etch chamber available from Applied Materials, Inc., Santa Clara, California. The processing chamber 122 may be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc., Santa Clara, California. The processing chambers 126, 128, or 130 may be Centura™ Epi chambers available from Applied Materials, Inc., Santa Clara, California.

[0019]

[0027] A system controller 168 is coupled to the processing system 100 to control the processing system 100 or components thereof. For example, the system controller 168 may control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 enables data collection and feedback from each chamber to regulate the performance of the processing system 100.

[0020]

[0028] The system controller 168 generally includes a central processing unit (CPU) 170, a memory 172, and support circuits 174. The CPU 170 may be one of any form of general-purpose processor that can be used in an industrial setting. The memory 172 or non-transitory computer-readable medium is accessible by the CPU 170 and may be one or more memories, such as a local or remote random access memory (RAM), a read-only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage. The support circuits 174 are coupled to the CPU 170 and may include cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein may generally be performed under the control of the CPU 170, for example, by executing computer instruction codes stored in the memory 172 (or in the memory of a particular process chamber) as software routines. When the computer instruction codes are executed by the CPU 170, the CPU 170 controls the chamber to perform processes according to various methods.

[0021]

[0029] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In one illustrated embodiment, the transfer apparatus includes transfer chambers 108, 110 and holding chambers 116, 118. In other embodiments, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer apparatus in a processing system.

[0022]

[0030] Figure 2A is a cross-sectional view of a processing chamber 200 according to one or more embodiments adapted to perform a pre-clean process as described in more detail below. The processing chamber 200 may be the processing chamber 122 shown in Figure 1. Figure 2B is an enlarged view of a portion of the processing chamber 200 of Figure 2A.

[0023]

[0031] The chamber 200 may be particularly useful for performing thermal or plasma-based cleaning processes and / or plasma-assisted dry etching processes. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed at an upper end of the chamber body 202, and the support assembly 206 is disposed at least partially within the chamber body 202. A vacuum system may be used to remove gases from the processing chamber 200. The vacuum system includes a vacuum pump 208 coupled to a vacuum port 210 disposed within the chamber body 202. The processing chamber 200 also includes a controller 212 for controlling processes within the processing chamber 200.

[0024]

[0032] The lid assembly 204 includes stacked components adapted to provide gas and / or plasma to the processing region 214 in the processing chamber 200. The first plate 216 is coupled to the second plate 218. The third plate 220 is coupled to the second plate 218. The lid assembly 204 may be connected to a power source (not shown) for providing plasma to a conical chamber 222 formed in the lid assembly 204. The lid assembly 204 may also be connected to a remote plasma source 224 that generates plasma upstream of the lid stack. The remote plasma cavity (e.g., the processing region 214, the first plate 216, and the second plate 218 of FIGS. 2A-2B) is coupled to a gas source 226 (or the gas source 226 is directly coupled to the lid assembly 204 without the remote plasma source 224). The gas source 226 may include a gas source adapted to provide helium, argon, or other inert gas. In some configurations, a gas provided by the gas source 226 can be excited into a plasma. The plasma is provided to the lid assembly 204 by use of a remote plasma source 224. In alternative embodiments, the gas source 226 can provide a process gas that can be activated by the remote plasma source 224 before being introduced to a surface of a substrate disposed in the processing chamber 200. Referring to FIG. 2B, the conical chamber 222 has an opening 228. The opening 228 allows the generated plasma to flow from the remote plasma source 224 to a space 230 formed in a fourth plate 232 of the lid assembly 204.

[0025]

[0033] In some configurations of the lid assembly 204, a plasma is generated within the conical chamber 222 by application of energy provided from a plasma source. In one embodiment, the energy may be provided by biasing the lid assembly 204 to capacitively couple RF, VHF, and / or UHF energy to the gas disposed within the conical chamber 222. In this configuration of the lid assembly 204, a remote plasma source 224 may not be used or may not be installed within the lid assembly 204.

[0026]

[0034] A central conduit 234 formed in the fourth plate 232 is adapted to provide plasma-generated species provided from the space 230 through a fifth plate 236 to a mixing chamber 238 formed in a sixth plate 240 of the lid assembly 204. The central conduit 234 communicates with the mixing chamber 238 through an opening 242 in the fifth plate 236. The opening 242 may have a smaller, larger, or the same diameter as the central conduit 234. In the embodiment of FIG. 2B, the opening 242 has the same diameter as the central conduit 234.

[0027]

[0035] The fourth plate 232 also includes inlets 244 and 246 adapted to provide gas to the mixing chamber 238. The inlet 244 is coupled to a first gas source 248, and the inlet 246 is coupled to a second gas source 250. The first gas source 248 and the second gas source 250 may include a process gas and an inert gas (e.g., an inert gas such as argon and / or helium utilized as a carrier gas). The first gas source 248 may include ammonia (NH3) and argon (Ar). The second gas source 250 may include a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof. In one example, the second gas source 250 may include hydrogen fluoride (HF) and argon (Ar).

[0028]

[0036] As shown in FIG. 2B, in some configurations, the inlet 244 is coupled to the mixing chamber 238 through a cylindrical channel 252 (shown in phantom lines) and holes 254 formed in the fifth plate 236. The inlet 246 is coupled to the mixing chamber 238 through a cylindrical channel 256 (shown in phantom lines) and holes 258 formed in the fifth plate 236. The holes 254, 258 formed in the fifth plate 236 are generally sized such that they allow for uniform gas flow. Gas is provided into the mixing chamber 238 from their respective gas sources 248, 250. In one configuration, the holes 258 have a diameter smaller than the width of the opening defined by the opposing sidewalls of the cylindrical channel 256 formed in the fourth plate 232. The holes 258 are typically distributed circumferentially about the centerline of the cylindrical channel 256 to provide uniform fluid flow to the mixing chamber 238. In one configuration, the holes 254 have a diameter less than the width of an opening defined by opposing sidewalls of the cylindrical channel 252 formed in the fourth plate 232. The holes 254 are typically distributed circumferentially about the centerline of the cylindrical channel 252 to provide uniform fluid flow to the mixing chamber 238.

[0029]

[0037] The inlets 244 and 246 each provide a fluid flow path through the fourth plate 232 laterally, turn toward the fifth plate 236, and penetrate the fifth plate 326 to enter the mixing chamber 238. The lid assembly 204 also includes a seventh plate or first gas distributor 260. The seventh plate or first gas distributor 260 may be a gas distribution plate, such as a showerhead. In that case, the various gases mixed within the lid assembly 204 are channeled through perforations 262 formed therein. The perforations 262 are in fluid communication with the mixing chamber 238 to provide a flow path from the mixing chamber 238 through the first gas distributor 260. Referring back to FIG. 2A, a blocker plate 264 and a gas distribution plate (such as a second gas distributor 266), such as a showerhead, are disposed below the lid assembly 204. The second gas distributor 266 may be a gas distribution plate.

[0030]

[0038] Alternatively, different cleaning processes may be used to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH3) may be introduced into the processing chamber 200 through the lid assembly 204. Alternatively, ammonia (NH3) may be injected directly into the processing chamber 200 through another gas inlet 268 located on the side of the chamber body 202 and coupled to a gas source (not shown).

[0031]

[0039] The support assembly 206 may include a substrate support 270 for supporting a substrate 272 thereon during processing. The substrate support 270 may be coupled to an actuator 274 by a shaft 276 that extends through a centrally located opening formed in a bottom portion of the chamber body 202. The actuator 274 may be flexibly sealed to the chamber body 202 by a bellows (not shown) that prevents vacuum leakage around the shaft 276. The actuator 274 may move the substrate support 270 vertically within the chamber body 202 between a processing position and a loading position. The loading position is slightly below a tunnel opening (not shown) formed in a sidewall of the chamber body 202.

[0032]

[0040] The substrate support 270 has a flat or substantially flat substrate support surface for supporting a substrate 272 to be processed thereon. The substrate support 270 can be moved vertically within the chamber body 202 by an actuator 274 coupled to the substrate support 270 by a shaft 276. In some steps, the substrate support 270 can be raised to a position adjacent to the lid assembly 204 to control the temperature of the substrate 272 being processed. Thus, the substrate 272 can be heated via radiation emitted from the second gas distributor 266, or another radiation source, or by convection or conduction from the second gas distributor 266 via an intervening gas. In some process steps, the substrate can be placed on lift pins 278 to perform further thermal treatment steps, such as performing an annealing step.

[0033]

[0041] 3 is a cross-sectional view of a processing chamber 300 according to one or more embodiments adapted to perform an epitaxial (Epi) deposition process, as described in more detail below. The processing chamber 300 may be the processing chamber 126, 128, or 130 shown in FIG.

[0034]

[0042] The processing chamber 300 includes a housing structure 302 made of a process resistant material such as aluminum or stainless steel (e.g., 316L stainless steel). The housing structure 302 encloses various functional elements of the processing chamber 300, such as a quartz chamber 304. The quartz chamber 304 includes an upper quartz chamber 306 and a lower quartz chamber 308, which contain a processing space 310 therein. Reactive species are provided to the quartz chamber 304 by a gas distribution assembly 312, and processing by-products are removed from the processing space 310 by an outlet port 314. The outlet port 314 is typically in communication with a reduced pressure source (not shown).

[0035]

[0043] The substrate support 316 is adapted to receive a substrate 318 transferred to the processing space 310. The substrate support 316 is disposed along a longitudinal axis 320 of the processing chamber 300. The substrate support 316 may be made of a ceramic or graphite material coated with a silicon material (such as silicon carbide) or other process resistant material. Reactive species from the precursor reactant material may be added to a surface 322 of the substrate 318, and by-products may then be removed from the surface 322 of the substrate 318. Heating of the substrate 318 and / or the processing space 310 may be provided by a radiation source, such as an upper lamp module 324A and a lower lamp module 324B.

[0036]

[0044] In one embodiment, the upper lamp module 324A and the lower lamp module 324B are infrared (IR) lamps. Non-thermal energy or radiation from the lamp modules 324A and 324B travels through an upper quartz window 326 of the upper quartz chamber 306 and through a lower quartz window 328 of the lower quartz chamber 308. Cooling gas for the upper quartz chamber 306, when needed, enters through an inlet 330 and exits through an outlet 332. Precursor reactant materials, as well as dilution, purge, and vent gases for the process chamber 300, enter through the gas distribution assembly 312 and exit through an outlet port 314. Although the upper quartz window 326 is illustrated as curved or convex, the upper quartz window 326 can be flat or concave, since the pressure on both sides of the upper quartz window 326 is substantially the same (i.e., atmospheric pressure).

[0037]

[0045] The low wavelength radiation in the processing space 310 used to energize reactive species and assist in adsorption of reactants and desorption of process by-products from the surface 322 of the substrate 318 is typically in the range of about 0.8 μm to about 1.2 μm, e.g., between about 0.95 μm to about 1.05 μm, with various combinations of wavelengths being provided depending, for example, on the composition of the film being epitaxially grown.

[0038]

[0046] The constituent gases enter the process space 310 via a gas distribution assembly 312. The gases flow from the gas distribution assembly 312 and exit through an outlet port 314, as generally indicated by a flow path 334. A combination of constituent gases is used to clean / passivate a substrate surface or form a silicon and / or germanium-containing film (epitaxially grown) and are typically mixed before entering the process space 310. The overall pressure in the process space 310 can be adjusted by a valve (not shown) at the outlet port 314. At least a portion of the inner surface of the process space 310 is lined with a liner 336. In one embodiment, the liner 336 comprises an opaque quartz material. In this manner, the chamber walls are insulated from the heat in the process space 310.

[0039]

[0047] The temperature of surfaces within the process space 310 can be controlled in a temperature range of about 200° C. to about 600° C. or higher by a combination of a flow of cooling gas and radiation from an upper lamp module 324A disposed above the upper quartz window 326. The cooling gas enters through an inlet 330 and exits through an outlet 332. The temperature within the lower quartz chamber 308 can be controlled in a temperature range of about 200° C. to about 600° C. or higher by adjusting the speed of a blower, not shown, and by radiation from a lower lamp module 324B disposed below the lower quartz chamber 308. The pressure within the process space 310 can be between about 0.1 Torr and about 600 Torr, such as between about 5 Torr and about 30 Torr.

[0040]

[0048] The temperature of the surface 322 of the substrate 318 can be controlled by adjusting the power to the lower lamp module 324B in the lower quartz chamber 308, or by adjusting the power to both the upper quartz module 324A overlying the upper quartz window 326 and the lower lamp module 324B in the lower quartz chamber 308. The power density in the process space 310 is about 80 W / cm 2 to about 120 W / cm 2 Between about 40W / cm 2 to about 400 W / cm 2 The range may be between 0.01 and 0.1.

[0041]

[0049] In one embodiment, the gas distribution assembly 312 is positioned perpendicular or radially 338 relative to the longitudinal axis 320 of the processing chamber 300 or substrate 318. In this orientation, the gas distribution assembly 312 is adapted to flow process gases in a radial direction 338 across or parallel to the surface 322 of the substrate 318. In one processing application, the process gases are preheated at the point of introduction into the processing chamber 300 to begin preheating the gases and / or breaking certain bonds in the gases prior to introduction into the processing space 310. In this manner, the surface reaction rate can be modified independent of the thermal temperature of the substrate 318.

[0042]

[0050] In operation, precursors used to form blanket or selective epitaxial films of silicon (Si) and silicon germanium (SiGe) are provided to the gas distribution assembly 312 from one or more gas sources 340A and 340B. IR lamps 342 (only one shown in FIG. 3) may be utilized to heat the precursors within the gas distribution assembly 312 and along the flow path 334. The gas sources 340A, 340B may be coupled to the gas distribution assembly 312 in a manner adapted to facilitate an introduction zone within the gas distribution assembly 312, such as a radially outer zone and a radially inner zone between the outer zones, when viewed from a top view. The gas sources 340A, 340B may include valves (not shown) to control the rate of introduction to the zones.

[0043]

[0051] The gas sources 340A, 340B may include silicon precursors such as silanes, including silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cl6), dibromosilane (SiH2Br2), higher silanes, derivatives thereof, and combinations thereof. The gas sources 340A, 340B may also include germanium-containing precursors, such as germane (GeH4), digermane (Ge2H6), germanium tetrachloride (GeCl4), dichlorogermane (GeH2Cl2), derivatives thereof, and combinations thereof. Silicon and / or germanium-containing precursors may be used in combination with hydrogen chloride (HCl), chlorine gas (Cl2), hydrogen bromide (HBr), and combinations thereof. The gas sources 340A, 340B can include one or more of a silicon-containing precursor and a germanium-containing precursor in one or both of the gas sources 340A, 340B.

[0044]

[0052] The precursor material in this excited state enters the process space 310 through openings or holes 344 in the perforated plate 346 (only one is shown in FIG. 3 ). The perforated plate 346 is a quartz material in one embodiment, having a plurality of holes 344 formed therethrough. The perforated plate 346 is transparent to IR energy and may be made of a transparent quartz material. In other embodiments, the perforated plate 346 may be any material that is transparent to IR energy and resistant to process chemistries and other processing chemistries. The excited precursor material flows through the holes 344 in the perforated plate 346 and through channels 348 (only one is shown in FIG. 3 ) toward the process space 310. A portion of the photons and non-thermal energy from the IR lamps 342 also pass through the holes 344, the perforated plate 346, and the channels 348, thereby illuminating the precursor material flow path 334. The passage is facilitated by reflective materials and / or surfaces disposed on the interior surface of the gas distribution assembly 312. In this manner, the vibrational energy of the precursor material may be maintained from the point of introduction into the processing space 310 along the flow path.

[0045]

[0053] 4 is a cross-sectional view of a processing chamber 400 according to one or more embodiments adapted to perform a selective removal process (SRP), as described in more detail below. The processing chamber 400 may be the processing chamber 124 shown in FIG.

[0046]

[0054] The processing chamber 400 includes a chamber body 402, a lid assembly 404, and a support assembly 406. The lid assembly 404 is disposed on an upper end of the chamber body 402, and the support assembly 406 is disposed at least partially within the chamber body 402. A vacuum system can be used to remove gases from the processing chamber 400. The vacuum system includes a vacuum pump 408 coupled to a vacuum port 410 disposed in the chamber body 402.

[0047]

[0055] The lid assembly 404 includes a remote plasma system (RPS) 412 that can process fluorine-containing precursors. The fluorine-containing precursors then travel through a gas inlet assembly 414. Two separate gas supply channels are visible in the gas inlet assembly 414. A first channel 416 carries gas through the RPS 412 while a second channel 418 bypasses the RPS 412. Either channel can be used for the fluorine-containing precursor. In some embodiments, the first channel 416 can be used for process gases and the second channel 418 can be used for processing gases. A lid (also called a "conductive top portion") 420 and a perforated partition (also called a "showerhead") 422 are shown with an insulating ring 424 between them. The insulating ring 424 allows an AC potential to be applied to the lid 420 relative to the perforated partition 422. The AC potential generates a plasma in the chamber plasma region 426. The process gas travels through the first channel 416 to the chamber plasma region 426 and can be excited by the plasma in the chamber plasma region 426 alone or in combination with the RPS 412. When the process gas (e.g., a fluorine-containing precursor) flows through the second channel 418, only the chamber plasma region 426 is used for excitation. The perforated partition 422 separates the chamber plasma region 426 from the substrate processing region 428 below the perforated partition 422. The perforated partition 422 allows the plasma present in the chamber plasma region 426 to avoid directly exciting the gases in the substrate processing region 428, while still allowing excited species to travel from the chamber plasma region 426 to the substrate processing region 428.

[0048]

[0056] The perforated partition 422 is disposed between the chamber plasma region 426 and the substrate processing region 428 and allows plasma effluents (excited derivatives of precursors or other gases) generated in the RPS 412 and / or the chamber plasma region 426 to pass through through holes 430 that traverse the thickness of the plate. The perforated partition 422 also has one or more hollow spaces 432. The one or more hollow spaces 432 may be filled with precursors in the form of vapors or gases (such as fluorine-containing gases) that may pass through small holes 434 into the substrate processing region 428 but not directly into the chamber plasma region 426. The perforated partition 422 is thicker than the length of the smallest diameter 436 of the through holes 430 in this embodiment. The length 438 of the smallest diameter 436 of the through-hole 430 may be limited by forming the larger diameter portion of the through-hole 430 partway through the perforated partition 422 in order to maintain a significant concentration of excited species penetrating from the chamber plasma region 426 to the substrate processing region 428. The length of the smallest diameter 436 of the through-hole 430 may be on the same order of magnitude as or smaller than the smallest diameter 436 of the through-hole 430 in some embodiments.

[0049]

[0057] The perforated partition 422 may be adapted to serve the purpose of an ion suppressor. Alternatively, a separate processing chamber element may be included (not shown). The separate processing chamber element suppresses the concentration of ions migrating into the substrate processing region 428. The lid 420 and the perforated partition 422 may function as a first electrode and a second electrode, respectively. Thereby, the lid 420 and the perforated partition 422 may receive different voltages. In these configurations, power (e.g., RF power) may be applied to the lid 420, the perforated partition 422, or both. For example, power may be applied to the lid 420 while the perforated partition 422 (acting as an ion suppressor) is grounded. An RF generator may provide power to the lid 420 and / or the perforated partition 422. The voltage applied to the lid 420 may facilitate a uniform distribution of plasma in the chamber plasma region 426 (i.e., reducing localized plasma). An insulating ring 424 may electrically insulate the lid 420 from the perforated partition 422 to enable generation of plasma in the chamber plasma region 426. The insulating ring 424 may be made of ceramic and may have a high breakdown voltage to avoid sparking. Portions of the processing chamber 400 near the capacitively coupled plasma components described above may further include a cooling unit (not shown) that includes one or more cooling fluid channels to cool surfaces exposed to the plasma with a circulating coolant (e.g., water).

[0050]

[0058] In the illustrated embodiment, the perforated partition 422 may distribute (through holes 430) the process gas. The process gas may include fluorine, hydrogen, and / or plasma effluents of such plasma gas excited by the plasma in the chamber plasma region 426. In some embodiments, the process gas introduced into the RPS 412 and / or the chamber plasma region 426 may include fluorine (e.g., F2, NF3, or XeF2). The process gas may also include a diluent gas, such as helium (He), argon (Ar), nitrogen (N2), etc. The plasma effluents may include ionized or neutral derivatives of the process gas, which may be referred to herein as radical fluorine and / or radical hydrogen, referring to the atomic constituents of the process gas introduced.

[0051]

[0059] The perforations 430 inhibit the transport of ionic charged species out of the chamber plasma region 426 while allowing uncharged neutral or radical species to pass through the perforated partition 422 and into the substrate processing region 428. These uncharged species may include highly reactive species that are carried along with the less reactive carrier gas by the perforations 430. As discussed above, the transport of ionic species through the perforations 430 may be reduced and in some cases completely inhibited. By controlling the amount of ionic species that pass through the perforated partition 422, increased control over the gas mixture that comes into contact with the underlying patterned substrate may be achieved. This, in turn, increases control over the deposition and / or etching characteristics of the gas mixture. For example, the ion concentration of the gas mixture may be adjusted to change the etch selectivity (e.g., the ratio of the etch rate of silicon germanium to the etch rate of silicon).

[0052]

[0060] In some embodiments, the number of through holes 430 may be between about 60 and about 2000. The through holes 430 may have a variety of shapes, but are most easily circular. The smallest diameter 436 of the through holes 430 may be between about 0.5 mm and about 20 mm, or between about 1 mm and about 6 mm, in some embodiments. There is also discretion in selecting the cross-sectional shape of the through holes, which may be made conical, cylindrical, or a combination of the two shapes. The number of small holes 434 used to introduce unexcited precursors into the substrate processing region 428 may be between about 100 and about 5000, or between about 500 and about 2000, in various embodiments. The diameter of the small holes 434 may be between about 0.1 mm and about 2 mm.

[0053]

[0061] The through holes 430 may control the passage of plasma active gas (i.e., ionic, radical, and / or neutral species) through the perforated partition 422. For example, the aspect ratio of the holes (i.e., diameter to length of the hole) and / or the geometry of the holes may be controlled to reduce the flow rate of ionic charged species in the active gas passing through the perforated partition 422. The through holes 430 in the perforated partition 422 may include a tapered section facing the chamber plasma region 426 and a cylindrical section facing the substrate processing region 428. The cylindrical section may be proportioned and sized to control the flow rate of ionic species into the substrate processing region 428. As an additional means to control the flow rate of ionic species through the perforated partition 422, an adjustable electrical bias may also be applied to the perforated partition 422.

[0054]

[0062] Alternatively, the through-hole 430 has a smaller inner diameter (ID) toward the top surface of the perforated partition 422 and a larger ID toward the bottom surface. In addition, the bottom edge of the through-hole 430 can be chamfered to help distribute the plasma effluents evenly in the substrate processing region 428 as the plasma effluents exit the perforated partition 422 and promote even distribution of the plasma effluents and precursor gases. The smaller ID can be placed at various positions along the through-hole 430 and still allow the perforated partition 422 to reduce the ion density in the substrate processing region 428. The reduction in ion density results from an increase in the number of collisions with the wall before entering the substrate processing region 428. Each collision increases the probability that an ion will be neutralized by gaining or losing an electron from the wall. Generally speaking, the smaller ID of the through-hole 430 can be between about 0.2 mm and about 20 mm. In other embodiments, the smaller ID can be between about 1 mm and 6 mm, or between about 0.2 mm and about 5 mm. Additionally, the aspect ratio of through hole 430 (i.e., the minor ID relative to the length of the hole) may be approximately 1 to 20. The minor ID of through hole 430 may be the smallest ID found along the length of through hole 430. The cross-sectional shape of through hole 430 may be generally cylindrical, conical, or any combination thereof.

[0055]

[0063] The support assembly 406 may include a substrate support 440 for supporting a substrate 442 thereon during processing. The substrate support 440 may be coupled to an actuator 444 by a shaft 446 that extends through a centrally located opening formed in a bottom portion of the chamber body 402. The actuator 444 may be flexibly sealed to the chamber body 402 by a bellows (not shown) that prevents vacuum leakage around the shaft 446. The actuator 444 may move the substrate support 440 vertically within the chamber body 402 between a processing position and a loading position. The loading position is slightly below a tunnel opening (not shown) formed in a sidewall of the chamber body 402.

[0056]

[0064] The substrate support 440 has a flat or substantially flat substrate support surface for supporting a substrate 442 to be processed thereon. The substrate support 440 may be moved vertically within the chamber body 402 by an actuator 444 coupled to the substrate support 440 by a shaft 446. In some process steps, the substrate may be placed on lift pins 488 to perform further thermal processing steps, such as performing an annealing step.

[0057] Process Example

[0065] FIG. 5 shows a process flow diagram of a method 500 of forming a contact layer in a semiconductor structure 600 according to a first embodiment of the present disclosure. FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, FIG. 6E, FIG. 6F, and FIG. 6G are cross-sectional views of a portion of the semiconductor structure 600 corresponding to various stages of the method 500. It should be understood that FIG. 6A, FIG. 6B, FIG. 6C, FIG. 6D, FIG. 6E, FIG. 6F, and FIG. 6G show only partial schematic views of the semiconductor structure 600, and the semiconductor structure 600 may include any number of transistor sections and additional materials having multiple aspects as shown in the figures. It should also be noted that although the method shown in FIG. 5 is described sequentially, other process sequences including one or more operations omitted and / or added and / or rearranged in another desired order are within the scope of multiple embodiments of the disclosure provided herein.

[0058]

[0066] Referring to Figures 6A, 6B, 6C, 6D, 6E, 6F, and 6G, a semiconductor structure 600 may include a first transistor device 602 and a second transistor device 604 formed on a substrate.

[0059]

[0067] The term "substrate" as used herein refers to a layer of material that serves as a base for subsequent processing operations and includes a surface to be cleaned. The substrate may be a silicon-based material or any suitable insulating or conductive material, as appropriate. The substrate may be crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0060]

[0068] As shown in FIG. 6A, a portion of a first transistor device 602 of a plurality of first transistor devices formed on a substrate includes a first semiconductor region 606 formed of a first material. A portion of a second transistor device 604 of a plurality of second transistor devices formed on a substrate includes a second semiconductor region 608 formed of a second material. The first and second materials include materials having different compositions, whereby the second material can be selectively etched with respect to the first material (i.e., the etch rate of the second material is higher than the etch rate of the first material). The etch selectivity of the second material (i.e., the etch rate of the second material relative to the etch rate of the first material) is between about 10:1 and 500:1. Exemplary combinations of the first and second materials include silicon (Si) / silicon germanium (SiGe), germanium (Ge) / silicon germanium (SiGe), or silicon (Si) / germanium tin (GeSn), respectively.

[0061]

[0069] The first semiconductor region 606 may be approximately 1020 cm2, depending on the desired conductive properties of the first transistor device 602. -3 and 5×1021cm -3The second semiconductor region 608 may be doped with an n-type dopant, such as phosphorus (P) or antimony (Sb), at a concentration between about 1020 cm-2 and about 1020 cm-2, depending on the desired conductive properties of the second transistor device 604. -3 and 5×1021cm -3 It may be doped with a p-type dopant, such as boron (B) or germanium (Ga), at a concentration between 0.1 and 0.5.

[0062]

[0070] The semiconductor structure 600 further includes a dielectric layer 610 having a first opening 612 formed over each of the first semiconductor regions 606 and a second opening 614 formed over each of the second semiconductor regions 608. The dielectric layer 610 may be formed of a dielectric material, such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0063]

[0071] The first semiconductor region 606 and the second semiconductor region 608 may be formed using any suitable deposition technique, such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the openings 612 and 614 are formed by patterning techniques, such as lithography and etching processes.

[0064]

[0072] The method 500 begins with a pre-clean process at block 510. The pre-clean process may be performed in a processing chamber, such as processing chamber 122 shown in FIG. 1 or processing chamber 200 shown in FIG.

[0065]

[0073] The pre-clean process is configured to remove contaminants, such as native oxide layers or patterning residues (e.g., fluorocarbons), formed on exposed surfaces of the first semiconductor region 606 in the first opening 612 and the second semiconductor region 608 in the second opening 614. The pre-clean process is used to prepare the exposed surfaces of the first semiconductor region 606 in the first opening 612 and the second semiconductor region 608 in the second opening 614 on which an epitaxial layer may be formed in a subsequent epitaxial deposition process. The use of the pre-clean process may further adjust the growth rate of an epitaxial layer subsequently deposited on the surface of the first semiconductor region 606 (e.g., silicon (Si)) and the surface of the second semiconductor region 608 (e.g., silicon germanium (SiGe)) in a subsequent epitaxial deposition process. Tuning the growth rate of a subsequently deposited epitaxial layer may be performed by controlling the amount of residual material disposed on the surfaces of the first and second semiconductor regions 606 and 608, such as the amount of residual oxide material, by altering the crystal structure of the material at the surfaces of the first and second semiconductor regions 606 and 608 (e.g., promoting an amorphous or crystalline structure) after performing a surface activation process and / or a pre-clean process. In some embodiments, the pre-clean process may have an etch rate selectivity between the surfaces of the SiGe:B-containing regions to be oxidized and the surfaces of the Si:P-containing regions to be oxidized, such that the pre-clean process, for example, "cleans" (e.g., removes oxide therefrom) the SiGe:B surfaces and leaves at least a portion of the oxide formed thereon on the Si:P surfaces.

[0066]

[0074] The pre-cleaning process may include an anisotropic remote plasma assisted dry etch process, such as a reactive ion etching (RIE) process, using a plasma generated from a gas including argon (Ar), helium (He), or a combination thereof. The plasma effluents are directionally impinged on the residual dielectric layer in the first opening 612 and the second opening 614 to remove the residual dielectric layer.

[0067]

[0075] The pre-cleaning process may include an isotropic plasma etching process, such as the SiCoNi™ dry chemical etching process, which uses a plasma generated from a gas containing ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof, and a carrier gas such as nitrogen (N2), hydrogen (H2), or a combination thereof. Dry chemical etching processes are selective to oxide layers and therefore cannot easily etch silicon, germanium, or nitride layers, whether they are amorphous, crystalline, or polycrystalline. The selectivity of the dry chemical etching process for oxide to silicon or germanium is at least about 3:1, usually 5:1 or more, and often 10:1. The dry chemical etching process also has a high selectivity for oxide to nitride. The selectivity of the dry chemical etching process for nitride is at least about 3:1, usually 5:1 or more, and often 10:1.

[0068]

[0076] The pre-clean process may include an inductively coupled plasma (ICP) etching process using a plasma generated from a gas containing chlorine (Cl2) and hydrogen (H2) and a carrier gas containing argon (Ar) and helium (He). The ICP etching process is used to form deep ridges with smooth sidewalls in the silicon.

[0069]

[0077] The pre-cleaning process may include a surface activation process based on an isotropic plasma etching process, such as a SiCoNi™ dry chemical etching process, using a plasma generated from a gas containing ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof, and a carrier gas, such as nitrogen (N2), hydrogen (H2), or a combination thereof. In one embodiment, the plasma cleaning process is a remote plasma-assisted dry etching process. The remote plasma-assisted dry etching process includes simultaneous exposure of the substrate to HF and NH3, and optionally includes one or more plasma by-products of the gases. Inert gases, such as argon or helium, may also be used. Any one or combination of the three gases, inert gas / HF / NH3, may be exposed to energy as described above to generate a plasma that is used to remove the desired contaminants and passivate at least a portion of the surface of the substrate. After exposing the substrate to the plasma, any compounds remaining on the surface of the substrate may then be removed by heating the substrate to a desired temperature.

[0070]

[0078] 6B, a first selective deposition process is performed to epitaxially form a first contact layer 616 on the exposed surface of the first semiconductor region 606 in the first opening 612 and a second contact layer 618 on the exposed surface of the second semiconductor region 608 in the second opening 614. The first selective deposition process may be performed in a processing chamber, such as processing chambers 126, 128, or 130 shown in FIG. 1 or processing chamber 300 shown in FIG.

[0071]

[0079] The first contact layer 616 is then removed, as described below. A second contact layer 618 is formed as an interface between the second semiconductor region 608 and a metal contact plug formed in the second opening 614 to minimize parasitic resistance. The first contact layer 616 and the second contact layer 618 are formed of a third material. An example of a third material includes silicon germanium (SiGe) with a germanium (Ge) percentage ranging between 20% and 100%. The first contact layer 616 and the second contact layer 618 may be formed of a third material having a thickness of about 1020 cm2, depending on the desired conductive properties of the second contact layer 618. -3 and 5×1021cm -3 It may be doped with a p-type dopant, such as boron (B) or germanium (Ga), at a concentration between 0.1 and 0.5.

[0072]

[0080] In some embodiments, the first selective deposition process includes a first deposition process and a first etching process. The first deposition process is an epitaxial deposition process. The selectivity in the first selective deposition process may result from a difference between the nucleation of the third material on the exposed surfaces of the first semiconductor region 606 and the second semiconductor region 608 (e.g., silicon (Si) or silicon germanium (SiGe)) and the nucleation of the third material on the exposed surfaces of the dielectric layer 610 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). The nucleation may occur at a faster rate on the exposed surfaces of the first semiconductor region 606 and the second semiconductor region 608 (e.g., silicon (Si) or silicon germanium (SiGe)) than on the exposed surfaces of the dielectric layer 610 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)) when the semiconductor structure 600 is exposed to a deposition gas in the first deposition process. Thus, an epitaxial layer of a third material may be formed on the exposed surfaces of the first semiconductor region 606 and the second semiconductor region (e.g., silicon (Si) or silicon germanium (SiGe)) 608, while an amorphous layer of the third material may be formed on the exposed surface of the dielectric layer 610 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)). In a subsequent first etching process, with an appropriate etching gas, the amorphous layer of the third material formed on the exposed surface of the dielectric layer 610 may be etched at a faster rate than the epitaxial layer of the third material formed on the exposed surfaces of the first semiconductor region 606 and the second semiconductor region 608. Thus, the overall result of the combination of the first deposition process and the first etching process may be epitaxial growth of a third material on the exposed surfaces of the first semiconductor region 606 and the second semiconductor region 608, while growth of the third material on the exposed surface of the dielectric layer 610 is minimized, if any.

[0073]

[0081] In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor is silane (SiH4), disilane (Si2H6), tetrasilane (Si4H 10), or combinations thereof. The germanium-containing precursor may include germane (GeH4), germanium tetrachloride (GeCl4), and digermane (Ge2H6). The dopant source may include, for example, boron or gallium depending on the desired conductive properties of the second contact layer 618. The dopant source may include the precursor diborane (B2H6). The etching gas includes an etchant gas and a carrier gas. The etchant gas may include a halogen-containing gas, such as hydrogen chloride (HCI), chlorine (Cl2), or hydrogen fluoride (HF). The carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2).

[0074]

[0082] The first deposition process and the first etch process may be carried out at low temperatures, below about 450° C., and at pressures between 5 and 600 Torr.

[0075]

[0083] The cycle of the first deposition process and the first etch process may be repeated as needed to obtain a desired thickness of the first contact layer 616 and the second contact layer 618. The thickness of the first contact layer 616 and the second contact layer 618 may be between about 30 Å and about 100 Å.

[0076]

[0084] At block 530, a patterning process is performed to form a patterning layer 620 over the second semiconductor region 608 to cover the second contact layer 618, as shown in Figure 6C. The patterning process may be performed using a conventional photolithographic patterning process.

[0077]

[0085] A patterning stack 620 may be deposited on the exposed surface of the semiconductor structure 600 using a planarizing fill process (e.g., spin coating) and then patterned by appropriate lithography and etching processes. The patterning stack 620 may be formed of an organic dielectric layer (ODL), a silicon antireflective coating (SiARC), or a photoresist.

[0078]

[0086] In block 540, a selective removal process (SRP) is performed to remove the first contact layer 616 (e.g., silicon germanium (SiGe)) selectively to the first semiconductor region 606 (e.g., silicon (Si)) and the dielectric layer 610 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)), as shown in Figure 6D. The SRP may be performed in a processing chamber, such as processing chamber 124 shown in Figure 1 or processing chamber 400 shown in Figure 4.

[0079]

[0087] SRP involves plasma etching using plasma effluents generated from a fluorine-containing precursor (e.g., nitrogen trifluoride (NF3)). Plasma effluents from a remote plasma source (e.g., remote plasma source 224 shown in FIG. 4) are flowed into a substrate processing region (e.g., substrate processing region 428 shown in FIG. 4). The plasma effluents react with the exposed surface of the semiconductor structure 600, selectively removing the first contact layer 616 (e.g., silicon germanium (SiGe)) while very slowly removing the first semiconductor region 606 (e.g., silicon (Si)). Generally speaking, SRP as described herein is a process for selectively removing the first contact layer 616 (e.g., silicon germanium (SiGe)) while very slowly removing the first semiconductor region 606 (e.g., silicon (Si)) for all X>Y. (1-Y) Ge Y Faster than Si (1-X) Ge X (including germanium, i.e., where X=1). In some embodiments, the silicon germanium etch selectivity results in part from the presence of an ion suppressor (e.g., perforated partition 422 shown in FIG. 4) disposed between the chamber plasma region (e.g., chamber plasma region 426 shown in FIG. 4) and the substrate processing region (e.g., substrate processing region 428 shown in FIG. 4).

[0080]

[0088] The fluorine-containing precursors include nitrogen trifluoride, fluorocarbons, atomic fluorine, diatomic fluorine, interhalogen fluorides (e.g., bromine trifluoride, chlorine trifluoride), sulfur hexafluoride, xenon difluoride, or combinations thereof. A diluent gas (e.g., argon (Ar), helium (He), nitrogen (N2), or combinations thereof) is also flowed into the chamber plasma region and simultaneously excited into the plasma with the fluorine-containing precursor. The diluent gas reduces the diffusivity of the plasma effluents and increases the etch selectivity of silicon germanium.

[0081]

[0089] In some embodiments, a fluorine-containing precursor (e.g., nitrogen trifluoride (NF3)) is provided at a flow rate between about 5 sccm (standard cubic centimeters per minute) and about 40 sccm, argon (Ar) at a flow rate between about 4 sccm and about 1500 sccm, helium (He) at a flow rate between about 100 sccm and about 5000 sccm, and nitrogen (N2) at a flow rate between about 100 sccm and about 5000 sccm. SRP can be performed at a temperature between about -20°C and about 60°C, and at a pressure between 1 Torr and 50 Torr. The etch selectivity of silicon germanium (SiGe) with a germanium (Ge) ratio of 30% to phosphorous doped silicon (Si:P) is greater than 200:1, and thermal silicon oxide (SiO x ) and greater than 500:1 for silicon nitride (Si3N4).

[0082]

[0090] In block 550, as shown in Figure 6E, a conventional plasma ashing process is performed to remove patterning stack 620. The plasma ashing process may be performed in a processing chamber, such as processing chamber 122 shown in Figure 1 or processing chamber 200 shown in Figure 2.

[0083]

[0091] The plasma ashing process may use a plasma generated from a gas containing oxygen (O2). The ashing process may use a wet cleaning process using a solution such as a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) to remove residues of the patterning stack 620 on the semiconductor structure 600.

[0084]

[0092] At block 560, a second deposition process is performed, as shown in Figure 6F. The second deposition process may be performed in a processing chamber, such as processing chamber 126, 128, or 130 shown in Figure 1 or processing chamber 300 shown in Figure 3.

[0085]

[0093] In a second deposition process, a metal layer 622 is formed on the exposed surfaces of the first semiconductor region 606 and the second contact layer 618. The metal layer 622 contacts the second contact layer 618 and provides and maintains an electrical connection between the contact plug formed in the second opening 614 and the second semiconductor region 608. The metal layer 622 may be formed of a metallic material, such as titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), tantalum (Ta), or a silicide thereof.

[0086]

[0094] In some embodiments, the metal source may include a precursor including titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), or molybdenum (Mo), or a combination thereof. The second deposition process may be carried out at a temperature between about 300° C. and about 800° C., and a pressure between 1 Torr and 50 Torr, respectively.

[0087]

[0095] In the second deposition process, a barrier metal layer 624 may also be formed on the exposed inner surfaces of the first opening 612 and the second opening 614 and on the exposed surfaces of the dielectric layer 610. The barrier metal layer 624 protects the metal layer 622 and enables nucleation and growth of contact plugs in the first opening 612 and the second opening 614, as described below. The barrier metal layer 624 may be formed of a barrier metal material that is titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the metal layer 622 is a silicide layer formed from a portion of the barrier metal layer 624 by use of a spike anneal process. In some other embodiments, the metal layer 622 is a silicide layer formed by another selective deposition process performed prior to forming the barrier metal layer 624.

[0088]

[0096] The second deposition process performed in block 560 may include any suitable deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., in a processing chamber, such as processing chambers 126, 128, or 130 shown in FIG. 1, at a temperature between about 100° C. and about 300° C.

[0089]

[0097] In block 570, a metal fill process is performed to form a first contact plug 626 in the first opening 612 and a second contact plug 628 in the second opening 614, as shown in FIG. 6G. The first contact plug 626 and the second contact plug 628 may be formed of a contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The first contact plug 626 and the second contact plug 628 may include a metal having a desired work function. The metal fill process in block 570 may include a chemical vapor deposition (CVD) process using a tungsten-containing precursor or a cobalt-containing precursor, such as WF6, in a processing chamber, such as the processing chamber 126, 128, or 130 shown in FIG. 1.

[0090]

[0098] After the metal fill process, the semiconductor structure 600 may be planarized, such as by using a chemical mechanical planarization (CMP) process.

[0091] Alternative examples

[0099] FIG. 7 shows a process flow diagram of a method 700 of forming a contact layer in a semiconductor structure 800 according to a second embodiment of the present disclosure. FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, and FIG. 8E are cross-sectional views of a portion of the semiconductor structure 800 corresponding to various stages of the method 700. It should be understood that FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, and FIG. 8E show only partial schematic views of the semiconductor structure 800, and the semiconductor structure 800 may include any number of transistor sections and additional materials having multiple aspects as shown in the drawings. It should also be noted that although the method shown in FIG. 7 is described sequentially, other process sequences including one or more operations omitted and / or added and / or rearranged in another desired order are within the scope of the embodiments of the disclosure provided herein. In the following description, components substantially the same as those in the first embodiment are given the same reference numerals, and descriptions of repeated components may be omitted.

[0092]

[0100] The method 700 starts with a pre-clean process at block 710. The pre-clean process at block 710 is generally the same as the pre-clean process at block 510. The pre-clean process at block 710 can be adjusted to have a higher growth rate of an epitaxial layer of a third material (e.g., silicon germanium (SiGe)) on the exposed surface of the second semiconductor region 608 (e.g., silicon germanium (SiGe)) than a growth rate of an epitaxial layer of a third material (e.g., silicon germanium (SiGe)) on the exposed surface of the first semiconductor region 606 (e.g., silicon (Si)). Knobs for controlling the pre-clean process can include gas chemistry, gas ratios, gas flow rates, substrate temperature, temperature gradients, chamber pressure, power and / or frequency of a power source, RF excitation frequency, duty cycle and / or frequency of RF power, etch time, or combinations thereof. As described above, the growth rate of the subsequently deposited epitaxial layers may be adjusted by controlling or adjusting the composition of the material disposed at the surfaces of the first semiconductor region 606 and the second semiconductor region 608 and / or by varying the crystal structure of the material at the surfaces of the first semiconductor region 606 and the second semiconductor region 608 after performing a pre-cleaning process.

[0093]

[0101] In block 720, a first selective deposition process is performed to epitaxially form a first contact layer 816 on the exposed surface of the first semiconductor region 606 in the first opening 612 and a second contact layer 818 on the exposed surface of the second semiconductor region 608 in the second opening 614, as shown in FIG. 8B. The first selective deposition process in block 720 may be generally the same as the first selective deposition process in block 520. In some embodiments, due to the way the pre-clean process in block 710 was performed and therefore the surface conditions of the first semiconductor region 606 and the second semiconductor region 608 during the first selective deposition process, the second contact layer 818 will grow to a thickness greater than the thickness of the first contact layer 816 during the same processing period.

[0094]

[0102] In some other embodiments of block 720, the process parameters used to simultaneously form the second contact layer 818 and the first contact layer 816 are adjusted such that the thickness of the second contact layer 818 formed on the second semiconductor region 608 is greater than the thickness of the first contact layer 816 formed on the first semiconductor region 606 during the same processing period. By controlling one or more of the deposition process parameters (e.g., temperature, process pressure, precursor gas composition, etc.), the growth rate of the silicon germanium (SiGe)-containing second contact layer 818 on the silicon germanium (SiGe)-containing second semiconductor region 608 can be significantly greater than the growth rate of the silicon germanium (SiGe)-containing first contact layer 816 on the silicon-containing first semiconductor region 606.

[0095]

[0103] In either embodiment of block 720, the first contact layer 816 may be formed to a thickness between about 5 Å and about 100 Å, and the second contact layer 818 may be formed to a thickness between about 30 Å and about 100 Å, where the thickness of the first contact layer 816 is less than the thickness of the second contact layer 818.

[0096]

[0104] In block 730, a selective removal process (SRP) is performed to selectively remove the first contact layer 816 (e.g., silicon germanium (SiGe)) with respect to the first semiconductor region 606 (e.g., silicon (Si)) and the dielectric layer 610 (e.g., silicon dioxide (SiO2) or silicon nitride (Si3N4)), as shown in FIG. 8C. The SRP in block 730 is generally the same as the SRP in block 540. However, the second contact layer 818 is exposed (unlike the second contact layer 618 covered by the patterning stack 620, as shown in FIGS. 6C and 6D), and therefore the second contact layer 818 is also selectively removed. In this process, an amount of the first contact layer 816 and the second contact layer 818 is removed, e.g., all of the first contact layer 816 is removed, and therefore an amount of the second contact layer 818 remains on the second semiconductor region 608 due to the increased thickness of the second contact layer 818 relative to the thickness of the first contact layer 816 formed during block 720. The cycle of the first selective deposition process in block 720 and the SRP in block 730 can be repeated as needed to obtain a desired thickness of the second contact layer 818. The thickness of the second contact layer 818 can be between about 30 Å and about 100 Å.

[0097]

[0105] 8D, a second deposition process is performed to form the metal layer 622 and the barrier metal layer 624. The second deposition process provided in block 740 may be the same as the second deposition process in block 560.

[0098]

[0106] At block 750, a metal fill process is performed to form a first contact plug 626 in the first opening 612 and a second contact plug 628 in the second opening 614, as shown in FIG. 6E. The metal fill process provided at block 750 may be the same as the metal fill process at block 670.

[0099]

[0107] The embodiments described herein provide a method and system for forming a contact epitaxial layer in a trench of a selected portion of a transistor structure. The contact trench structure includes a metal contact plug formed in the trench between adjacent device modules and a contact that interacts between the contact plug and a silicon base channel in the device module. The contact is formed by a selective deposition process to reduce parasitic resistance. The metal contact plug is formed void-free by repeated deposition processes to reduce contact resistance. The contact epitaxial layer may be p-type silicon germanium formed on exposed surfaces of p-type MOS devices (e.g., germanium), while there may be no epitaxial layer on n-type MOS (e.g., silicon) or on a dielectric layer formed on p-type MOS devices and n-type MOS devices. The method and system do not require patterning of the epitaxial layer using a photomask, thus reducing damage to the semiconductor structure being fabricated.

[0100]

[0108] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which is defined by the following claims.

Claims

1. 1. A method for forming an electrical contact in a semiconductor structure, comprising: performing a pre-cleaning process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, the exposed surfaces of the plurality of first semiconductor regions and the plurality of second semiconductor regions each being disposed within an opening formed in a dielectric layer disposed over the substrate; performing a first selective epitaxial deposition process to form a first contact layer on the exposed surface of the first semiconductor region and a second contact layer on the exposed surface of the second semiconductor region; performing a patterning process to form a patterning stack, the patterning stack including the patterned layer including openings formed on the first contact layer disposed in each opening in the dielectric layer and portions of the patterned layer disposed on each second contact layer disposed in each opening in the dielectric layer; and performing a selective removal process on the plurality of first semiconductor regions, the dielectric layer, and the patterned layer to selectively remove the first contact layer.

2. the first semiconductor region formed on the substrate comprises silicon; the second semiconductor region formed on the substrate includes silicon germanium; The method of claim 1 , wherein the first contact layer and the second contact layer comprise silicon germanium.

3. The method of claim 1 , wherein the patterning stack comprises a material selected from an organic dielectric layer, a silicon anti-reflective coating, and a photoresist.

4. The selective removal process comprises: Temperatures between -20°C and 60°C, Pressure between 1 Torr and 50 Torr, a flow rate of a fluorine-containing precursor between about 5 sccm and about 40 sccm; Argon (Ar) flow rate between 4 sccm and 1500 sccm; a flow rate of helium (He) between 100 sccm and 5000 sccm, and Nitrogen (N 2 2. The method of claim 1 , wherein the flow rate is 0.5-1.0 s.

5. The method of claim 1 , further comprising performing an ashing process subsequent to the selective removal process to remove the patterning stack.

6. 6. The method of claim 5, further comprising performing a second deposition process following the ashing process to form a metal layer on the exposed surfaces of the first semiconductor region and the second contact layer formed on the second semiconductor region.

7. 7. The method of claim 6, wherein the metal layer comprises a material selected from titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, and tantalum (Ta) silicide.

8. 1. A method for forming a contact layer in a semiconductor structure, comprising: performing a pre-cleaning process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, the exposed surfaces of the plurality of first semiconductor regions and the plurality of second semiconductor regions each being disposed within an opening formed in a dielectric layer disposed over the substrate; performing a first selective epitaxial deposition process to simultaneously form a first contact layer having a first thickness on the exposed surface of the first semiconductor region and a second contact layer having a second thickness on the exposed surface of the second semiconductor region, the second thickness being greater than the first thickness; and performing a selective removal process on the plurality of first semiconductor regions and the dielectric layer to selectively remove the first contact layer and the second contact layer until the first contact layer is substantially removed from the first semiconductor regions and a portion of the second contact layer remains on the second semiconductor regions.

9. the first semiconductor region formed on the substrate comprises silicon; the second semiconductor region formed on the substrate includes silicon germanium; The method of claim 8 , wherein the first contact layer and the second contact layer comprise silicon germanium.

10. The selective removal process comprises: Temperatures between -20°C and 60°C, Pressure between 1 Torr and 50 Torr, a flow rate of a fluorine-containing precursor between about 5 sccm and about 40 sccm; Argon (Ar) flow rate between 4 sccm and 1500 sccm; a flow rate of helium (He) between 100 sccm and 5000 sccm, and Nitrogen (N 2 9. The method of claim 8, wherein the flow rate is 0.1-0.

25.

11. 10. The method of claim 8, further comprising performing a second selective epitaxial deposition process to form a metal layer on an exposed surface of the first semiconductor region and an exposed surface of the second contact layer formed on the second semiconductor region.

12. 12. The method of claim 11, wherein the metal layer comprises a material selected from titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, and tantalum (Ta) silicide.

13. A first processing chamber; A second processing chamber; a third processing chamber; and 1. A processing system comprising a system controller, the system controller comprising: performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate in the first processing chamber; performing a first selective deposition process in the second processing chamber to epitaxially form a first contact layer on the exposed surface of the first semiconductor region of the substrate and to epitaxially form a second contact layer on the exposed surface of the second semiconductor region of the substrate; and performing a selective removal process in the third processing chamber to remove the first contact layer selectively to the first semiconductor region.

14. 14. The processing system of claim 13, wherein the system controller is further configured to transfer the substrate between the first processing chamber, the second processing chamber, and the third processing chamber without breaking a reduced pressure environment.

15. the first semiconductor region formed on the substrate comprises silicon; the second semiconductor region formed on the substrate includes silicon germanium; 14. The processing system of claim 13, wherein said first contact layer and said second contact layer comprise silicon germanium.

16. The selective removal process in the third processing chamber comprises: Temperatures between -20°C and 60°C, Pressure between 1 Torr and 50 Torr, a flow rate of a fluorine-containing precursor between about 5 sccm and about 40 sccm; Argon (Ar) flow rate between 4 sccm and 1500 sccm; a flow rate of helium (He) between 100 sccm and 5000 sccm, and Nitrogen (N 2 14. The treatment system of claim 13, wherein the treatment system is operated at a flow rate of 0.1 to 1.5 times the flow rate of the first anode.

17. a fourth processing chamber, the system controller further comprising:

14. The processing system of claim 13, further configured to perform a second deposition process in the fourth processing chamber to form a metal layer on an exposed surface of the first semiconductor region formed on the substrate and an exposed surface of the second contact layer formed on the second semiconductor region, the metal layer comprising a material selected from titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, molybdenum (Mo) silicide, and tantalum (Ta) silicide.

18. a fifth processing chamber, the system controller further comprising:

20. The processing system of claim 17, further configured to perform a conformal deposition process in the fifth processing chamber to form a barrier metal layer on the metal layer, the barrier metal layer comprising a material selected from titanium nitride (TiN) and tantalum nitride (TaN).

19. a sixth processing chamber; 20. The processing system of claim 18, wherein the system controller is further configured to: perform an ashing process in the sixth processing chamber prior to the second deposition process in the fourth processing chamber and following the selective removal process in the third processing chamber to remove a patterning stack.

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